2cd7f9592b7965f9b3d4fa2f1a6f4ad00b749a5c
[openwrt.git] / target / linux / au1000 / patches-2.6.32 / 005-revert_mtx1_board_gpiolib.patch
1 commit 1cd692621e6d4b1f707039ea0b4e5ad3143312fb
2 Author: Florian Fainelli <ffainelli@freebox.fr>
3 Date: Thu Jul 1 10:02:53 2010 +0200
4
5 Revert "MIPS: Alchemy: MTX-1: Use linux gpio api."
6
7 This reverts commit b312ab3b5a86c8be5753cdf32ea429ba80651298.
8
9 diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
10 index cc32c69..8ed1ae1 100644
11 --- a/arch/mips/alchemy/mtx-1/board_setup.c
12 +++ b/arch/mips/alchemy/mtx-1/board_setup.c
13 @@ -28,7 +28,6 @@
14 * 675 Mass Ave, Cambridge, MA 02139, USA.
15 */
16
17 -#include <linux/gpio.h>
18 #include <linux/init.h>
19
20 #include <asm/mach-au1x00/au1000.h>
21 @@ -56,11 +55,10 @@ void __init board_setup(void)
22 }
23 #endif
24
25 - alchemy_gpio2_enable();
26 -
27 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
28 /* Enable USB power switch */
29 - alchemy_gpio_direction_output(204, 0);
30 + au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR);
31 + au_writel(0x100000, GPIO2_OUTPUT);
32 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
33
34 #ifdef CONFIG_PCI
35 @@ -76,14 +74,14 @@ void __init board_setup(void)
36
37 /* Initialize GPIO */
38 au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);
39 - alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
40 - alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
41 - alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
42 - alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
43 + au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */
44 + au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */
45 + au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */
46 + au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */
47
48 /* Enable LED and set it to green */
49 - alchemy_gpio_direction_output(211, 1); /* green on */
50 - alchemy_gpio_direction_output(212, 0); /* red off */
51 + au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR);
52 + au_writel(0x18000800, GPIO2_OUTPUT);
53
54 board_pci_idsel = mtx1_pci_idsel;
55
56 @@ -103,10 +101,10 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
57
58 if (assert && devsel != 0)
59 /* Suppress signal to Cardbus */
60 - gpio_set_value(1, 0); /* set EXT_IO3 OFF */
61 + au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */
62 else
63 - gpio_set_value(1, 1); /* set EXT_IO3 ON */
64 -
65 + au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */
66 au_sync_udelay(1);
67 return 1;
68 }
69 +
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