target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

   1 /*
   2  *  Atheros AR724x PCI host controller driver
   3  *
   4  *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  Parts of this file are based on Atheros' 2.6.15 BSP
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/resource.h>
  14 #include <linux/types.h>
  15 #include <linux/delay.h>
  16 #include <linux/bitops.h>
  17 #include <linux/pci.h>
  18 #include <linux/pci_regs.h>
  19 #include <linux/interrupt.h>
  20
  21 #include <asm/mach-ar71xx/ar71xx.h>
  22 #include <asm/mach-ar71xx/pci.h>
  23
  24 #undef DEBUG
  25 #ifdef DEBUG
  26 #define DBG(fmt, args...)       printk(KERN_INFO fmt, ## args)
  27 #else
  28 #define DBG(fmt, args...)
  29 #endif
  30
  31 static void __iomem *ar724x_pci_localcfg_base;
  32 static void __iomem *ar724x_pci_devcfg_base;
  33 static void __iomem *ar724x_pci_ctrl_base;
  34 static int ar724x_pci_fixup_enable;
  35
  36 static DEFINE_SPINLOCK(ar724x_pci_lock);
  37
  38 static inline void ar724x_pci_wr(unsigned reg, u32 val)
  39 {
  40         __raw_writel(val, ar724x_pci_ctrl_base + reg);
  41         (void) __raw_readl(ar724x_pci_ctrl_base + reg);
  42 }
  43
  44 static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
  45 {
  46         __raw_writel(val, ar724x_pci_ctrl_base + reg);
  47 }
  48
  49 static inline u32 ar724x_pci_rr(unsigned reg)
  50 {
  51         return __raw_readl(ar724x_pci_ctrl_base + reg);
  52 }
  53
  54 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
  55 {
  56         unsigned long flags;
  57         u32 data;
  58
  59         spin_lock_irqsave(&ar724x_pci_lock, flags);
  60         data = __raw_readl(base + (where & ~3));
  61
  62         switch (size) {
  63         case 1:
  64                 if (where & 1)
  65                         data >>= 8;
  66                 if (where & 2)
  67                         data >>= 16;
  68                 data &= 0xFF;
  69                 break;
  70         case 2:
  71                 if (where & 2)
  72                         data >>= 16;
  73                 data &= 0xFFFF;
  74                 break;
  75         }
  76
  77         *value = data;
  78         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  79 }
  80
  81 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
  82 {
  83         unsigned long flags;
  84         u32 data;
  85         int s;
  86
  87         spin_lock_irqsave(&ar724x_pci_lock, flags);
  88         data = __raw_readl(base + (where & ~3));
  89
  90         switch (size) {
  91         case 1:
  92                 s = ((where & 3) << 3);
  93                 data &= ~(0xFF << s);
  94                 data |= ((value & 0xFF) << s);
  95                 break;
  96         case 2:
  97                 s = ((where & 2) << 3);
  98                 data &= ~(0xFFFF << s);
  99                 data |= ((value & 0xFFFF) << s);
 100                 break;
 101         case 4:
 102                 data = value;
 103                 break;
 104         }
 105
 106         __raw_writel(data, base + (where & ~3));
 107         /* flush write */
 108         (void)__raw_readl(base + (where & ~3));
 109         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
 110 }
 111
 112 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 113                                   int where, int size, u32 *value)
 114 {
 115
 116         if (bus->number != 0 || devfn != 0)
 117                 return PCIBIOS_DEVICE_NOT_FOUND;
 118
 119         ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
 120
 121         DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 122                         bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 123                         where, size, *value);
 124
 125         /*
 126          * WAR for BAR issue - We are unable to access the PCI device space
 127          * if we set the BAR with proper base address
 128          */
 129         if ((where == 0x10) && (size == 4))
 130                 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
 131
 132         return PCIBIOS_SUCCESSFUL;
 133 }
 134
 135 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 136                                    int where, int size, u32 value)
 137 {
 138         if (bus->number != 0 || devfn != 0)
 139                 return PCIBIOS_DEVICE_NOT_FOUND;
 140
 141         DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 142                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 143                 where, size, value);
 144
 145         ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
 146
 147         return PCIBIOS_SUCCESSFUL;
 148 }
 149
 150 static void ar724x_pci_fixup(struct pci_dev *dev)
 151 {
 152         u16 cmd;
 153
 154         if (!ar724x_pci_fixup_enable)
 155                 return;
 156
 157         if (dev->bus->number != 0 || dev->devfn != 0)
 158                 return;
 159
 160         /* setup COMMAND register */
 161         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 162         cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 163                PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
 164                PCI_COMMAND_FAST_BACK;
 165
 166         pci_write_config_word(dev, PCI_COMMAND, cmd);
 167 }
 168 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
 169
 170 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
 171                                   uint8_t pin)
 172 {
 173         int irq = -1;
 174         int i;
 175
 176         for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
 177                 struct ar71xx_pci_irq *entry;
 178                 entry = &ar71xx_pci_irq_map[i];
 179
 180                 if (entry->slot == slot && entry->pin == pin) {
 181                         irq = entry->irq;
 182                         break;
 183                 }
 184         }
 185
 186         if (irq < 0)
 187                 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
 188                                 pin, pci_name((struct pci_dev *)dev));
 189         else
 190                 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
 191                                 irq, pin, pci_name((struct pci_dev *)dev));
 192
 193         return irq;
 194 }
 195
 196 static struct pci_ops ar724x_pci_ops = {
 197         .read   = ar724x_pci_read_config,
 198         .write  = ar724x_pci_write_config,
 199 };
 200
 201 static struct resource ar724x_pci_io_resource = {
 202         .name           = "PCI IO space",
 203         .start          = 0,
 204         .end            = 0,
 205         .flags          = IORESOURCE_IO,
 206 };
 207
 208 static struct resource ar724x_pci_mem_resource = {
 209         .name           = "PCI memory space",
 210         .start          = AR71XX_PCI_MEM_BASE,
 211         .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 212         .flags          = IORESOURCE_MEM
 213 };
 214
 215 static struct pci_controller ar724x_pci_controller = {
 216         .pci_ops        = &ar724x_pci_ops,
 217         .mem_resource   = &ar724x_pci_mem_resource,
 218         .io_resource    = &ar724x_pci_io_resource,
 219 };
 220
 221 static void __init ar724x_pci_reset(void)
 222 {
 223         ar71xx_device_stop(AR724X_RESET_PCIE);
 224         ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
 225         ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
 226         udelay(100);
 227
 228         ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
 229         udelay(100);
 230         ar71xx_device_start(AR724X_RESET_PCIE_PHY);
 231         ar71xx_device_start(AR724X_RESET_PCIE);
 232 }
 233
 234 static int __init ar724x_pci_setup(void)
 235 {
 236         u32 t;
 237
 238         /* setup COMMAND register */
 239         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
 240             PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
 241
 242         ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
 243         ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
 244         ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
 245
 246         t = ar724x_pci_rr(AR724X_PCI_REG_RESET);
 247         if (t != 0x7) {
 248                 udelay(100000);
 249                 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 0);
 250                 udelay(100);
 251                 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 4);
 252                 udelay(100000);
 253         }
 254
 255         ar724x_pci_wr(AR724X_PCI_REG_APP, AR724X_PCI_APP_LTSSM_ENABLE);
 256         udelay(1000);
 257
 258         t = ar724x_pci_rr(AR724X_PCI_REG_APP);
 259         if ((t & AR724X_PCI_APP_LTSSM_ENABLE) == 0x0) {
 260                 printk(KERN_WARNING "PCI: no PCIe module found\n");
 261                 return -ENODEV;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 268 {
 269         u32 pending;
 270
 271         pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
 272                   ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 273
 274         if (pending & AR724X_PCI_INT_DEV0)
 275                 generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
 276
 277         else
 278                 spurious_interrupt();
 279 }
 280
 281 static void ar724x_pci_irq_unmask(unsigned int irq)
 282 {
 283         switch (irq) {
 284         case AR71XX_PCI_IRQ_DEV0:
 285                 irq -= AR71XX_PCI_IRQ_BASE;
 286                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 287                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
 288                                             AR724X_PCI_INT_DEV0);
 289                 /* flush write */
 290                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 291         }
 292 }
 293
 294 static void ar724x_pci_irq_mask(unsigned int irq)
 295 {
 296         switch (irq) {
 297         case AR71XX_PCI_IRQ_DEV0:
 298                 irq -= AR71XX_PCI_IRQ_BASE;
 299                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 300                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
 301                                             ~AR724X_PCI_INT_DEV0);
 302                 /* flush write */
 303                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 304
 305                 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
 306                               ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
 307                                             AR724X_PCI_INT_DEV0);
 308                 /* flush write */
 309                 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
 310         }
 311 }
 312
 313 static struct irq_chip ar724x_pci_irq_chip = {
 314         .name           = "AR724X PCI ",
 315         .mask           = ar724x_pci_irq_mask,
 316         .unmask         = ar724x_pci_irq_unmask,
 317         .mask_ack       = ar724x_pci_irq_mask,
 318 };
 319
 320 static void __init ar724x_pci_irq_init(void)
 321 {
 322         u32 t;
 323         int i;
 324
 325         t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
 326         if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
 327                  AR724X_RESET_PCIE_PHY_SERIAL)) {
 328                 return;
 329         }
 330
 331         ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
 332         ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
 333
 334         for (i = AR71XX_PCI_IRQ_BASE;
 335              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 336                 irq_desc[i].status = IRQ_DISABLED;
 337                 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
 338                                          handle_level_irq);
 339         }
 340
 341         set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
 342 }
 343
 344 int __init ar724x_pcibios_init(void)
 345 {
 346         int ret = -ENOMEM;
 347
 348         ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
 349                                                    AR724X_PCI_CRP_SIZE);
 350         if (ar724x_pci_localcfg_base == NULL)
 351                 goto err;
 352
 353         ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
 354                                                  AR724X_PCI_CFG_SIZE);
 355         if (ar724x_pci_devcfg_base == NULL)
 356                 goto err_unmap_localcfg;
 357
 358         ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE,
 359                                                AR724X_PCI_CTRL_SIZE);
 360         if (ar724x_pci_ctrl_base == NULL)
 361                 goto err_unmap_devcfg;
 362
 363         ar724x_pci_reset();
 364         ret = ar724x_pci_setup();
 365         if (ret)
 366                 goto err_unmap_ctrl;
 367
 368         ar724x_pci_fixup_enable = 1;
 369         ar724x_pci_irq_init();
 370         register_pci_controller(&ar724x_pci_controller);
 371
 372         return 0;
 373
 374  err_unmap_ctrl:
 375         iounmap(ar724x_pci_ctrl_base);
 376   err_unmap_devcfg:
 377         iounmap(ar724x_pci_devcfg_base);
 378  err_unmap_localcfg:
 379         iounmap(ar724x_pci_localcfg_base);
 380  err:
 381         return ret;
 382 }