package/ubsec_ssb/src/ubsecvar.h

   1 /* $Id: $ */
   2
   3 /*
   4  * Copyright (c) 2008 Daniel Mueller (daniel@danm.de)
   5  * Copyright (c) 2000 Theo de Raadt
   6  * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Effort sponsored in part by the Defense Advanced Research Projects
  30  * Agency (DARPA) and Air Force Research Laboratory, Air Force
  31  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
  32  *
  33  */
  34
  35 /* Maximum queue length */
  36 #ifndef UBS_MAX_NQUEUE
  37 #define UBS_MAX_NQUEUE      60
  38 #endif
  39
  40 #define UBS_MAX_SCATTER     64  /* Maximum scatter/gather depth */
  41
  42 #ifndef UBS_MAX_AGGR
  43 #define UBS_MAX_AGGR        5   /* Maximum aggregation count */
  44 #endif
  45
  46 #define UBSEC_CARD(sid)     (((sid) & 0xf0000000) >> 28)
  47 #define UBSEC_SESSION(sid)  ( (sid) & 0x0fffffff)
  48 #define UBSEC_SID(crd, sesn)    (((crd) << 28) | ((sesn) & 0x0fffffff))
  49
  50 #define UBS_DEF_RTY     0xff    /* PCI Retry Timeout */
  51 #define UBS_DEF_TOUT        0xff    /* PCI TRDY Timeout */
  52 #define UBS_DEF_CACHELINE   0x01    /* Cache Line setting */
  53
  54 #define DEFAULT_HMAC_LEN     12
  55
  56 struct ubsec_dma_alloc {
  57     dma_addr_t      dma_paddr;
  58     void            *dma_vaddr;
  59     /*
  60     bus_dmamap_t            dma_map;
  61     bus_dma_segment_t       dma_seg;
  62     */
  63     size_t          dma_size;
  64     /*
  65     int             dma_nseg;
  66     */
  67 };
  68
  69 struct ubsec_q2 {
  70     BSD_SIMPLEQ_ENTRY(ubsec_q2)     q_next;
  71     struct ubsec_dma_alloc      q_mcr;
  72     struct ubsec_dma_alloc      q_ctx;
  73     u_int               q_type;
  74 };
  75
  76 struct ubsec_q2_rng {
  77     struct ubsec_q2         rng_q;
  78     struct ubsec_dma_alloc      rng_buf;
  79     int             rng_used;
  80 };
  81
  82 /* C = (M ^ E) mod N */
  83 #define UBS_MODEXP_PAR_M    0
  84 #define UBS_MODEXP_PAR_E    1
  85 #define UBS_MODEXP_PAR_N    2
  86 struct ubsec_q2_modexp {
  87     struct ubsec_q2         me_q;
  88     struct cryptkop *       me_krp;
  89     struct ubsec_dma_alloc      me_M;
  90     struct ubsec_dma_alloc      me_E;
  91     struct ubsec_dma_alloc      me_C;
  92     struct ubsec_dma_alloc      me_epb;
  93     int             me_modbits;
  94     int             me_shiftbits;
  95     int             me_normbits;
  96 };
  97
  98 #define UBS_RSAPRIV_PAR_P   0
  99 #define UBS_RSAPRIV_PAR_Q   1
 100 #define UBS_RSAPRIV_PAR_DP  2
 101 #define UBS_RSAPRIV_PAR_DQ  3
 102 #define UBS_RSAPRIV_PAR_PINV    4
 103 #define UBS_RSAPRIV_PAR_MSGIN   5
 104 #define UBS_RSAPRIV_PAR_MSGOUT  6
 105 struct ubsec_q2_rsapriv {
 106     struct ubsec_q2         rpr_q;
 107     struct cryptkop *       rpr_krp;
 108     struct ubsec_dma_alloc      rpr_msgin;
 109     struct ubsec_dma_alloc      rpr_msgout;
 110 };
 111
 112 #define UBSEC_RNG_BUFSIZ    16      /* measured in 32bit words */
 113
 114 struct ubsec_dmachunk {
 115     struct ubsec_mcr    d_mcr;
 116     struct ubsec_mcr_add    d_mcradd[UBS_MAX_AGGR-1];
 117     struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1];
 118     struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1];
 119     u_int32_t       d_macbuf[5];
 120     union {
 121         struct ubsec_pktctx_aes256 ctxaes256;
 122         struct ubsec_pktctx_aes192 ctxaes192;
 123         struct ubsec_pktctx_des ctxdes;
 124         struct ubsec_pktctx_aes128 ctxaes128;
 125         struct ubsec_pktctx     ctx;
 126     } d_ctx;
 127 };
 128
 129 struct ubsec_dma {
 130     BSD_SIMPLEQ_ENTRY(ubsec_dma)    d_next;
 131     struct ubsec_dmachunk       *d_dma;
 132     struct ubsec_dma_alloc      d_alloc;
 133 };
 134
 135 #define UBS_FLAGS_KEY       0x01        /* has key accelerator */
 136 #define UBS_FLAGS_LONGCTX   0x02        /* uses long ipsec ctx */
 137 #define UBS_FLAGS_BIGKEY    0x04        /* 2048bit keys */
 138 #define UBS_FLAGS_HWNORM    0x08        /* hardware normalization */
 139 #define UBS_FLAGS_RNG       0x10        /* hardware rng */
 140 #define UBS_FLAGS_AES       0x20        /* hardware AES support */
 141
 142 struct ubsec_q {
 143     BSD_SIMPLEQ_ENTRY(ubsec_q)      q_next;
 144     int             q_nstacked_mcrs;
 145     struct ubsec_q          *q_stacked_mcr[UBS_MAX_AGGR-1];
 146     struct cryptop          *q_crp;
 147     struct ubsec_dma        *q_dma;
 148
 149     //struct mbuf           *q_src_m, *q_dst_m;
 150     struct sk_buff      *q_src_m, *q_dst_m;
 151     struct uio          *q_src_io, *q_dst_io;
 152
 153     /*
 154     bus_dmamap_t            q_src_map;
 155     bus_dmamap_t            q_dst_map;
 156     */
 157
 158     /* DMA addresses for In-/Out packages */
 159     int q_src_len;
 160     int q_dst_len;
 161     struct ubsec_dma_alloc  q_src_map[UBS_MAX_SCATTER];
 162     struct ubsec_dma_alloc  q_dst_map[UBS_MAX_SCATTER];
 163     int q_has_dst;
 164
 165     int             q_sesn;
 166     int             q_flags;
 167 };
 168
 169 struct ubsec_softc {
 170     softc_device_decl   sc_dev;
 171     struct ssb_device   *sdev;      /* device backpointer */
 172
 173     struct device       *sc_dv;     /* generic device */
 174     void                *sc_ih;     /* interrupt handler cookie */
 175     int                 sc_flags;   /* device specific flags */
 176     u_int32_t           sc_statmask;    /* interrupt status mask */
 177     int32_t             sc_cid;     /* crypto tag */
 178     BSD_SIMPLEQ_HEAD(,ubsec_q)  sc_queue;   /* packet queue, mcr1 */
 179     int                 sc_nqueue;  /* count enqueued, mcr1 */
 180     BSD_SIMPLEQ_HEAD(,ubsec_q)  sc_qchip;   /* on chip, mcr1 */
 181     BSD_SIMPLEQ_HEAD(,ubsec_q)  sc_freequeue;   /* list of free queue elements */
 182     BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_queue2;  /* packet queue, mcr2 */
 183     int                 sc_nqueue2; /* count enqueued, mcr2 */
 184     BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2;  /* on chip, mcr2 */
 185     int                 sc_nsessions;   /* # of sessions */
 186     struct ubsec_session        *sc_sessions;   /* sessions */
 187     int                 sc_rnghz;   /* rng poll time */
 188     struct ubsec_q2_rng sc_rng;
 189     struct ubsec_dma    sc_dmaa[UBS_MAX_NQUEUE];
 190     struct ubsec_q      *sc_queuea[UBS_MAX_NQUEUE];
 191     BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_q2free;  /* free list */
 192     spinlock_t          sc_ringmtx; /* PE ring lock */
 193 };
 194
 195 #define UBSEC_QFLAGS_COPYOUTIV      0x1
 196
 197 struct ubsec_session {
 198     u_int32_t   ses_used;
 199     u_int32_t   ses_key[8];         /* 3DES/AES key */
 200     u_int32_t   ses_hminner[5];     /* hmac inner state */
 201     u_int32_t   ses_hmouter[5];     /* hmac outer state */
 202     u_int32_t   ses_iv[4];          /* [3]DES/AES iv */
 203     u_int32_t   ses_keysize;        /* AES key size */
 204     u_int32_t   ses_mlen;           /* hmac/hash length */
 205 };
 206
 207 struct ubsec_stats {
 208     u_int64_t hst_ibytes;
 209     u_int64_t hst_obytes;
 210     u_int32_t hst_ipackets;
 211     u_int32_t hst_opackets;
 212     u_int32_t hst_invalid;
 213     u_int32_t hst_nomem;
 214     u_int32_t hst_queuefull;
 215     u_int32_t hst_dmaerr;
 216     u_int32_t hst_mcrerr;
 217     u_int32_t hst_nodmafree;
 218 };
 219
 220 struct ubsec_generic_ctx {
 221     u_int32_t   pc_key[8];      /* [3]DES/AES key */
 222     u_int32_t   pc_hminner[5];  /* hmac inner state */
 223     u_int32_t   pc_hmouter[5];  /* hmac outer state */
 224     u_int32_t   pc_iv[4];       /* [3]DES/AES iv */
 225     u_int16_t   pc_flags;       /* flags, below */
 226     u_int16_t   pc_offset;      /* crypto offset */
 227     u_int16_t   pc_type;        /* Cryptographic operation */
 228 };
 229