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[adm5120] flash driver fixes
[openwrt.git] / target / linux / ixp4xx-2.6 / patches / 178-via_velocity_bigendian.patch
1 Index: linux-2.6.20-rc3/drivers/net/via-velocity.c
2 ===================================================================
3 --- linux-2.6.20-rc3.orig/drivers/net/via-velocity.c 2007-01-02 10:30:25.892465963 +0000
4 +++ linux-2.6.20-rc3/drivers/net/via-velocity.c 2007-01-02 10:30:36.261113964 +0000
5 @@ -96,11 +96,31 @@
6 MODULE_LICENSE("GPL");
7 MODULE_DESCRIPTION("VIA Networking Velocity Family Gigabit Ethernet Adapter Driver");
8
9 +/* Valid values for vdebug (additive, this is a bitmask):
10 + * 0x00 => off
11 + * 0x01 => always on
12 + * 0x02 => additional detail on tx (rx, too, if anyone implements same)
13 + * 0x04 => detail the initialization process
14 + * 0x08 => spot debug detail; to be used as developers see fit
15 + */
16 +static int vdebug = 0;
17 +
18 +/* HAIL - these macros are for the normal 0x01-type tracing... */
19 +#define HAIL(S) \
20 + if (vdebug&1) printk(KERN_NOTICE "%s\n", (S));
21 +#define HAILS(S,T) \
22 + if (vdebug&1) printk(KERN_NOTICE "%s -> status=0x%x\n", (S), (T));
23 +
24 #define VELOCITY_PARAM(N,D) \
25 static int N[MAX_UNITS]=OPTION_DEFAULT;\
26 module_param_array(N, int, NULL, 0); \
27 MODULE_PARM_DESC(N, D);
28
29 +#define VELO_DEBUG_MIN 0
30 +#define VELO_DEBUG_MAX 255
31 +#define VELO_DEBUG_DEF 0
32 +VELOCITY_PARAM(velo_debug, "Debug level");
33 +
34 #define RX_DESC_MIN 64
35 #define RX_DESC_MAX 255
36 #define RX_DESC_DEF 64
37 @@ -385,12 +405,12 @@
38 if (val == -1)
39 *opt = def;
40 else if (val < min || val > max) {
41 - VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
42 - devname, name, min, max);
43 + VELOCITY_PRT(MSG_LEVEL_INFO, KERN_NOTICE "via-velocity: the value of parameter %s is invalid, the valid range is (%d-%d)\n",
44 + name, min, max);
45 *opt = def;
46 } else {
47 - VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "%s: set value of parameter %s to %d\n",
48 - devname, name, val);
49 + VELOCITY_PRT(MSG_LEVEL_INFO, KERN_INFO "via-velocity: set value of parameter %s to %d\n",
50 + name, val);
51 *opt = val;
52 }
53 }
54 @@ -415,12 +435,12 @@
55 if (val == -1)
56 *opt |= (def ? flag : 0);
57 else if (val < 0 || val > 1) {
58 - printk(KERN_NOTICE "%s: the value of parameter %s is invalid, the valid range is (0-1)\n",
59 - devname, name);
60 + printk(KERN_NOTICE "via-velocity: the value of parameter %s is invalid, the valid range is (0-1)\n",
61 + name);
62 *opt |= (def ? flag : 0);
63 } else {
64 - printk(KERN_INFO "%s: set parameter %s to %s\n",
65 - devname, name, val ? "TRUE" : "FALSE");
66 + printk(KERN_INFO "via-velocity: set parameter %s to %s\n",
67 + name, val ? "TRUE" : "FALSE");
68 *opt |= (val ? flag : 0);
69 }
70 }
71 @@ -438,6 +458,7 @@
72 static void __devinit velocity_get_options(struct velocity_opt *opts, int index, char *devname)
73 {
74
75 + velocity_set_int_opt(&opts->velo_debug, velo_debug[index], VELO_DEBUG_MIN, VELO_DEBUG_MAX, VELO_DEBUG_DEF, "velo_debug", devname);
76 velocity_set_int_opt(&opts->rx_thresh, rx_thresh[index], RX_THRESH_MIN, RX_THRESH_MAX, RX_THRESH_DEF, "rx_thresh", devname);
77 velocity_set_int_opt(&opts->DMA_length, DMA_length[index], DMA_LENGTH_MIN, DMA_LENGTH_MAX, DMA_LENGTH_DEF, "DMA_length", devname);
78 velocity_set_int_opt(&opts->numrx, RxDescriptors[index], RX_DESC_MIN, RX_DESC_MAX, RX_DESC_DEF, "RxDescriptors", devname);
79 @@ -452,6 +473,7 @@
80 velocity_set_int_opt((int *) &opts->wol_opts, wol_opts[index], WOL_OPT_MIN, WOL_OPT_MAX, WOL_OPT_DEF, "Wake On Lan options", devname);
81 velocity_set_int_opt((int *) &opts->int_works, int_works[index], INT_WORKS_MIN, INT_WORKS_MAX, INT_WORKS_DEF, "Interrupt service works", devname);
82 opts->numrx = (opts->numrx & ~3);
83 + vdebug = opts->velo_debug;
84 }
85
86 /**
87 @@ -466,6 +488,8 @@
88 {
89 struct mac_regs __iomem * regs = vptr->mac_regs;
90
91 + HAIL("velocity_init_cam_filter");
92 +
93 /* Turn on MCFG_PQEN, turn off MCFG_RTGOPT */
94 WORD_REG_BITS_SET(MCFG_PQEN, MCFG_RTGOPT, &regs->MCFG);
95 WORD_REG_BITS_ON(MCFG_VIDFR, &regs->MCFG);
96 @@ -484,14 +508,12 @@
97 WORD_REG_BITS_ON(MCFG_RTGOPT, &regs->MCFG);
98
99 mac_set_cam(regs, 0, (u8 *) & (vptr->options.vid), VELOCITY_VLAN_ID_CAM);
100 - vptr->vCAMmask[0] |= 1;
101 - mac_set_cam_mask(regs, vptr->vCAMmask, VELOCITY_VLAN_ID_CAM);
102 } else {
103 u16 temp = 0;
104 mac_set_cam(regs, 0, (u8 *) &temp, VELOCITY_VLAN_ID_CAM);
105 - temp = 1;
106 - mac_set_cam_mask(regs, (u8 *) &temp, VELOCITY_VLAN_ID_CAM);
107 }
108 + vptr->vCAMmask[0] |= 1;
109 + mac_set_cam_mask(regs, vptr->vCAMmask, VELOCITY_VLAN_ID_CAM);
110 }
111
112 /**
113 @@ -508,13 +530,15 @@
114 struct mac_regs __iomem * regs = vptr->mac_regs;
115 int i;
116
117 + HAIL("velocity_rx_reset");
118 vptr->rd_dirty = vptr->rd_filled = vptr->rd_curr = 0;
119
120 /*
121 * Init state, all RD entries belong to the NIC
122 */
123 for (i = 0; i < vptr->options.numrx; ++i)
124 - vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC;
125 + /* vptr->rd_ring[i].rdesc0.owner = OWNED_BY_NIC; BE */
126 + vptr->rd_ring[i].rdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
127
128 writew(vptr->options.numrx, &regs->RBRDU);
129 writel(vptr->rd_pool_dma, &regs->RDBaseLo);
130 @@ -537,12 +561,15 @@
131 struct mac_regs __iomem * regs = vptr->mac_regs;
132 int i, mii_status;
133
134 + if (vdebug&5) printk(KERN_NOTICE "velocity_init_registers: entering\n");
135 +
136 mac_wol_reset(regs);
137
138 switch (type) {
139 case VELOCITY_INIT_RESET:
140 case VELOCITY_INIT_WOL:
141
142 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: RESET or WOL\n");
143 netif_stop_queue(vptr->dev);
144
145 /*
146 @@ -570,12 +597,13 @@
147
148 case VELOCITY_INIT_COLD:
149 default:
150 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: COLD or default\n");
151 /*
152 * Do reset
153 */
154 velocity_soft_reset(vptr);
155 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: soft reset complete.\n");
156 mdelay(5);
157 -
158 mac_eeprom_reload(regs);
159 for (i = 0; i < 6; i++) {
160 writeb(vptr->dev->dev_addr[i], &(regs->PAR[i]));
161 @@ -593,11 +621,16 @@
162 */
163 BYTE_REG_BITS_SET(CFGB_OFSET, (CFGB_CRANDOM | CFGB_CAP | CFGB_MBA | CFGB_BAKOPT), &regs->CFGB);
164
165 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Initializing CAM filter\n");
166 /*
167 * Init CAM filter
168 */
169 + if (vdebug&8) printk(KERN_NOTICE "velocity: spot debug: about to init CAM filters\n");
170 + mdelay(5); /* MJW - ARM processors, kernel 2.6.19 - this fixes oopses and hangs */
171 velocity_init_cam_filter(vptr);
172 + if (vdebug&8) printk(KERN_NOTICE "velocity: spot debug: init CAM filters complete\n");
173
174 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Setting packet filter\n");
175 /*
176 * Set packet filter: Receive directed and broadcast address
177 */
178 @@ -607,10 +640,12 @@
179 * Enable MII auto-polling
180 */
181 enable_mii_autopoll(regs);
182 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: enable_mii_autopoll complete.\n");
183
184 vptr->int_mask = INT_MASK_DEF;
185
186 - writel(cpu_to_le32(vptr->rd_pool_dma), &regs->RDBaseLo);
187 + /* writel(cpu_to_le32(vptr->rd_pool_dma), &regs->RDBaseLo); BE */
188 + writel((vptr->rd_pool_dma), &regs->RDBaseLo); /* BE */
189 writew(vptr->options.numrx - 1, &regs->RDCSize);
190 mac_rx_queue_run(regs);
191 mac_rx_queue_wake(regs);
192 @@ -618,10 +653,13 @@
193 writew(vptr->options.numtx - 1, &regs->TDCSize);
194
195 for (i = 0; i < vptr->num_txq; i++) {
196 - writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i]));
197 + /* writel(cpu_to_le32(vptr->td_pool_dma[i]), &(regs->TDBaseLo[i])); BE */
198 + writel((vptr->td_pool_dma[i]), &(regs->TDBaseLo[i])); /* BE */
199 mac_tx_queue_run(regs, i);
200 }
201
202 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: DMA settings complete.\n");
203 +
204 init_flow_control_register(vptr);
205
206 writel(CR0_STOP, &regs->CR0Clr);
207 @@ -640,8 +678,10 @@
208
209 enable_flow_control_ability(vptr);
210 mac_hw_mibs_init(regs);
211 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: Set interrupt mask\n");
212 mac_write_int_mask(vptr->int_mask, regs);
213 mac_clear_isr(regs);
214 + if (vdebug&4) printk(KERN_NOTICE "velocity_init_registers: complete.\n");
215
216 }
217 }
218 @@ -659,6 +699,7 @@
219 struct mac_regs __iomem * regs = vptr->mac_regs;
220 int i = 0;
221
222 + HAIL("velocity_soft_reset");
223 writel(CR0_SFRST, &regs->CR0Set);
224
225 for (i = 0; i < W_MAX_TIMEOUT; i++) {
226 @@ -722,6 +763,7 @@
227 VELOCITY_FULL_DRV_NAM, VELOCITY_VERSION);
228 printk(KERN_INFO "Copyright (c) 2002, 2003 VIA Networking Technologies, Inc.\n");
229 printk(KERN_INFO "Copyright (c) 2004 Red Hat Inc.\n");
230 + printk(KERN_INFO "BE support, misc. fixes MJW 01Jan2007 - may be unstable\n");
231 first = 0;
232 }
233
234 @@ -935,6 +977,7 @@
235 dma_addr_t pool_dma;
236 u8 *pool;
237
238 + HAIL("velocity_init_rings");
239 /*
240 * Allocate all RD/TD rings a single pool
241 */
242 @@ -997,6 +1040,7 @@
243 static void velocity_free_rings(struct velocity_info *vptr)
244 {
245 int size;
246 + HAIL("velocity_free_rings");
247
248 size = vptr->options.numrx * sizeof(struct rx_desc) +
249 vptr->options.numtx * sizeof(struct tx_desc) * vptr->num_txq;
250 @@ -1013,6 +1057,7 @@
251 struct mac_regs __iomem *regs = vptr->mac_regs;
252 int avail, dirty, unusable;
253
254 + HAIL("velocity_give_many_rx_descs");
255 /*
256 * RD number must be equal to 4X per hardware spec
257 * (programming guide rev 1.20, p.13)
258 @@ -1026,7 +1071,8 @@
259 dirty = vptr->rd_dirty - unusable;
260 for (avail = vptr->rd_filled & 0xfffc; avail; avail--) {
261 dirty = (dirty > 0) ? dirty - 1 : vptr->options.numrx - 1;
262 - vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC;
263 + /* vptr->rd_ring[dirty].rdesc0.owner = OWNED_BY_NIC; BE */
264 + vptr->rd_ring[dirty].rdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
265 }
266
267 writew(vptr->rd_filled & 0xfffc, &regs->RBRDU);
268 @@ -1036,12 +1082,14 @@
269 static int velocity_rx_refill(struct velocity_info *vptr)
270 {
271 int dirty = vptr->rd_dirty, done = 0, ret = 0;
272 + HAIL("velocity_rx_refill");
273
274 do {
275 struct rx_desc *rd = vptr->rd_ring + dirty;
276
277 /* Fine for an all zero Rx desc at init time as well */
278 - if (rd->rdesc0.owner == OWNED_BY_NIC)
279 + /* if (rd->rdesc0.owner == OWNED_BY_NIC) BE */
280 + if (rd->rdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
281 break;
282
283 if (!vptr->rd_info[dirty].skb) {
284 @@ -1076,6 +1124,7 @@
285 unsigned int rsize = sizeof(struct velocity_rd_info) *
286 vptr->options.numrx;
287
288 + HAIL("velocity_init_rd_ring");
289 vptr->rd_info = kmalloc(rsize, GFP_KERNEL);
290 if(vptr->rd_info == NULL)
291 goto out;
292 @@ -1105,6 +1154,7 @@
293 {
294 int i;
295
296 + HAIL("velocity_free_rd_ring");
297 if (vptr->rd_info == NULL)
298 return;
299
300 @@ -1146,6 +1196,7 @@
301 unsigned int tsize = sizeof(struct velocity_td_info) *
302 vptr->options.numtx;
303
304 + HAIL("velocity_init_td_ring");
305 /* Init the TD ring entries */
306 for (j = 0; j < vptr->num_txq; j++) {
307 curr = vptr->td_pool_dma[j];
308 @@ -1182,6 +1233,7 @@
309 struct velocity_td_info * td_info = &(vptr->td_infos[q][n]);
310 int i;
311
312 + HAIL("velocity_free_td_ring_entry");
313 if (td_info == NULL)
314 return;
315
316 @@ -1211,6 +1263,7 @@
317 {
318 int i, j;
319
320 + HAIL("velocity_free_td_ring");
321 for (j = 0; j < vptr->num_txq; j++) {
322 if (vptr->td_infos[j] == NULL)
323 continue;
324 @@ -1238,34 +1291,42 @@
325 struct net_device_stats *stats = &vptr->stats;
326 int rd_curr = vptr->rd_curr;
327 int works = 0;
328 + u16 wRSR; /* BE */
329
330 + HAILS("velocity_rx_srv", status);
331 do {
332 struct rx_desc *rd = vptr->rd_ring + rd_curr;
333
334 if (!vptr->rd_info[rd_curr].skb)
335 break;
336
337 - if (rd->rdesc0.owner == OWNED_BY_NIC)
338 + /* if (rd->rdesc0.owner == OWNED_BY_NIC) BE */
339 + if (rd->rdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
340 break;
341
342 rmb();
343
344 + wRSR = (u16)(cpu_to_le32(rd->rdesc0)); /* BE */
345 /*
346 * Don't drop CE or RL error frame although RXOK is off
347 */
348 - if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) {
349 + /* if ((rd->rdesc0.RSR & RSR_RXOK) || (!(rd->rdesc0.RSR & RSR_RXOK) && (rd->rdesc0.RSR & (RSR_CE | RSR_RL)))) { BE */
350 + if ((wRSR & RSR_RXOK) || (!(wRSR & RSR_RXOK) && (wRSR & (RSR_CE | RSR_RL)))) { /* BE */
351 if (velocity_receive_frame(vptr, rd_curr) < 0)
352 stats->rx_dropped++;
353 } else {
354 - if (rd->rdesc0.RSR & RSR_CRC)
355 + /* if (rd->rdesc0.RSR & RSR_CRC) BE */
356 + if (wRSR & RSR_CRC) /* BE */
357 stats->rx_crc_errors++;
358 - if (rd->rdesc0.RSR & RSR_FAE)
359 + /* if (rd->rdesc0.RSR & RSR_FAE) BE */
360 + if (wRSR & RSR_FAE) /* BE */
361 stats->rx_frame_errors++;
362
363 stats->rx_dropped++;
364 }
365
366 - rd->inten = 1;
367 + /* rd->inten = 1; BE */
368 + rd->ltwo |= cpu_to_le32(BE_INT_ENABLE); /* BE */
369
370 vptr->dev->last_rx = jiffies;
371
372 @@ -1296,13 +1357,21 @@
373
374 static inline void velocity_rx_csum(struct rx_desc *rd, struct sk_buff *skb)
375 {
376 + u8 bCSM;
377 + HAIL("velocity_rx_csum");
378 skb->ip_summed = CHECKSUM_NONE;
379
380 - if (rd->rdesc1.CSM & CSM_IPKT) {
381 - if (rd->rdesc1.CSM & CSM_IPOK) {
382 - if ((rd->rdesc1.CSM & CSM_TCPKT) ||
383 - (rd->rdesc1.CSM & CSM_UDPKT)) {
384 - if (!(rd->rdesc1.CSM & CSM_TUPOK)) {
385 +// if (rd->rdesc1.CSM & CSM_IPKT) {
386 +// if (rd->rdesc1.CSM & CSM_IPOK) {
387 +// if ((rd->rdesc1.CSM & CSM_TCPKT) ||
388 +// (rd->rdesc1.CSM & CSM_UDPKT)) {
389 +// if (!(rd->rdesc1.CSM & CSM_TUPOK)) {
390 + bCSM = (u8)(cpu_to_le32(rd->rdesc1) >> 16); /* BE */
391 + if (bCSM & CSM_IPKT) {
392 + if (bCSM & CSM_IPOK) {
393 + if ((bCSM & CSM_TCPKT) ||
394 + (bCSM & CSM_UDPKT)) {
395 + if (!(bCSM & CSM_TUPOK)) { /* BE */
396 return;
397 }
398 }
399 @@ -1328,9 +1397,11 @@
400 {
401 int ret = -1;
402
403 + HAIL("velocity_rx_copy");
404 if (pkt_size < rx_copybreak) {
405 struct sk_buff *new_skb;
406
407 + HAIL("velocity_rx_copy (working...)");
408 new_skb = dev_alloc_skb(pkt_size + 2);
409 if (new_skb) {
410 new_skb->dev = vptr->dev;
411 @@ -1360,10 +1431,12 @@
412 static inline void velocity_iph_realign(struct velocity_info *vptr,
413 struct sk_buff *skb, int pkt_size)
414 {
415 + HAIL("velocity_iph_realign");
416 /* FIXME - memmove ? */
417 if (vptr->flags & VELOCITY_FLAGS_IP_ALIGN) {
418 int i;
419
420 + HAIL("velocity_iph_realign (working...)");
421 for (i = pkt_size; i >= 0; i--)
422 *(skb->data + i + 2) = *(skb->data + i);
423 skb_reserve(skb, 2);
424 @@ -1382,19 +1455,27 @@
425 static int velocity_receive_frame(struct velocity_info *vptr, int idx)
426 {
427 void (*pci_action)(struct pci_dev *, dma_addr_t, size_t, int);
428 + u16 pkt_len; /* BE */
429 + u16 wRSR; /* BE */
430 + struct sk_buff *skb;
431 struct net_device_stats *stats = &vptr->stats;
432 struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
433 struct rx_desc *rd = &(vptr->rd_ring[idx]);
434 - int pkt_len = rd->rdesc0.len;
435 - struct sk_buff *skb;
436 + /* int pkt_len = rd->rdesc0.len BE */;
437 +
438 + pkt_len = ((cpu_to_le32(rd->rdesc0) >> 16) & 0x00003FFFUL); /* BE */
439 + wRSR = (u16)(cpu_to_le32(rd->rdesc0)); /* BE */
440
441 - if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) {
442 + HAIL("velocity_receive_frame");
443 + /* if (rd->rdesc0.RSR & (RSR_STP | RSR_EDP)) { BE */
444 + if (wRSR & (RSR_STP | RSR_EDP)) { /* BE */
445 VELOCITY_PRT(MSG_LEVEL_VERBOSE, KERN_ERR " %s : the received frame span multple RDs.\n", vptr->dev->name);
446 stats->rx_length_errors++;
447 return -EINVAL;
448 }
449
450 - if (rd->rdesc0.RSR & RSR_MAR)
451 + /* if (rd->rdesc0.RSR & RSR_MAR) BE */
452 + if (wRSR & RSR_MAR) /* BE */
453 vptr->stats.multicast++;
454
455 skb = rd_info->skb;
456 @@ -1408,7 +1489,8 @@
457 */
458
459 if (vptr->flags & VELOCITY_FLAGS_VAL_PKT_LEN) {
460 - if (rd->rdesc0.RSR & RSR_RL) {
461 + /* if (rd->rdesc0.RSR & RSR_RL) { BE */
462 + if (wRSR & RSR_RL) { /* BE */
463 stats->rx_length_errors++;
464 return -EINVAL;
465 }
466 @@ -1452,6 +1534,7 @@
467 struct rx_desc *rd = &(vptr->rd_ring[idx]);
468 struct velocity_rd_info *rd_info = &(vptr->rd_info[idx]);
469
470 + HAIL("velocity_alloc_rx_buf");
471 rd_info->skb = dev_alloc_skb(vptr->rx_buf_sz + 64);
472 if (rd_info->skb == NULL)
473 return -ENOMEM;
474 @@ -1469,10 +1552,14 @@
475 */
476
477 *((u32 *) & (rd->rdesc0)) = 0;
478 - rd->len = cpu_to_le32(vptr->rx_buf_sz);
479 - rd->inten = 1;
480 + /* rd->len = cpu_to_le32(vptr->rx_buf_sz); BE */
481 + /* rd->inten = 1; BE */
482 rd->pa_low = cpu_to_le32(rd_info->skb_dma);
483 - rd->pa_high = 0;
484 + /* rd->pa_high = 0; BE */
485 + rd->ltwo &= cpu_to_le32(0xC000FFFFUL); /* BE */
486 + rd->ltwo |= cpu_to_le32((vptr->rx_buf_sz << 16)); /* BE */
487 + rd->ltwo |= cpu_to_le32(BE_INT_ENABLE); /* BE */
488 + rd->ltwo &= cpu_to_le32(0xFFFF0000UL); /* BE */
489 return 0;
490 }
491
492 @@ -1493,9 +1580,11 @@
493 int full = 0;
494 int idx;
495 int works = 0;
496 + u16 wTSR; /* BE */
497 struct velocity_td_info *tdinfo;
498 struct net_device_stats *stats = &vptr->stats;
499
500 + HAILS("velocity_tx_srv", status);
501 for (qnum = 0; qnum < vptr->num_txq; qnum++) {
502 for (idx = vptr->td_tail[qnum]; vptr->td_used[qnum] > 0;
503 idx = (idx + 1) % vptr->options.numtx) {
504 @@ -1506,22 +1595,29 @@
505 td = &(vptr->td_rings[qnum][idx]);
506 tdinfo = &(vptr->td_infos[qnum][idx]);
507
508 - if (td->tdesc0.owner == OWNED_BY_NIC)
509 + /* if (td->tdesc0.owner == OWNED_BY_NIC) BE */
510 + if (td->tdesc0 & cpu_to_le32(BE_OWNED_BY_NIC)) /* BE */
511 break;
512
513 if ((works++ > 15))
514 break;
515
516 - if (td->tdesc0.TSR & TSR0_TERR) {
517 + wTSR = (u16)cpu_to_le32(td->tdesc0);
518 + /* if (td->tdesc0.TSR & TSR0_TERR) { BE */
519 + if (wTSR & TSR0_TERR) { /* BE */
520 stats->tx_errors++;
521 stats->tx_dropped++;
522 - if (td->tdesc0.TSR & TSR0_CDH)
523 + /* if (td->tdesc0.TSR & TSR0_CDH) BE */
524 + if (wTSR & TSR0_CDH) /* BE */
525 stats->tx_heartbeat_errors++;
526 - if (td->tdesc0.TSR & TSR0_CRS)
527 + /* if (td->tdesc0.TSR & TSR0_CRS) BE */
528 + if (wTSR & TSR0_CRS) /* BE */
529 stats->tx_carrier_errors++;
530 - if (td->tdesc0.TSR & TSR0_ABT)
531 + /* if (td->tdesc0.TSR & TSR0_ABT) BE */
532 + if (wTSR & TSR0_ABT) /* BE */
533 stats->tx_aborted_errors++;
534 - if (td->tdesc0.TSR & TSR0_OWC)
535 + /* if (td->tdesc0.TSR & TSR0_OWC) BE */
536 + if (wTSR & TSR0_OWC) /* BE */
537 stats->tx_window_errors++;
538 } else {
539 stats->tx_packets++;
540 @@ -1610,6 +1706,7 @@
541
542 static void velocity_error(struct velocity_info *vptr, int status)
543 {
544 + HAILS("velocity_error", status);
545
546 if (status & ISR_TXSTLI) {
547 struct mac_regs __iomem * regs = vptr->mac_regs;
548 @@ -1699,6 +1796,7 @@
549 struct sk_buff *skb = tdinfo->skb;
550 int i;
551
552 + HAIL("velocity_free_tx_buf");
553 /*
554 * Don't unmap the pre-allocated tx_bufs
555 */
556 @@ -1902,6 +2000,7 @@
557 struct velocity_td_info *tdinfo;
558 unsigned long flags;
559 int index;
560 + u32 lbufsz; /* BE */
561
562 int pktlen = skb->len;
563
564 @@ -1918,9 +2017,18 @@
565 td_ptr = &(vptr->td_rings[qnum][index]);
566 tdinfo = &(vptr->td_infos[qnum][index]);
567
568 - td_ptr->tdesc1.TCPLS = TCPLS_NORMAL;
569 - td_ptr->tdesc1.TCR = TCR0_TIC;
570 - td_ptr->td_buf[0].queue = 0;
571 + td_ptr->tdesc0 = 0x00000000UL; /* BE */
572 + td_ptr->tdesc1 = 0x00000000UL; /* BE */
573 +
574 + /* td_ptr->tdesc1.TCPLS = TCPLS_NORMAL; BE */
575 + td_ptr->tdesc1 &= cpu_to_le32(0xfcffffffUL); /* BE */
576 + td_ptr->tdesc1 |= cpu_to_le32(((u32)TCPLS_NORMAL) << 24); /* BE */
577 +
578 + /* td_ptr->tdesc1.TCR = TCR0_TIC; BE */
579 + td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_TIC); /* BE */
580 +
581 + /* td_ptr->td_buf[0].queue = 0; BE */
582 + td_ptr->td_buf[0].ltwo &= cpu_to_le32(~BE_QUEUE_ENABLE); /* BE */
583
584 /*
585 * Pad short frames.
586 @@ -1932,20 +2040,35 @@
587 memset(tdinfo->buf + skb->len, 0, ETH_ZLEN - skb->len);
588 tdinfo->skb = skb;
589 tdinfo->skb_dma[0] = tdinfo->buf_dma;
590 - td_ptr->tdesc0.pktsize = pktlen;
591 + /* td_ptr->tdesc0.pktsize = pktlen; */
592 + td_ptr->tdesc0 &= cpu_to_le32(0xc000ffffUL); /* BE */
593 + lbufsz = pktlen; /* Assign, and make sure it's unsigned 32 bits - BE */
594 + lbufsz = lbufsz << 16; /* BE - shift over */
595 + td_ptr->tdesc0 |= cpu_to_le32(lbufsz); /* BE */
596 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
597 - td_ptr->td_buf[0].pa_high = 0;
598 - td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
599 + /* td_ptr->td_buf[0].pa_high = 0; */
600 + /* td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize; */
601 + td_ptr->td_buf[0].ltwo = cpu_to_le32(lbufsz); /* BE */
602 tdinfo->nskb_dma = 1;
603 - td_ptr->tdesc1.CMDZ = 2;
604 + /* td_ptr->tdesc1.CMDZ = 2; */
605 + td_ptr->tdesc1 &= cpu_to_le32(0x0fffffffUL); /* BE */
606 + td_ptr->tdesc1 |= cpu_to_le32(((u32)0x2) << 28); /* BE */
607 } else
608 #ifdef VELOCITY_ZERO_COPY_SUPPORT
609 + /*
610 + * BE - NOTE on the VELOCITY_ZERO_COPY_SUPPORT:
611 + * This block of code has NOT been patched up for BE support, as
612 + * it is certainly broken -- if it compiles at all. Since the BE
613 + * fixes depend on the broken code, attempts to convert to BE support
614 + * would almost certainly confuse more than help.
615 + */
616 if (skb_shinfo(skb)->nr_frags > 0) {
617 int nfrags = skb_shinfo(skb)->nr_frags;
618 tdinfo->skb = skb;
619 if (nfrags > 6) {
620 memcpy(tdinfo->buf, skb->data, skb->len);
621 tdinfo->skb_dma[0] = tdinfo->buf_dma;
622 + /* BE: Er, exactly what value are we assigning in this next line? */
623 td_ptr->tdesc0.pktsize =
624 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
625 td_ptr->td_buf[0].pa_high = 0;
626 @@ -1962,6 +2085,7 @@
627 /* FIXME: support 48bit DMA later */
628 td_ptr->td_buf[i].pa_low = cpu_to_le32(tdinfo->skb_dma);
629 td_ptr->td_buf[i].pa_high = 0;
630 + /* BE: This next line can't be right: */
631 td_ptr->td_buf[i].bufsize = skb->len->skb->data_len;
632
633 for (i = 0; i < nfrags; i++) {
634 @@ -1979,7 +2103,7 @@
635 }
636
637 } else
638 -#endif
639 +#endif /* (broken) VELOCITY_ZERO_COPY_SUPPORT */
640 {
641 /*
642 * Map the linear network buffer into PCI space and
643 @@ -1987,19 +2111,30 @@
644 */
645 tdinfo->skb = skb;
646 tdinfo->skb_dma[0] = pci_map_single(vptr->pdev, skb->data, pktlen, PCI_DMA_TODEVICE);
647 - td_ptr->tdesc0.pktsize = pktlen;
648 + /* td_ptr->tdesc0.pktsize = pktlen; BE */
649 + td_ptr->tdesc0 &= cpu_to_le32(0xc000ffffUL); /* BE */
650 + lbufsz = pktlen; /* Assign, and make sure it's unsigned 32 bits - BE */
651 + lbufsz = lbufsz << 16; /* BE */
652 + td_ptr->tdesc0 |= cpu_to_le32(lbufsz); /* BE */
653 td_ptr->td_buf[0].pa_low = cpu_to_le32(tdinfo->skb_dma[0]);
654 - td_ptr->td_buf[0].pa_high = 0;
655 - td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize;
656 + /* td_ptr->td_buf[0].pa_high = 0; BE */
657 + /* td_ptr->td_buf[0].bufsize = td_ptr->tdesc0.pktsize; BE */
658 + td_ptr->td_buf[0].ltwo = cpu_to_le32(lbufsz); /* BE */
659 +
660 tdinfo->nskb_dma = 1;
661 - td_ptr->tdesc1.CMDZ = 2;
662 + /* td_ptr->tdesc1.CMDZ = 2; BE */
663 + td_ptr->tdesc1 &= cpu_to_le32(0x0fffffffUL); /* BE */
664 + td_ptr->tdesc1 |= cpu_to_le32(((u32)0x2) << 28);/* BE */
665 }
666
667 if (vptr->flags & VELOCITY_FLAGS_TAGGING) {
668 - td_ptr->tdesc1.pqinf.VID = (vptr->options.vid & 0xfff);
669 - td_ptr->tdesc1.pqinf.priority = 0;
670 - td_ptr->tdesc1.pqinf.CFI = 0;
671 - td_ptr->tdesc1.TCR |= TCR0_VETAG;
672 + /* td_ptr->tdesc1.pqinf.priority = 0; BE */
673 + /* td_ptr->tdesc1.pqinf.CFI = 0; BE */
674 + td_ptr->tdesc1 &= cpu_to_le32(0xFFFF0000UL); /* BE */
675 + /* td_ptr->tdesc1.pqinf.VID = (vptr->options.vid & 0xfff); BE */
676 + td_ptr->tdesc1 |= cpu_to_le32((vptr->options.vid & 0xfff)); /* BE */
677 + /* td_ptr->tdesc1.TCR |= TCR0_VETAG; BE */
678 + td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_VETAG); /* BE */
679 }
680
681 /*
682 @@ -2009,26 +2144,34 @@
683 && (skb->ip_summed == CHECKSUM_PARTIAL)) {
684 struct iphdr *ip = skb->nh.iph;
685 if (ip->protocol == IPPROTO_TCP)
686 - td_ptr->tdesc1.TCR |= TCR0_TCPCK;
687 + /* td_ptr->tdesc1.TCR |= TCR0_TCPCK; BE */
688 + td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_TCPCK); /* BE */
689 else if (ip->protocol == IPPROTO_UDP)
690 - td_ptr->tdesc1.TCR |= (TCR0_UDPCK);
691 - td_ptr->tdesc1.TCR |= TCR0_IPCK;
692 - }
693 + /* td_ptr->tdesc1.TCR |= (TCR0_UDPCK); BE */
694 + td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_UDPCK); /* BE */
695 + /* td_ptr->tdesc1.TCR |= TCR0_IPCK; BE */
696 + td_ptr->tdesc1 |= cpu_to_le32(BE_TCR_IPCK); /* BE */
697 + }
698 {
699
700 int prev = index - 1;
701
702 if (prev < 0)
703 prev = vptr->options.numtx - 1;
704 - td_ptr->tdesc0.owner = OWNED_BY_NIC;
705 + /* td_ptr->tdesc0.owner = OWNED_BY_NIC; BE */
706 + td_ptr->tdesc0 |= cpu_to_le32(BE_OWNED_BY_NIC); /* BE */
707 vptr->td_used[qnum]++;
708 vptr->td_curr[qnum] = (index + 1) % vptr->options.numtx;
709
710 if (AVAIL_TD(vptr, qnum) < 1)
711 netif_stop_queue(dev);
712
713 - td_ptr = &(vptr->td_rings[qnum][prev]);
714 - td_ptr->td_buf[0].queue = 1;
715 + td_ptr = &(vptr->td_rings[qnum][prev]);
716 + /* td_ptr->td_buf[0].queue = 1; BE */
717 + td_ptr->td_buf[0].ltwo |= cpu_to_le32(BE_QUEUE_ENABLE); /* BE */
718 + if (vdebug&2) printk(KERN_NOTICE "velocity_xmit: (%s) len=%d idx=%d tdesc0=0x%x tdesc1=0x%x ltwo=0x%x\n",
719 + (pktlen<ETH_ZLEN) ? "short" : "normal", pktlen, index,
720 + td_ptr->tdesc0, td_ptr->tdesc1, td_ptr->td_buf[0].ltwo);
721 mac_tx_queue_wake(vptr->mac_regs, qnum);
722 }
723 dev->trans_start = jiffies;
724 @@ -2054,7 +2197,7 @@
725 u32 isr_status;
726 int max_count = 0;
727
728 -
729 + HAIL("velocity_intr");
730 spin_lock(&vptr->lock);
731 isr_status = mac_read_isr(vptr->mac_regs);
732
733 @@ -2073,7 +2216,10 @@
734
735 while (isr_status != 0) {
736 mac_write_isr(vptr->mac_regs, isr_status);
737 - if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI)))
738 + HAILS("velocity_intr",isr_status);
739 + /* MJW - velocity_error is ALWAYS called; need to mask off some other flags */
740 + /* if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI))) */
741 + if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI | ISR_PTX0I | ISR_ISR0)))
742 velocity_error(vptr, isr_status);
743 if (isr_status & (ISR_PRXI | ISR_PPRXI))
744 max_count += velocity_rx_srv(vptr, isr_status);
745 @@ -2111,6 +2257,7 @@
746 int i;
747 struct dev_mc_list *mclist;
748
749 + HAIL("velocity_set_multi");
750 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
751 writel(0xffffffff, &regs->MARCAM[0]);
752 writel(0xffffffff, &regs->MARCAM[4]);
753 @@ -2154,6 +2301,7 @@
754 {
755 struct velocity_info *vptr = netdev_priv(dev);
756
757 + HAIL("net_device_stats");
758 /* If the hardware is down, don't touch MII */
759 if(!netif_running(dev))
760 return &vptr->stats;
761 @@ -2198,6 +2346,7 @@
762 struct velocity_info *vptr = netdev_priv(dev);
763 int ret;
764
765 + HAIL("velocity_ioctl");
766 /* If we are asked for information and the device is power
767 saving then we need to bring the device back up to talk to it */
768
769 @@ -2416,6 +2565,7 @@
770 {
771 u16 ww;
772
773 + HAIL("velocity_mii_read");
774 /*
775 * Disable MIICR_MAUTO, so that mii addr can be set normally
776 */
777 @@ -2452,6 +2602,7 @@
778 {
779 u16 ww;
780
781 + HAIL("velocity_mii_write");
782 /*
783 * Disable MIICR_MAUTO, so that mii addr can be set normally
784 */
785 Index: linux-2.6.20-rc3/drivers/net/via-velocity.h
786 ===================================================================
787 --- linux-2.6.20-rc3.orig/drivers/net/via-velocity.h 2006-11-29 21:57:37.000000000 +0000
788 +++ linux-2.6.20-rc3/drivers/net/via-velocity.h 2007-01-02 10:30:36.265114211 +0000
789 @@ -196,64 +196,70 @@
790 * Receive descriptor
791 */
792
793 -struct rdesc0 {
794 - u16 RSR; /* Receive status */
795 - u16 len:14; /* Received packet length */
796 - u16 reserved:1;
797 - u16 owner:1; /* Who owns this buffer ? */
798 -};
799 -
800 -struct rdesc1 {
801 - u16 PQTAG;
802 - u8 CSM;
803 - u8 IPKT;
804 -};
805 +//struct rdesc0 {
806 +// u16 RSR; /* Receive status */
807 +// u16 len:14; /* Received packet length */
808 +// u16 reserved:1;
809 +// u16 owner:1; /* Who owns this buffer ? */
810 +//};
811 +
812 +//struct rdesc1 {
813 +// u16 PQTAG;
814 +// u8 CSM;
815 +// u8 IPKT;
816 +//};
817
818 struct rx_desc {
819 - struct rdesc0 rdesc0;
820 - struct rdesc1 rdesc1;
821 +// struct rdesc0 rdesc0;
822 +// struct rdesc1 rdesc1;
823 + u32 rdesc0;
824 + u32 rdesc1;
825 u32 pa_low; /* Low 32 bit PCI address */
826 - u16 pa_high; /* Next 16 bit PCI address (48 total) */
827 - u16 len:15; /* Frame size */
828 - u16 inten:1; /* Enable interrupt */
829 +// u16 pa_high; /* Next 16 bit PCI address (48 total) */
830 +// u16 len:15; /* Frame size */
831 +// u16 inten:1; /* Enable interrupt */
832 + u32 ltwo;
833 } __attribute__ ((__packed__));
834
835 /*
836 * Transmit descriptor
837 */
838
839 -struct tdesc0 {
840 - u16 TSR; /* Transmit status register */
841 - u16 pktsize:14; /* Size of frame */
842 - u16 reserved:1;
843 - u16 owner:1; /* Who owns the buffer */
844 -};
845 -
846 -struct pqinf { /* Priority queue info */
847 - u16 VID:12;
848 - u16 CFI:1;
849 - u16 priority:3;
850 -} __attribute__ ((__packed__));
851 -
852 -struct tdesc1 {
853 - struct pqinf pqinf;
854 - u8 TCR;
855 - u8 TCPLS:2;
856 - u8 reserved:2;
857 - u8 CMDZ:4;
858 -} __attribute__ ((__packed__));
859 +//struct tdesc0 {
860 +// u16 TSR; /* Transmit status register */
861 +// u16 pktsize:14; /* Size of frame */
862 +// u16 reserved:1;
863 +// u16 owner:1; /* Who owns the buffer */
864 +//};
865 +
866 +//struct pqinf { /* Priority queue info */
867 +// u16 VID:12;
868 +// u16 CFI:1;
869 +// u16 priority:3;
870 +//} __attribute__ ((__packed__));
871 +
872 +//struct tdesc1 {
873 +// struct pqinf pqinf;
874 +// u8 TCR;
875 +// u8 TCPLS:2;
876 +// u8 reserved:2;
877 +// u8 CMDZ:4;
878 +//} __attribute__ ((__packed__));
879
880 struct td_buf {
881 u32 pa_low;
882 - u16 pa_high;
883 - u16 bufsize:14;
884 - u16 reserved:1;
885 - u16 queue:1;
886 +// u16 pa_high;
887 +// u16 bufsize:14;
888 +// u16 reserved:1;
889 +// u16 queue:1;
890 + u32 ltwo;
891 } __attribute__ ((__packed__));
892
893 struct tx_desc {
894 - struct tdesc0 tdesc0;
895 - struct tdesc1 tdesc1;
896 +// struct tdesc0 tdesc0;
897 +// struct tdesc1 tdesc1;
898 + u32 tdesc0;
899 + u32 tdesc1;
900 struct td_buf td_buf[7];
901 };
902
903 @@ -279,6 +285,16 @@
904 OWNED_BY_NIC = 1
905 };
906
907 +/* Constants added for the BE fixes */
908 +#define BE_OWNED_BY_NIC 0x80000000UL
909 +#define BE_INT_ENABLE 0x80000000UL
910 +#define BE_QUEUE_ENABLE 0x80000000UL
911 +#define BE_TCR_TIC 0x00800000UL
912 +#define BE_TCR_VETAG 0x00200000UL
913 +#define BE_TCR_TCPCK 0x00040000UL
914 +#define BE_TCR_UDPCK 0x00080000UL
915 +#define BE_TCR_IPCK 0x00100000UL
916 +
917
918 /*
919 * MAC registers and macros.
920 @@ -1698,6 +1714,7 @@
921 };
922
923 struct velocity_opt {
924 + int velo_debug; /* debug flag */
925 int numrx; /* Number of RX descriptors */
926 int numtx; /* Number of TX descriptors */
927 enum speed_opt spd_dpx; /* Media link mode */
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