target/linux/cns3xxx/patches-3.0/049-cns3xxx_smp_support.patch

   1 --- a/arch/arm/mach-cns3xxx/Makefile
   2 +++ b/arch/arm/mach-cns3xxx/Makefile
   3 @@ -1,3 +1,6 @@
   4  obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
   5  obj-$(CONFIG_PCI)                      += pcie.o
   6  obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o
   7 +obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
   8 +obj-$(CONFIG_HOTPLUG_CPU)              += hotplug.o
   9 +obj-$(CONFIG_LOCAL_TIMERS)             += localtimer.o
  10 --- /dev/null
  11 +++ b/arch/arm/mach-cns3xxx/headsmp.S
  12 @@ -0,0 +1,42 @@
  13 +/*
  14 + *  linux/arch/arm/mach-cns3xxx/headsmp.S
  15 + *
  16 + *  Cloned from linux/arch/arm/plat-versatile/headsmp.S
  17 + *
  18 + *  Copyright (c) 2003 ARM Limited
  19 + *  All Rights Reserved
  20 + *
  21 + * This program is free software; you can redistribute it and/or modify
  22 + * it under the terms of the GNU General Public License version 2 as
  23 + * published by the Free Software Foundation.
  24 + */
  25 +#include <linux/linkage.h>
  26 +#include <linux/init.h>
  27 +
  28 +       __INIT
  29 +
  30 +/*
  31 + * CNS3XXX specific entry point for secondary CPUs.  This provides
  32 + * a "holding pen" into which all secondary cores are held until we're
  33 + * ready for them to initialise.
  34 + */
  35 +ENTRY(cns3xxx_secondary_startup)
  36 +       mrc     p15, 0, r0, c0, c0, 5
  37 +       and     r0, r0, #15
  38 +       adr     r4, 1f
  39 +       ldmia   r4, {r5, r6}
  40 +       sub     r4, r4, r5
  41 +       add     r6, r6, r4
  42 +pen:   ldr     r7, [r6]
  43 +       cmp     r7, r0
  44 +       bne     pen
  45 +
  46 +       /*
  47 +        * we've been released from the holding pen: secondary_stack
  48 +        * should now contain the SVC stack for this core
  49 +        */
  50 +       b       secondary_startup
  51 +
  52 +       .align
  53 +1:     .long   .
  54 +       .long   pen_release
  55 --- /dev/null
  56 +++ b/arch/arm/mach-cns3xxx/hotplug.c
  57 @@ -0,0 +1,130 @@
  58 +/* linux arch/arm/mach-cns3xxx/hotplug.c
  59 + *
  60 + *  Cloned from linux/arch/arm/mach-realview/hotplug.c
  61 + *
  62 + *  Copyright (C) 2002 ARM Ltd.
  63 + *  All Rights Reserved
  64 + *
  65 + * This program is free software; you can redistribute it and/or modify
  66 + * it under the terms of the GNU General Public License version 2 as
  67 + * published by the Free Software Foundation.
  68 +*/
  69 +
  70 +#include <linux/kernel.h>
  71 +#include <linux/errno.h>
  72 +#include <linux/smp.h>
  73 +
  74 +#include <asm/cacheflush.h>
  75 +
  76 +extern volatile int pen_release;
  77 +
  78 +static inline void cpu_enter_lowpower(void)
  79 +{
  80 +       unsigned int v;
  81 +
  82 +       flush_cache_all();
  83 +       asm volatile(
  84 +       "       mcr     p15, 0, %1, c7, c5, 0\n"
  85 +       "       mcr     p15, 0, %1, c7, c10, 4\n"
  86 +       /*
  87 +        * Turn off coherency
  88 +        */
  89 +       "       mrc     p15, 0, %0, c1, c0, 1\n"
  90 +       "       bic     %0, %0, %3\n"
  91 +       "       mcr     p15, 0, %0, c1, c0, 1\n"
  92 +       "       mrc     p15, 0, %0, c1, c0, 0\n"
  93 +       "       bic     %0, %0, %2\n"
  94 +       "       mcr     p15, 0, %0, c1, c0, 0\n"
  95 +         : "=&r" (v)
  96 +         : "r" (0), "Ir" (CR_C), "Ir" (0x40)
  97 +         : "cc");
  98 +}
  99 +
 100 +static inline void cpu_leave_lowpower(void)
 101 +{
 102 +       unsigned int v;
 103 +
 104 +       asm volatile(
 105 +       "mrc    p15, 0, %0, c1, c0, 0\n"
 106 +       "       orr     %0, %0, %1\n"
 107 +       "       mcr     p15, 0, %0, c1, c0, 0\n"
 108 +       "       mrc     p15, 0, %0, c1, c0, 1\n"
 109 +       "       orr     %0, %0, %2\n"
 110 +       "       mcr     p15, 0, %0, c1, c0, 1\n"
 111 +         : "=&r" (v)
 112 +         : "Ir" (CR_C), "Ir" (0x40)
 113 +         : "cc");
 114 +}
 115 +
 116 +static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 117 +{
 118 +       /*
 119 +        * there is no power-control hardware on this platform, so all
 120 +        * we can do is put the core into WFI; this is safe as the calling
 121 +        * code will have already disabled interrupts
 122 +        */
 123 +       for (;;) {
 124 +               /*
 125 +                * here's the WFI
 126 +                */
 127 +               asm(".word      0xe320f003\n"
 128 +                   :
 129 +                   :
 130 +                   : "memory", "cc");
 131 +
 132 +               if (pen_release == cpu) {
 133 +                       /*
 134 +                        * OK, proper wakeup, we're done
 135 +                        */
 136 +                       break;
 137 +               }
 138 +
 139 +               /*
 140 +                * Getting here, means that we have come out of WFI without
 141 +                * having been woken up - this shouldn't happen
 142 +                *
 143 +                * Just note it happening - when we're woken, we can report
 144 +                * its occurrence.
 145 +                */
 146 +               (*spurious)++;
 147 +       }
 148 +}
 149 +
 150 +int platform_cpu_kill(unsigned int cpu)
 151 +{
 152 +       return 1;
 153 +}
 154 +
 155 +/*
 156 + * platform-specific code to shutdown a CPU
 157 + *
 158 + * Called with IRQs disabled
 159 + */
 160 +void platform_cpu_die(unsigned int cpu)
 161 +{
 162 +       int spurious = 0;
 163 +
 164 +       /*
 165 +        * we're ready for shutdown now, so do it
 166 +        */
 167 +       cpu_enter_lowpower();
 168 +       platform_do_lowpower(cpu, &spurious);
 169 +
 170 +       /*
 171 +        * bring this CPU back into the world of cache
 172 +        * coherency, and then restore interrupts
 173 +        */
 174 +       cpu_leave_lowpower();
 175 +
 176 +       if (spurious)
 177 +               pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 178 +}
 179 +
 180 +int platform_cpu_disable(unsigned int cpu)
 181 +{
 182 +       /*
 183 +        * we don't allow CPU 0 to be shutdown (it is still too special
 184 +        * e.g. clock tick interrupts)
 185 +        */
 186 +       return cpu == 0 ? -EPERM : 0;
 187 +}
 188 --- a/arch/arm/mach-cns3xxx/Kconfig
 189 +++ b/arch/arm/mach-cns3xxx/Kconfig
 190 @@ -3,6 +3,7 @@ menu "CNS3XXX platform type"
 191
 192  config MACH_CNS3420VB
 193         bool "Support for CNS3420 Validation Board"
 194 +       select HAVE_ARM_SCU if SMP
 195         select MIGHT_HAVE_PCI
 196         help
 197           Include support for the Cavium Networks CNS3420 MPCore Platform
 198 --- /dev/null
 199 +++ b/arch/arm/mach-cns3xxx/localtimer.c
 200 @@ -0,0 +1,26 @@
 201 +/* linux/arch/arm/mach-cns3xxx/localtimer.c
 202 + *
 203 + * Cloned from linux/arch/arm/mach-realview/localtimer.c
 204 + *
 205 + *  Copyright (C) 2002 ARM Ltd.
 206 + *  All Rights Reserved
 207 + *
 208 + * This program is free software; you can redistribute it and/or modify
 209 + * it under the terms of the GNU General Public License version 2 as
 210 + * published by the Free Software Foundation.
 211 +*/
 212 +
 213 +#include <linux/clockchips.h>
 214 +
 215 +#include <asm/irq.h>
 216 +#include <asm/localtimer.h>
 217 +
 218 +/*
 219 + * Setup the local clock events for a CPU.
 220 + */
 221 +int __cpuinit local_timer_setup(struct clock_event_device *evt)
 222 +{
 223 +       evt->irq = IRQ_LOCALTIMER;
 224 +       twd_timer_setup(evt);
 225 +       return 0;
 226 +}
 227 --- /dev/null
 228 +++ b/arch/arm/mach-cns3xxx/platsmp.c
 229 @@ -0,0 +1,175 @@
 230 +/* linux/arch/arm/mach-cns3xxx/platsmp.c
 231 + *
 232 + * Copyright 2011 Gateworks Corporation
 233 + *                Chris Lang <clang@gateworks.com>
 234 + * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
 235 + *
 236 + *  Copyright (C) 2002 ARM Ltd.
 237 + *  All Rights Reserved
 238 + *
 239 + * This program is free software; you can redistribute it and/or modify
 240 + * it under the terms of the GNU General Public License version 2 as
 241 + * published by the Free Software Foundation.
 242 +*/
 243 +
 244 +#include <linux/init.h>
 245 +#include <linux/errno.h>
 246 +#include <linux/delay.h>
 247 +#include <linux/device.h>
 248 +#include <linux/jiffies.h>
 249 +#include <linux/smp.h>
 250 +#include <linux/io.h>
 251 +
 252 +#include <asm/cacheflush.h>
 253 +#include <asm/hardware/gic.h>
 254 +#include <asm/smp_scu.h>
 255 +#include <asm/unified.h>
 256 +
 257 +#include <mach/hardware.h>
 258 +#include <mach/cns3xxx.h>
 259 +
 260 +extern void cns3xxx_secondary_startup(void);
 261 +
 262 +/*
 263 + * control for which core is the next to come out of the secondary
 264 + * boot "holding pen"
 265 + */
 266 +
 267 +volatile int __cpuinitdata pen_release = -1;
 268 +
 269 +/*
 270 + * Write pen_release in a way that is guaranteed to be visible to all
 271 + * observers, irrespective of whether they're taking part in coherency
 272 + * or not.  This is necessary for the hotplug code to work reliably.
 273 + */
 274 +static void write_pen_release(int val)
 275 +{
 276 +       pen_release = val;
 277 +       smp_wmb();
 278 +       __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 279 +       outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 280 +}
 281 +
 282 +static void __iomem *scu_base_addr(void)
 283 +{
 284 +       return (void __iomem *)(CNS3XXX_TC11MP_SCU_BASE_VIRT);
 285 +}
 286 +
 287 +static DEFINE_SPINLOCK(boot_lock);
 288 +
 289 +void __cpuinit platform_secondary_init(unsigned int cpu)
 290 +{
 291 +       /*
 292 +        * if any interrupts are already enabled for the primary
 293 +        * core (e.g. timer irq), then they will not have been enabled
 294 +        * for us: do so
 295 +        */
 296 +       gic_secondary_init(0);
 297 +
 298 +       /*
 299 +        * let the primary processor know we're out of the
 300 +        * pen, then head off into the C entry point
 301 +        */
 302 +       write_pen_release(-1);
 303 +
 304 +       /*
 305 +        * Synchronise with the boot thread.
 306 +        */
 307 +       spin_lock(&boot_lock);
 308 +       spin_unlock(&boot_lock);
 309 +}
 310 +
 311 +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 312 +{
 313 +       unsigned long timeout;
 314 +
 315 +       /*
 316 +        * Set synchronisation state between this boot processor
 317 +        * and the secondary one
 318 +        */
 319 +       spin_lock(&boot_lock);
 320 +
 321 +       /*
 322 +        * The secondary processor is waiting to be released from
 323 +        * the holding pen - release it, then wait for it to flag
 324 +        * that it has been released by resetting pen_release.
 325 +        *
 326 +        * Note that "pen_release" is the hardware CPU ID, whereas
 327 +        * "cpu" is Linux's internal ID.
 328 +        */
 329 +       write_pen_release(cpu);
 330 +
 331 +       /*
 332 +        * Send the secondary CPU a soft interrupt, thereby causing
 333 +        * the boot monitor to read the system wide flags register,
 334 +        * and branch to the address found there.
 335 +        */
 336 +       gic_raise_softirq(cpumask_of(cpu), 1);
 337 +
 338 +       timeout = jiffies + (1 * HZ);
 339 +       while (time_before(jiffies, timeout)) {
 340 +               smp_rmb();
 341 +               if (pen_release == -1)
 342 +                       break;
 343 +
 344 +               udelay(10);
 345 +       }
 346 +
 347 +       /*
 348 +        * now the secondary core is starting up let it run its
 349 +        * calibrations, then wait for it to finish
 350 +        */
 351 +       spin_unlock(&boot_lock);
 352 +
 353 +       return pen_release != -1 ? -ENOSYS : 0;
 354 +}
 355 +
 356 +/*
 357 + * Initialise the CPU possible map early - this describes the CPUs
 358 + * which may be present or become present in the system.
 359 + */
 360 +
 361 +void __init smp_init_cpus(void)
 362 +{
 363 +       void __iomem *scu_base = scu_base_addr();
 364 +       unsigned int i, ncores;
 365 +
 366 +       ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 367 +
 368 +       /* sanity check */
 369 +       if (ncores > NR_CPUS) {
 370 +               printk(KERN_WARNING
 371 +                      "cns3xxx: no. of cores (%d) greater than configured "
 372 +                      "maximum of %d - clipping\n",
 373 +                      ncores, NR_CPUS);
 374 +               ncores = NR_CPUS;
 375 +       }
 376 +
 377 +       for (i = 0; i < ncores; i++)
 378 +               set_cpu_possible(i, true);
 379 +
 380 +       set_smp_cross_call(gic_raise_softirq);
 381 +}
 382 +
 383 +void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 384 +{
 385 +       int i;
 386 +
 387 +       /*
 388 +        * Initialise the present map, which describes the set of CPUs
 389 +        * actually populated at the present time.
 390 +        */
 391 +       for (i = 0; i < max_cpus; i++)
 392 +               set_cpu_present(i, true);
 393 +
 394 +       scu_enable(scu_base_addr());
 395 +
 396 +       /*
 397 +        * Write the address of secondary startup into the
 398 +        * system-wide flags register. The boot monitor waits
 399 +        * until it receives a soft interrupt, and then the
 400 +        * secondary CPU branches to this address.
 401 +        */
 402 +       __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
 403 +                       (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
 404 +}
 405 --- a/arch/arm/Kconfig
 406 +++ b/arch/arm/Kconfig
 407 @@ -1313,7 +1313,7 @@ config SMP
 408         depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
 409                  MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
 410                  ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
 411 -                ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
 412 +                ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_CNS3XXX
 413         select USE_GENERIC_SMP_HELPERS
 414         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
 415         help