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[openwrt.git] / target / linux / ixp4xx / patches-2.6.25 / 200-npe_driver.patch
1 Index: linux-2.6.25.1/drivers/net/arm/Kconfig
2 ===================================================================
3 --- linux-2.6.25.1.orig/drivers/net/arm/Kconfig
4 +++ linux-2.6.25.1/drivers/net/arm/Kconfig
5 @@ -47,3 +47,11 @@ config EP93XX_ETH
6 help
7 This is a driver for the ethernet hardware included in EP93xx CPUs.
8 Say Y if you are building a kernel for EP93xx based devices.
9 +
10 +config IXP4XX_ETH
11 + tristate "Intel IXP4xx Ethernet support"
12 + depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR
13 + select MII
14 + help
15 + Say Y here if you want to use built-in Ethernet ports
16 + on IXP4xx processor.
17 Index: linux-2.6.25.1/drivers/net/arm/Makefile
18 ===================================================================
19 --- linux-2.6.25.1.orig/drivers/net/arm/Makefile
20 +++ linux-2.6.25.1/drivers/net/arm/Makefile
21 @@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3) += ether3.o
22 obj-$(CONFIG_ARM_ETHER1) += ether1.o
23 obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
24 obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
25 +obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o
26 Index: linux-2.6.25.1/drivers/net/arm/ixp4xx_eth.c
27 ===================================================================
28 --- /dev/null
29 +++ linux-2.6.25.1/drivers/net/arm/ixp4xx_eth.c
30 @@ -0,0 +1,1265 @@
31 +/*
32 + * Intel IXP4xx Ethernet driver for Linux
33 + *
34 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
35 + *
36 + * This program is free software; you can redistribute it and/or modify it
37 + * under the terms of version 2 of the GNU General Public License
38 + * as published by the Free Software Foundation.
39 + *
40 + * Ethernet port config (0x00 is not present on IXP42X):
41 + *
42 + * logical port 0x00 0x10 0x20
43 + * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
44 + * physical PortId 2 0 1
45 + * TX queue 23 24 25
46 + * RX-free queue 26 27 28
47 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
48 + *
49 + *
50 + * Queue entries:
51 + * bits 0 -> 1 - NPE ID (RX and TX-done)
52 + * bits 0 -> 2 - priority (TX, per 802.1D)
53 + * bits 3 -> 4 - port ID (user-set?)
54 + * bits 5 -> 31 - physical descriptor address
55 + */
56 +
57 +#include <linux/delay.h>
58 +#include <linux/dma-mapping.h>
59 +#include <linux/dmapool.h>
60 +#include <linux/etherdevice.h>
61 +#include <linux/io.h>
62 +#include <linux/kernel.h>
63 +#include <linux/mii.h>
64 +#include <linux/platform_device.h>
65 +#include <asm/arch/npe.h>
66 +#include <asm/arch/qmgr.h>
67 +
68 +#define DEBUG_QUEUES 0
69 +#define DEBUG_DESC 0
70 +#define DEBUG_RX 0
71 +#define DEBUG_TX 0
72 +#define DEBUG_PKT_BYTES 0
73 +#define DEBUG_MDIO 0
74 +#define DEBUG_CLOSE 0
75 +
76 +#define DRV_NAME "ixp4xx_eth"
77 +
78 +#define MAX_NPES 3
79 +
80 +#define RX_DESCS 64 /* also length of all RX queues */
81 +#define TX_DESCS 16 /* also length of all TX queues */
82 +#define TXDONE_QUEUE_LEN 64 /* dwords */
83 +
84 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
85 +#define REGS_SIZE 0x1000
86 +#define MAX_MRU 1536 /* 0x600 */
87 +#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
88 +
89 +#define NAPI_WEIGHT 16
90 +#define MDIO_INTERVAL (3 * HZ)
91 +#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
92 +#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
93 +#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
94 +
95 +#define NPE_ID(port_id) ((port_id) >> 4)
96 +#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
97 +#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
98 +#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
99 +#define TXDONE_QUEUE 31
100 +
101 +/* TX Control Registers */
102 +#define TX_CNTRL0_TX_EN 0x01
103 +#define TX_CNTRL0_HALFDUPLEX 0x02
104 +#define TX_CNTRL0_RETRY 0x04
105 +#define TX_CNTRL0_PAD_EN 0x08
106 +#define TX_CNTRL0_APPEND_FCS 0x10
107 +#define TX_CNTRL0_2DEFER 0x20
108 +#define TX_CNTRL0_RMII 0x40 /* reduced MII */
109 +#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
110 +
111 +/* RX Control Registers */
112 +#define RX_CNTRL0_RX_EN 0x01
113 +#define RX_CNTRL0_PADSTRIP_EN 0x02
114 +#define RX_CNTRL0_SEND_FCS 0x04
115 +#define RX_CNTRL0_PAUSE_EN 0x08
116 +#define RX_CNTRL0_LOOP_EN 0x10
117 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
118 +#define RX_CNTRL0_RX_RUNT_EN 0x40
119 +#define RX_CNTRL0_BCAST_DIS 0x80
120 +#define RX_CNTRL1_DEFER_EN 0x01
121 +
122 +/* Core Control Register */
123 +#define CORE_RESET 0x01
124 +#define CORE_RX_FIFO_FLUSH 0x02
125 +#define CORE_TX_FIFO_FLUSH 0x04
126 +#define CORE_SEND_JAM 0x08
127 +#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
128 +
129 +#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
130 + TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
131 + TX_CNTRL0_2DEFER)
132 +#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
133 +#define DEFAULT_CORE_CNTRL CORE_MDC_EN
134 +
135 +
136 +/* NPE message codes */
137 +#define NPE_GETSTATUS 0x00
138 +#define NPE_EDB_SETPORTADDRESS 0x01
139 +#define NPE_EDB_GETMACADDRESSDATABASE 0x02
140 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
141 +#define NPE_GETSTATS 0x04
142 +#define NPE_RESETSTATS 0x05
143 +#define NPE_SETMAXFRAMELENGTHS 0x06
144 +#define NPE_VLAN_SETRXTAGMODE 0x07
145 +#define NPE_VLAN_SETDEFAULTRXVID 0x08
146 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
147 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
148 +#define NPE_VLAN_SETRXQOSENTRY 0x0B
149 +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
150 +#define NPE_STP_SETBLOCKINGSTATE 0x0D
151 +#define NPE_FW_SETFIREWALLMODE 0x0E
152 +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
153 +#define NPE_PC_SETAPMACTABLE 0x11
154 +#define NPE_SETLOOPBACK_MODE 0x12
155 +#define NPE_PC_SETBSSIDTABLE 0x13
156 +#define NPE_ADDRESS_FILTER_CONFIG 0x14
157 +#define NPE_APPENDFCSCONFIG 0x15
158 +#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
159 +#define NPE_MAC_RECOVERY_START 0x17
160 +
161 +
162 +#ifdef __ARMEB__
163 +typedef struct sk_buff buffer_t;
164 +#define free_buffer dev_kfree_skb
165 +#define free_buffer_irq dev_kfree_skb_irq
166 +#else
167 +typedef void buffer_t;
168 +#define free_buffer kfree
169 +#define free_buffer_irq kfree
170 +#endif
171 +
172 +struct eth_regs {
173 + u32 tx_control[2], __res1[2]; /* 000 */
174 + u32 rx_control[2], __res2[2]; /* 010 */
175 + u32 random_seed, __res3[3]; /* 020 */
176 + u32 partial_empty_threshold, __res4; /* 030 */
177 + u32 partial_full_threshold, __res5; /* 038 */
178 + u32 tx_start_bytes, __res6[3]; /* 040 */
179 + u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
180 + u32 tx_2part_deferral[2], __res8[2]; /* 060 */
181 + u32 slot_time, __res9[3]; /* 070 */
182 + u32 mdio_command[4]; /* 080 */
183 + u32 mdio_status[4]; /* 090 */
184 + u32 mcast_mask[6], __res10[2]; /* 0A0 */
185 + u32 mcast_addr[6], __res11[2]; /* 0C0 */
186 + u32 int_clock_threshold, __res12[3]; /* 0E0 */
187 + u32 hw_addr[6], __res13[61]; /* 0F0 */
188 + u32 core_control; /* 1FC */
189 +};
190 +
191 +struct port {
192 + struct resource *mem_res;
193 + struct eth_regs __iomem *regs;
194 + struct npe *npe;
195 + struct net_device *netdev;
196 + struct napi_struct napi;
197 + struct net_device_stats stat;
198 + struct mii_if_info mii;
199 + struct delayed_work mdio_thread;
200 + struct eth_plat_info *plat;
201 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
202 + struct desc *desc_tab; /* coherent */
203 + u32 desc_tab_phys;
204 + int id; /* logical port ID */
205 + u16 mii_bmcr;
206 +};
207 +
208 +/* NPE message structure */
209 +struct msg {
210 +#ifdef __ARMEB__
211 + u8 cmd, eth_id, byte2, byte3;
212 + u8 byte4, byte5, byte6, byte7;
213 +#else
214 + u8 byte3, byte2, eth_id, cmd;
215 + u8 byte7, byte6, byte5, byte4;
216 +#endif
217 +};
218 +
219 +/* Ethernet packet descriptor */
220 +struct desc {
221 + u32 next; /* pointer to next buffer, unused */
222 +
223 +#ifdef __ARMEB__
224 + u16 buf_len; /* buffer length */
225 + u16 pkt_len; /* packet length */
226 + u32 data; /* pointer to data buffer in RAM */
227 + u8 dest_id;
228 + u8 src_id;
229 + u16 flags;
230 + u8 qos;
231 + u8 padlen;
232 + u16 vlan_tci;
233 +#else
234 + u16 pkt_len; /* packet length */
235 + u16 buf_len; /* buffer length */
236 + u32 data; /* pointer to data buffer in RAM */
237 + u16 flags;
238 + u8 src_id;
239 + u8 dest_id;
240 + u16 vlan_tci;
241 + u8 padlen;
242 + u8 qos;
243 +#endif
244 +
245 +#ifdef __ARMEB__
246 + u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
247 + u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
248 + u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
249 +#else
250 + u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
251 + u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
252 + u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
253 +#endif
254 +};
255 +
256 +
257 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
258 + (n) * sizeof(struct desc))
259 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
260 +
261 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
262 + ((n) + RX_DESCS) * sizeof(struct desc))
263 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
264 +
265 +#ifndef __ARMEB__
266 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
267 +{
268 + int i;
269 + for (i = 0; i < cnt; i++)
270 + dest[i] = swab32(src[i]);
271 +}
272 +#endif
273 +
274 +static spinlock_t mdio_lock;
275 +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
276 +static int ports_open;
277 +static struct port *npe_port_tab[MAX_NPES];
278 +static struct dma_pool *dma_pool;
279 +
280 +
281 +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
282 + int write, u16 cmd)
283 +{
284 + int cycles = 0;
285 +
286 + if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
287 + printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
288 + return 0;
289 + }
290 +
291 + if (write) {
292 + __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
293 + __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
294 + }
295 + __raw_writel(((phy_id << 5) | location) & 0xFF,
296 + &mdio_regs->mdio_command[2]);
297 + __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
298 + &mdio_regs->mdio_command[3]);
299 +
300 + while ((cycles < MAX_MDIO_RETRIES) &&
301 + (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
302 + udelay(1);
303 + cycles++;
304 + }
305 +
306 + if (cycles == MAX_MDIO_RETRIES) {
307 + printk(KERN_ERR "%s: MII write failed\n", dev->name);
308 + return 0;
309 + }
310 +
311 +#if DEBUG_MDIO
312 + printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
313 + cycles);
314 +#endif
315 +
316 + if (write)
317 + return 0;
318 +
319 + if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
320 + printk(KERN_ERR "%s: MII read failed\n", dev->name);
321 + return 0;
322 + }
323 +
324 + return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
325 + (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
326 +}
327 +
328 +static int mdio_read(struct net_device *dev, int phy_id, int location)
329 +{
330 + unsigned long flags;
331 + u16 val;
332 +
333 + spin_lock_irqsave(&mdio_lock, flags);
334 + val = mdio_cmd(dev, phy_id, location, 0, 0);
335 + spin_unlock_irqrestore(&mdio_lock, flags);
336 + return val;
337 +}
338 +
339 +static void mdio_write(struct net_device *dev, int phy_id, int location,
340 + int val)
341 +{
342 + unsigned long flags;
343 +
344 + spin_lock_irqsave(&mdio_lock, flags);
345 + mdio_cmd(dev, phy_id, location, 1, val);
346 + spin_unlock_irqrestore(&mdio_lock, flags);
347 +}
348 +
349 +static void phy_reset(struct net_device *dev, int phy_id)
350 +{
351 + struct port *port = netdev_priv(dev);
352 + int cycles = 0;
353 +
354 + mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
355 +
356 + while (cycles < MAX_MII_RESET_RETRIES) {
357 + if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
358 +#if DEBUG_MDIO
359 + printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
360 + dev->name, cycles);
361 +#endif
362 + return;
363 + }
364 + udelay(1);
365 + cycles++;
366 + }
367 +
368 + printk(KERN_ERR "%s: MII reset failed\n", dev->name);
369 +}
370 +
371 +static void eth_set_duplex(struct port *port)
372 +{
373 + if (port->mii.full_duplex)
374 + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
375 + &port->regs->tx_control[0]);
376 + else
377 + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
378 + &port->regs->tx_control[0]);
379 +}
380 +
381 +
382 +static void phy_check_media(struct port *port, int init)
383 +{
384 + if (mii_check_media(&port->mii, 1, init))
385 + eth_set_duplex(port);
386 + if (port->mii.force_media) { /* mii_check_media() doesn't work */
387 + struct net_device *dev = port->netdev;
388 + int cur_link = mii_link_ok(&port->mii);
389 + int prev_link = netif_carrier_ok(dev);
390 +
391 + if (!prev_link && cur_link) {
392 + printk(KERN_INFO "%s: link up\n", dev->name);
393 + netif_carrier_on(dev);
394 + } else if (prev_link && !cur_link) {
395 + printk(KERN_INFO "%s: link down\n", dev->name);
396 + netif_carrier_off(dev);
397 + }
398 + }
399 +}
400 +
401 +
402 +static void mdio_thread(struct work_struct *work)
403 +{
404 + struct port *port = container_of(work, struct port, mdio_thread.work);
405 +
406 + phy_check_media(port, 0);
407 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
408 +}
409 +
410 +
411 +static inline void debug_pkt(struct net_device *dev, const char *func,
412 + u8 *data, int len)
413 +{
414 +#if DEBUG_PKT_BYTES
415 + int i;
416 +
417 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
418 + for (i = 0; i < len; i++) {
419 + if (i >= DEBUG_PKT_BYTES)
420 + break;
421 + printk("%s%02X",
422 + ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
423 + data[i]);
424 + }
425 + printk("\n");
426 +#endif
427 +}
428 +
429 +
430 +static inline void debug_desc(u32 phys, struct desc *desc)
431 +{
432 +#if DEBUG_DESC
433 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
434 + " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
435 + phys, desc->next, desc->buf_len, desc->pkt_len,
436 + desc->data, desc->dest_id, desc->src_id, desc->flags,
437 + desc->qos, desc->padlen, desc->vlan_tci,
438 + desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
439 + desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
440 + desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
441 + desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
442 +#endif
443 +}
444 +
445 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
446 +{
447 +#if DEBUG_QUEUES
448 + static struct {
449 + int queue;
450 + char *name;
451 + } names[] = {
452 + { TX_QUEUE(0x10), "TX#0 " },
453 + { TX_QUEUE(0x20), "TX#1 " },
454 + { TX_QUEUE(0x00), "TX#2 " },
455 + { RXFREE_QUEUE(0x10), "RX-free#0 " },
456 + { RXFREE_QUEUE(0x20), "RX-free#1 " },
457 + { RXFREE_QUEUE(0x00), "RX-free#2 " },
458 + { TXDONE_QUEUE, "TX-done " },
459 + };
460 + int i;
461 +
462 + for (i = 0; i < ARRAY_SIZE(names); i++)
463 + if (names[i].queue == queue)
464 + break;
465 +
466 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
467 + i < ARRAY_SIZE(names) ? names[i].name : "",
468 + is_get ? "->" : "<-", phys);
469 +#endif
470 +}
471 +
472 +static inline u32 queue_get_entry(unsigned int queue)
473 +{
474 + u32 phys = qmgr_get_entry(queue);
475 + debug_queue(queue, 1, phys);
476 + return phys;
477 +}
478 +
479 +static inline int queue_get_desc(unsigned int queue, struct port *port,
480 + int is_tx)
481 +{
482 + u32 phys, tab_phys, n_desc;
483 + struct desc *tab;
484 +
485 + if (!(phys = queue_get_entry(queue)))
486 + return -1;
487 +
488 + phys &= ~0x1F; /* mask out non-address bits */
489 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
490 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
491 + n_desc = (phys - tab_phys) / sizeof(struct desc);
492 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
493 + debug_desc(phys, &tab[n_desc]);
494 + BUG_ON(tab[n_desc].next);
495 + return n_desc;
496 +}
497 +
498 +static inline void queue_put_desc(unsigned int queue, u32 phys,
499 + struct desc *desc)
500 +{
501 + debug_queue(queue, 0, phys);
502 + debug_desc(phys, desc);
503 + BUG_ON(phys & 0x1F);
504 + qmgr_put_entry(queue, phys);
505 + BUG_ON(qmgr_stat_overflow(queue));
506 +}
507 +
508 +
509 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
510 +{
511 +#ifdef __ARMEB__
512 + dma_unmap_single(&port->netdev->dev, desc->data,
513 + desc->buf_len, DMA_TO_DEVICE);
514 +#else
515 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
516 + ALIGN((desc->data & 3) + desc->buf_len, 4),
517 + DMA_TO_DEVICE);
518 +#endif
519 +}
520 +
521 +
522 +static void eth_rx_irq(void *pdev)
523 +{
524 + struct net_device *dev = pdev;
525 + struct port *port = netdev_priv(dev);
526 +
527 +#if DEBUG_RX
528 + printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
529 +#endif
530 + qmgr_disable_irq(port->plat->rxq);
531 + netif_rx_schedule(dev, &port->napi);
532 +}
533 +
534 +static int eth_poll(struct napi_struct *napi, int budget)
535 +{
536 + struct port *port = container_of(napi, struct port, napi);
537 + struct net_device *dev = port->netdev;
538 + unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
539 + int received = 0;
540 +
541 +#if DEBUG_RX
542 + printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
543 +#endif
544 +
545 + while (received < budget) {
546 + struct sk_buff *skb;
547 + struct desc *desc;
548 + int n;
549 +#ifdef __ARMEB__
550 + struct sk_buff *temp;
551 + u32 phys;
552 +#endif
553 +
554 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
555 + received = 0; /* No packet received */
556 +#if DEBUG_RX
557 + printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
558 + dev->name);
559 +#endif
560 + netif_rx_complete(dev, napi);
561 + qmgr_enable_irq(rxq);
562 + if (!qmgr_stat_empty(rxq) &&
563 + netif_rx_reschedule(dev, napi)) {
564 +#if DEBUG_RX
565 + printk(KERN_DEBUG "%s: eth_poll"
566 + " netif_rx_reschedule successed\n",
567 + dev->name);
568 +#endif
569 + qmgr_disable_irq(rxq);
570 + continue;
571 + }
572 +#if DEBUG_RX
573 + printk(KERN_DEBUG "%s: eth_poll all done\n",
574 + dev->name);
575 +#endif
576 + return 0; /* all work done */
577 + }
578 +
579 + desc = rx_desc_ptr(port, n);
580 +
581 +#ifdef __ARMEB__
582 + if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
583 + phys = dma_map_single(&dev->dev, skb->data,
584 + RX_BUFF_SIZE, DMA_FROM_DEVICE);
585 + if (dma_mapping_error(phys)) {
586 + dev_kfree_skb(skb);
587 + skb = NULL;
588 + }
589 + }
590 +#else
591 + skb = netdev_alloc_skb(dev,
592 + ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
593 +#endif
594 +
595 + if (!skb) {
596 + port->stat.rx_dropped++;
597 + /* put the desc back on RX-ready queue */
598 + desc->buf_len = MAX_MRU;
599 + desc->pkt_len = 0;
600 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
601 + continue;
602 + }
603 +
604 + /* process received frame */
605 +#ifdef __ARMEB__
606 + temp = skb;
607 + skb = port->rx_buff_tab[n];
608 + dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
609 + RX_BUFF_SIZE, DMA_FROM_DEVICE);
610 +#else
611 + dma_sync_single(&dev->dev, desc->data - NET_IP_ALIGN,
612 + RX_BUFF_SIZE, DMA_FROM_DEVICE);
613 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
614 + ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
615 +#endif
616 + skb_reserve(skb, NET_IP_ALIGN);
617 + skb_put(skb, desc->pkt_len);
618 +
619 + debug_pkt(dev, "eth_poll", skb->data, skb->len);
620 +
621 + skb->protocol = eth_type_trans(skb, dev);
622 + dev->last_rx = jiffies;
623 + port->stat.rx_packets++;
624 + port->stat.rx_bytes += skb->len;
625 + netif_receive_skb(skb);
626 +
627 + /* put the new buffer on RX-free queue */
628 +#ifdef __ARMEB__
629 + port->rx_buff_tab[n] = temp;
630 + desc->data = phys + NET_IP_ALIGN;
631 +#endif
632 + desc->buf_len = MAX_MRU;
633 + desc->pkt_len = 0;
634 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
635 + received++;
636 + }
637 +
638 +#if DEBUG_RX
639 + printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
640 +#endif
641 + return received; /* not all work done */
642 +}
643 +
644 +
645 +static void eth_txdone_irq(void *unused)
646 +{
647 + u32 phys;
648 +
649 +#if DEBUG_TX
650 + printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
651 +#endif
652 + while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
653 + u32 npe_id, n_desc;
654 + struct port *port;
655 + struct desc *desc;
656 + int start;
657 +
658 + npe_id = phys & 3;
659 + BUG_ON(npe_id >= MAX_NPES);
660 + port = npe_port_tab[npe_id];
661 + BUG_ON(!port);
662 + phys &= ~0x1F; /* mask out non-address bits */
663 + n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
664 + BUG_ON(n_desc >= TX_DESCS);
665 + desc = tx_desc_ptr(port, n_desc);
666 + debug_desc(phys, desc);
667 +
668 + if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
669 + port->stat.tx_packets++;
670 + port->stat.tx_bytes += desc->pkt_len;
671 +
672 + dma_unmap_tx(port, desc);
673 +#if DEBUG_TX
674 + printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
675 + port->netdev->name, port->tx_buff_tab[n_desc]);
676 +#endif
677 + free_buffer_irq(port->tx_buff_tab[n_desc]);
678 + port->tx_buff_tab[n_desc] = NULL;
679 + }
680 +
681 + start = qmgr_stat_empty(port->plat->txreadyq);
682 + queue_put_desc(port->plat->txreadyq, phys, desc);
683 + if (start) {
684 +#if DEBUG_TX
685 + printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
686 + port->netdev->name);
687 +#endif
688 + netif_wake_queue(port->netdev);
689 + }
690 + }
691 +}
692 +
693 +static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
694 +{
695 + struct port *port = netdev_priv(dev);
696 + unsigned int txreadyq = port->plat->txreadyq;
697 + int len, offset, bytes, n;
698 + void *mem;
699 + u32 phys;
700 + struct desc *desc;
701 +
702 +#if DEBUG_TX
703 + printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
704 +#endif
705 +
706 + if (unlikely(skb->len > MAX_MRU)) {
707 + dev_kfree_skb(skb);
708 + port->stat.tx_errors++;
709 + return NETDEV_TX_OK;
710 + }
711 +
712 + debug_pkt(dev, "eth_xmit", skb->data, skb->len);
713 +
714 + len = skb->len;
715 +#ifdef __ARMEB__
716 + offset = 0; /* no need to keep alignment */
717 + bytes = len;
718 + mem = skb->data;
719 +#else
720 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
721 + bytes = ALIGN(offset + len, 4);
722 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
723 + dev_kfree_skb(skb);
724 + port->stat.tx_dropped++;
725 + return NETDEV_TX_OK;
726 + }
727 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
728 + dev_kfree_skb(skb);
729 +#endif
730 +
731 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
732 + if (dma_mapping_error(phys)) {
733 +#ifdef __ARMEB__
734 + dev_kfree_skb(skb);
735 +#else
736 + kfree(mem);
737 +#endif
738 + port->stat.tx_dropped++;
739 + return NETDEV_TX_OK;
740 + }
741 +
742 + n = queue_get_desc(txreadyq, port, 1);
743 + BUG_ON(n < 0);
744 + desc = tx_desc_ptr(port, n);
745 +
746 +#ifdef __ARMEB__
747 + port->tx_buff_tab[n] = skb;
748 +#else
749 + port->tx_buff_tab[n] = mem;
750 +#endif
751 + desc->data = phys + offset;
752 + desc->buf_len = desc->pkt_len = len;
753 +
754 + /* NPE firmware pads short frames with zeros internally */
755 + wmb();
756 + queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
757 + dev->trans_start = jiffies;
758 +
759 + if (qmgr_stat_empty(txreadyq)) {
760 +#if DEBUG_TX
761 + printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
762 +#endif
763 + netif_stop_queue(dev);
764 + /* we could miss TX ready interrupt */
765 + if (!qmgr_stat_empty(txreadyq)) {
766 +#if DEBUG_TX
767 + printk(KERN_DEBUG "%s: eth_xmit ready again\n",
768 + dev->name);
769 +#endif
770 + netif_wake_queue(dev);
771 + }
772 + }
773 +
774 +#if DEBUG_TX
775 + printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
776 +#endif
777 + return NETDEV_TX_OK;
778 +}
779 +
780 +
781 +static struct net_device_stats *eth_stats(struct net_device *dev)
782 +{
783 + struct port *port = netdev_priv(dev);
784 + return &port->stat;
785 +}
786 +
787 +static void eth_set_mcast_list(struct net_device *dev)
788 +{
789 + struct port *port = netdev_priv(dev);
790 + struct dev_mc_list *mclist = dev->mc_list;
791 + u8 diffs[ETH_ALEN], *addr;
792 + int cnt = dev->mc_count, i;
793 +
794 + if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
795 + __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
796 + &port->regs->rx_control[0]);
797 + return;
798 + }
799 +
800 + memset(diffs, 0, ETH_ALEN);
801 + addr = mclist->dmi_addr; /* first MAC address */
802 +
803 + while (--cnt && (mclist = mclist->next))
804 + for (i = 0; i < ETH_ALEN; i++)
805 + diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
806 +
807 + for (i = 0; i < ETH_ALEN; i++) {
808 + __raw_writel(addr[i], &port->regs->mcast_addr[i]);
809 + __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
810 + }
811 +
812 + __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
813 + &port->regs->rx_control[0]);
814 +}
815 +
816 +
817 +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
818 +{
819 + struct port *port = netdev_priv(dev);
820 + unsigned int duplex_chg;
821 + int err;
822 +
823 + if (!netif_running(dev))
824 + return -EINVAL;
825 + err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
826 + if (duplex_chg)
827 + eth_set_duplex(port);
828 + return err;
829 +}
830 +
831 +
832 +static int request_queues(struct port *port)
833 +{
834 + int err;
835 +
836 + err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
837 + if (err)
838 + return err;
839 +
840 + err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
841 + if (err)
842 + goto rel_rxfree;
843 +
844 + err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
845 + if (err)
846 + goto rel_rx;
847 +
848 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
849 + if (err)
850 + goto rel_tx;
851 +
852 + /* TX-done queue handles skbs sent out by the NPEs */
853 + if (!ports_open) {
854 + err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
855 + if (err)
856 + goto rel_txready;
857 + }
858 + return 0;
859 +
860 +rel_txready:
861 + qmgr_release_queue(port->plat->txreadyq);
862 +rel_tx:
863 + qmgr_release_queue(TX_QUEUE(port->id));
864 +rel_rx:
865 + qmgr_release_queue(port->plat->rxq);
866 +rel_rxfree:
867 + qmgr_release_queue(RXFREE_QUEUE(port->id));
868 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
869 + port->netdev->name);
870 + return err;
871 +}
872 +
873 +static void release_queues(struct port *port)
874 +{
875 + qmgr_release_queue(RXFREE_QUEUE(port->id));
876 + qmgr_release_queue(port->plat->rxq);
877 + qmgr_release_queue(TX_QUEUE(port->id));
878 + qmgr_release_queue(port->plat->txreadyq);
879 +
880 + if (!ports_open)
881 + qmgr_release_queue(TXDONE_QUEUE);
882 +}
883 +
884 +static int init_queues(struct port *port)
885 +{
886 + int i;
887 +
888 + if (!ports_open)
889 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
890 + POOL_ALLOC_SIZE, 32, 0)))
891 + return -ENOMEM;
892 +
893 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
894 + &port->desc_tab_phys)))
895 + return -ENOMEM;
896 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
897 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
898 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
899 +
900 + /* Setup RX buffers */
901 + for (i = 0; i < RX_DESCS; i++) {
902 + struct desc *desc = rx_desc_ptr(port, i);
903 + buffer_t *buff; /* skb or kmalloc()ated memory */
904 + void *data;
905 +#ifdef __ARMEB__
906 + if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
907 + return -ENOMEM;
908 + data = buff->data;
909 +#else
910 + if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
911 + return -ENOMEM;
912 + data = buff;
913 +#endif
914 + desc->buf_len = MAX_MRU;
915 + desc->data = dma_map_single(&port->netdev->dev, data,
916 + RX_BUFF_SIZE, DMA_FROM_DEVICE);
917 + if (dma_mapping_error(desc->data)) {
918 + free_buffer(buff);
919 + return -EIO;
920 + }
921 + desc->data += NET_IP_ALIGN;
922 + port->rx_buff_tab[i] = buff;
923 + }
924 +
925 + return 0;
926 +}
927 +
928 +static void destroy_queues(struct port *port)
929 +{
930 + int i;
931 +
932 + if (port->desc_tab) {
933 + for (i = 0; i < RX_DESCS; i++) {
934 + struct desc *desc = rx_desc_ptr(port, i);
935 + buffer_t *buff = port->rx_buff_tab[i];
936 + if (buff) {
937 + dma_unmap_single(&port->netdev->dev,
938 + desc->data - NET_IP_ALIGN,
939 + RX_BUFF_SIZE, DMA_FROM_DEVICE);
940 + free_buffer(buff);
941 + }
942 + }
943 + for (i = 0; i < TX_DESCS; i++) {
944 + struct desc *desc = tx_desc_ptr(port, i);
945 + buffer_t *buff = port->tx_buff_tab[i];
946 + if (buff) {
947 + dma_unmap_tx(port, desc);
948 + free_buffer(buff);
949 + }
950 + }
951 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
952 + port->desc_tab = NULL;
953 + }
954 +
955 + if (!ports_open && dma_pool) {
956 + dma_pool_destroy(dma_pool);
957 + dma_pool = NULL;
958 + }
959 +}
960 +
961 +static int eth_open(struct net_device *dev)
962 +{
963 + struct port *port = netdev_priv(dev);
964 + struct npe *npe = port->npe;
965 + struct msg msg;
966 + int i, err;
967 +
968 + if (!npe_running(npe)) {
969 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
970 + if (err)
971 + return err;
972 +
973 + if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
974 + printk(KERN_ERR "%s: %s not responding\n", dev->name,
975 + npe_name(npe));
976 + return -EIO;
977 + }
978 + }
979 +
980 + mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
981 +
982 + memset(&msg, 0, sizeof(msg));
983 + msg.cmd = NPE_VLAN_SETRXQOSENTRY;
984 + msg.eth_id = port->id;
985 + msg.byte5 = port->plat->rxq | 0x80;
986 + msg.byte7 = port->plat->rxq << 4;
987 + for (i = 0; i < 8; i++) {
988 + msg.byte3 = i;
989 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
990 + return -EIO;
991 + }
992 +
993 + msg.cmd = NPE_EDB_SETPORTADDRESS;
994 + msg.eth_id = PHYSICAL_ID(port->id);
995 + msg.byte2 = dev->dev_addr[0];
996 + msg.byte3 = dev->dev_addr[1];
997 + msg.byte4 = dev->dev_addr[2];
998 + msg.byte5 = dev->dev_addr[3];
999 + msg.byte6 = dev->dev_addr[4];
1000 + msg.byte7 = dev->dev_addr[5];
1001 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1002 + return -EIO;
1003 +
1004 + memset(&msg, 0, sizeof(msg));
1005 + msg.cmd = NPE_FW_SETFIREWALLMODE;
1006 + msg.eth_id = port->id;
1007 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1008 + return -EIO;
1009 +
1010 + if ((err = request_queues(port)) != 0)
1011 + return err;
1012 +
1013 + if ((err = init_queues(port)) != 0) {
1014 + destroy_queues(port);
1015 + release_queues(port);
1016 + return err;
1017 + }
1018 +
1019 + for (i = 0; i < ETH_ALEN; i++)
1020 + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1021 + __raw_writel(0x08, &port->regs->random_seed);
1022 + __raw_writel(0x12, &port->regs->partial_empty_threshold);
1023 + __raw_writel(0x30, &port->regs->partial_full_threshold);
1024 + __raw_writel(0x08, &port->regs->tx_start_bytes);
1025 + __raw_writel(0x15, &port->regs->tx_deferral);
1026 + __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1027 + __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1028 + __raw_writel(0x80, &port->regs->slot_time);
1029 + __raw_writel(0x01, &port->regs->int_clock_threshold);
1030 +
1031 + /* Populate queues with buffers, no failure after this point */
1032 + for (i = 0; i < TX_DESCS; i++)
1033 + queue_put_desc(port->plat->txreadyq,
1034 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
1035 +
1036 + for (i = 0; i < RX_DESCS; i++)
1037 + queue_put_desc(RXFREE_QUEUE(port->id),
1038 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
1039 +
1040 + __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1041 + __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1042 + __raw_writel(0, &port->regs->rx_control[1]);
1043 + __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1044 +
1045 + napi_enable(&port->napi);
1046 + phy_check_media(port, 1);
1047 + eth_set_mcast_list(dev);
1048 + netif_start_queue(dev);
1049 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1050 +
1051 + qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1052 + eth_rx_irq, dev);
1053 + if (!ports_open) {
1054 + qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1055 + eth_txdone_irq, NULL);
1056 + qmgr_enable_irq(TXDONE_QUEUE);
1057 + }
1058 + ports_open++;
1059 + /* we may already have RX data, enables IRQ */
1060 + netif_rx_schedule(dev, &port->napi);
1061 + return 0;
1062 +}
1063 +
1064 +static int eth_close(struct net_device *dev)
1065 +{
1066 + struct port *port = netdev_priv(dev);
1067 + struct msg msg;
1068 + int buffs = RX_DESCS; /* allocated RX buffers */
1069 + int i;
1070 +
1071 + ports_open--;
1072 + qmgr_disable_irq(port->plat->rxq);
1073 + napi_disable(&port->napi);
1074 + netif_stop_queue(dev);
1075 +
1076 + while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1077 + buffs--;
1078 +
1079 + memset(&msg, 0, sizeof(msg));
1080 + msg.cmd = NPE_SETLOOPBACK_MODE;
1081 + msg.eth_id = port->id;
1082 + msg.byte3 = 1;
1083 + if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1084 + printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1085 +
1086 + i = 0;
1087 + do { /* drain RX buffers */
1088 + while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1089 + buffs--;
1090 + if (!buffs)
1091 + break;
1092 + if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1093 + /* we have to inject some packet */
1094 + struct desc *desc;
1095 + u32 phys;
1096 + int n = queue_get_desc(port->plat->txreadyq, port, 1);
1097 + BUG_ON(n < 0);
1098 + desc = tx_desc_ptr(port, n);
1099 + phys = tx_desc_phys(port, n);
1100 + desc->buf_len = desc->pkt_len = 1;
1101 + wmb();
1102 + queue_put_desc(TX_QUEUE(port->id), phys, desc);
1103 + }
1104 + udelay(1);
1105 + } while (++i < MAX_CLOSE_WAIT);
1106 +
1107 + if (buffs)
1108 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1109 + " left in NPE\n", dev->name, buffs);
1110 +#if DEBUG_CLOSE
1111 + if (!buffs)
1112 + printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1113 +#endif
1114 +
1115 + buffs = TX_DESCS;
1116 + while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1117 + buffs--; /* cancel TX */
1118 +
1119 + i = 0;
1120 + do {
1121 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1122 + buffs--;
1123 + if (!buffs)
1124 + break;
1125 + } while (++i < MAX_CLOSE_WAIT);
1126 +
1127 + if (buffs)
1128 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1129 + "left in NPE\n", dev->name, buffs);
1130 +#if DEBUG_CLOSE
1131 + if (!buffs)
1132 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1133 +#endif
1134 +
1135 + msg.byte3 = 0;
1136 + if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1137 + printk(KERN_CRIT "%s: unable to disable loopback\n",
1138 + dev->name);
1139 +
1140 + port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
1141 + ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
1142 + mdio_write(dev, port->plat->phy, MII_BMCR,
1143 + port->mii_bmcr | BMCR_PDOWN);
1144 +
1145 + if (!ports_open)
1146 + qmgr_disable_irq(TXDONE_QUEUE);
1147 + cancel_rearming_delayed_work(&port->mdio_thread);
1148 + destroy_queues(port);
1149 + release_queues(port);
1150 + return 0;
1151 +}
1152 +
1153 +static int __devinit eth_init_one(struct platform_device *pdev)
1154 +{
1155 + struct port *port;
1156 + struct net_device *dev;
1157 + struct eth_plat_info *plat = pdev->dev.platform_data;
1158 + u32 regs_phys;
1159 + int err;
1160 +
1161 + if (!(dev = alloc_etherdev(sizeof(struct port))))
1162 + return -ENOMEM;
1163 +
1164 + SET_NETDEV_DEV(dev, &pdev->dev);
1165 + port = netdev_priv(dev);
1166 + port->netdev = dev;
1167 + port->id = pdev->id;
1168 +
1169 + switch (port->id) {
1170 + case IXP4XX_ETH_NPEA:
1171 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1172 + regs_phys = IXP4XX_EthA_BASE_PHYS;
1173 + break;
1174 + case IXP4XX_ETH_NPEB:
1175 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1176 + regs_phys = IXP4XX_EthB_BASE_PHYS;
1177 + break;
1178 + case IXP4XX_ETH_NPEC:
1179 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1180 + regs_phys = IXP4XX_EthC_BASE_PHYS;
1181 + break;
1182 + default:
1183 + err = -ENOSYS;
1184 + goto err_free;
1185 + }
1186 +
1187 + dev->open = eth_open;
1188 + dev->hard_start_xmit = eth_xmit;
1189 + dev->stop = eth_close;
1190 + dev->get_stats = eth_stats;
1191 + dev->do_ioctl = eth_ioctl;
1192 + dev->set_multicast_list = eth_set_mcast_list;
1193 + dev->tx_queue_len = 100;
1194 +
1195 + netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1196 +
1197 + if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1198 + err = -EIO;
1199 + goto err_free;
1200 + }
1201 +
1202 + if (register_netdev(dev)) {
1203 + err = -EIO;
1204 + goto err_npe_rel;
1205 + }
1206 +
1207 + port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1208 + if (!port->mem_res) {
1209 + err = -EBUSY;
1210 + goto err_unreg;
1211 + }
1212 +
1213 + port->plat = plat;
1214 + npe_port_tab[NPE_ID(port->id)] = port;
1215 + memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1216 +
1217 + platform_set_drvdata(pdev, dev);
1218 +
1219 + __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1220 + &port->regs->core_control);
1221 + udelay(50);
1222 + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1223 + udelay(50);
1224 +
1225 + port->mii.dev = dev;
1226 + port->mii.mdio_read = mdio_read;
1227 + port->mii.mdio_write = mdio_write;
1228 + port->mii.phy_id = plat->phy;
1229 + port->mii.phy_id_mask = 0x1F;
1230 + port->mii.reg_num_mask = 0x1F;
1231 +
1232 + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1233 + npe_name(port->npe));
1234 +
1235 + phy_reset(dev, plat->phy);
1236 + port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
1237 + ~(BMCR_RESET | BMCR_PDOWN);
1238 + mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
1239 +
1240 + INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
1241 + return 0;
1242 +
1243 +err_unreg:
1244 + unregister_netdev(dev);
1245 +err_npe_rel:
1246 + npe_release(port->npe);
1247 +err_free:
1248 + free_netdev(dev);
1249 + return err;
1250 +}
1251 +
1252 +static int __devexit eth_remove_one(struct platform_device *pdev)
1253 +{
1254 + struct net_device *dev = platform_get_drvdata(pdev);
1255 + struct port *port = netdev_priv(dev);
1256 +
1257 + unregister_netdev(dev);
1258 + npe_port_tab[NPE_ID(port->id)] = NULL;
1259 + platform_set_drvdata(pdev, NULL);
1260 + npe_release(port->npe);
1261 + release_resource(port->mem_res);
1262 + free_netdev(dev);
1263 + return 0;
1264 +}
1265 +
1266 +static struct platform_driver drv = {
1267 + .driver.name = DRV_NAME,
1268 + .probe = eth_init_one,
1269 + .remove = eth_remove_one,
1270 +};
1271 +
1272 +static int __init eth_init_module(void)
1273 +{
1274 + if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
1275 + return -ENOSYS;
1276 +
1277 + /* All MII PHY accesses use NPE-B Ethernet registers */
1278 + spin_lock_init(&mdio_lock);
1279 + mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1280 + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
1281 +
1282 + return platform_driver_register(&drv);
1283 +}
1284 +
1285 +static void __exit eth_cleanup_module(void)
1286 +{
1287 + platform_driver_unregister(&drv);
1288 +}
1289 +
1290 +MODULE_AUTHOR("Krzysztof Halasa");
1291 +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1292 +MODULE_LICENSE("GPL v2");
1293 +MODULE_ALIAS("platform:ixp4xx_eth");
1294 +module_init(eth_init_module);
1295 +module_exit(eth_cleanup_module);
1296 Index: linux-2.6.25.1/arch/arm/mach-ixp4xx/ixp4xx_npe.c
1297 ===================================================================
1298 --- linux-2.6.25.1.orig/arch/arm/mach-ixp4xx/ixp4xx_npe.c
1299 +++ linux-2.6.25.1/arch/arm/mach-ixp4xx/ixp4xx_npe.c
1300 @@ -448,7 +448,9 @@ int npe_send_message(struct npe *npe, co
1301 return -ETIMEDOUT;
1302 }
1303
1304 +#if DEBUG_MSG > 1
1305 debug_msg(npe, "Sending a message took %i cycles\n", cycles);
1306 +#endif
1307 return 0;
1308 }
1309
1310 @@ -484,7 +486,9 @@ int npe_recv_message(struct npe *npe, vo
1311 return -ETIMEDOUT;
1312 }
1313
1314 +#if DEBUG_MSG > 1
1315 debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
1316 +#endif
1317 return 0;
1318 }
1319
1320 Index: linux-2.6.25.1/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
1321 ===================================================================
1322 --- linux-2.6.25.1.orig/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
1323 +++ linux-2.6.25.1/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
1324 @@ -184,6 +184,8 @@ void qmgr_release_queue(unsigned int que
1325 case 3: mask[0] = 0xFF; break;
1326 }
1327
1328 + mask[1] = mask[2] = mask[3] = 0;
1329 +
1330 while (addr--)
1331 shift_mask(mask);
1332
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