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52f5241511c1793587f3a217150d506a68bd3b62
[openwrt.git] / target / linux / brcm63xx / patches-2.6.32 / 240-spi.patch
1 Index: linux-2.6.32.13/arch/mips/bcm63xx/cpu.c
2 ===================================================================
3 --- linux-2.6.32.13.orig/arch/mips/bcm63xx/cpu.c 2010-05-27 21:34:54.000000000 -0400
4 +++ linux-2.6.32.13/arch/mips/bcm63xx/cpu.c 2010-05-27 21:48:23.000000000 -0400
5 @@ -55,6 +55,7 @@
6
7 static const int bcm96338_irqs[] = {
8 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
9 + [IRQ_SPI] = BCM_6338_SPI_IRQ,
10 [IRQ_UART0] = BCM_6338_UART0_IRQ,
11 [IRQ_DSL] = BCM_6338_DSL_IRQ,
12 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
13 @@ -127,6 +128,7 @@
14
15 static const int bcm96348_irqs[] = {
16 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
17 + [IRQ_SPI] = BCM_6348_SPI_IRQ,
18 [IRQ_UART0] = BCM_6348_UART0_IRQ,
19 [IRQ_DSL] = BCM_6348_DSL_IRQ,
20 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
21 @@ -169,6 +171,7 @@
22
23 static const int bcm96358_irqs[] = {
24 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
25 + [IRQ_SPI] = BCM_6358_SPI_IRQ,
26 [IRQ_UART0] = BCM_6358_UART0_IRQ,
27 [IRQ_DSL] = BCM_6358_DSL_IRQ,
28 [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
29 Index: linux-2.6.32.13/arch/mips/bcm63xx/dev-spi.c
30 ===================================================================
31 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
32 +++ linux-2.6.32.13/arch/mips/bcm63xx/dev-spi.c 2010-05-27 21:48:23.000000000 -0400
33 @@ -0,0 +1,60 @@
34 +/*
35 + * This file is subject to the terms and conditions of the GNU General Public
36 + * License. See the file "COPYING" in the main directory of this archive
37 + * for more details.
38 + *
39 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
40 + */
41 +
42 +#include <linux/init.h>
43 +#include <linux/kernel.h>
44 +#include <linux/platform_device.h>
45 +
46 +#include <bcm63xx_cpu.h>
47 +#include <bcm63xx_dev_spi.h>
48 +#include <bcm63xx_regs.h>
49 +
50 +static struct resource spi_resources[] = {
51 + {
52 + .start = -1, /* filled at runtime */
53 + .end = -1, /* filled at runtime */
54 + .flags = IORESOURCE_MEM,
55 + },
56 + {
57 + .start = -1, /* filled at runtime */
58 + .flags = IORESOURCE_IRQ,
59 + },
60 +};
61 +
62 +static struct bcm63xx_spi_pdata spi_pdata = {
63 + .bus_num = 0,
64 + .num_chipselect = 4,
65 + .speed_hz = 50000000, /* Fclk */
66 +};
67 +
68 +static struct platform_device bcm63xx_spi_device = {
69 + .name = "bcm63xx-spi",
70 + .id = 0,
71 + .num_resources = ARRAY_SIZE(spi_resources),
72 + .resource = spi_resources,
73 + .dev = {
74 + .platform_data = &spi_pdata,
75 + },
76 +};
77 +
78 +int __init bcm63xx_spi_register(void)
79 +{
80 + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
81 + spi_resources[0].end = spi_resources[0].start;
82 + spi_resources[0].end += RSET_SPI_SIZE - 1;
83 + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
84 +
85 + /* Fill in platform data */
86 + if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
87 + spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
88 +
89 + if (BCMCPU_IS_6358())
90 + spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
91 +
92 + return platform_device_register(&bcm63xx_spi_device);
93 +}
94 Index: linux-2.6.32.13/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
95 ===================================================================
96 --- linux-2.6.32.13.orig/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h 2010-05-27 21:44:19.000000000 -0400
97 +++ linux-2.6.32.13/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h 2010-05-27 21:48:23.000000000 -0400
98 @@ -108,6 +108,7 @@
99 #define RSET_WDT_SIZE 12
100 #define RSET_ENET_SIZE 2048
101 #define RSET_ENETDMA_SIZE 2048
102 +#define RSET_SPI_SIZE 256
103 #define RSET_UART_SIZE 24
104 #define RSET_UDC_SIZE 256
105 #define RSET_OHCI_SIZE 256
106 @@ -209,7 +210,7 @@
107 #define BCM_6358_WDT_BASE (0xfffe005c)
108 #define BCM_6358_UART0_BASE (0xfffe0100)
109 #define BCM_6358_GPIO_BASE (0xfffe0080)
110 -#define BCM_6358_SPI_BASE (0xdeadbeef)
111 +#define BCM_6358_SPI_BASE (0xfffe0800)
112 #define BCM_6358_UDC0_BASE (0xfffe0400)
113 #define BCM_6358_OHCI0_BASE (0xfffe1400)
114 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
115 @@ -428,6 +429,7 @@
116 */
117 enum bcm63xx_irq {
118 IRQ_TIMER = 0,
119 + IRQ_SPI,
120 IRQ_UART0,
121 IRQ_DSL,
122 IRQ_UDC0,
123 @@ -493,6 +495,7 @@
124 * 6348 irqs
125 */
126 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
127 +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
128 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
129 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
130 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
131 @@ -517,6 +520,7 @@
132 * 6358 irqs
133 */
134 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
135 +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
136 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
137 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
138 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
139 Index: linux-2.6.32.13/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
140 ===================================================================
141 --- linux-2.6.32.13.orig/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h 2010-05-27 21:34:54.000000000 -0400
142 +++ linux-2.6.32.13/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h 2010-05-27 21:48:23.000000000 -0400
143 @@ -769,5 +769,117 @@
144 #define DMIPSPLLCFG_N2_SHIFT 29
145 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
146
147 +/*************************************************************************
148 + * _REG relative to RSET_SPI
149 + *************************************************************************/
150 +
151 +/* BCM 6338 SPI core */
152 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
153 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02
154 +#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
155 +#define SPI_BCM_6338_SPI_INT_MASK 0x04
156 +#define SPI_BCM_6338_SPI_ST 0x05
157 +#define SPI_BCM_6338_SPI_CLK_CFG 0x06
158 +#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
159 +#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
160 +#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
161 +#define SPI_BCM_6338_SPI_MSG_CTL 0x40
162 +#define SPI_BCM_6338_SPI_MSG_DATA 0x41
163 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
164 +#define SPI_BCM_6338_SPI_RX_DATA 0x80
165 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
166 +
167 +/* BCM 6348 SPI core */
168 +#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
169 +#define SPI_BCM_6348_SPI_INT_STATUS 0x01
170 +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
171 +#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
172 +#define SPI_BCM_6348_SPI_CLK_CFG 0x05
173 +#define SPI_BCM_6348_SPI_ST 0x06
174 +#define SPI_BCM_6348_SPI_INT_MASK 0x07
175 +#define SPI_BCM_6348_SPI_RX_TAIL 0x08
176 +#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
177 +#define SPI_BCM_6348_SPI_MSG_DATA 0x40
178 +#define SPI_BCM_6348_SPI_MSG_CTL 0x42
179 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
180 +#define SPI_BCM_6348_SPI_RX_DATA 0x80
181 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
182 +
183 +/* BCM 6358 SPI core */
184 +#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
185 +
186 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02
187 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
188 +
189 +#define SPI_BCM_6358_SPI_RX_DATA 0x400
190 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
191 +
192 +#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
193 +
194 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702
195 +#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
196 +
197 +#define SPI_BCM_6358_SPI_INT_MASK 0x704
198 +
199 +#define SPI_BCM_6358_SPI_STATUS 0x705
200 +
201 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706
202 +
203 +#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
204 +#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
205 +#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
206 +
207 +/* Shared SPI definitions */
208 +
209 +/* Message configuration */
210 +#define SPI_FD_RW 0x00
211 +#define SPI_HD_W 0x01
212 +#define SPI_HD_R 0x02
213 +#define SPI_BYTE_CNT_SHIFT 0
214 +#define SPI_MSG_TYPE_SHIFT 14
215 +
216 +/* Command */
217 +#define SPI_CMD_NOOP 0x01
218 +#define SPI_CMD_SOFT_RESET 0x02
219 +#define SPI_CMD_HARD_RESET 0x04
220 +#define SPI_CMD_START_IMMEDIATE 0x08
221 +#define SPI_CMD_COMMAND_SHIFT 0
222 +#define SPI_CMD_COMMAND_MASK 0x000f
223 +#define SPI_CMD_DEVICE_ID_SHIFT 4
224 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
225 +#define SPI_CMD_ONE_BYTE_SHIFT 11
226 +#define SPI_CMD_ONE_WIRE_SHIFT 12
227 +#define SPI_DEV_ID_0 0
228 +#define SPI_DEV_ID_1 1
229 +#define SPI_DEV_ID_2 2
230 +#define SPI_DEV_ID_3 3
231 +
232 +/* Interrupt mask */
233 +#define SPI_INTR_CMD_DONE 0x01
234 +#define SPI_INTR_RX_OVERFLOW 0x02
235 +#define SPI_INTR_TX_UNDERFLOW 0x04
236 +#define SPI_INTR_TX_OVERFLOW 0x08
237 +#define SPI_INTR_RX_UNDERFLOW 0x10
238 +#define SPI_INTR_CLEAR_ALL 0x1f
239 +
240 +/* Status */
241 +#define SPI_RX_EMPTY 0x02
242 +#define SPI_CMD_BUSY 0x04
243 +#define SPI_SERIAL_BUSY 0x08
244 +
245 +/* Clock configuration */
246 +#define SPI_CLK_20MHZ 0x00
247 +#define SPI_CLK_0_391MHZ 0x01
248 +#define SPI_CLK_0_781MHZ 0x02 /* default */
249 +#define SPI_CLK_1_563MHZ 0x03
250 +#define SPI_CLK_3_125MHZ 0x04
251 +#define SPI_CLK_6_250MHZ 0x05
252 +#define SPI_CLK_12_50MHZ 0x06
253 +#define SPI_CLK_25MHZ 0x07
254 +#define SPI_CLK_MASK 0x07
255 +#define SPI_SSOFFTIME_MASK 0x38
256 +#define SPI_SSOFFTIME_SHIFT 3
257 +#define SPI_BYTE_SWAP 0x80
258 +
259 #endif /* BCM63XX_REGS_H_ */
260
261 Index: linux-2.6.32.13/drivers/spi/bcm63xx_spi.c
262 ===================================================================
263 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
264 +++ linux-2.6.32.13/drivers/spi/bcm63xx_spi.c 2010-05-27 21:48:23.000000000 -0400
265 @@ -0,0 +1,628 @@
266 +/*
267 + * Broadcom BCM63xx SPI controller support
268 + *
269 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
270 + *
271 + * This program is free software; you can redistribute it and/or
272 + * modify it under the terms of the GNU General Public License
273 + * as published by the Free Software Foundation; either version 2
274 + * of the License, or (at your option) any later version.
275 + *
276 + * This program is distributed in the hope that it will be useful,
277 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
278 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
279 + * GNU General Public License for more details.
280 + *
281 + * You should have received a copy of the GNU General Public License
282 + * along with this program; if not, write to the
283 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
284 + */
285 +
286 +#include <linux/kernel.h>
287 +#include <linux/init.h>
288 +#include <linux/clk.h>
289 +#include <linux/module.h>
290 +#include <linux/platform_device.h>
291 +#include <linux/delay.h>
292 +#include <linux/interrupt.h>
293 +#include <linux/spi/spi.h>
294 +#include <linux/spi/spi_bitbang.h>
295 +#include <linux/gpio.h>
296 +#include <linux/completion.h>
297 +#include <linux/err.h>
298 +
299 +#include <bcm63xx_io.h>
300 +#include <bcm63xx_regs.h>
301 +#include <bcm63xx_dev_spi.h>
302 +
303 +#define PFX KBUILD_MODNAME
304 +#define DRV_VER "0.1.2"
305 +
306 +enum bcm63xx_regs_spi {
307 + SPI_CMD,
308 + SPI_INT_STATUS,
309 + SPI_INT_MASK_ST,
310 + SPI_INT_MASK,
311 + SPI_ST,
312 + SPI_CLK_CFG,
313 + SPI_FILL_BYTE,
314 + SPI_MSG_TAIL,
315 + SPI_RX_TAIL,
316 + SPI_MSG_CTL,
317 + SPI_MSG_DATA,
318 + SPI_RX_DATA,
319 +};
320 +
321 +/*
322 + * register offsets
323 + */
324 +static const unsigned long bcm96338_regs_spi[] = {
325 + [SPI_CMD] = SPI_BCM_6338_SPI_CMD,
326 + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
327 + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
328 + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
329 + [SPI_ST] = SPI_BCM_6338_SPI_ST,
330 + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
331 + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
332 + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
333 + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
334 + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
335 + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
336 + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
337 +};
338 +
339 +static const unsigned long bcm96348_regs_spi[] = {
340 + [SPI_CMD] = SPI_BCM_6348_SPI_CMD,
341 + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
342 + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
343 + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
344 + [SPI_ST] = SPI_BCM_6348_SPI_ST,
345 + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
346 + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
347 + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
348 + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
349 + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
350 + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
351 + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
352 +};
353 +
354 +static const unsigned long bcm96358_regs_spi[] = {
355 + [SPI_CMD] = SPI_BCM_6358_SPI_CMD,
356 + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
357 + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
358 + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
359 + [SPI_ST] = SPI_BCM_6358_SPI_STATUS,
360 + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
361 + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
362 + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
363 + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
364 + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
365 + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
366 + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA,
367 +};
368 +
369 +
370 +#ifdef BCMCPU_RUNTIME_DETECT
371 +static const unsigned long *bcm63xx_regs_spi;
372 +
373 +static __init void bcm63xx_spi_regs_init(void)
374 +{
375 + if (BCMCPU_IS_6338())
376 + bcm63xx_regs_spi = bcm96338_regs_spi;
377 + if (BCMCPU_IS_6348())
378 + bcm63xx_regs_spi = bcm96348_regs_spi;
379 + if (BCMCPU_IS_6358())
380 + bcm63xx_regs_spi = bcm96358_regs_spi;
381 +}
382 +#else
383 +static __init void bcm63xx_spi_regs_init(void) { }
384 +#endif
385 +
386 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
387 +{
388 +#ifdef BCMCPU_RUNTIME_DETECT
389 + return bcm63xx_regs_spi[reg];
390 +#else
391 +#ifdef CONFIG_BCM63XX_CPU_6338
392 +switch (reg) {
393 + case SPI_CMD:
394 + return SPI_BCM_6338_SPI_CMD;
395 + case SPI_INT_STATUS:
396 + return SPI_BCM_6338_SPI_INT_STATUS;
397 + case SPI_INT_MASK_ST:
398 + return SPI_BCM_6338_SPI_MASK_INT_ST;
399 + case SPI_INT_MASK:
400 + return SPI_BCM_6338_SPI_INT_MASK;
401 + case SPI_ST:
402 + return SPI_BCM_6338_SPI_ST;
403 + case SPI_CLK_CFG:
404 + return SPI_BCM_6338_SPI_CLK_CFG;
405 + case SPI_FILL_BYTE:
406 + return SPI_BCM_6338_SPI_FILL_BYTE;
407 + case SPI_MSG_TAIL:
408 + return SPI_BCM_6338_SPI_MSG_TAIL;
409 + case SPI_RX_TAIL:
410 + return SPI_BCM_6338_SPI_RX_TAIL;
411 + case SPI_MSG_CTL:
412 + return SPI_BCM_6338_SPI_MSG_CTL;
413 + case SPI_MSG_DATA:
414 + return SPI_BCM_6338_SPI_MSG_DATA;
415 + case SPI_RX_DATA:
416 + return SPI_BCM_6338_SPI_RX_DATA;
417 +}
418 +#endif
419 +#ifdef CONFIG_BCM63XX_CPU_6348
420 +switch (reg) {
421 + case SPI_CMD:
422 + return SPI_BCM_6348_SPI_CMD;
423 + case SPI_INT_MASK_ST:
424 + return SPI_BCM_6348_SPI_MASK_INT_ST;
425 + case SPI_INT_MASK:
426 + return SPI_BCM_6348_SPI_INT_MASK;
427 + case SPI_INT_STATUS:
428 + return SPI_BCM_6348_SPI_INT_STATUS;
429 + case SPI_ST:
430 + return SPI_BCM_6348_SPI_ST;
431 + case SPI_CLK_CFG:
432 + return SPI_BCM_6348_SPI_CLK_CFG;
433 + case SPI_FILL_BYTE:
434 + return SPI_BCM_6348_SPI_FILL_BYTE;
435 + case SPI_MSG_TAIL:
436 + return SPI_BCM_6348_SPI_MSG_TAIL;
437 + case SPI_RX_TAIL:
438 + return SPI_BCM_6348_SPI_RX_TAIL;
439 + case SPI_MSG_CTL:
440 + return SPI_BCM_6348_SPI_MSG_CTL;
441 + case SPI_MSG_DATA:
442 + return SPI_BCM_6348_SPI_MSG_DATA;
443 + case SPI_RX_DATA:
444 + return SPI_BCM_6348_SPI_RX_DATA;
445 +}
446 +#endif
447 +#ifdef CONFIG_BCM63XX_CPU_6358
448 +switch (reg) {
449 + case SPI_CMD:
450 + return SPI_BCM_6358_SPI_CMD;
451 + case SPI_INT_STATUS:
452 + return SPI_BCM_6358_SPI_INT_STATUS;
453 + case SPI_INT_MASK_ST:
454 + return SPI_BCM_6358_SPI_MASK_INT_ST;
455 + case SPI_INT_MASK:
456 + return SPI_BCM_6358_SPI_INT_MASK;
457 + case SPI_ST:
458 + return SPI_BCM_6358_SPI_STATUS;
459 + case SPI_CLK_CFG:
460 + return SPI_BCM_6358_SPI_CLK_CFG;
461 + case SPI_FILL_BYTE:
462 + return SPI_BCM_6358_SPI_FILL_BYTE;
463 + case SPI_MSG_TAIL:
464 + return SPI_BCM_6358_SPI_MSG_TAIL;
465 + case SPI_RX_TAIL:
466 + return SPI_BCM_6358_SPI_RX_TAIL;
467 + case SPI_MSG_CTL:
468 + return SPI_BCM_6358_MSG_CTL;
469 + case SPI_MSG_DATA:
470 + return SPI_BCM_6358_SPI_MSG_DATA;
471 + case SPI_RX_DATA:
472 + return SPI_BCM_6358_SPI_RX_DATA;
473 +}
474 +#endif
475 +#endif
476 + return 0;
477 +}
478 +
479 +/*
480 + * helpers for the SPI register sets
481 + */
482 +#define bcm_spi_readb(b,o) bcm_readb((b) + bcm63xx_spireg(o))
483 +#define bcm_spi_readw(b,o) bcm_readw((b) + bcm63xx_spireg(o))
484 +#define bcm_spi_writeb(v,b,o) bcm_writeb((v), (b) + bcm63xx_spireg(o))
485 +#define bcm_spi_writew(v,b,o) bcm_writew((v), (b) + bcm63xx_spireg(o))
486 +
487 +struct bcm63xx_spi {
488 + /* bitbang has to be first */
489 + struct spi_bitbang bitbang;
490 + struct completion done;
491 +
492 + void __iomem *regs;
493 + int irq;
494 +
495 + /* Platform data */
496 + u32 speed_hz;
497 + unsigned fifo_size;
498 +
499 + /* Data buffers */
500 + const unsigned char *tx_ptr;
501 + unsigned char *rx_ptr;
502 + int remaining_bytes;
503 +
504 + struct clk *clk;
505 + struct resource *ioarea;
506 + struct platform_device *pdev;
507 +};
508 +
509 +static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on)
510 +{
511 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
512 + u16 val;
513 +
514 + val = bcm_spi_readw(bs->regs, SPI_CMD);
515 + if (is_on == BITBANG_CS_INACTIVE)
516 + val |= SPI_CMD_NOOP;
517 + else if (is_on == BITBANG_CS_ACTIVE)
518 + val |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
519 +
520 + bcm_spi_writew(val, bs->regs, SPI_CMD);
521 +}
522 +
523 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
524 + struct spi_transfer *t)
525 +{
526 + u8 bits_per_word;
527 + u8 clk_cfg;
528 + u32 hz;
529 + unsigned int div;
530 +
531 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
532 +
533 + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
534 + hz = (t) ? t->speed_hz : spi->max_speed_hz;
535 + if (bits_per_word != 8) {
536 + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
537 + __func__, bits_per_word);
538 + return -EINVAL;
539 + }
540 +
541 + if (spi->chip_select > spi->master->num_chipselect) {
542 + dev_err(&spi->dev, "%s, unsupported slave %d\n",
543 + __func__, spi->chip_select);
544 + return -EINVAL;
545 + }
546 +
547 + /* Check clock setting */
548 + div = (bs->speed_hz / hz);
549 + switch (div) {
550 + case 2:
551 + clk_cfg = SPI_CLK_25MHZ;
552 + break;
553 + case 4:
554 + clk_cfg = SPI_CLK_12_50MHZ;
555 + break;
556 + case 8:
557 + clk_cfg = SPI_CLK_6_250MHZ;
558 + break;
559 + case 16:
560 + clk_cfg = SPI_CLK_3_125MHZ;
561 + break;
562 + case 32:
563 + clk_cfg = SPI_CLK_1_563MHZ;
564 + break;
565 + case 128:
566 + clk_cfg = SPI_CLK_0_781MHZ;
567 + break;
568 + case 64:
569 + default:
570 + /* Set to slowest mode for compatibility */
571 + clk_cfg = SPI_CLK_0_781MHZ;
572 + break;
573 + }
574 +
575 + bcm_spi_writeb(clk_cfg, bs->regs, SPI_CLK_CFG);
576 + dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
577 + div, hz, clk_cfg);
578 +
579 + return 0;
580 +}
581 +
582 +/* the spi->mode bits understood by this driver: */
583 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
584 +
585 +static int bcm63xx_spi_setup(struct spi_device *spi)
586 +{
587 + struct spi_bitbang *bitbang;
588 + struct bcm63xx_spi *bs;
589 + int retval;
590 +
591 + bs = spi_master_get_devdata(spi->master);
592 + bitbang = &bs->bitbang;
593 +
594 + if (!spi->bits_per_word)
595 + spi->bits_per_word = 8;
596 +
597 + if (spi->mode & ~MODEBITS) {
598 + dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
599 + __func__, spi->mode & ~MODEBITS);
600 + return -EINVAL;
601 + }
602 +
603 + retval = bcm63xx_spi_setup_transfer(spi, NULL);
604 + if (retval < 0) {
605 + dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
606 + spi->mode & ~MODEBITS);
607 + return retval;
608 + }
609 +
610 + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
611 + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
612 +
613 + return 0;
614 +}
615 +
616 +/* Fill the TX FIFO with as many bytes as possible */
617 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
618 +{
619 + u8 tail;
620 +
621 + /* Fill the Tx FIFO with as many bytes as possible */
622 + tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
623 + while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
624 + if (bs->tx_ptr)
625 + bcm_spi_writeb(*bs->tx_ptr++, bs->regs, SPI_MSG_DATA);
626 + else
627 + bcm_spi_writeb(0, bs->regs, SPI_MSG_DATA);
628 + bs->remaining_bytes--;
629 + tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
630 + }
631 +}
632 +
633 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
634 +{
635 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
636 + u8 msg_ctl;
637 + u16 cmd;
638 +
639 + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
640 + t->tx_buf, t->rx_buf, t->len);
641 +
642 + /* Transmitter is inhibited */
643 + bs->tx_ptr = t->tx_buf;
644 + bs->rx_ptr = t->rx_buf;
645 + bs->remaining_bytes = t->len;
646 + init_completion(&bs->done);
647 +
648 + bcm63xx_spi_fill_tx_fifo(bs);
649 +
650 + /* Enable the command done interrupt which
651 + * we use to determine completion of a command */
652 + bcm_spi_writeb(SPI_INTR_CMD_DONE, bs->regs, SPI_INT_MASK);
653 +
654 + /* Fill in the Message control register */
655 + msg_ctl = bcm_spi_readb(bs->regs, SPI_MSG_CTL);
656 + msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT);
657 + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
658 + bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL);
659 +
660 + /* Issue the transfer */
661 + cmd = bcm_spi_readw(bs->regs, SPI_CMD);
662 + cmd |= SPI_CMD_START_IMMEDIATE;
663 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
664 + bcm_spi_writew(cmd, bs->regs, SPI_CMD);
665 +
666 + wait_for_completion(&bs->done);
667 +
668 + /* Disable the CMD_DONE interrupt */
669 + bcm_spi_writeb(~(SPI_INTR_CMD_DONE), bs->regs, SPI_INT_MASK);
670 +
671 + return t->len - bs->remaining_bytes;
672 +}
673 +
674 +/* This driver supports single master mode only. Hence
675 + * CMD_DONE is the only interrupt we care about
676 + */
677 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
678 +{
679 + struct spi_master *master = (struct spi_master *)dev_id;
680 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
681 + u8 intr;
682 + u16 cmd;
683 +
684 + /* Read interupts and clear them immediately */
685 + intr = bcm_spi_readb(bs->regs, SPI_INT_STATUS);
686 + bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
687 +
688 + /* A tansfer completed */
689 + if (intr & SPI_INTR_CMD_DONE) {
690 + u8 rx_empty;
691 +
692 + rx_empty = bcm_spi_readb(bs->regs, SPI_ST);
693 + /* Read out all the data */
694 + while ((rx_empty & SPI_RX_EMPTY) == 0) {
695 + u8 data;
696 +
697 + data = bcm_spi_readb(bs->regs, SPI_RX_DATA);
698 + if (bs->rx_ptr)
699 + *bs->rx_ptr++ = data;
700 +
701 + rx_empty = bcm_spi_readb(bs->regs, SPI_RX_EMPTY);
702 + }
703 +
704 + /* See if there is more data to send */
705 + if (bs->remaining_bytes > 0) {
706 + bcm63xx_spi_fill_tx_fifo(bs);
707 +
708 + /* Start the transfer */
709 + cmd = bcm_spi_readw(bs->regs, SPI_CMD);
710 + cmd |= SPI_CMD_START_IMMEDIATE;
711 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
712 + bcm_spi_writew(cmd, bs->regs, SPI_CMD);
713 + } else
714 + complete(&bs->done);
715 + }
716 +
717 + return IRQ_HANDLED;
718 +}
719 +
720 +
721 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
722 +{
723 + struct resource *r;
724 + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
725 + int irq;
726 + struct spi_master *master;
727 + struct clk *clk;
728 + struct bcm63xx_spi *bs;
729 + int ret;
730 +
731 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
732 + if (!r) {
733 + ret = -ENXIO;
734 + goto out;
735 + }
736 +
737 + irq = platform_get_irq(pdev, 0);
738 + if (irq < 0) {
739 + ret = -ENXIO;
740 + goto out;
741 + }
742 +
743 + bcm63xx_spi_regs_init();
744 +
745 + clk = clk_get(&pdev->dev, "spi");
746 + if (IS_ERR(clk)) {
747 + dev_err(&pdev->dev, "No clock for device\n");
748 + ret = -ENODEV;
749 + goto out;
750 + }
751 +
752 + master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi));
753 + if (!master) {
754 + ret = -ENOMEM;
755 + goto out_free;
756 + }
757 +
758 + bs = spi_master_get_devdata(master);
759 + bs->bitbang.master = spi_master_get(master);
760 + bs->bitbang.chipselect = bcm63xx_spi_chipselect;
761 + bs->bitbang.setup_transfer = bcm63xx_spi_setup_transfer;
762 + bs->bitbang.txrx_bufs = bcm63xx_txrx_bufs;
763 + bs->bitbang.master->setup = bcm63xx_spi_setup;
764 + init_completion(&bs->done);
765 +
766 + platform_set_drvdata(pdev, master);
767 + bs->pdev = pdev;
768 +
769 + if (!request_mem_region(r->start,
770 + r->end - r->start, PFX)) {
771 + ret = -ENXIO;
772 + goto out_free;
773 + }
774 +
775 + bs->regs = ioremap_nocache(r->start, r->end - r->start);
776 + if (!bs->regs) {
777 + printk(KERN_ERR PFX " unable to ioremap regs\n");
778 + ret = -ENOMEM;
779 + goto out_free;
780 + }
781 + bs->irq = irq;
782 + bs->clk = clk;
783 + bs->fifo_size = pdata->fifo_size;
784 +
785 + ret = request_irq(irq, bcm63xx_spi_interrupt, 0,
786 + pdev->name, master);
787 + if (ret) {
788 + printk(KERN_ERR PFX " unable to request irq\n");
789 + goto out_unmap;
790 + }
791 +
792 + master->bus_num = pdata->bus_num;
793 + master->num_chipselect = pdata->num_chipselect;
794 + bs->speed_hz = pdata->speed_hz;
795 +
796 + /* Initialize hardware */
797 + clk_enable(bs->clk);
798 + bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
799 +
800 + dev_info(&pdev->dev, " at 0x%08x (irq %d, FIFOs size %d) v%s\n",
801 + r->start, irq, bs->fifo_size, DRV_VER);
802 +
803 + ret = spi_bitbang_start(&bs->bitbang);
804 + if (ret) {
805 + dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
806 + goto out_reset_hw;
807 + }
808 +
809 + return ret;
810 +
811 +out_reset_hw:
812 + clk_disable(clk);
813 + free_irq(irq, master);
814 +out_unmap:
815 + iounmap(bs->regs);
816 +out_free:
817 + clk_put(clk);
818 + spi_master_put(master);
819 +out:
820 + return ret;
821 +}
822 +
823 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
824 +{
825 + struct spi_master *master = platform_get_drvdata(pdev);
826 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
827 +
828 + spi_bitbang_stop(&bs->bitbang);
829 + clk_disable(bs->clk);
830 + clk_put(bs->clk);
831 + free_irq(bs->irq, master);
832 + iounmap(bs->regs);
833 + platform_set_drvdata(pdev, 0);
834 + spi_master_put(bs->bitbang.master);
835 +
836 + return 0;
837 +}
838 +
839 +#ifdef CONFIG_PM
840 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
841 +{
842 + struct spi_master *master = platform_get_drvdata(pdev);
843 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
844 +
845 + clk_disable(bs->clk);
846 +
847 + return 0;
848 +}
849 +
850 +static int bcm63xx_spi_resume(struct platform_device *pdev)
851 +{
852 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
853 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
854 +
855 + clk_enable(bs->clk);
856 +
857 + return 0;
858 +}
859 +#else
860 +#define bcm63xx_spi_suspend NULL
861 +#define bcm63xx_spi_resume NULL
862 +#endif
863 +
864 +static struct platform_driver bcm63xx_spi_driver = {
865 + .driver = {
866 + .name = "bcm63xx-spi",
867 + .owner = THIS_MODULE,
868 + },
869 + .probe = bcm63xx_spi_probe,
870 + .remove = bcm63xx_spi_remove,
871 + .suspend = bcm63xx_spi_suspend,
872 + .resume = bcm63xx_spi_resume,
873 +};
874 +
875 +
876 +static int __init bcm63xx_spi_init(void)
877 +{
878 + return platform_driver_register(&bcm63xx_spi_driver);
879 +}
880 +
881 +static void __exit bcm63xx_spi_exit(void)
882 +{
883 + platform_driver_unregister(&bcm63xx_spi_driver);
884 +}
885 +
886 +module_init(bcm63xx_spi_init);
887 +module_exit(bcm63xx_spi_exit);
888 +
889 +MODULE_ALIAS("platform:bcm63xx_spi");
890 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
891 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
892 +MODULE_LICENSE("GPL");
893 +MODULE_VERSION(DRV_VER);
894 Index: linux-2.6.32.13/drivers/spi/Kconfig
895 ===================================================================
896 --- linux-2.6.32.13.orig/drivers/spi/Kconfig 2010-05-27 21:34:54.000000000 -0400
897 +++ linux-2.6.32.13/drivers/spi/Kconfig 2010-05-27 21:48:23.000000000 -0400
898 @@ -60,6 +60,13 @@
899 This selects a driver for the Atmel SPI Controller, present on
900 many AT32 (AVR32) and AT91 (ARM) chips.
901
902 +config SPI_BCM63XX
903 + tristate "Broadcom BCM63xx SPI controller"
904 + depends on BCM63XX
905 + select SPI_BITBANG
906 + help
907 + This is the SPI controller master driver for Broadcom BCM63xx SoC.
908 +
909 config SPI_BFIN
910 tristate "SPI controller driver for ADI Blackfin5xx"
911 depends on BLACKFIN
912 Index: linux-2.6.32.13/drivers/spi/Makefile
913 ===================================================================
914 --- linux-2.6.32.13.orig/drivers/spi/Makefile 2010-05-27 21:34:54.000000000 -0400
915 +++ linux-2.6.32.13/drivers/spi/Makefile 2010-05-27 21:48:23.000000000 -0400
916 @@ -34,6 +34,7 @@
917 obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
918 obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
919 obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
920 +obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
921 # ... add above this line ...
922
923 # SPI protocol drivers (device/link on bus)
924 Index: linux-2.6.32.13/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
925 ===================================================================
926 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
927 +++ linux-2.6.32.13/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h 2010-05-27 21:48:23.000000000 -0400
928 @@ -0,0 +1,15 @@
929 +#ifndef BCM63XX_DEV_SPI_H
930 +#define BCM63XX_DEV_SPI_H
931 +
932 +#include <linux/types.h>
933 +
934 +int __init bcm63xx_spi_register(void);
935 +
936 +struct bcm63xx_spi_pdata {
937 + unsigned int fifo_size;
938 + int bus_num;
939 + int num_chipselect;
940 + u32 speed_hz;
941 +};
942 +
943 +#endif /* BCM63XX_DEV_SPI_H */
944 Index: linux-2.6.32.13/arch/mips/bcm63xx/Makefile
945 ===================================================================
946 --- linux-2.6.32.13.orig/arch/mips/bcm63xx/Makefile 2010-05-27 21:44:19.000000000 -0400
947 +++ linux-2.6.32.13/arch/mips/bcm63xx/Makefile 2010-05-27 21:48:23.000000000 -0400
948 @@ -1,6 +1,6 @@
949 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
950 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
951 - dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
952 + dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
953 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
954
955 obj-y += boards/
956 Index: linux-2.6.32.13/arch/mips/bcm63xx/boards/board_bcm963xx.c
957 ===================================================================
958 --- linux-2.6.32.13.orig/arch/mips/bcm63xx/boards/board_bcm963xx.c 2010-05-27 21:46:39.000000000 -0400
959 +++ linux-2.6.32.13/arch/mips/bcm63xx/boards/board_bcm963xx.c 2010-05-27 21:48:23.000000000 -0400
960 @@ -30,6 +30,7 @@
961 #include <bcm63xx_dev_usb_ohci.h>
962 #include <bcm63xx_dev_usb_ehci.h>
963 #include <bcm63xx_dev_usb_udc.h>
964 +#include <bcm63xx_dev_spi.h>
965 #include <board_bcm963xx.h>
966
967 #define PFX "board_bcm963xx: "
968 @@ -1479,6 +1480,9 @@
969 if (board.has_udc0)
970 bcm63xx_udc_register();
971
972 + if (!BCMCPU_IS_6345())
973 + bcm63xx_spi_register();
974 +
975 /* Generate MAC address for WLAN and
976 * register our SPROM */
977 #ifdef CONFIG_SSB_PCIHOST
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