target/linux/lantiq/patches-2.6.39/110-falcon_board.patch

   1 --- /dev/null
   2 +++ b/arch/mips/lantiq/falcon/Kconfig
   3 @@ -0,0 +1,11 @@
   4 +if SOC_FALCON
   5 +
   6 +menu "Mips Machine"
   7 +
   8 +config LANTIQ_MACH_EASY98000
   9 +       bool "Easy98000"
  10 +       default y
  11 +
  12 +endmenu
  13 +
  14 +endif
  15 --- /dev/null
  16 +++ b/arch/mips/lantiq/falcon/Makefile
  17 @@ -0,0 +1,4 @@
  18 +obj-y := clk-falcon.o devices.o gpio.o prom.o sysctrl.o reset.o
  19 +obj-y += softdog_vpe.o
  20 +obj-$(CONFIG_LANTIQ_MACH_EASY98000) += addon-easy98000.o
  21 +obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
  22 --- /dev/null
  23 +++ b/arch/mips/lantiq/falcon/clk-falcon.c
  24 @@ -0,0 +1,48 @@
  25 +/*
  26 + * This program is free software; you can redistribute it and/or modify
  27 + * it under the terms of the GNU General Public License as published by
  28 + * the Free Software Foundation; either version 2 of the License, or
  29 + * (at your option) any later version.
  30 + *
  31 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  32 + */
  33 +
  34 +#include <linux/io.h>
  35 +#include <linux/module.h>
  36 +#include <linux/init.h>
  37 +
  38 +#include <asm/time.h>
  39 +#include <asm/irq.h>
  40 +#include <asm/div64.h>
  41 +
  42 +#include <lantiq_soc.h>
  43 +
  44 +#include <falcon.h>
  45 +#include <gpon_reg_base.h>
  46 +#include <sys1_reg.h>
  47 +
  48 +static struct gpon_reg_sys1 * const pSYS1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
  49 +
  50 +unsigned int
  51 +ltq_get_io_region_clock(void)
  52 +{
  53 +       return 200000000; /* 200 MHz */
  54 +}
  55 +EXPORT_SYMBOL(ltq_get_io_region_clock);
  56 +
  57 +unsigned int
  58 +ltq_get_cpu_hz(void)
  59 +{
  60 +       if ((ltq_r32(&pSYS1->cpu0cc) & CPU0CC_CPUDIV) == CPU0CC_CPUDIV_SELFHALF)
  61 +               return 200000000; /* 200 MHz */
  62 +       else
  63 +               return 400000000; /* 400 MHz */
  64 +}
  65 +EXPORT_SYMBOL(ltq_get_cpu_hz);
  66 +
  67 +unsigned int
  68 +ltq_get_fpi_hz(void)
  69 +{
  70 +       return 100000000;
  71 +}
  72 +EXPORT_SYMBOL(ltq_get_fpi_hz);
  73 --- /dev/null
  74 +++ b/arch/mips/lantiq/falcon/devices.c
  75 @@ -0,0 +1,254 @@
  76 +#include <linux/init.h>
  77 +#include <linux/module.h>
  78 +#include <linux/types.h>
  79 +#include <linux/string.h>
  80 +#include <linux/mtd/physmap.h>
  81 +#include <linux/kernel.h>
  82 +#include <linux/reboot.h>
  83 +#include <linux/platform_device.h>
  84 +#include <linux/leds.h>
  85 +#include <linux/etherdevice.h>
  86 +#include <linux/reboot.h>
  87 +#include <linux/time.h>
  88 +#include <linux/io.h>
  89 +#include <linux/gpio.h>
  90 +#include <linux/leds.h>
  91 +#include <linux/spi/spi.h>
  92 +#include <linux/mtd/nand.h>
  93 +
  94 +#include <asm/bootinfo.h>
  95 +#include <asm/irq.h>
  96 +
  97 +#include <lantiq.h>
  98 +
  99 +#include <falcon/falcon_irq.h>
 100 +#include <falcon/gpon_reg_base.h>
 101 +#include <falcon/ebu_reg.h>
 102 +#include <falcon/sys1_reg.h>
 103 +#include <falcon/sys_eth_reg.h>
 104 +
 105 +#include <falcon/sysctrl.h>
 106 +
 107 +#include "devices.h"
 108 +
 109 +unsigned char ltq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
 110 +EXPORT_SYMBOL(ltq_ethaddr);
 111 +
 112 +static int __init
 113 +falcon_set_ethaddr(char *str)
 114 +{
 115 +       sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
 116 +               &ltq_ethaddr[0], &ltq_ethaddr[1], &ltq_ethaddr[2],
 117 +               &ltq_ethaddr[3], &ltq_ethaddr[4], &ltq_ethaddr[5]);
 118 +       return 0;
 119 +}
 120 +__setup("ethaddr=", falcon_set_ethaddr);
 121 +
 122 +/* asc ports */
 123 +static struct resource falcon_asc0_resources[] =
 124 +{
 125 +       MEM_RES("asc0",GPON_ASC0_BASE,GPON_ASC0_END),
 126 +       IRQ_RES("tx",INT_NUM_IM3_IRL0),
 127 +       IRQ_RES("rx",INT_NUM_IM3_IRL0+1),
 128 +       IRQ_RES("err",INT_NUM_IM3_IRL0+2),
 129 +};
 130 +
 131 +static struct resource falcon_asc1_resources[] =
 132 +{
 133 +       MEM_RES("asc1",GPON_ASC1_BASE,GPON_ASC1_END),
 134 +       IRQ_RES("tx",INT_NUM_IM3_IRL0+8),
 135 +       IRQ_RES("rx",INT_NUM_IM3_IRL0+9),
 136 +       IRQ_RES("err",INT_NUM_IM3_IRL0+10),
 137 +};
 138 +
 139 +void __init falcon_register_asc(int port)
 140 +{
 141 +       switch (port) {
 142 +       case 0:
 143 +               platform_device_register_simple("ltq_asc", 0,
 144 +                       falcon_asc0_resources, ARRAY_SIZE(falcon_asc0_resources));
 145 +               break;
 146 +       case 1:
 147 +               platform_device_register_simple("ltq_asc", 1,
 148 +                       falcon_asc1_resources, ARRAY_SIZE(falcon_asc1_resources));
 149 +               break;
 150 +       default:
 151 +               break;
 152 +       }
 153 +}
 154 +
 155 +/* nor flash */
 156 +static struct resource ltq_nor_resource =
 157 +       MEM_RES("nor",LTQ_FLASH_START,LTQ_FLASH_START + LTQ_FLASH_MAX - 1);
 158 +
 159 +static struct platform_device ltq_nor = {
 160 +       .name                   = "ltq_nor",
 161 +       .resource               = &ltq_nor_resource,
 162 +       .num_resources  = 1,
 163 +};
 164 +
 165 +void __init falcon_register_nor(struct physmap_flash_data *data)
 166 +{
 167 +       ltq_nor.dev.platform_data = data;
 168 +       platform_device_register(&ltq_nor);
 169 +}
 170 +
 171 +/* spi flash */
 172 +static struct resource ltq_spi_resources[] = {
 173 +       MEM_RES("ebu", GPON_EBU_BASE, GPON_EBU_END),
 174 +       MEM_RES("sys1", GPON_SYS1_BASE, GPON_SYS1_END)
 175 +};
 176 +
 177 +static struct platform_device ltq_spi = {
 178 +       .name                   = "falcon_spi",
 179 +       .resource               = ltq_spi_resources,
 180 +       .num_resources          = ARRAY_SIZE(ltq_spi_resources)
 181 +};
 182 +
 183 +void __init falcon_register_spi_flash(struct spi_board_info *data)
 184 +{
 185 +       spi_register_board_info(data, 1);
 186 +       platform_device_register(&ltq_spi);
 187 +}
 188 +
 189 +/* nand flash */
 190 +static struct gpon_reg_ebu __iomem *membase_ebu;
 191 +static const char *part_probes[] = { "cmdlinepart", NULL };
 192 +
 193 +static int falcon_nand_ready(struct mtd_info *mtd)
 194 +{
 195 +       u32 modcon = __raw_readl(&membase_ebu->modcon);
 196 +
 197 +       return (((modcon & (MODCON_STS|MODCON_STSEDGE)) ==
 198 +                                               (MODCON_STS|MODCON_STSEDGE)));
 199 +}
 200 +
 201 +/* address lines used for NAND control signals */
 202 +#define NAND_ADDR_ALE          (1<<16)
 203 +#define NAND_ADDR_CLE          (1<<17)
 204 +
 205 +static void falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 206 +{
 207 +       struct nand_chip *this = mtd->priv;
 208 +       unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
 209 +
 210 +       if (ctrl & NAND_CTRL_CHANGE) {
 211 +               nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
 212 +
 213 +               if (ctrl & NAND_CLE)
 214 +                       nandaddr |= NAND_ADDR_CLE;
 215 +               if (ctrl & NAND_ALE)
 216 +                       nandaddr |= NAND_ADDR_ALE;
 217 +
 218 +               this->IO_ADDR_W = (void __iomem *) nandaddr;
 219 +       }
 220 +
 221 +       if (cmd != NAND_CMD_NONE)
 222 +               writeb(cmd, this->IO_ADDR_W);
 223 +}
 224 +
 225 +static struct platform_nand_data falcon_flash_nand_data = {
 226 +       .chip = {
 227 +               .nr_chips               = 1,
 228 +               .chip_delay             = 25,
 229 +               .part_probe_types       = part_probes,
 230 +       },
 231 +       .ctrl = {
 232 +               .cmd_ctrl               = falcon_hwcontrol,
 233 +               .dev_ready              = falcon_nand_ready,
 234 +       }
 235 +};
 236 +
 237 +static struct resource ltq_nand_resources[] = {
 238 +       MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_START + LTQ_FLASH_MAX - 1),
 239 +       MEM_RES("ebu", GPON_EBU_BASE, GPON_EBU_END),
 240 +};
 241 +
 242 +static struct platform_device ltq_flash_nand = {
 243 +       .name           = "gen_nand",
 244 +       .id             = -1,
 245 +       .num_resources  = ARRAY_SIZE(ltq_nand_resources),
 246 +       .resource       = ltq_nand_resources,
 247 +       .dev            = {
 248 +               .platform_data = &falcon_flash_nand_data,
 249 +       },
 250 +};
 251 +
 252 +void __init falcon_register_nand(void)
 253 +{
 254 +       membase_ebu = ioremap_nocache(ltq_nand_resources[1].start,
 255 +                       resource_size(&ltq_nand_resources[1]));
 256 +
 257 +       if (membase_ebu)
 258 +               platform_device_register(&ltq_flash_nand);
 259 +}
 260 +
 261 +/* watchdog */
 262 +static struct resource falcon_wdt_resource =
 263 +       MEM_RES("watchdog",GPON_WDT_BASE,GPON_WDT_END);
 264 +
 265 +void __init falcon_register_wdt(void)
 266 +{
 267 +       platform_device_register_simple("ltq_wdt", 0, &falcon_wdt_resource, 1);
 268 +}
 269 +
 270 +/* gpio */
 271 +#define DECLARE_GPIO_RES(port) \
 272 +static struct resource falcon_gpio ## port ## _resources[] = { \
 273 +       MEM_RES("gpio"#port,GPON_GPIO ## port ## _BASE,GPON_GPIO ## port ## _END), \
 274 +       MEM_RES("padctrl"#port,GPON_PADCTRL ## port ## _BASE,GPON_PADCTRL ## port ## _END), \
 275 +       IRQ_RES("gpio_mux"#port,FALCON_IRQ_GPIO_P ## port ) \
 276 +}
 277 +DECLARE_GPIO_RES(0);
 278 +DECLARE_GPIO_RES(1);
 279 +DECLARE_GPIO_RES(2);
 280 +#ifdef REGISTER_ALL_GPIO_PORTS
 281 +#if NR_IRQS < 328
 282 +#error NR_IRQS to low for all gpio irqs
 283 +#endif
 284 +DECLARE_GPIO_RES(3);
 285 +DECLARE_GPIO_RES(4);
 286 +#endif
 287 +
 288 +void __init falcon_register_gpio(void)
 289 +{
 290 +       platform_device_register_simple("falcon_gpio", 0,
 291 +               falcon_gpio0_resources, ARRAY_SIZE(falcon_gpio0_resources));
 292 +       platform_device_register_simple("falcon_gpio", 1,
 293 +               falcon_gpio1_resources, ARRAY_SIZE(falcon_gpio1_resources));
 294 +       platform_device_register_simple("falcon_gpio", 2,
 295 +               falcon_gpio2_resources, ARRAY_SIZE(falcon_gpio2_resources));
 296 +       sys1_hw_activate(ACTS_PADCTRL1 | ACTS_P1);
 297 +       sys_eth_hw_activate(SYS_ETH_ACTS_PADCTRL0 | SYS_ETH_ACTS_PADCTRL2 |
 298 +               SYS_ETH_ACTS_P0 | SYS_ETH_ACTS_P2);
 299 +
 300 +#ifdef REGISTER_ALL_GPIO_PORTS
 301 +       /* optional gpio ports: not registered,
 302 +          as the pins are EBU specific and always used by linux */
 303 +       platform_device_register_simple("falcon_gpio", 3,
 304 +               falcon_gpio3_resources, ARRAY_SIZE(falcon_gpio3_resources));
 305 +       platform_device_register_simple("falcon_gpio", 4,
 306 +               falcon_gpio4_resources, ARRAY_SIZE(falcon_gpio4_resources));
 307 +       sys1_hw_activate(ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
 308 +#endif
 309 +}
 310 +
 311 +static struct resource falcon_i2c_resources[] = {
 312 +       MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
 313 +       IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
 314 +       IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
 315 +       IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
 316 +       IRQ_RES("i2c_p", FALCON_IRQ_I2C_I2C_P),
 317 +};
 318 +
 319 +void __init falcon_register_i2c(void)
 320 +{
 321 +       platform_device_register_simple("i2c-falcon", 0,
 322 +               falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
 323 +       sys1_hw_activate(ACTS_I2C_ACT);
 324 +}
 325 +
 326 +void __init falcon_register_crypto(void)
 327 +{
 328 +       platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
 329 +}
 330 --- /dev/null
 331 +++ b/arch/mips/lantiq/falcon/devices.h
 332 @@ -0,0 +1,22 @@
 333 +#ifndef _FALCON_DEVICES_H__
 334 +#define _FALCON_DEVICES_H__
 335 +
 336 +#include <linux/mtd/physmap.h>
 337 +#include <linux/spi/spi.h>
 338 +#include <linux/spi/flash.h>
 339 +
 340 +extern void __init falcon_register_asc(int port);
 341 +extern void __init falcon_register_i2c(void);
 342 +extern void __init falcon_register_spi_flash(struct spi_board_info *data);
 343 +extern void __init falcon_register_gpio(void);
 344 +extern void __init falcon_register_nor(struct physmap_flash_data *data);
 345 +extern void __init falcon_register_nand(void);
 346 +extern void __init falcon_register_wdt(void);
 347 +extern void __init falcon_register_crypto(void);
 348 +
 349 +#define IRQ_RES(resname,irq) {.name=resname,.start=(irq),.flags=IORESOURCE_IRQ}
 350 +#define MEM_RES(resname,adr_start,adr_end) \
 351 +       { .name=resname, .flags=IORESOURCE_MEM, \
 352 +         .start=((adr_start)&~KSEG1),.end=((adr_end)&~KSEG1) }
 353 +
 354 +#endif
 355 --- /dev/null
 356 +++ b/arch/mips/lantiq/falcon/prom.c
 357 @@ -0,0 +1,52 @@
 358 +/*
 359 + * This program is free software; you can redistribute it and/or modify
 360 + * it under the terms of the GNU General Public License as published by
 361 + * the Free Software Foundation; either version 2 of the License, or
 362 + * (at your option) any later version.
 363 + *
 364 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 365 + */
 366 +
 367 +#include <linux/module.h>
 368 +#include <linux/clk.h>
 369 +#include <asm/bootinfo.h>
 370 +#include <asm/time.h>
 371 +
 372 +#include <lantiq_soc.h>
 373 +
 374 +#include <falcon.h>
 375 +
 376 +#include <falcon/gpon_reg_base.h>
 377 +#include <falcon/status_reg.h>
 378 +#include <falcon/sys1_reg.h>
 379 +
 380 +#include "../prom.h"
 381 +
 382 +static struct gpon_reg_status * const pSTATUS = (struct gpon_reg_status *)GPON_STATUS_BASE;
 383 +
 384 +#define SOC_FALCON             "Falcon"
 385 +
 386 +void __init
 387 +ltq_soc_setup(void)
 388 +{
 389 +       /* not used */
 390 +}
 391 +
 392 +void __init
 393 +ltq_soc_detect(struct ltq_soc_info *i)
 394 +{
 395 +       i->partnum = (ltq_r32(&pSTATUS->chipid) & STATUS_CHIPID_PARTNR_MASK) >> STATUS_CHIPID_PARTNR_OFFSET;
 396 +       i->rev = (ltq_r32(&pSTATUS->chipid) & STATUS_CHIPID_VERSION_MASK) >> STATUS_CHIPID_VERSION_OFFSET;
 397 +       switch (i->partnum)
 398 +       {
 399 +       case SOC_ID_FALCON:
 400 +               i->name = SOC_FALCON;
 401 +               i->type = SOC_TYPE_FALCON;
 402 +               break;
 403 +
 404 +       default:
 405 +               printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum);
 406 +               while(1) {      };
 407 +               break;
 408 +       }
 409 +}
 410 --- /dev/null
 411 +++ b/arch/mips/lantiq/falcon/sysctrl.c
 412 @@ -0,0 +1,381 @@
 413 +/*
 414 + * This program is free software; you can redistribute it and/or
 415 + * modify it under the terms of the GNU General Public License as
 416 + * published by the Free Software Foundation; either version 2 of
 417 + * the License, or (at your option) any later version.
 418 + *
 419 + * This program is distributed in the hope that it will be useful,
 420 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 421 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 422 + * GNU General Public License for more details.
 423 + *
 424 + * You should have received a copy of the GNU General Public License
 425 + * along with this program; if not, write to the Free Software
 426 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 427 + * MA 02111-1307 USA
 428 + *
 429 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
 430 + */
 431 +
 432 +#include <linux/cpu.h>
 433 +#include <linux/init.h>
 434 +#include <linux/kernel.h>
 435 +#include <linux/pm.h>
 436 +#include <linux/io.h>
 437 +#include <linux/ioport.h>
 438 +#include <linux/clk.h>
 439 +#include <asm/reboot.h>
 440 +
 441 +#include <falcon/gpon_reg_base.h>
 442 +#include <falcon/status_reg.h>
 443 +#include <falcon/sys1_reg.h>
 444 +#include <falcon/sys_eth_reg.h>
 445 +#include <falcon/sys_gpe_reg.h>
 446 +
 447 +#include <falcon/sysctrl.h>
 448 +
 449 +/* mapping to linux hw-accessor routines */
 450 +#define reg_r32(reg)                   __raw_readl(reg)
 451 +#define reg_w32(val, reg)              __raw_writel(val, reg)
 452 +#define reg_w32_mask(clear, set, reg)  reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
 453 +
 454 +static struct gpon_reg_sys1 * const sys1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
 455 +static struct gpon_reg_sys_eth * const sys_eth = (struct gpon_reg_sys_eth *)GPON_SYS_ETH_BASE;
 456 +static struct gpon_reg_sys_gpe * const sys_gpe = (struct gpon_reg_sys_gpe *)GPON_SYS_GPE_BASE;
 457 +static struct gpon_reg_status * const status = (struct gpon_reg_status *)GPON_STATUS_BASE;
 458 +
 459 +/**
 460 + * Activate the selected module(s)
 461 + * Enables the clock of the module and activates the module itself.
 462 + *
 463 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.ACT
 464 + * \return void
 465 + */
 466 +void sys1_hw_activate(u32 mask)
 467 +{
 468 +       sys1_w32(mask, clken);
 469 +       sys1_w32(mask, act);
 470 +
 471 +       while ( (sys1_r32(acts) & mask) != mask) {
 472 +               /*NOP;*/
 473 +       };
 474 +}
 475 +EXPORT_SYMBOL(sys1_hw_activate);
 476 +
 477 +/**
 478 + * Deactivate the selected module(s)
 479 + * Disables the clock of the module and deactivates the module itself.
 480 + *
 481 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.DEACT
 482 + * \return void
 483 + */
 484 +void sys1_hw_deactivate(u32 mask)
 485 +{
 486 +       sys1_w32(mask, clkclr);
 487 +       sys1_w32(mask, deact);
 488 +
 489 +       while ( (sys1_r32(acts) & mask) != 0) {
 490 +               /*NOP;*/
 491 +       };
 492 +}
 493 +EXPORT_SYMBOL(sys1_hw_deactivate);
 494 +
 495 +/**
 496 + * Clock enable for the selected module(s)
 497 + * Enables the clock of the module.
 498 + *
 499 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.CLKEN
 500 + * \return void
 501 + */
 502 +void sys1_hw_clk_enable(u32 mask)
 503 +{
 504 +       sys1_w32(mask, clken);
 505 +
 506 +       while ( (sys1_r32(clks) & mask) != mask) {
 507 +               /*NOP;*/
 508 +       };
 509 +}
 510 +EXPORT_SYMBOL(sys1_hw_clk_enable);
 511 +
 512 +/**
 513 + * Clock disable for the selected module(s)
 514 + * disables the clock of the module.
 515 + *
 516 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.CLKCLR
 517 + * \return void
 518 + */
 519 +void sys1_hw_clk_disable(u32 mask)
 520 +{
 521 +       sys1_w32(mask, clkclr);
 522 +
 523 +       while ( (sys1_r32(clks) & mask) != 0) {
 524 +               /*NOP;*/
 525 +       };
 526 +}
 527 +EXPORT_SYMBOL(sys1_hw_clk_disable);
 528 +
 529 +/**
 530 + * Reboots the selected module(s)
 531 + * Triggers the reboot of the module.
 532 + *
 533 + * \param[in]   mask    bitmask of module(s), as for registers SYS1.RBT
 534 + * \return void
 535 + */
 536 +void sys1_hw_activate_or_reboot(u32 mask)
 537 +{
 538 +       u32 acts = sys1_r32(acts);
 539 +       /* is not already active? */
 540 +       if ((~acts & mask) != 0)
 541 +               sys1_hw_activate(~acts & mask);
 542 +       sys1_w32(acts & mask, rbt);
 543 +       while ( (sys1_r32(acts) & mask) != mask) {
 544 +               /*NOP;*/
 545 +       };
 546 +}
 547 +EXPORT_SYMBOL(sys1_hw_activate_or_reboot);
 548 +
 549 +/**
 550 + * Activate the selected module(s)
 551 + * Enables the clock of the module and activates the module itself.
 552 + *
 553 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.ACT
 554 + * \return void
 555 + */
 556 +void sys_eth_hw_activate(u32 mask)
 557 +{
 558 +       sys_eth_w32(mask, clken);
 559 +       sys_eth_w32(mask, act);
 560 +
 561 +       while ( (sys_eth_r32(acts) & mask) != mask) {
 562 +               /*NOP;*/
 563 +       };
 564 +}
 565 +EXPORT_SYMBOL(sys_eth_hw_activate);
 566 +
 567 +/**
 568 + * Deactivate the selected module(s)
 569 + * Disables the clock of the module and deactivates the module itself.
 570 + *
 571 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.DEACT
 572 + * \return void
 573 + */
 574 +void sys_eth_hw_deactivate(u32 mask)
 575 +{
 576 +       sys_eth_w32(mask, clkclr);
 577 +       sys_eth_w32(mask, deact);
 578 +
 579 +       while ( (sys_eth_r32(acts) & mask) != 0) {
 580 +               /*NOP;*/
 581 +       };
 582 +}
 583 +EXPORT_SYMBOL(sys_eth_hw_deactivate);
 584 +
 585 +/**
 586 + * Clock enable for the selected module(s)
 587 + * Enables the clock of the module.
 588 + *
 589 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.CLKEN
 590 + * \return void
 591 + */
 592 +void sys_eth_hw_clk_enable(u32 mask)
 593 +{
 594 +       sys_eth_w32(mask, clken);
 595 +
 596 +       while ( (sys_eth_r32(clks) & mask) != mask) {
 597 +               /*NOP;*/
 598 +       };
 599 +}
 600 +EXPORT_SYMBOL(sys_eth_hw_clk_enable);
 601 +
 602 +/**
 603 + * Clock disable for the selected module(s)
 604 + * disables the clock of the module.
 605 + *
 606 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.CLKCLR
 607 + * \return void
 608 + */
 609 +void sys_eth_hw_clk_disable(u32 mask)
 610 +{
 611 +       sys_eth_w32(mask, clkclr);
 612 +
 613 +       while ( (sys_eth_r32(clks) & mask) != 0) {
 614 +               /*NOP;*/
 615 +       };
 616 +}
 617 +EXPORT_SYMBOL(sys_eth_hw_clk_disable);
 618 +
 619 +/**
 620 + * Reboots the selected module(s)
 621 + * Triggers the reboot of the module.
 622 + *
 623 + * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.RBT
 624 + * \return void
 625 + */
 626 +void sys_eth_hw_activate_or_reboot(u32 mask)
 627 +{
 628 +       u32 acts = sys_eth_r32(acts);
 629 +       /* is not already active? */
 630 +       if ((~acts & mask) != 0)
 631 +               sys_eth_hw_activate(~acts & mask);
 632 +       sys_eth_w32(acts & mask, rbt);
 633 +       while ( (sys_eth_r32(acts) & mask) != mask) {
 634 +               /*NOP;*/
 635 +       };
 636 +}
 637 +EXPORT_SYMBOL(sys_eth_hw_activate_or_reboot);
 638 +
 639 +static int gpe_clk_is_enabled(void)
 640 +{
 641 +       u32 rd_data;
 642 +
 643 +       rd_data = sys1_r32(infrac);
 644 +       if (rd_data & (1<<(INFRAC_GP_OFFSET+1)))
 645 +               return 1;
 646 +       return 0;
 647 +}
 648 +
 649 +static void enable_gpe_clk(void)
 650 +{
 651 +       u32 aeFreq;
 652 +       u32 rd_data;
 653 +       u32 rd_data_to_keep;
 654 +       int i;
 655 +
 656 +       if (gpe_clk_is_enabled())
 657 +               /* clock already active, no need to change here */
 658 +               return;
 659 +
 660 +       if (status_r32(config) == 0)
 661 +               aeFreq = 1; /* use 625MHz on unfused chip */
 662 +       else
 663 +               aeFreq = (status_r32(config) & STATUS_CONFIG_GPEFREQ_MASK) >> STATUS_CONFIG_GPEFREQ_OFFSET;
 664 +       rd_data = sys1_r32(infrac);
 665 +       /* clear gpe-fsel and enable bits */
 666 +       rd_data_to_keep = rd_data & ~(7<<(INFRAC_GP_OFFSET+1));
 667 +
 668 +       /* set new fsel */
 669 +       sys1_w32(rd_data_to_keep | (aeFreq<<(INFRAC_GP_OFFSET+2)), infrac);
 670 +
 671 +       for (i = 0; i <10; i++) /* wait 10 cycles */
 672 +               {}
 673 +
 674 +       /* keep new fsel and enable */
 675 +       sys1_w32(rd_data_to_keep | (aeFreq<<(INFRAC_GP_OFFSET+2)) |
 676 +               (1<<(INFRAC_GP_OFFSET+1)), infrac);
 677 +       for (i = 0; i <100; i++) /* wait 100 cycles */
 678 +               {}
 679 +}
 680 +
 681 +/**
 682 + * Activate the selected module(s)
 683 + * Enables the clock of the module and activates the module itself.
 684 + *
 685 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.ACT
 686 + * \return void
 687 + */
 688 +void sys_gpe_hw_activate(u32 mask)
 689 +{
 690 +       enable_gpe_clk();
 691 +       sys_gpe_w32(mask, clken);
 692 +       sys_gpe_w32(mask, act);
 693 +
 694 +       while ( (sys_gpe_r32(acts) & mask) != mask) {
 695 +               /*NOP;*/
 696 +       };
 697 +}
 698 +EXPORT_SYMBOL(sys_gpe_hw_activate);
 699 +
 700 +/**
 701 + * Deactivate the selected module(s)
 702 + * Disables the clock of the module and deactivates the module itself.
 703 + *
 704 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.DEACT
 705 + * \return void
 706 + */
 707 +void sys_gpe_hw_deactivate(u32 mask)
 708 +{
 709 +       enable_gpe_clk();
 710 +       sys_gpe_w32(mask, clkclr);
 711 +       sys_gpe_w32(mask, deact);
 712 +
 713 +       while ( (sys_gpe_r32(acts) & mask) != 0) {
 714 +               /*NOP;*/
 715 +       };
 716 +}
 717 +EXPORT_SYMBOL(sys_gpe_hw_deactivate);
 718 +
 719 +/**
 720 + * Clock enable for the selected module(s)
 721 + * Enables the clock of the module.
 722 + *
 723 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.CLKEN
 724 + * \return void
 725 + */
 726 +void sys_gpe_hw_clk_enable(u32 mask)
 727 +{
 728 +       enable_gpe_clk();
 729 +       sys_gpe_w32(mask, clken);
 730 +
 731 +       while ( (sys_gpe_r32(clks) & mask) != mask) {
 732 +               /*NOP;*/
 733 +       };
 734 +}
 735 +EXPORT_SYMBOL(sys_gpe_hw_clk_enable);
 736 +
 737 +/**
 738 + * Clock disable for the selected module(s)
 739 + * disables the clock of the module.
 740 + *
 741 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.CLKCLR
 742 + * \return void
 743 + */
 744 +void sys_gpe_hw_clk_disable(u32 mask)
 745 +{
 746 +       enable_gpe_clk();
 747 +       sys_gpe_w32(mask, clkclr);
 748 +
 749 +       while ( (sys_gpe_r32(clks) & mask) != 0) {
 750 +               /*NOP;*/
 751 +       };
 752 +}
 753 +EXPORT_SYMBOL(sys_gpe_hw_clk_disable);
 754 +
 755 +/**
 756 + * Reboots the selected module(s)
 757 + * Triggers the reboot of the module.
 758 + *
 759 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.RBT
 760 + * \return void
 761 + */
 762 +void sys_gpe_hw_activate_or_reboot(u32 mask)
 763 +{
 764 +       u32 acts;
 765 +       enable_gpe_clk();
 766 +       acts = sys_gpe_r32(acts);
 767 +       /* is not already active? */
 768 +       if ((~acts & mask) != 0)
 769 +               sys_gpe_hw_activate(~acts & mask);
 770 +       sys_gpe_w32(acts & mask, rbt);
 771 +       while ( (sys_gpe_r32(acts) & mask) != mask) {
 772 +               /*NOP;*/
 773 +       };
 774 +}
 775 +EXPORT_SYMBOL(sys_gpe_hw_activate_or_reboot);
 776 +
 777 +/**
 778 + * Retrieve activation status of the selected hardware module(s)
 779 + *
 780 + * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.RBT
 781 + * \return int 1 - if hardware module(s) is activated (including clock)
 782 + */
 783 + int sys_gpe_hw_is_activated(u32 mask)
 784 +{
 785 +       if (gpe_clk_is_enabled() == 0)
 786 +               return 0;
 787 +
 788 +       if ((sys_gpe_r32(clks) & mask) != mask)
 789 +               return 0;
 790 +
 791 +       return ((sys_gpe_r32(acts) & mask) == mask);
 792 +}
 793 +EXPORT_SYMBOL(sys_gpe_hw_is_activated);
 794 --- /dev/null
 795 +++ b/arch/mips/lantiq/falcon/gpio.c
 796 @@ -0,0 +1,463 @@
 797 +/*
 798 + *   This program is free software; you can redistribute it and/or modify
 799 + *   it under the terms of the GNU General Public License as published by
 800 + *   the Free Software Foundation; either version 2 of the License, or
 801 + *   (at your option) any later version.
 802 + *
 803 + *   This program is distributed in the hope that it will be useful,
 804 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 805 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 806 + *   GNU General Public License for more details.
 807 + *
 808 + *   You should have received a copy of the GNU General Public License
 809 + *   along with this program; if not, write to the Free Software
 810 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 811 + *
 812 + *   Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
 813 + */
 814 +
 815 +/**
 816 +       TODO:
 817 +               - add locking?
 818 +               - provide mask of available pins per platform_data
 819 +*/
 820 +
 821 +#include <linux/module.h>
 822 +#include <linux/types.h>
 823 +#include <linux/errno.h>
 824 +#include <linux/init.h>
 825 +#include <linux/seq_file.h>
 826 +#include <linux/platform_device.h>
 827 +#include <linux/uaccess.h>
 828 +#include <linux/gpio.h>
 829 +#include <linux/irq.h>
 830 +#include <linux/interrupt.h>
 831 +#include <linux/slab.h>
 832 +
 833 +#include <falcon.h>
 834 +#include <falcon/falcon_irq.h>
 835 +
 836 +#include <linux/version.h>
 837 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35))
 838 +#define for_each_set_bit for_each_bit
 839 +#endif
 840 +
 841 +#define gpio_r32(reg)                  __raw_readl(reg)
 842 +#define gpio_w32(val, reg)                     __raw_writel(val, reg)
 843 +#define gpio_w32_mask(clear, set, reg) gpio_w32((gpio_r32(reg) & ~(clear)) | (set), reg)
 844 +
 845 +
 846 +/** register structure for padctrl
 847 +    (mainly needed for mux control) */
 848 +typedef struct gpon_padctrl_s
 849 +{
 850 +       /** Multiplexer Control Register
 851 +           The value 0 (the reset-value) is always the default function corresponding to the pad's name. The value 1 selects always the GPIO functionality (if available). */
 852 +       unsigned int muxc[32];
 853 +       /** Pull Up Enable Register */
 854 +       unsigned int puen; /* 0x00000080 */
 855 +       /** Pull Down Enable Register */
 856 +       unsigned int pden; /* 0x00000084 */
 857 +       /** Slew Rate Control Register */
 858 +       unsigned int src; /* 0x00000088 */
 859 +       /** Drive Current Control Register */
 860 +       unsigned int dcc; /* 0x0000008C */
 861 +       /** Reserved */
 862 +       unsigned int res_0[24]; /* 0x00000090 */
 863 +       /** Pad Control Availability Register */
 864 +       unsigned int avail; /* 0x000000F0 */
 865 +} gpon_padctrl0_t;
 866 +
 867 +/** register structure for gpio port */
 868 +typedef struct gpon_gpio_s
 869 +{
 870 +       /** Data Output Register
 871 +           Via this register the output values of the different bits can be set if they are switched as outputs. */
 872 +       unsigned int out; /* 0x00000000 */
 873 +       /** Data Input Register
 874 +           Via this register the input values of the different bits can be observed. */
 875 +       unsigned int in; /* 0x00000004 */
 876 +       /** Direction Register
 877 +           Via this register the input direction of the different bits can be determined. */
 878 +       unsigned int dir; /* 0x00000008 */
 879 +       /** Reserved */
 880 +       unsigned int res_0[3]; /* 0x0000000C */
 881 +       /** External Interrupt Control Register 0 */
 882 +       unsigned int exintcr0; /* 0x00000018 */
 883 +       /** External Interrupt Control Register 1 */
 884 +       unsigned int exintcr1; /* 0x0000001C */
 885 +       /** IRN Capture Register
 886 +           This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
 887 +       unsigned int irncr; /* 0x00000020 */
 888 +       /** IRN Interrupt Control Register
 889 +           A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
 890 +       unsigned int irnicr; /* 0x00000024 */
 891 +       /** IRN Interrupt Enable Register
 892 +           This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
 893 +       unsigned int irnen; /* 0x00000028 */
 894 +       /** IRN Interrupt Configuration Register
 895 +           Configures the interrupts bitwise to be edge-senstivie or level-sensitive. */
 896 +       unsigned int irncfg; /* 0x0000002C */
 897 +       /** IRN Interrupt Enable Set Register
 898 +           The corresponding bit in the IRNEN register can be set with an atomic access. */
 899 +       unsigned int irnenset; /* 0x00000030 */
 900 +       /** IRN Interrupt Enable Clear Register
 901 +           The corresponding bit in the IRNEN register can be cleared with an atomic access. */
 902 +       unsigned int irnenclr; /* 0x00000034 */
 903 +       /** Reserved */
 904 +       unsigned int res_1[2]; /* 0x00000038 */
 905 +       /** Output Set Register
 906 +           This register can be used to set certain bits within the OUT register without touching the other bits. */
 907 +       unsigned int outset; /* 0x00000040 */
 908 +       /** Output Clear Register
 909 +           This register can be used to clear certain bits within the OUT register without touching the other bits. */
 910 +       unsigned int outclr; /* 0x00000044 */
 911 +       /** Direction Set Register
 912 +           This register can be used to set certain bits within the DIR register without touching the other bits. */
 913 +       unsigned int dirset; /* 0x00000048 */
 914 +       /** Direction Clear Register
 915 +           This register can be used to clear certain bits within the DIR register without touching the other bits. */
 916 +       unsigned int dirclr; /* 0x0000004C */
 917 +} gpon_gpio_t;
 918 +
 919 +struct falcon_gpio_port {
 920 +       struct gpio_chip gpio_chip;
 921 +       gpon_padctrl0_t __iomem *pad;
 922 +       gpon_gpio_t __iomem *port;
 923 +       struct resource *pad_req;   /* resources requested */
 924 +       struct resource *port_req;
 925 +       unsigned int irq_base;
 926 +       unsigned int chained_irq;
 927 +};
 928 +
 929 +static int gpio_exported = 0;
 930 +static int __init gpio_export_setup(char *str)
 931 +{
 932 +       get_option(&str, &gpio_exported);
 933 +       return 1;
 934 +}
 935 +__setup("gpio_exported=", gpio_export_setup);
 936 +
 937 +static inline struct falcon_gpio_port *to_falcon_gpio_port(struct gpio_chip *chip)
 938 +{
 939 +       return container_of(chip, struct falcon_gpio_port, gpio_chip);
 940 +}
 941 +
 942 +static int falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
 943 +{
 944 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 945 +       gpio_w32(1<<offset, &gpio_port->port->dirclr);
 946 +       return 0;
 947 +}
 948 +
 949 +static int falcon_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
 950 +{
 951 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 952 +       gpio_w32(1<<offset, &gpio_port->port->dirset);
 953 +       return 0;
 954 +}
 955 +
 956 +static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
 957 +{
 958 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 959 +       if (value)
 960 +               gpio_w32(1<<offset, &gpio_port->port->outset);
 961 +       else
 962 +               gpio_w32(1<<offset, &gpio_port->port->outclr);
 963 +}
 964 +
 965 +static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
 966 +{
 967 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 968 +       if ((gpio_r32(&gpio_port->port->dir) >> offset) & 1)
 969 +               return (gpio_r32(&gpio_port->port->out) >> offset) & 1;
 970 +       else
 971 +               return (gpio_r32(&gpio_port->port->in) >> offset) & 1;
 972 +}
 973 +
 974 +static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
 975 +{
 976 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 977 +       if ( (gpio_r32(&gpio_port->pad->avail) >> offset) & 1) {
 978 +               if (gpio_r32(&gpio_port->pad->muxc[offset]) > 1)
 979 +                       return -EBUSY;
 980 +               /* switch on gpio function */
 981 +               gpio_w32(1, &gpio_port->pad->muxc[offset]);
 982 +               return 0;
 983 +       }
 984 +
 985 +       return -ENODEV;
 986 +}
 987 +
 988 +static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
 989 +{
 990 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
 991 +       if ( (gpio_r32(&gpio_port->pad->avail) >> offset) & 1) {
 992 +               if (gpio_r32(&gpio_port->pad->muxc[offset]) > 1)
 993 +                       return;
 994 +               /* switch off gpio function */
 995 +               gpio_w32(0, &gpio_port->pad->muxc[offset]);
 996 +       }
 997 +}
 998 +
 999 +static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1000 +{
1001 +       struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
1002 +       /* no checks: this functions is only registered with valid irq_base */
1003 +       return gpio_port->irq_base + offset;
1004 +}
1005 +
1006 +static void falcon_gpio_disable_irq(struct irq_data *d)
1007 +{
1008 +       struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
1009 +       unsigned int offset = d->irq-gpio_port->irq_base;
1010 +       gpio_w32(1<<offset, &gpio_port->port->irnenclr);
1011 +}
1012 +
1013 +static void falcon_gpio_enable_irq(struct irq_data *d)
1014 +{
1015 +       struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
1016 +       unsigned int offset = d->irq-gpio_port->irq_base;
1017 +
1018 +       if (gpio_r32(&gpio_port->pad->muxc[offset]) < 1) {
1019 +               /* switch on gpio function */
1020 +               gpio_w32(1, &gpio_port->pad->muxc[offset]);
1021 +       }
1022 +
1023 +       gpio_w32(1<<offset, &gpio_port->port->irnenset);
1024 +}
1025 +
1026 +static void falcon_gpio_ack_irq(struct irq_data *d)
1027 +{
1028 +       struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
1029 +       unsigned int offset = d->irq-gpio_port->irq_base;
1030 +       gpio_w32(1<<offset, &gpio_port->port->irncr);
1031 +}
1032 +
1033 +static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
1034 +{
1035 +       struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
1036 +       unsigned int offset = d->irq-gpio_port->irq_base;
1037 +       gpio_w32(1<<offset, &gpio_port->port->irnenclr);
1038 +       gpio_w32(1<<offset, &gpio_port->port->irncr);
1039 +}
1040 +
1041 +static struct irq_chip falcon_gpio_irq_chip;
1042 +static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
1043 +{
1044 +       struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
1045 +       unsigned int offset = d->irq-gpio_port->irq_base;
1046 +       unsigned int mask = 1 << offset;
1047 +
1048 +       if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
1049 +               return 0;
1050 +
1051 +       if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
1052 +               /* level triggered */
1053 +               gpio_w32_mask(0, mask, &gpio_port->port->irncfg);
1054 +               irq_set_chip_and_handler_name(d->irq,
1055 +                               &falcon_gpio_irq_chip, handle_level_irq, "mux");
1056 +       } else {
1057 +               /* edge triggered */
1058 +               gpio_w32_mask(mask, 0, &gpio_port->port->irncfg);
1059 +               irq_set_chip_and_handler_name(d->irq,
1060 +                               &falcon_gpio_irq_chip, handle_simple_irq, "mux");
1061 +       }
1062 +
1063 +       if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1064 +               gpio_w32_mask(mask, 0, &gpio_port->port->exintcr0);
1065 +               gpio_w32_mask(0, mask, &gpio_port->port->exintcr1);
1066 +       } else {
1067 +               if ((type & (IRQ_TYPE_EDGE_RISING |IRQ_TYPE_LEVEL_HIGH)) != 0) {
1068 +                       /* positive logic: rising edge, high level */
1069 +                       gpio_w32_mask(mask, 0, &gpio_port->port->exintcr0);
1070 +               } else {
1071 +                       /* negative logic: falling edge, low level */
1072 +                       gpio_w32_mask(0, mask, &gpio_port->port->exintcr0);
1073 +               }
1074 +               gpio_w32_mask(mask, 0, &gpio_port->port->exintcr1);
1075 +       }
1076 +
1077 +       return gpio_direction_input(gpio_port->gpio_chip.base + offset);
1078 +}
1079 +
1080 +static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1081 +{
1082 +       struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
1083 +       unsigned long irncr;
1084 +       int offset;
1085 +
1086 +       irncr = gpio_r32(&gpio_port->port->irncr);
1087 +       /* acknowledge interrupt */
1088 +       gpio_w32(irncr, &gpio_port->port->irncr);
1089 +
1090 +       desc->irq_data.chip->irq_ack(&desc->irq_data);
1091 +
1092 +       for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
1093 +               generic_handle_irq(gpio_port->irq_base + offset);
1094 +}
1095 +
1096 +static struct irq_chip falcon_gpio_irq_chip = {
1097 +       .name = "gpio_irq_mux",
1098 +       .irq_mask = falcon_gpio_disable_irq,
1099 +       .irq_unmask = falcon_gpio_enable_irq,
1100 +       .irq_ack = falcon_gpio_ack_irq,
1101 +       .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
1102 +       .irq_set_type = falcon_gpio_irq_type,
1103 +};
1104 +
1105 +static struct irqaction gpio_cascade = {
1106 +       .handler = no_action,
1107 +       .flags = IRQF_DISABLED,
1108 +       .name = "gpio_cascade",
1109 +};
1110 +
1111 +static int falcon_gpio_probe(struct platform_device *pdev)
1112 +{
1113 +       struct falcon_gpio_port *gpio_port;
1114 +       int ret, i;
1115 +       struct resource *gpiores, *padres;
1116 +       int irq;
1117 +
1118 +       gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1119 +       padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1120 +       irq = platform_get_irq(pdev, 0);
1121 +       if (!gpiores || !padres)
1122 +               return -ENODEV;
1123 +
1124 +       gpio_port = kzalloc(sizeof(*gpio_port), GFP_KERNEL);
1125 +       if (gpio_port == NULL)
1126 +               return -ENOMEM;
1127 +
1128 +       gpio_port->gpio_chip.label = "falcon-gpio";
1129 +       gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
1130 +       gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
1131 +       gpio_port->gpio_chip.get = falcon_gpio_get;
1132 +       gpio_port->gpio_chip.set = falcon_gpio_set;
1133 +       gpio_port->gpio_chip.request = falcon_gpio_request;
1134 +       gpio_port->gpio_chip.free = falcon_gpio_free;
1135 +       gpio_port->gpio_chip.base = 100 * pdev->id;
1136 +       gpio_port->gpio_chip.ngpio = 32;
1137 +       gpio_port->gpio_chip.dev = &pdev->dev;
1138 +       gpio_port->gpio_chip.exported = gpio_exported;
1139 +
1140 +       gpio_port->port_req = request_mem_region(gpiores->start,
1141 +               resource_size(gpiores), pdev->name);
1142 +       gpio_port->pad_req = request_mem_region(padres->start,
1143 +               resource_size(padres), pdev->name);
1144 +       if (!gpio_port->port_req || !gpio_port->pad_req) {
1145 +               dev_err(&pdev->dev, "cannot claim register area\n");
1146 +               ret = -EIO;
1147 +               goto err;
1148 +       }
1149 +
1150 +       gpio_port->port = ioremap_nocache(gpiores->start,
1151 +               resource_size(gpiores));
1152 +       gpio_port->pad = ioremap_nocache(padres->start,
1153 +               resource_size(padres));
1154 +       if (!gpio_port->port || !gpio_port->pad) {
1155 +               dev_err(&pdev->dev, "Could not map io ranges\n");
1156 +               ret = -ENOMEM;
1157 +               goto err;
1158 +       }
1159 +
1160 +       if (irq>0) {
1161 +               /*
1162 +                * irq_chip support
1163 +                */
1164 +               gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
1165 +               gpio_port->irq_base = INT_NUM_EXTRA_START + 32 * pdev->id;
1166 +
1167 +               for (i = 0; i < 32; i++) {
1168 +                       irq_set_chip_and_handler_name(gpio_port->irq_base + i,
1169 +                               &falcon_gpio_irq_chip, handle_simple_irq, "mux");
1170 +                       irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
1171 +                       /* FIXME: set default cfg to level triggered */
1172 +                       //gpio_w32_mask(0, 1<<i, &gpio_port->port->irncfg);
1173 +                       /* set to negative logic (falling edge, low level) */
1174 +                       gpio_w32_mask(0, 1<<i, &gpio_port->port->exintcr0);
1175 +               }
1176 +
1177 +               gpio_port->chained_irq = irq;
1178 +               setup_irq(irq, &gpio_cascade);
1179 +               irq_set_handler_data(irq, gpio_port);
1180 +               irq_set_chained_handler(irq, falcon_gpio_irq_handler);
1181 +       }
1182 +
1183 +       ret = gpiochip_add(&gpio_port->gpio_chip);
1184 +       if (ret < 0) {
1185 +               dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
1186 +                       pdev->id, ret);
1187 +               goto err;
1188 +       }
1189 +       platform_set_drvdata(pdev, gpio_port);
1190 +       return ret;
1191 +
1192 +err:
1193 +       dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
1194 +       if (gpio_port->port_req)
1195 +               release_resource(gpio_port->port_req);
1196 +       if (gpio_port->pad_req)
1197 +               release_resource(gpio_port->pad_req);
1198 +
1199 +       if (gpio_port->port)
1200 +               iounmap(gpio_port->port);
1201 +       if (gpio_port->pad)
1202 +               iounmap(gpio_port->pad);
1203 +       kfree(gpio_port);
1204 +       return ret;
1205 +}
1206 +
1207 +static int falcon_gpio_remove(struct platform_device *pdev)
1208 +{
1209 +       struct falcon_gpio_port *gpio_port = platform_get_drvdata(pdev);
1210 +       int ret;
1211 +
1212 +       ret = gpiochip_remove(&gpio_port->gpio_chip);
1213 +       if (gpio_port->port_req)
1214 +               release_resource(gpio_port->port_req);
1215 +       if (gpio_port->pad_req)
1216 +               release_resource(gpio_port->pad_req);
1217 +       if (gpio_port->port)
1218 +               iounmap(gpio_port->port);
1219 +       if (gpio_port->pad)
1220 +               iounmap(gpio_port->pad);
1221 +       if (ret == 0)
1222 +               kfree(gpio_port);
1223 +
1224 +       return ret;
1225 +}
1226 +
1227 +static struct platform_driver falcon_gpio_driver = {
1228 +       .probe = falcon_gpio_probe,
1229 +       .remove = __devexit_p(falcon_gpio_remove),
1230 +       .driver = {
1231 +               .name = "falcon_gpio",
1232 +               .owner = THIS_MODULE,
1233 +       },
1234 +};
1235 +
1236 +int __init falcon_gpio_init(void)
1237 +{
1238 +       int ret;
1239 +
1240 +       printk(KERN_INFO "FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
1241 +       ret = platform_driver_register(&falcon_gpio_driver);
1242 +       if (ret)
1243 +               pr_err( "falcon_gpio: Error registering platform driver!");
1244 +       return ret;
1245 +}
1246 +
1247 +void __exit falcon_gpio_exit(void)
1248 +{
1249 +       platform_driver_unregister(&falcon_gpio_driver);
1250 +}
1251 +
1252 +int gpio_to_irq(unsigned int gpio)
1253 +{
1254 +       return __gpio_to_irq(gpio);
1255 +}
1256 +EXPORT_SYMBOL(gpio_to_irq);
1257 +
1258 +module_init(falcon_gpio_init);
1259 +module_exit(falcon_gpio_exit);
1260 --- /dev/null
1261 +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon.h
1262 @@ -0,0 +1,16 @@
1263 +/*
1264 + *   This program is free software; you can redistribute it and/or modify
1265 + *   it under the terms of the GNU General Public License as published by
1266 + *   the Free Software Foundation; either version 2 of the License, or
1267 + *   (at your option) any later version.
1268 + *
1269 + *   Copyright (C) 2005 infineon
1270 + *   Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1271 + */
1272 +
1273 +#ifdef CONFIG_SOC_FALCON
1274 +
1275 +#include <lantiq_soc.h>
1276 +#include <falcon/gpon_reg_base.h>
1277 +
1278 +#endif
1279 --- /dev/null
1280 +++ b/arch/mips/lantiq/falcon/reset.c
1281 @@ -0,0 +1,80 @@
1282 +/*
1283 + * This program is free software; you can redistribute it and/or modify
1284 + * it under the terms of the GNU General Public License as published by
1285 + * the Free Software Foundation; either version 2 of the License, or
1286 + * (at your option) any later version.
1287 + *
1288 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1289 + */
1290 +
1291 +#include <linux/init.h>
1292 +#include <linux/io.h>
1293 +#include <linux/pm.h>
1294 +#include <asm/reboot.h>
1295 +#include <linux/module.h>
1296 +
1297 +#include <falcon.h>
1298 +#include <falcon/gpon_reg_base.h>
1299 +#include <falcon/status_reg.h>
1300 +#include <falcon/sys1_reg.h>
1301 +
1302 +static struct gpon_reg_sys1 * const pSYS1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
1303 +
1304 +#define WDT_PW1                        0x00BE0000
1305 +#define WDT_PW2                        0x00DC0000
1306 +#define WDT_REG_BASE           (KSEG1 | 0x1F8803F0)
1307 +
1308 +/* This function is used by the watchdog driver */
1309 +int ltq_reset_cause(void)
1310 +{
1311 +       return 0;
1312 +}
1313 +EXPORT_SYMBOL_GPL(ltq_reset_cause);
1314 +
1315 +static void
1316 +ltq_machine_restart(char *command)
1317 +{
1318 +       printk(KERN_NOTICE "System restart\n");
1319 +       local_irq_disable();
1320 +       ltq_w32(0, (void*)0xBF200000); /* reset Bootreg RVEC */
1321 +#if 0
1322 +       ltq_w32(RBT_CPU_TRIG, &pSYS1->rbt);
1323 +#else
1324 +       /* use workaround via watchdog timer */
1325 +       ltq_w32(WDT_PW1, (void*)WDT_REG_BASE);
1326 +       ltq_w32(WDT_PW2 |
1327 +               (0x3 << 26) | /* PWL */
1328 +               (0x2 << 24) | /* CLKDIV */
1329 +               (0x1 << 31) | /* enable */
1330 +               (1), /* reload */
1331 +               (void*)WDT_REG_BASE);
1332 +#endif
1333 +       for(;;);
1334 +}
1335 +
1336 +static void
1337 +ltq_machine_halt(void)
1338 +{
1339 +       printk(KERN_NOTICE "System halted.\n");
1340 +       local_irq_disable();
1341 +       for(;;);
1342 +}
1343 +
1344 +static void
1345 +ltq_machine_power_off(void)
1346 +{
1347 +       printk(KERN_NOTICE "Please turn off the power now.\n");
1348 +       local_irq_disable();
1349 +       for(;;);
1350 +}
1351 +
1352 +static int __init
1353 +mips_reboot_setup(void)
1354 +{
1355 +       _machine_restart = ltq_machine_restart;
1356 +       _machine_halt = ltq_machine_halt;
1357 +       pm_power_off = ltq_machine_power_off;
1358 +       return 0;
1359 +}
1360 +
1361 +arch_initcall(mips_reboot_setup);
1362 --- /dev/null
1363 +++ b/arch/mips/lantiq/falcon/mach-easy98000.c
1364 @@ -0,0 +1,263 @@
1365 +#include <linux/init.h>
1366 +#include <linux/platform_device.h>
1367 +#include <linux/leds.h>
1368 +#include <linux/gpio.h>
1369 +#include <linux/gpio_buttons.h>
1370 +#include <linux/etherdevice.h>
1371 +#include <linux/mtd/mtd.h>
1372 +#include <linux/mtd/partitions.h>
1373 +#include <linux/mtd/physmap.h>
1374 +#include <linux/input.h>
1375 +#include <linux/interrupt.h>
1376 +#include <linux/dm9000.h>
1377 +#include <linux/i2c.h>
1378 +#include <linux/i2c-gpio.h>
1379 +#include <linux/spi/spi.h>
1380 +#include <linux/spi/spi_gpio.h>
1381 +#include <linux/spi/eeprom.h>
1382 +
1383 +#include "../machtypes.h"
1384 +
1385 +#include "devices.h"
1386 +#include "dev-leds-gpio.h"
1387 +
1388 +#define EASY98000_GPIO_LED_0 9
1389 +#define EASY98000_GPIO_LED_1 10
1390 +#define EASY98000_GPIO_LED_2 11
1391 +#define EASY98000_GPIO_LED_3 12
1392 +#define EASY98000_GPIO_LED_4 13
1393 +#define EASY98000_GPIO_LED_5 14
1394 +
1395 +extern unsigned char ltq_ethaddr[6];
1396 +
1397 +#ifdef CONFIG_MTD_PARTITIONS
1398 +static struct mtd_partition easy98000_nor_partitions[] =
1399 +{
1400 +       {
1401 +               .name   = "uboot",
1402 +               .offset = 0x0,
1403 +               .size   = 0x40000,
1404 +       },
1405 +       {
1406 +               .name   = "uboot_env",
1407 +               .offset = 0x40000,
1408 +               .size   = 0x40000,      /* 2 sectors for redundant env. */
1409 +       },
1410 +       {
1411 +               .name   = "linux",
1412 +               .offset = 0x80000,
1413 +               .size   = 0xF80000,     /* map only 16 MiB */
1414 +       },
1415 +};
1416 +#endif
1417 +
1418 +static struct physmap_flash_data easy98000_nor_flash_data = {
1419 +#ifdef CONFIG_MTD_PARTITIONS
1420 +       .nr_parts       = ARRAY_SIZE(easy98000_nor_partitions),
1421 +       .parts          = easy98000_nor_partitions,
1422 +#endif
1423 +};
1424 +
1425 +#ifdef CONFIG_MTD_PARTITIONS
1426 +static struct flash_platform_data easy98000_spi_flash_platform_data = {
1427 +       .name = "sflash",
1428 +       .parts = easy98000_nor_partitions,
1429 +       .nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
1430 +};
1431 +#endif
1432 +
1433 +static struct spi_board_info easy98000_spi_flash_data __initdata = {
1434 +       .modalias               = "m25p80",
1435 +       .bus_num                = 0,
1436 +       .chip_select            = 0,
1437 +       .max_speed_hz           = 10 * 1000 * 1000,
1438 +       .mode                   = SPI_MODE_3,
1439 +#ifdef CONFIG_MTD_PARTITIONS
1440 +       .platform_data          = &easy98000_spi_flash_platform_data
1441 +#endif
1442 +};
1443 +
1444 +static struct gpio_led easy98000_leds_gpio[] __initdata = {
1445 +       {
1446 +               .name           = "easy98000:green:0",
1447 +               .gpio           = EASY98000_GPIO_LED_0,
1448 +               .active_low     = 0,
1449 +       }, {
1450 +               .name           = "easy98000:green:1",
1451 +               .gpio           = EASY98000_GPIO_LED_1,
1452 +               .active_low     = 0,
1453 +       }, {
1454 +               .name           = "easy98000:green:2",
1455 +               .gpio           = EASY98000_GPIO_LED_2,
1456 +               .active_low     = 0,
1457 +       }, {
1458 +               .name           = "easy98000:green:3",
1459 +               .gpio           = EASY98000_GPIO_LED_3,
1460 +               .active_low     = 0,
1461 +       }, {
1462 +               .name           = "easy98000:green:4",
1463 +               .gpio           = EASY98000_GPIO_LED_4,
1464 +               .active_low     = 0,
1465 +       }, {
1466 +               .name           = "easy98000:green:5",
1467 +               .gpio           = EASY98000_GPIO_LED_5,
1468 +               .active_low     = 0,
1469 +       }
1470 +};
1471 +
1472 +#define CONFIG_DM9000_BASE             0x14000000
1473 +#define DM9000_IO                      (CONFIG_DM9000_BASE + 3)
1474 +#define DM9000_DATA                    (CONFIG_DM9000_BASE + 1)
1475 +
1476 +static struct dm9000_plat_data dm9000_plat_data = {
1477 +       .flags = DM9000_PLATF_8BITONLY,
1478 +       //.dev_addr = { }, /* possibility to provide an ethernet address for the chip */
1479 +};
1480 +
1481 +static struct resource dm9000_resources[] = {
1482 +       MEM_RES("dm9000_io", DM9000_IO, DM9000_IO),
1483 +       MEM_RES("dm9000_data", DM9000_DATA, DM9000_DATA),
1484 +       [2] = {
1485 +               /* with irq (210 -> gpio 110) the driver is very unreliable */
1486 +               .start  = -1,           /* use polling */
1487 +               .end    = -1,
1488 +               .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
1489 +       },
1490 +};
1491 +
1492 +static struct platform_device dm9000_platform = {
1493 +       .name = "dm9000",
1494 +       .id = 0,
1495 +       .num_resources  = ARRAY_SIZE(dm9000_resources),
1496 +       .resource       = dm9000_resources,
1497 +       .dev = {
1498 +               .platform_data = (void *) &dm9000_plat_data,
1499 +       }
1500 +};
1501 +
1502 +extern int easy98000_addon_has_dm9000(void);
1503 +static void __init register_davicom(void)
1504 +{
1505 +       if (!easy98000_addon_has_dm9000())
1506 +               return;
1507 +
1508 +       if (!is_valid_ether_addr(ltq_ethaddr))
1509 +               random_ether_addr(dm9000_plat_data.dev_addr);
1510 +       else {
1511 +               memcpy(dm9000_plat_data.dev_addr, ltq_ethaddr, 6);
1512 +               /* change to "Locally Administered Address" */
1513 +               dm9000_plat_data.dev_addr[0] |= 0x2;
1514 +       }
1515 +       platform_device_register(&dm9000_platform);
1516 +}
1517 +
1518 +static struct i2c_gpio_platform_data easy98000_i2c_gpio_data = {
1519 +       .sda_pin        = 107,
1520 +       .scl_pin        = 108,
1521 +};
1522 +
1523 +static struct platform_device easy98000_i2c_gpio_device = {
1524 +       .name           = "i2c-gpio",
1525 +       .id             = 0,
1526 +       .dev = {
1527 +               .platform_data  = &easy98000_i2c_gpio_data,
1528 +       }
1529 +};
1530 +
1531 +void __init register_easy98000_cpld(void)
1532 +{
1533 +       platform_device_register_simple("easy98000_cpld_led", 0, NULL, 0);
1534 +       platform_device_register_simple("easy98000_addon", 0, NULL, 0);
1535 +}
1536 +
1537 +/* setup gpio based spi bus/device for access to the eeprom on the board */
1538 +#define SPI_GPIO_MRST  102
1539 +#define SPI_GPIO_MTSR  103
1540 +#define SPI_GPIO_CLK   104
1541 +#define SPI_GPIO_CS0   105
1542 +#define SPI_GPIO_CS1   106
1543 +#define SPI_GPIO_BUS_NUM       1
1544 +
1545 +static struct spi_gpio_platform_data easy98000_spi_gpio_data = {
1546 +       .sck            = SPI_GPIO_CLK,
1547 +       .mosi           = SPI_GPIO_MTSR,
1548 +       .miso           = SPI_GPIO_MRST,
1549 +       .num_chipselect = 2,
1550 +};
1551 +
1552 +static struct platform_device easy98000_spi_gpio_device = {
1553 +       .name                   = "spi_gpio",
1554 +       .id                     = SPI_GPIO_BUS_NUM,
1555 +       .dev.platform_data      = &easy98000_spi_gpio_data,
1556 +};
1557 +
1558 +static struct spi_eeprom at25160n = {
1559 +       .byte_len       = 16 * 1024 / 8,
1560 +       .name           = "at25160n",
1561 +       .page_size      = 32,
1562 +       .flags          = EE_ADDR2,
1563 +};
1564 +
1565 +static struct spi_board_info easy98000_spi_gpio_devices __initdata = {
1566 +       .modalias               = "at25",
1567 +       .bus_num                = SPI_GPIO_BUS_NUM,
1568 +       .max_speed_hz           = 1000 * 1000,
1569 +       .mode                   = SPI_MODE_3,
1570 +       .chip_select            = 1,
1571 +       .controller_data        = (void *) SPI_GPIO_CS1,
1572 +       .platform_data          = &at25160n,
1573 +};
1574 +
1575 +static void __init easy98000_spi_gpio_init(void)
1576 +{
1577 +       spi_register_board_info(&easy98000_spi_gpio_devices, 1);
1578 +       platform_device_register(&easy98000_spi_gpio_device);
1579 +}
1580 +
1581 +static void __init easy98000_init_common(void)
1582 +{
1583 +       falcon_register_asc(0);
1584 +       falcon_register_gpio();
1585 +       falcon_register_wdt();
1586 +       falcon_register_i2c();
1587 +       platform_device_register(&easy98000_i2c_gpio_device);
1588 +       register_davicom();
1589 +       ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98000_leds_gpio),
1590 +                                       easy98000_leds_gpio);
1591 +       register_easy98000_cpld();
1592 +       falcon_register_crypto();
1593 +       easy98000_spi_gpio_init();
1594 +}
1595 +
1596 +static void __init easy98000_init(void)
1597 +{
1598 +       easy98000_init_common();
1599 +       falcon_register_nor(&easy98000_nor_flash_data);
1600 +}
1601 +
1602 +static void __init easy98000sf_init(void)
1603 +{
1604 +       easy98000_init_common();
1605 +       falcon_register_spi_flash(&easy98000_spi_flash_data);
1606 +}
1607 +
1608 +static void __init easy98000nand_init(void)
1609 +{
1610 +       easy98000_init_common();
1611 +       falcon_register_nand();
1612 +}
1613 +
1614 +MIPS_MACHINE(LANTIQ_MACH_EASY98000,
1615 +                       "EASY98000",
1616 +                       "EASY98000 Eval Board",
1617 +                       easy98000_init);
1618 +
1619 +MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
1620 +                       "EASY98000SF",
1621 +                       "EASY98000 Eval Board (Serial Flash)",
1622 +                       easy98000sf_init);
1623 +
1624 +MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
1625 +                       "EASY98000NAND",
1626 +                       "EASY98000 Eval Board (NAND Flash)",
1627 +                       easy98000nand_init);
1628 --- /dev/null
1629 +++ b/arch/mips/lantiq/falcon/softdog_vpe.c
1630 @@ -0,0 +1,109 @@
1631 +/*
1632 +** =============================================================================
1633 +** FILE NAME     : softdog_vpe.c
1634 +** MODULES       : LXDB
1635 +** DATE          : 24-03-2008
1636 +** AUTHOR        : LXDB Team
1637 +** DESCRIPTION   : This header file contains the code for the watchdog
1638 +**                 implentation on vpe1 side.
1639 +** REFERENCES    :
1640 +** COPYRIGHT     : Copyright (c) 2008
1641 +**                 Am Campeon 1-12, 85579 Neubiberg, Germany
1642 +** Any use of this software is subject to the conclusion of a respective
1643 +** License agreement. Without such a License agreement no rights to the
1644 +** software are granted
1645 +**
1646 +** HISTORY       :
1647 +** $Date   $Author    $Comment
1648 +** 24-03-2008   LXDB    Initial version
1649 +** ============================================================================
1650 +*/
1651 +
1652 +#include <linux/module.h>
1653 +#include <linux/moduleparam.h>
1654 +#include <linux/types.h>
1655 +#include <linux/timer.h>
1656 +#include <linux/reboot.h>
1657 +#include <linux/init.h>
1658 +#include <linux/jiffies.h>
1659 +
1660 +#include <falcon/vpe.h>
1661 +
1662 +static unsigned long last_wdog_value;
1663 +static unsigned long vpe1_wdog_cleared;
1664 +
1665 +static unsigned long vpe1_wdog_dead;
1666 +static void watchdog_vpe0_fire(unsigned long); /* Called when vpe0 timer expires */
1667 +static void keep_alive_vpe0(unsigned long);
1668 +VPE_SW_WDOG_RESET reset_local_fn;
1669 +
1670 +
1671 +static struct timer_list watchdog_vpe0_ticktock =
1672 +                TIMER_INITIALIZER(watchdog_vpe0_fire, 0, 0);
1673 +
1674 +static void watchdog_vpe0_fire (unsigned long flags)
1675 +{
1676 +       volatile unsigned long *wdog_ctr_value;
1677 +       wdog_ctr_value = (void*)vpe1_wdog_ctr;
1678 +       if (*wdog_ctr_value == last_wdog_value) { /* VPE1 watchdog expiry handling */
1679 +               vpe1_sw_wdog_stop(flags);
1680 +               vpe1_wdog_dead++;
1681 +               printk(KERN_DEBUG "VPE1 watchdog reset handler called\n");
1682 +       /* Call the reset handler function */
1683 +               reset_local_fn(flags);
1684 +       } else { /* Everything is OK on vpe1 side. Continue. */
1685 +               last_wdog_value = *wdog_ctr_value;
1686 +               vpe1_wdog_cleared++;
1687 +               keep_alive_vpe0(flags);
1688 +       }
1689 +}
1690 +
1691 +int32_t vpe1_sw_wdog_register_reset_handler (VPE_SW_WDOG_RESET reset_fn)
1692 +{
1693 +       reset_local_fn = (VPE_SW_WDOG_RESET)reset_fn;
1694 +       return 0;
1695 +}
1696 +
1697 +static void keep_alive_vpe0(unsigned long flags)
1698 +{
1699 +       mod_timer(&watchdog_vpe0_ticktock, jiffies+ vpe1_wdog_timeout );
1700 +}
1701 +
1702 +unsigned long vpe1_sw_wdog_start(unsigned long flags)
1703 +{
1704 +       volatile unsigned long *wdog_ctr_value;
1705 +       wdog_ctr_value = (void*)vpe1_wdog_ctr;
1706 +       *wdog_ctr_value = 0;
1707 +       last_wdog_value = 0;
1708 +       keep_alive_vpe0(flags);
1709 +       return 0;
1710 +}
1711 +
1712 +unsigned long vpe1_sw_wdog_stop(unsigned long flags)
1713 +{
1714 +       del_timer(&watchdog_vpe0_ticktock);
1715 +       return 0;
1716 +}
1717 +
1718 +static int __init watchdog_vpe1_init(void)
1719 +{
1720 +       /* Nothing to be done here */
1721 +       return 0;
1722 +}
1723 +
1724 +static void __exit watchdog_vpe1_exit(void)
1725 +{
1726 +       unsigned long flags=0;
1727 +       vpe1_sw_wdog_stop(flags);
1728 +}
1729 +
1730 +module_init(watchdog_vpe1_init);
1731 +module_exit(watchdog_vpe1_exit);
1732 +
1733 +EXPORT_SYMBOL(vpe1_sw_wdog_register_reset_handler);
1734 +EXPORT_SYMBOL(vpe1_sw_wdog_start);
1735 +EXPORT_SYMBOL(vpe1_sw_wdog_stop);
1736 +
1737 +MODULE_AUTHOR("LXDB");
1738 +MODULE_DESCRIPTION("Software Watchdog For VPE1");
1739 +MODULE_LICENSE("GPL");
1740 --- /dev/null
1741 +++ b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h
1742 @@ -0,0 +1,44 @@
1743 +/*
1744 + *   This program is free software; you can redistribute it and/or modify
1745 + *   it under the terms of the GNU General Public License as published by
1746 + *   the Free Software Foundation; either version 2 of the License, or
1747 + *   (at your option) any later version.
1748 + *
1749 + *   This program is distributed in the hope that it will be useful,
1750 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1751 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1752 + *   GNU General Public License for more details.
1753 + *
1754 + *   You should have received a copy of the GNU General Public License
1755 + *   along with this program; if not, write to the Free Software
1756 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1757 + *
1758 + *   Copyright (C) 2005 infineon
1759 + *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
1760 + *
1761 + */
1762 +#ifndef _IFXMIPS_VPE_H__
1763 +#define _IFXMIPS_VPE_H__
1764 +
1765 +/* For the explanation of the APIs please refer the section "MT APRP Kernel
1766 + * Programming" in AR9 SW Architecture Specification
1767 + */
1768 +int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags);
1769 +int32_t vpe1_sw_stop(uint32_t flags);
1770 +uint32_t vpe1_get_load_addr (uint32_t flags);
1771 +uint32_t vpe1_get_max_mem (uint32_t flags);
1772 +
1773 +int32_t vpe1_set_boot_param(char *field, char *value, char flags);
1774 +int32_t vpe1_get_boot_param(char *field, char **value, char flags);
1775 +
1776 +/* Watchdog APIs */
1777 +extern unsigned long vpe1_wdog_ctr;
1778 +extern unsigned long vpe1_wdog_timeout;
1779 +
1780 +unsigned long vpe1_sw_wdog_start(unsigned long);
1781 +unsigned long vpe1_sw_wdog_stop(unsigned long);
1782 +
1783 +typedef int (*VPE_SW_WDOG_RESET)(unsigned long wdog_cleared_ok_count);
1784 +int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn);
1785 +
1786 +#endif
1787 --- a/arch/mips/lantiq/Kconfig
1788 +++ b/arch/mips/lantiq/Kconfig
1789 @@ -16,8 +16,12 @@ config SOC_XWAY
1790         bool "XWAY"
1791         select SOC_TYPE_XWAY
1792         select HW_HAS_PCI
1793 +
1794 +config SOC_FALCON
1795 +       bool "FALCON"
1796  endchoice
1797
1798  source "arch/mips/lantiq/xway/Kconfig"
1799 +source "arch/mips/lantiq/falcon/Kconfig"
1800
1801  endif
1802 --- a/arch/mips/lantiq/Makefile
1803 +++ b/arch/mips/lantiq/Makefile
1804 @@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devi
1805  obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
1806
1807  obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
1808 +obj-$(CONFIG_SOC_FALCON) += falcon/
1809 --- a/arch/mips/lantiq/Platform
1810 +++ b/arch/mips/lantiq/Platform
1811 @@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ)       += lantiq/
1812  cflags-$(CONFIG_LANTIQ)                += -I$(srctree)/arch/mips/include/asm/mach-lantiq
1813  load-$(CONFIG_LANTIQ)          = 0xffffffff80002000
1814  cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
1815 +cflags-$(CONFIG_SOC_FALCON)    += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
1816 --- a/arch/mips/lantiq/machtypes.h
1817 +++ b/arch/mips/lantiq/machtypes.h
1818 @@ -15,6 +15,12 @@ enum lantiq_mach_type {
1819         LTQ_MACH_GENERIC = 0,
1820         LTQ_MACH_EASY50712,     /* Danube evaluation board */
1821         LTQ_MACH_EASY50601,     /* Amazon SE evaluation board */
1822 +
1823 +       /* FALCON */
1824 +       LANTIQ_MACH_EASY98000,          /* Falcon Eval Board, NOR Flash */
1825 +       LANTIQ_MACH_EASY98000SF,        /* Falcon Eval Board, Serial Flash */
1826 +       LANTIQ_MACH_EASY98000NAND,      /* Falcon Eval Board, NAND Flash */
1827 +       LANTIQ_MACH_EASY98020,          /* Falcon Reference Board */
1828  };
1829
1830  #endif
1831 --- /dev/null
1832 +++ b/arch/mips/lantiq/falcon/addon-easy98000.c
1833 @@ -0,0 +1,212 @@
1834 +/*
1835 + *  EASY98000 CPLD Addon driver
1836 + *
1837 + *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
1838 + *
1839 + *  This program is free software; you can redistribute it and/or modify it
1840 + *  under the terms of the GNU General Public License version 2  as published
1841 + *  by the Free Software Foundation.
1842 + *
1843 + */
1844 +
1845 +#include <linux/kernel.h>
1846 +#include <linux/version.h>
1847 +#include <linux/types.h>
1848 +#include <linux/init.h>
1849 +#include <linux/platform_device.h>
1850 +#include <linux/errno.h>
1851 +#include <linux/slab.h>
1852 +#include <linux/proc_fs.h>
1853 +#include <linux/seq_file.h>
1854 +
1855 +struct easy98000_reg_cpld {
1856 +       u16 cmdreg1;            /* 0x1 */
1857 +       u16 cmdreg0;            /* 0x0 */
1858 +       u16 idreg0;             /* 0x3 */
1859 +       u16 resreg;             /* 0x2 */
1860 +       u16 intreg;             /* 0x5 */
1861 +       u16 idreg1;             /* 0x4 */
1862 +       u16 ledreg;             /* 0x7 */
1863 +       u16 pcmconconfig;       /* 0x6 */
1864 +       u16 res0;               /* 0x9 */
1865 +       u16 ethledreg;          /* 0x8 */
1866 +       u16 res1[4];            /* 0xa-0xd */
1867 +       u16 cpld1v;             /* 0xf */
1868 +       u16 cpld2v;             /* 0xe */
1869 +};
1870 +static struct easy98000_reg_cpld * const cpld =
1871 +       (struct easy98000_reg_cpld *)(KSEG1 | 0x17c00000);
1872 +#define cpld_r8(reg) (__raw_readw(&cpld->reg) & 0xFF)
1873 +#define cpld_w8(val, reg) __raw_writew((val) & 0xFF, &cpld->reg)
1874 +
1875 +int easy98000_addon_has_dm9000(void)
1876 +{
1877 +       if ((cpld_r8(idreg0) & 0xF) == 1)
1878 +               return 1;
1879 +       return 0;
1880 +}
1881 +
1882 +#if defined(CONFIG_PROC_FS)
1883 +typedef void (*cpld_dump) (struct seq_file *s);
1884 +struct proc_entry {
1885 +       char *name;
1886 +       void *callback;
1887 +};
1888 +
1889 +static int cpld_proc_show ( struct seq_file *s, void *p )
1890 +{
1891 +       cpld_dump dump = s->private;
1892 +
1893 +       if ( dump != NULL )
1894 +               dump(s);
1895 +
1896 +       return 0;
1897 +}
1898 +
1899 +static int cpld_proc_open ( struct inode *inode, struct file *file )
1900 +{
1901 +       return single_open ( file, cpld_proc_show, PDE(inode)->data );
1902 +}
1903 +
1904 +static void cpld_versions_get ( struct seq_file *s )
1905 +{
1906 +       seq_printf(s, "CPLD1: V%d\n", cpld_r8(cpld1v));
1907 +       seq_printf(s, "CPLD2: V%d\n", cpld_r8(cpld2v));
1908 +}
1909 +
1910 +static void cpld_ebu_module_get ( struct seq_file *s )
1911 +{
1912 +       u8 addon_id;
1913 +
1914 +       addon_id = cpld_r8(idreg0) & 0xF;
1915 +       switch (addon_id) {
1916 +       case 0xF: /* nothing connected */
1917 +               break;
1918 +       case 1:
1919 +               seq_printf(s, "Ethernet Controller module (dm9000)\n");
1920 +               break;
1921 +       default:
1922 +               seq_printf(s, "Unknown EBU module (EBU_ID=0x%02X)\n", addon_id);
1923 +               break;
1924 +       }
1925 +}
1926 +
1927 +static void cpld_xmii_module_get ( struct seq_file *s )
1928 +{
1929 +       u8 addon_id;
1930 +       char *mod = NULL;
1931 +
1932 +       addon_id = cpld_r8(idreg1) & 0xF;
1933 +       switch (addon_id) {
1934 +       case 0xF:
1935 +               mod = "no module";
1936 +               break;
1937 +       case 0x1:
1938 +               mod = "RGMII module";
1939 +               break;
1940 +       case 0x4:
1941 +               mod = "GMII MAC Mode (XWAY TANTOS-3G)";
1942 +               break;
1943 +       case 0x6:
1944 +               mod = "TMII MAC Mode (XWAY TANTOS-3G)";
1945 +               break;
1946 +       case 0x8:
1947 +               mod = "GMII PHY module";
1948 +               break;
1949 +       case 0x9:
1950 +               mod = "MII PHY module";
1951 +               break;
1952 +       case 0xA:
1953 +               mod = "RMII PHY module";
1954 +               break;
1955 +       default:
1956 +               break;
1957 +       }
1958 +       if (mod)
1959 +               seq_printf(s, "%s\n", mod);
1960 +       else
1961 +               seq_printf(s, "unknown xMII module (xMII_ID=0x%02X)\n", addon_id);
1962 +}
1963 +
1964 +static struct proc_entry proc_entries[] = {
1965 +       {"versions",    cpld_versions_get},
1966 +       {"ebu",         cpld_ebu_module_get},
1967 +       {"xmii",        cpld_xmii_module_get},
1968 +};
1969 +
1970 +static struct file_operations ops = {
1971 +       .owner   = THIS_MODULE,
1972 +       .open    = cpld_proc_open,
1973 +       .read    = seq_read,
1974 +       .llseek  = seq_lseek,
1975 +       .release = single_release,
1976 +};
1977 +
1978 +static void cpld_proc_entry_create(struct proc_dir_entry *parent_node,
1979 +                                  struct proc_entry *proc_entry)
1980 +{
1981 +       proc_create_data ( proc_entry->name, (S_IFREG | S_IRUGO), parent_node,
1982 +                          &ops, proc_entry->callback);
1983 +}
1984 +
1985 +static int cpld_proc_install(void)
1986 +{
1987 +       struct proc_dir_entry *driver_proc_node;
1988 +
1989 +       driver_proc_node = proc_mkdir("cpld", NULL);
1990 +       if (driver_proc_node != NULL) {
1991 +               int i;
1992 +               for (i = 0; i < ARRAY_SIZE(proc_entries); i++)
1993 +                       cpld_proc_entry_create(driver_proc_node,
1994 +                                             &proc_entries[i]);
1995 +       } else {
1996 +               printk("cannot create proc entry");
1997 +               return -1;
1998 +       }
1999 +       return 0;
2000 +}
2001 +#else
2002 +static inline int cpld_proc_install(void) {}
2003 +#endif
2004 +
2005 +static int easy98000_addon_probe(struct platform_device *pdev)
2006 +{
2007 +       return cpld_proc_install();
2008 +}
2009 +
2010 +static int easy98000_addon_remove(struct platform_device *pdev)
2011 +{
2012 +#if defined(CONFIG_PROC_FS)
2013 +       char buf[64];
2014 +       int i;
2015 +
2016 +       for (i = 0; i < sizeof(proc_entries) / sizeof(proc_entries[0]); i++) {
2017 +               sprintf(buf, "cpld/%s", proc_entries[i].name);
2018 +               remove_proc_entry(buf, 0);
2019 +       }
2020 +       remove_proc_entry("cpld", 0);
2021 +#endif
2022 +       return 0;
2023 +}
2024 +
2025 +static struct platform_driver easy98000_addon_driver = {
2026 +       .probe = easy98000_addon_probe,
2027 +       .remove = __devexit_p(easy98000_addon_remove),
2028 +       .driver = {
2029 +               .name = "easy98000_addon",
2030 +               .owner = THIS_MODULE,
2031 +       },
2032 +};
2033 +
2034 +int __init easy98000_addon_init(void)
2035 +{
2036 +       return platform_driver_register(&easy98000_addon_driver);
2037 +}
2038 +
2039 +void __exit easy98000_addon_exit(void)
2040 +{
2041 +       platform_driver_unregister(&easy98000_addon_driver);
2042 +}
2043 +
2044 +module_init(easy98000_addon_init);
2045 +module_exit(easy98000_addon_exit);