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[package] mac80211: update compat-wireless to 2009-03-05, add more rt2x00 and ath9k...
[openwrt.git] / package / mac80211 / patches / 302-rt2x00-Implement-support-for-rt2800pci.patch
1 From b11cae133872a0ff531a1d2646f1e46378510fe0 Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Tue, 3 Mar 2009 19:18:56 +0100
4 Subject: [PATCH] rt2x00: Implement support for rt2800pci
5
6 Add support for the rt2800pci chipset.
7
8 Includes various patches from Mattias, Mark, Felix and Xose.
9
10 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
11 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
12 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
13 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
15 ---
16 drivers/net/wireless/rt2x00/Kconfig | 15 +
17 drivers/net/wireless/rt2x00/Makefile | 1 +
18 drivers/net/wireless/rt2x00/rt2800pci.c | 2831 +++++++++++++++++++++++++++++++
19 drivers/net/wireless/rt2x00/rt2800pci.h | 1867 ++++++++++++++++++++
20 drivers/net/wireless/rt2x00/rt2x00.h | 4 +
21 5 files changed, 4718 insertions(+), 0 deletions(-)
22 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
23 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
24
25 --- a/drivers/net/wireless/rt2x00/Makefile
26 +++ b/drivers/net/wireless/rt2x00/Makefile
27 @@ -16,5 +16,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
28 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
29 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
30 obj-$(CONFIG_RT61PCI) += rt61pci.o
31 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
32 obj-$(CONFIG_RT2500USB) += rt2500usb.o
33 obj-$(CONFIG_RT73USB) += rt73usb.o
34 --- /dev/null
35 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
36 @@ -0,0 +1,2831 @@
37 +/*
38 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
39 + <http://rt2x00.serialmonkey.com>
40 +
41 + This program is free software; you can redistribute it and/or modify
42 + it under the terms of the GNU General Public License as published by
43 + the Free Software Foundation; either version 2 of the License, or
44 + (at your option) any later version.
45 +
46 + This program is distributed in the hope that it will be useful,
47 + but WITHOUT ANY WARRANTY; without even the implied warranty of
48 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
49 + GNU General Public License for more details.
50 +
51 + You should have received a copy of the GNU General Public License
52 + along with this program; if not, write to the
53 + Free Software Foundation, Inc.,
54 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
55 + */
56 +
57 +/*
58 + Module: rt2800pci
59 + Abstract: rt2800pci device specific routines.
60 + Supported chipsets: RT2800E & RT2800ED.
61 + */
62 +
63 +#include <linux/crc-ccitt.h>
64 +#include <linux/delay.h>
65 +#include <linux/etherdevice.h>
66 +#include <linux/init.h>
67 +#include <linux/kernel.h>
68 +#include <linux/module.h>
69 +#include <linux/pci.h>
70 +#include <linux/eeprom_93cx6.h>
71 +
72 +#include "rt2x00.h"
73 +#include "rt2x00pci.h"
74 +#include "rt2800pci.h"
75 +
76 +/*
77 + * Allow hardware encryption to be disabled.
78 + */
79 +static int modparam_nohwcrypt = 0;
80 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
81 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82 +
83 +/*
84 + * Register access.
85 + * BBP and RF register require indirect register access,
86 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
87 + * These indirect registers work with busy bits,
88 + * and we will try maximal REGISTER_BUSY_COUNT times to access
89 + * the register while taking a REGISTER_BUSY_DELAY us delay
90 + * between each attampt. When the busy bit is still set at that time,
91 + * the access attempt is considered to have failed,
92 + * and we will print an error.
93 + */
94 +#define WAIT_FOR_BBP(__dev, __reg) \
95 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
96 +#define WAIT_FOR_RF(__dev, __reg) \
97 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
98 +#define WAIT_FOR_MCU(__dev, __reg) \
99 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
100 + H2M_MAILBOX_CSR_OWNER, (__reg))
101 +
102 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
103 + const unsigned int word, const u8 value)
104 +{
105 + u32 reg;
106 +
107 + mutex_lock(&rt2x00dev->csr_mutex);
108 +
109 + /*
110 + * Wait until the BBP becomes available, afterwards we
111 + * can safely write the new data into the register.
112 + */
113 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
114 + reg = 0;
115 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
116 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
117 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
118 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
119 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
120 +
121 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
122 + }
123 +
124 + mutex_unlock(&rt2x00dev->csr_mutex);
125 +}
126 +
127 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
128 + const unsigned int word, u8 *value)
129 +{
130 + u32 reg;
131 +
132 + mutex_lock(&rt2x00dev->csr_mutex);
133 +
134 + /*
135 + * Wait until the BBP becomes available, afterwards we
136 + * can safely write the read request into the register.
137 + * After the data has been written, we wait until hardware
138 + * returns the correct value, if at any time the register
139 + * doesn't become available in time, reg will be 0xffffffff
140 + * which means we return 0xff to the caller.
141 + */
142 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
143 + reg = 0;
144 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
145 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
146 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
147 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
148 +
149 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
150 +
151 + WAIT_FOR_BBP(rt2x00dev, &reg);
152 + }
153 +
154 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
155 +
156 + mutex_unlock(&rt2x00dev->csr_mutex);
157 +}
158 +
159 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
160 + const unsigned int word, const u32 value)
161 +{
162 + u32 reg;
163 +
164 + mutex_lock(&rt2x00dev->csr_mutex);
165 +
166 + /*
167 + * Wait until the RF becomes available, afterwards we
168 + * can safely write the new data into the register.
169 + */
170 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
171 + reg = 0;
172 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
173 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
174 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
175 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
176 +
177 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
178 + rt2x00_rf_write(rt2x00dev, word, value);
179 + }
180 +
181 + mutex_unlock(&rt2x00dev->csr_mutex);
182 +}
183 +
184 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
185 + const u8 command, const u8 token,
186 + const u8 arg0, const u8 arg1)
187 +{
188 + u32 reg;
189 +
190 + mutex_lock(&rt2x00dev->csr_mutex);
191 +
192 + /*
193 + * Wait until the MCU becomes available, afterwards we
194 + * can safely write the new data into the register.
195 + */
196 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
197 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
198 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
199 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
200 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
201 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
202 +
203 + reg = 0;
204 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
205 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
206 + }
207 +
208 + mutex_unlock(&rt2x00dev->csr_mutex);
209 +}
210 +
211 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
212 +{
213 + struct rt2x00_dev *rt2x00dev = eeprom->data;
214 + u32 reg;
215 +
216 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
217 +
218 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
219 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
220 + eeprom->reg_data_clock =
221 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
222 + eeprom->reg_chip_select =
223 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
224 +}
225 +
226 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
227 +{
228 + struct rt2x00_dev *rt2x00dev = eeprom->data;
229 + u32 reg = 0;
230 +
231 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
232 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
233 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
234 + !!eeprom->reg_data_clock);
235 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
236 + !!eeprom->reg_chip_select);
237 +
238 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
239 +}
240 +
241 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
242 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
243 + .owner = THIS_MODULE,
244 + .csr = {
245 + .read = rt2x00pci_register_read,
246 + .write = rt2x00pci_register_write,
247 + .flags = RT2X00DEBUGFS_OFFSET,
248 + .word_base = CSR_REG_BASE,
249 + .word_size = sizeof(u32),
250 + .word_count = CSR_REG_SIZE / sizeof(u32),
251 + },
252 + .eeprom = {
253 + .read = rt2x00_eeprom_read,
254 + .write = rt2x00_eeprom_write,
255 + .word_base = EEPROM_BASE,
256 + .word_size = sizeof(u16),
257 + .word_count = EEPROM_SIZE / sizeof(u16),
258 + },
259 + .bbp = {
260 + .read = rt2800pci_bbp_read,
261 + .write = rt2800pci_bbp_write,
262 + .word_base = BBP_BASE,
263 + .word_size = sizeof(u8),
264 + .word_count = BBP_SIZE / sizeof(u8),
265 + },
266 + .rf = {
267 + .read = rt2x00_rf_read,
268 + .write = rt2800pci_rf_write,
269 + .word_base = RF_BASE,
270 + .word_size = sizeof(u32),
271 + .word_count = RF_SIZE / sizeof(u32),
272 + },
273 +};
274 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
275 +
276 +#ifdef CONFIG_RT2X00_LIB_RFKILL
277 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
278 +{
279 + u32 reg;
280 +
281 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
282 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
283 +}
284 +#else
285 +#define rt2800pci_rfkill_poll NULL
286 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
287 +
288 +#ifdef CONFIG_RT2X00_LIB_LEDS
289 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
290 + enum led_brightness brightness)
291 +{
292 + struct rt2x00_led *led =
293 + container_of(led_cdev, struct rt2x00_led, led_dev);
294 + unsigned int enabled = brightness != LED_OFF;
295 + unsigned int bg_mode =
296 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
297 + unsigned int polarity =
298 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
299 + EEPROM_FREQ_LED_POLARITY);
300 + unsigned int ledmode =
301 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
302 + EEPROM_FREQ_LED_MODE);
303 +
304 + if (led->type == LED_TYPE_RADIO) {
305 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
306 + enabled ? 0x20 : 0);
307 + } else if (led->type == LED_TYPE_ASSOC) {
308 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
309 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
310 + } else if (led->type == LED_TYPE_QUALITY) {
311 + /*
312 + * The brightness is divided into 6 levels (0 - 5),
313 + * The specs tell us the following levels:
314 + * 0, 1 ,3, 7, 15, 31
315 + * to determine the level in a simple way we can simply
316 + * work with bitshifting:
317 + * (1 << level) - 1
318 + */
319 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
320 + (1 << brightness / (LED_FULL / 6)) - 1,
321 + polarity);
322 + }
323 +}
324 +
325 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
326 + unsigned long *delay_on,
327 + unsigned long *delay_off)
328 +{
329 + struct rt2x00_led *led =
330 + container_of(led_cdev, struct rt2x00_led, led_dev);
331 + u32 reg;
332 +
333 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
334 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
335 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
336 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
337 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
338 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
339 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
340 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
341 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
342 +
343 + return 0;
344 +}
345 +
346 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
347 + struct rt2x00_led *led,
348 + enum led_type type)
349 +{
350 + led->rt2x00dev = rt2x00dev;
351 + led->type = type;
352 + led->led_dev.brightness_set = rt2800pci_brightness_set;
353 + led->led_dev.blink_set = rt2800pci_blink_set;
354 + led->flags = LED_INITIALIZED;
355 +}
356 +#endif /* CONFIG_RT2X00_LIB_LEDS */
357 +
358 +/*
359 + * Configuration handlers.
360 + */
361 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
362 + struct rt2x00lib_crypto *crypto,
363 + struct ieee80211_key_conf *key)
364 +{
365 + struct mac_wcid_entry wcid_entry;
366 + struct mac_iveiv_entry iveiv_entry;
367 + u32 offset;
368 + u32 reg;
369 +
370 + offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
371 +
372 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
373 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
374 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
375 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, crypto->cipher);
376 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
377 + (crypto->cmd == SET_KEY) * crypto->bssidx);
378 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
379 + rt2x00pci_register_write(rt2x00dev, offset, reg);
380 +
381 + offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
382 +
383 + memset(&iveiv_entry, 0, sizeof(iveiv_entry));
384 + if ((crypto->cipher == CIPHER_TKIP) ||
385 + (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
386 + (crypto->cipher == CIPHER_AES))
387 + iveiv_entry.iv[3] |= 0x20;
388 + iveiv_entry.iv[3] |= key->keyidx << 6;
389 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
390 + &iveiv_entry, sizeof(iveiv_entry));
391 +
392 + offset = MAC_WCID_ENTRY(key->hw_key_idx);
393 +
394 + memset(&wcid_entry, 0, sizeof(wcid_entry));
395 + if (crypto->cmd == SET_KEY)
396 + memcpy(&wcid_entry, crypto->address, ETH_ALEN);
397 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
398 + &wcid_entry, sizeof(wcid_entry));
399 +}
400 +
401 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
402 + struct rt2x00lib_crypto *crypto,
403 + struct ieee80211_key_conf *key)
404 +{
405 + struct hw_key_entry key_entry;
406 + struct rt2x00_field32 field;
407 + u32 offset;
408 + u32 reg;
409 +
410 + if (crypto->cmd == SET_KEY) {
411 + key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
412 +
413 + memcpy(key_entry.key, crypto->key,
414 + sizeof(key_entry.key));
415 + memcpy(key_entry.tx_mic, crypto->tx_mic,
416 + sizeof(key_entry.tx_mic));
417 + memcpy(key_entry.rx_mic, crypto->rx_mic,
418 + sizeof(key_entry.rx_mic));
419 +
420 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
421 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
422 + &key_entry, sizeof(key_entry));
423 + }
424 +
425 + /*
426 + * The cipher types are stored over multiple registers
427 + * starting with SHARED_KEY_MODE_BASE each word will have
428 + * 32 bits and contains the cipher types for 2 bssidx each.
429 + * Using the correct defines correctly will cause overhead,
430 + * so just calculate the correct offset.
431 + */
432 + field.bit_offset = (4 * key->keyidx) + (16 * (crypto->bssidx & 1));
433 + field.bit_mask = 0x7 << field.bit_offset;
434 +
435 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 2);
436 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
437 + rt2x00_set_field32(&reg, field,
438 + (crypto->cmd == SET_KEY) * crypto->cipher);
439 + rt2x00pci_register_write(rt2x00dev, offset, reg);
440 +
441 + /*
442 + * Update WCID information
443 + */
444 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
445 +
446 + return 0;
447 +}
448 +
449 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
450 + struct rt2x00lib_crypto *crypto,
451 + struct ieee80211_key_conf *key)
452 +{
453 + struct hw_key_entry key_entry;
454 + u32 offset;
455 +
456 + if (crypto->cmd == SET_KEY) {
457 + /*
458 + * 1 pairwise key is possible per AID, this means that the AID
459 + * equals our hw_key_idx.
460 + */
461 + key->hw_key_idx = crypto->aid;
462 +
463 + memcpy(key_entry.key, crypto->key,
464 + sizeof(key_entry.key));
465 + memcpy(key_entry.tx_mic, crypto->tx_mic,
466 + sizeof(key_entry.tx_mic));
467 + memcpy(key_entry.rx_mic, crypto->rx_mic,
468 + sizeof(key_entry.rx_mic));
469 +
470 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
471 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
472 + &key_entry, sizeof(key_entry));
473 + }
474 +
475 + /*
476 + * Update WCID information
477 + */
478 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
479 +
480 + return 0;
481 +}
482 +
483 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
484 + const unsigned int filter_flags)
485 +{
486 + u32 reg;
487 +
488 + /*
489 + * Start configuration steps.
490 + * Note that the version error will always be dropped
491 + * and broadcast frames will always be accepted since
492 + * there is no filter for it at this time.
493 + */
494 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
495 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
496 + !(filter_flags & FIF_FCSFAIL));
497 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
498 + !(filter_flags & FIF_PLCPFAIL));
499 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
500 + !(filter_flags & FIF_PROMISC_IN_BSS));
501 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
502 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
503 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
504 + !(filter_flags & FIF_ALLMULTI));
505 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
506 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
507 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
508 + !(filter_flags & FIF_CONTROL));
509 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
510 + !(filter_flags & FIF_CONTROL));
511 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
512 + !(filter_flags & FIF_CONTROL));
513 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
514 + !(filter_flags & FIF_CONTROL));
515 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
516 + !(filter_flags & FIF_CONTROL));
517 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
518 + !(filter_flags & FIF_CONTROL));
519 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
520 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
521 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
522 + !(filter_flags & FIF_CONTROL));
523 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
524 +}
525 +
526 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
527 + struct rt2x00_intf *intf,
528 + struct rt2x00intf_conf *conf,
529 + const unsigned int flags)
530 +{
531 + unsigned int beacon_base;
532 + u32 reg;
533 +
534 + if (flags & CONFIG_UPDATE_TYPE) {
535 + /*
536 + * Clear current synchronisation setup.
537 + * For the Beacon base registers we only need to clear
538 + * the first byte since that byte contains the VALID and OWNER
539 + * bits which (when set to 0) will invalidate the entire beacon.
540 + */
541 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
542 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
543 +
544 + /*
545 + * Enable synchronisation.
546 + */
547 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
548 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
549 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
550 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
551 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
552 + }
553 +
554 + if (flags & CONFIG_UPDATE_MAC) {
555 + reg = le32_to_cpu(conf->mac[1]);
556 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
557 + conf->mac[1] = cpu_to_le32(reg);
558 +
559 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
560 + conf->mac, sizeof(conf->mac));
561 + }
562 +
563 + if (flags & CONFIG_UPDATE_BSSID) {
564 + reg = le32_to_cpu(conf->bssid[1]);
565 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
566 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
567 + conf->bssid[1] = cpu_to_le32(reg);
568 +
569 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
570 + conf->bssid, sizeof(conf->bssid));
571 + }
572 +}
573 +
574 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
575 + struct rt2x00lib_erp *erp)
576 +{
577 + u32 reg;
578 +
579 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
580 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
581 + DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
582 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
583 +
584 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
585 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
586 + !!erp->short_preamble);
587 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
588 + !!erp->short_preamble);
589 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
590 +
591 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
592 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
593 + erp->cts_protection ? 2 : 0);
594 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
595 +
596 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
597 + erp->basic_rates);
598 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
599 +
600 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
601 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
602 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
603 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
604 +
605 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
606 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
607 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
608 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
609 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
610 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
611 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
612 +}
613 +
614 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
615 + struct antenna_setup *ant)
616 +{
617 + u16 eeprom;
618 + u8 r1;
619 + u8 r3;
620 +
621 + /*
622 + * FIXME: Use requested antenna configuration.
623 + */
624 +
625 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
626 +
627 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
628 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
629 +
630 + /*
631 + * Configure the TX antenna.
632 + */
633 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
634 + case 1:
635 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
636 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
637 + break;
638 + case 2:
639 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
640 + break;
641 + case 3:
642 + /* Do nothing */
643 + break;
644 + }
645 +
646 + /*
647 + * Configure the RX antenna.
648 + */
649 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
650 + case 1:
651 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
652 + break;
653 + case 2:
654 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
655 + break;
656 + case 3:
657 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
658 + break;
659 + }
660 +
661 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
662 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
663 +}
664 +
665 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
666 + struct rt2x00lib_conf *libconf)
667 +{
668 + u16 eeprom;
669 + short lna_gain;
670 +
671 + if (libconf->rf.channel <= 14) {
672 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
673 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
674 + } else if (libconf->rf.channel <= 64) {
675 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
676 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
677 + } else if (libconf->rf.channel <= 128) {
678 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
679 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
680 + } else {
681 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
682 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
683 + }
684 +
685 + rt2x00dev->lna_gain = lna_gain;
686 +}
687 +
688 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
689 + struct ieee80211_conf *conf,
690 + struct rf_channel *rf,
691 + struct channel_info *info)
692 +{
693 + u32 reg;
694 + unsigned int tx_pin;
695 + u16 eeprom;
696 +
697 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
698 +
699 + /*
700 + * Determine antenna settings from EEPROM
701 + */
702 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
703 +
704 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
705 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
706 + }
707 +
708 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
709 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
710 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
711 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
712 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
713 +
714 + if (rf->channel > 14) {
715 + /*
716 + * When TX power is below 0, we should increase it by 7 to
717 + * make it a positive value (Minumum value is -7).
718 + * However this means that values between 0 and 7 have
719 + * double meaning, and we should set a 7DBm boost flag.
720 + */
721 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
722 + (info->tx_power1 >= 0));
723 +
724 + if (info->tx_power1 < 0)
725 + info->tx_power1 += 7;
726 +
727 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
728 + TXPOWER_A_TO_DEV(info->tx_power1));
729 +
730 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
731 + (info->tx_power2 >= 0));
732 +
733 + if (info->tx_power2 < 0)
734 + info->tx_power2 += 7;
735 +
736 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
737 + TXPOWER_A_TO_DEV(info->tx_power2));
738 + } else {
739 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
740 + TXPOWER_G_TO_DEV(info->tx_power1));
741 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
742 + TXPOWER_G_TO_DEV(info->tx_power2));
743 + }
744 +
745 + rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
746 +
747 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
748 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
749 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
750 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
751 +
752 + udelay(200);
753 +
754 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
755 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
756 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
757 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
758 +
759 + udelay(200);
760 +
761 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
762 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
763 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
764 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
765 +
766 + /*
767 + * Change BBP settings
768 + */
769 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
770 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
771 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
772 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
773 +
774 + if (rf->channel <= 14) {
775 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
776 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
777 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
778 + } else {
779 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
780 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
781 + }
782 + } else {
783 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
784 +
785 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
786 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
787 + else
788 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
789 + }
790 +
791 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
792 + rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
793 + rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
794 + rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
795 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
796 +
797 + tx_pin = 0;
798 +
799 + /* Turn on unused PA or LNA when not using 1T or 1R */
800 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
801 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
802 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
803 + }
804 +
805 + /* Turn on unused PA or LNA when not using 1T or 1R */
806 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
807 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
808 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
809 + }
810 +
811 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
812 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
813 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
814 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
815 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
816 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
817 +
818 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
819 +
820 + msleep(1);
821 +}
822 +
823 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
824 + const int txpower)
825 +{
826 + u32 reg;
827 + u32 value = TXPOWER_G_TO_DEV(txpower);
828 + u8 r1;
829 +
830 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
831 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
832 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
833 +
834 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
835 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
836 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
837 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
838 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
839 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
840 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
841 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
842 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
843 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
844 +
845 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
846 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
847 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
848 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
849 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
850 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
851 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
852 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
853 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
854 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
855 +
856 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
857 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
858 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
859 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
860 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
861 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
862 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
863 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
864 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
865 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
866 +
867 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
868 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
869 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
870 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
871 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
872 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
873 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
874 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
875 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
876 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
877 +
878 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
879 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
880 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
881 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
882 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
883 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
884 +}
885 +
886 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
887 + struct rt2x00lib_conf *libconf)
888 +{
889 + u32 reg;
890 +
891 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
892 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
893 + libconf->conf->short_frame_max_tx_count);
894 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
895 + libconf->conf->long_frame_max_tx_count);
896 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
897 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
898 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
899 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
900 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
901 +}
902 +
903 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
904 + struct rt2x00lib_conf *libconf)
905 +{
906 + u32 reg;
907 +
908 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
909 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
910 + libconf->conf->beacon_int * 16);
911 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
912 +}
913 +
914 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
915 + struct rt2x00lib_conf *libconf)
916 +{
917 + enum dev_state state =
918 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
919 + STATE_SLEEP : STATE_AWAKE;
920 + u32 reg;
921 +
922 + if (state == STATE_SLEEP) {
923 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
924 +
925 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
926 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
927 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
928 + libconf->conf->listen_interval - 1);
929 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
930 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
931 +
932 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
933 + } else {
934 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
935 +
936 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
937 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
938 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
939 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
940 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
941 + }
942 +}
943 +
944 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
945 + struct rt2x00lib_conf *libconf,
946 + const unsigned int flags)
947 +{
948 + /* Always recalculate LNA gain before changing configuration */
949 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
950 +
951 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
952 + rt2800pci_config_channel(rt2x00dev, libconf->conf,
953 + &libconf->rf, &libconf->channel);
954 + if (flags & IEEE80211_CONF_CHANGE_POWER)
955 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
956 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
957 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
958 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
959 + rt2800pci_config_duration(rt2x00dev, libconf);
960 + if (flags & IEEE80211_CONF_CHANGE_PS)
961 + rt2800pci_config_ps(rt2x00dev, libconf);
962 +}
963 +
964 +/*
965 + * Link tuning
966 + */
967 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
968 + struct link_qual *qual)
969 +{
970 + u32 reg;
971 +
972 + /*
973 + * Update FCS error count from register.
974 + */
975 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
976 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
977 +}
978 +
979 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
980 +{
981 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
982 + return 0x2e + rt2x00dev->lna_gain;
983 +
984 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
985 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
986 + else
987 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
988 +}
989 +
990 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
991 + struct link_qual *qual, u8 vgc_level)
992 +{
993 + if (qual->vgc_level != vgc_level) {
994 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
995 + qual->vgc_level = vgc_level;
996 + qual->vgc_level_reg = vgc_level;
997 + }
998 +}
999 +
1000 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1001 + struct link_qual *qual)
1002 +{
1003 + rt2800pci_set_vgc(rt2x00dev, qual,
1004 + rt2800pci_get_default_vgc(rt2x00dev));
1005 +}
1006 +
1007 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1008 + struct link_qual *qual, const u32 count)
1009 +{
1010 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1011 + return;
1012 +
1013 + /*
1014 + * When RSSI is better then -80 increase VGC level with 0x10
1015 + */
1016 + rt2800pci_set_vgc(rt2x00dev, qual,
1017 + rt2800pci_get_default_vgc(rt2x00dev) +
1018 + ((qual->rssi > -80) * 0x10));
1019 +}
1020 +
1021 +/*
1022 + * Firmware functions
1023 + */
1024 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1025 +{
1026 + return FIRMWARE_RT2860;
1027 +}
1028 +
1029 +static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1030 + const u8 *data, const size_t len)
1031 +{
1032 + u16 fw_crc;
1033 + u16 crc;
1034 +
1035 + /*
1036 + * Only support 8kb firmware files.
1037 + */
1038 + if (len != 8192)
1039 + return FW_BAD_LENGTH;
1040 +
1041 + /*
1042 + * The last 2 bytes in the firmware array are the crc checksum itself,
1043 + * this means that we should never pass those 2 bytes to the crc
1044 + * algorithm.
1045 + */
1046 + fw_crc = (data[len - 2] << 8 | data[len - 1]);
1047 +
1048 + /*
1049 + * Use the crc ccitt algorithm.
1050 + * This will return the same value as the legacy driver which
1051 + * used bit ordering reversion on the both the firmware bytes
1052 + * before input input as well as on the final output.
1053 + * Obviously using crc ccitt directly is much more efficient.
1054 + */
1055 + crc = crc_ccitt(~0, data, len - 2);
1056 +
1057 + /*
1058 + * There is a small difference between the crc-itu-t + bitrev and
1059 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1060 + * will be swapped, use swab16 to convert the crc to the correct
1061 + * value.
1062 + */
1063 + crc = swab16(crc);
1064 +
1065 + return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1066 +}
1067 +
1068 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1069 + const u8 *data, const size_t len)
1070 +{
1071 + unsigned int i;
1072 + u32 reg;
1073 +
1074 + /*
1075 + * Wait for stable hardware.
1076 + */
1077 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1078 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1079 + if (reg && reg != ~0)
1080 + break;
1081 + msleep(1);
1082 + }
1083 +
1084 + if (i == REGISTER_BUSY_COUNT) {
1085 + ERROR(rt2x00dev, "Unstable hardware.\n");
1086 + return -EBUSY;
1087 + }
1088 +
1089 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1090 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1091 +
1092 + /*
1093 + * Disable DMA, will be reenabled later when enabling
1094 + * the radio.
1095 + */
1096 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1097 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1098 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1099 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1100 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1101 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1102 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1103 +
1104 + /*
1105 + * enable Host program ram write selection
1106 + */
1107 + reg = 0;
1108 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1109 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1110 +
1111 + /*
1112 + * Write firmware to device.
1113 + */
1114 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1115 + data, len);
1116 +
1117 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1118 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1119 +
1120 + /*
1121 + * Wait for device to stabilize.
1122 + */
1123 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1124 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1125 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1126 + break;
1127 + msleep(1);
1128 + }
1129 +
1130 + if (i == REGISTER_BUSY_COUNT) {
1131 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1132 + return -EBUSY;
1133 + }
1134 +
1135 + /*
1136 + * Disable interrupts
1137 + */
1138 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1139 +
1140 + /*
1141 + * Initialize BBP R/W access agent
1142 + */
1143 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1144 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1145 +
1146 + return 0;
1147 +}
1148 +
1149 +/*
1150 + * Initialization functions.
1151 + */
1152 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1153 +{
1154 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1155 + u32 word;
1156 +
1157 + if (entry->queue->qid == QID_RX) {
1158 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1159 +
1160 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1161 + } else {
1162 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1163 +
1164 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1165 + }
1166 +}
1167 +
1168 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1169 +{
1170 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1171 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1172 + u32 word;
1173 +
1174 + if (entry->queue->qid == QID_RX) {
1175 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1176 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1177 + rt2x00_desc_write(entry_priv->desc, 0, word);
1178 +
1179 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1180 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1181 + rt2x00_desc_write(entry_priv->desc, 1, word);
1182 + } else {
1183 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1184 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1185 + rt2x00_desc_write(entry_priv->desc, 1, word);
1186 + }
1187 +}
1188 +
1189 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1190 +{
1191 + struct queue_entry_priv_pci *entry_priv;
1192 + u32 reg;
1193 +
1194 + /*
1195 + * Initialize registers.
1196 + */
1197 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1198 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1199 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1200 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1201 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1202 +
1203 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1204 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1205 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1206 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1207 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1208 +
1209 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1210 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1211 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1212 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1213 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1214 +
1215 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1216 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1217 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1218 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1219 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1220 +
1221 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1222 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1223 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1224 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1225 + rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1226 +
1227 + /*
1228 + * Enable global DMA configuration
1229 + */
1230 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1231 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1232 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1233 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1234 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1235 +
1236 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1237 +
1238 + return 0;
1239 +}
1240 +
1241 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1242 +{
1243 + u32 reg;
1244 + unsigned int i;
1245 +
1246 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1247 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1248 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1249 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1250 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1251 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1252 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1253 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1254 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1255 +
1256 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1257 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1258 +
1259 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1260 +
1261 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1262 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1263 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1264 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1265 +
1266 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1267 +
1268 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1269 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1270 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1271 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1272 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1273 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1274 +
1275 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1276 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1277 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1278 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1279 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1280 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1281 +
1282 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1283 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1284 +
1285 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1286 +
1287 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1288 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1289 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1290 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1291 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1292 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1293 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1294 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1295 +
1296 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1297 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1298 +
1299 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1300 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1301 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1302 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1303 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1304 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1305 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1306 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1307 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1308 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1309 +
1310 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1311 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1312 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1313 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1314 +
1315 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1316 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1317 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1318 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1319 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1320 + else
1321 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1322 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1323 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1324 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1325 +
1326 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1327 +
1328 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1329 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1330 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1331 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1332 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1333 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1334 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1335 +
1336 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1337 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1338 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1339 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1340 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1341 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1342 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1343 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1344 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1345 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1346 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1347 +
1348 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1349 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1350 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1351 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1352 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1353 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1354 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1355 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1356 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1357 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1358 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1359 +
1360 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1361 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1362 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1363 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1364 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1365 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1366 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1367 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1368 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1369 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1370 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1371 +
1372 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1373 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1374 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1375 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1376 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1377 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1378 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1379 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1380 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1381 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1382 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1383 +
1384 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1385 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1386 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1387 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1388 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1389 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1390 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1391 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1392 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1393 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1394 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1395 +
1396 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1397 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1398 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1399 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1400 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1401 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1402 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1403 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1404 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1405 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1406 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1407 +
1408 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1409 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1410 +
1411 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1412 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1413 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1414 + IEEE80211_MAX_RTS_THRESHOLD);
1415 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1416 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1417 +
1418 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1419 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1420 +
1421 + /*
1422 + * ASIC will keep garbage value after boot, clear encryption keys.
1423 + */
1424 + for (i = 0; i < 256; i++) {
1425 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1426 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1427 + wcid, sizeof(wcid));
1428 +
1429 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1430 + rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1431 + }
1432 +
1433 + for (i = 0; i < 16; i++)
1434 + rt2x00pci_register_write(rt2x00dev,
1435 + SHARED_KEY_MODE_ENTRY(i), 0);
1436 +
1437 + /*
1438 + * Clear all beacons
1439 + * For the Beacon base registers we only need to clear
1440 + * the first byte since that byte contains the VALID and OWNER
1441 + * bits which (when set to 0) will invalidate the entire beacon.
1442 + */
1443 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1444 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1445 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1446 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1447 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1448 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1449 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1450 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1451 +
1452 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1453 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1454 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1455 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1456 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1457 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1458 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1459 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1460 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1461 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1462 +
1463 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1464 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1465 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1466 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1467 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1468 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1469 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1470 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1471 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1472 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1473 +
1474 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1475 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1476 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1477 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1478 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1479 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1480 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1481 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1482 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1483 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1484 +
1485 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1486 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1487 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1488 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1489 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1490 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1491 +
1492 + /*
1493 + * We must clear the error counters.
1494 + * These registers are cleared on read,
1495 + * so we may pass a useless variable to store the value.
1496 + */
1497 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1498 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1499 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1500 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1501 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1502 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1503 +
1504 + return 0;
1505 +}
1506 +
1507 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1508 +{
1509 + unsigned int i;
1510 + u32 reg;
1511 +
1512 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1513 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1514 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1515 + return 0;
1516 +
1517 + udelay(REGISTER_BUSY_DELAY);
1518 + }
1519 +
1520 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1521 + return -EACCES;
1522 +}
1523 +
1524 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1525 +{
1526 + unsigned int i;
1527 + u8 value;
1528 +
1529 + /*
1530 + * BBP was enabled after firmware was loaded,
1531 + * but we need to reactivate it now.
1532 + */
1533 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0x00000000);
1534 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0x00000000);
1535 + msleep(1);
1536 +
1537 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1538 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1539 + if ((value != 0xff) && (value != 0x00))
1540 + return 0;
1541 + udelay(REGISTER_BUSY_DELAY);
1542 + }
1543 +
1544 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1545 + return -EACCES;
1546 +}
1547 +
1548 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1549 +{
1550 + unsigned int i;
1551 + u16 eeprom;
1552 + u8 reg_id;
1553 + u8 value;
1554 +
1555 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1556 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1557 + return -EACCES;
1558 +
1559 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1560 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1561 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1562 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1563 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1564 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1565 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1566 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1567 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1568 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1569 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1570 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1571 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1572 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1573 +
1574 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1575 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1576 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1577 + }
1578 +
1579 + if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1580 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1581 +
1582 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1583 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1584 +
1585 + if (eeprom != 0xffff && eeprom != 0x0000) {
1586 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1587 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1588 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1589 + }
1590 + }
1591 +
1592 + return 0;
1593 +}
1594 +
1595 +/*
1596 + * Device state switch handlers.
1597 + */
1598 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1599 + enum dev_state state)
1600 +{
1601 + u32 reg;
1602 +
1603 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1604 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1605 + (state == STATE_RADIO_RX_ON) ||
1606 + (state == STATE_RADIO_RX_ON_LINK));
1607 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1608 +}
1609 +
1610 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1611 + enum dev_state state)
1612 +{
1613 + int mask = (state == STATE_RADIO_IRQ_ON);
1614 + u32 reg;
1615 +
1616 + /*
1617 + * When interrupts are being enabled, the interrupt registers
1618 + * should clear the register to assure a clean state.
1619 + */
1620 + if (state == STATE_RADIO_IRQ_ON) {
1621 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1622 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1623 + }
1624 +
1625 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1626 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1627 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1628 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1629 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1630 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1631 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1632 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1633 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1634 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1635 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1636 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1637 + rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1638 + rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1639 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1640 + rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1641 + rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1642 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1643 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1644 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1645 +}
1646 +
1647 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1648 +{
1649 + unsigned int i;
1650 + u32 reg;
1651 +
1652 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1653 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1654 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1655 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1656 + return 0;
1657 +
1658 + msleep(1);
1659 + }
1660 +
1661 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1662 + return -EACCES;
1663 +}
1664 +
1665 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1666 +{
1667 + u32 reg;
1668 + u16 word;
1669 +
1670 + /*
1671 + * Initialize all registers.
1672 + */
1673 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1674 + rt2800pci_init_queues(rt2x00dev) ||
1675 + rt2800pci_init_registers(rt2x00dev) ||
1676 + rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1677 + rt2800pci_init_bbp(rt2x00dev)))
1678 + return -EIO;
1679 +
1680 + /*
1681 + * Send signal to firmware during boot time.
1682 + */
1683 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1684 +
1685 + /*
1686 + * Enable RX.
1687 + */
1688 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1689 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1690 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
1691 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1692 +
1693 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1694 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1695 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1696 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
1697 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1698 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1699 +
1700 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1701 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1702 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1703 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1704 +
1705 + /*
1706 + * Initialize LED control
1707 + */
1708 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1709 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1710 + word & 0xff, (word >> 8) & 0xff);
1711 +
1712 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1713 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1714 + word & 0xff, (word >> 8) & 0xff);
1715 +
1716 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1717 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1718 + word & 0xff, (word >> 8) & 0xff);
1719 +
1720 + return 0;
1721 +}
1722 +
1723 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1724 +{
1725 + u32 reg;
1726 +
1727 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1728 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1729 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1730 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1731 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1732 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1733 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1734 +
1735 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1736 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1737 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1738 +
1739 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1740 +
1741 + /* Wait for DMA, ignore error */
1742 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1743 +}
1744 +
1745 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1746 + enum dev_state state)
1747 +{
1748 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1749 +
1750 + if (state == STATE_AWAKE)
1751 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1752 + else
1753 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1754 +
1755 + return 0;
1756 +}
1757 +
1758 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1759 + enum dev_state state)
1760 +{
1761 + int retval = 0;
1762 +
1763 + switch (state) {
1764 + case STATE_RADIO_ON:
1765 + /*
1766 + * Before the radio can be enabled, the device first has
1767 + * to be woken up. After that it needs a bit of time
1768 + * to be fully awake and the radio can be enabled.
1769 + */
1770 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1771 + msleep(1);
1772 + retval = rt2800pci_enable_radio(rt2x00dev);
1773 + break;
1774 + case STATE_RADIO_OFF:
1775 + /*
1776 + * After the radio has been disablee, the device should
1777 + * be put to sleep for powersaving.
1778 + */
1779 + rt2800pci_disable_radio(rt2x00dev);
1780 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1781 + break;
1782 + case STATE_RADIO_RX_ON:
1783 + case STATE_RADIO_RX_ON_LINK:
1784 + case STATE_RADIO_RX_OFF:
1785 + case STATE_RADIO_RX_OFF_LINK:
1786 + rt2800pci_toggle_rx(rt2x00dev, state);
1787 + break;
1788 + case STATE_RADIO_IRQ_ON:
1789 + case STATE_RADIO_IRQ_OFF:
1790 + rt2800pci_toggle_irq(rt2x00dev, state);
1791 + break;
1792 + case STATE_DEEP_SLEEP:
1793 + case STATE_SLEEP:
1794 + case STATE_STANDBY:
1795 + case STATE_AWAKE:
1796 + retval = rt2800pci_set_state(rt2x00dev, state);
1797 + break;
1798 + default:
1799 + retval = -ENOTSUPP;
1800 + break;
1801 + }
1802 +
1803 + if (unlikely(retval))
1804 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1805 + state, retval);
1806 +
1807 + return retval;
1808 +}
1809 +
1810 +/*
1811 + * TX descriptor initialization
1812 + */
1813 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1814 + struct sk_buff *skb,
1815 + struct txentry_desc *txdesc)
1816 +{
1817 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1818 + __le32 *txd = skbdesc->desc;
1819 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1820 + u32 word;
1821 +
1822 + /*
1823 + * Initialize TX Info descriptor
1824 + */
1825 + rt2x00_desc_read(txwi, 0, &word);
1826 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1827 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1828 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1829 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1830 + rt2x00_set_field32(&word, TXWI_W0_TS,
1831 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1832 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1833 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1834 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1835 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1836 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1837 + rt2x00_set_field32(&word, TXWI_W0_BW,
1838 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1839 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1840 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1841 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1842 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1843 + rt2x00_desc_write(txwi, 0, word);
1844 +
1845 + rt2x00_desc_read(txwi, 1, &word);
1846 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1847 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1848 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1849 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1850 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1851 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1852 + test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
1853 + txdesc->key_idx : 0xff);
1854 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1855 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1856 + skbdesc->entry->queue->qid);
1857 + rt2x00_desc_write(txwi, 1, word);
1858 +
1859 + /*
1860 + * Always write 0 to IV/EIV fields, hardware will insert the IV
1861 + * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
1862 + * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
1863 + * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
1864 + * crypto entry in the registers should be used to encrypt the frame.
1865 + */
1866 + _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
1867 + _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
1868 +
1869 + /*
1870 + * Initialize TX descriptor
1871 + */
1872 + rt2x00_desc_read(txd, 0, &word);
1873 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1874 + rt2x00_desc_write(txd, 0, word);
1875 +
1876 + rt2x00_desc_read(txd, 1, &word);
1877 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1878 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1879 + rt2x00_set_field32(&word, TXD_W1_BURST,
1880 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1881 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1882 + rt2x00dev->hw->extra_tx_headroom);
1883 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1884 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1885 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1886 + rt2x00_desc_write(txd, 1, word);
1887 +
1888 + rt2x00_desc_read(txd, 2, &word);
1889 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1890 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1891 + rt2x00_desc_write(txd, 2, word);
1892 +
1893 + rt2x00_desc_read(txd, 3, &word);
1894 + rt2x00_set_field32(&word, TXD_W3_WIV,
1895 + !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
1896 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1897 + rt2x00_desc_write(txd, 3, word);
1898 +}
1899 +
1900 +/*
1901 + * TX data initialization
1902 + */
1903 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1904 +{
1905 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1906 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1907 + unsigned int beacon_base;
1908 + u32 reg;
1909 +
1910 + /*
1911 + * Disable beaconing while we are reloading the beacon data,
1912 + * otherwise we might be sending out invalid data.
1913 + */
1914 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1915 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1916 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1917 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1918 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1919 +
1920 + /*
1921 + * Write entire beacon with descriptor to register.
1922 + */
1923 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1924 + rt2x00pci_register_multiwrite(rt2x00dev,
1925 + beacon_base,
1926 + skbdesc->desc, skbdesc->desc_len);
1927 + rt2x00pci_register_multiwrite(rt2x00dev,
1928 + beacon_base + skbdesc->desc_len,
1929 + entry->skb->data, entry->skb->len);
1930 +
1931 + /*
1932 + * Clean up beacon skb.
1933 + */
1934 + dev_kfree_skb_any(entry->skb);
1935 + entry->skb = NULL;
1936 +}
1937 +
1938 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1939 + const enum data_queue_qid queue_idx)
1940 +{
1941 + struct data_queue *queue;
1942 + unsigned int idx, qidx = 0;
1943 + u32 reg;
1944 +
1945 + if (queue_idx == QID_BEACON) {
1946 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1947 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1948 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1949 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1950 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1951 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1952 + }
1953 + return;
1954 + }
1955 +
1956 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1957 + return;
1958 +
1959 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1960 + idx = queue->index[Q_INDEX];
1961 +
1962 + if (queue_idx == QID_MGMT)
1963 + qidx = 5;
1964 + else
1965 + qidx = queue_idx;
1966 +
1967 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
1968 +}
1969 +
1970 +static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1971 + const enum data_queue_qid qid)
1972 +{
1973 + u32 reg;
1974 +
1975 + if (qid == QID_BEACON) {
1976 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
1977 + return;
1978 + }
1979 +
1980 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1981 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
1982 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
1983 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
1984 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
1985 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1986 +}
1987 +
1988 +/*
1989 + * RX control handlers
1990 + */
1991 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1992 + struct rxdone_entry_desc *rxdesc)
1993 +{
1994 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1995 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1996 + __le32 *rxd = entry_priv->desc;
1997 + __le32 *rxwi = (__le32 *)entry->skb->data;
1998 + u32 rxd3;
1999 + u32 rxwi0;
2000 + u32 rxwi1;
2001 + u32 rxwi2;
2002 + u32 rxwi3;
2003 +
2004 + rt2x00_desc_read(rxd, 3, &rxd3);
2005 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2006 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2007 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2008 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2009 +
2010 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2011 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2012 +
2013 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2014 + /*
2015 + * Unfortunately we don't know the cipher type used during
2016 + * decryption. This prevents us from correct providing
2017 + * correct statistics through debugfs.
2018 + */
2019 + rxdesc->cipher = CIPHER_NONE;
2020 + rxdesc->cipher_status =
2021 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2022 + }
2023 +
2024 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2025 + /*
2026 + * Hardware has stripped IV/EIV data from 802.11 frame during
2027 + * decryption. Unfortunately the descriptor doesn't contain
2028 + * any fields with the EIV/IV data either, so they can't
2029 + * be restored by rt2x00lib.
2030 + */
2031 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2032 +
2033 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2034 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2035 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2036 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2037 + }
2038 +
2039 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2040 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2041 +
2042 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2043 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2044 +
2045 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2046 + rxdesc->flags |= RX_FLAG_40MHZ;
2047 +
2048 + /*
2049 + * Detect RX rate, always use MCS as signal type.
2050 + */
2051 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2052 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2053 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2054 +
2055 + /*
2056 + * Mask of 0x8 bit to remove the short preamble flag.
2057 + */
2058 + if (rxdesc->dev_flags == RATE_MODE_CCK)
2059 + rxdesc->signal &= ~0x8;
2060 +
2061 + rxdesc->rssi =
2062 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2063 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2064 +
2065 + rxdesc->noise =
2066 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2067 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2068 +
2069 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2070 +
2071 + /*
2072 + * Remove TXWI descriptor from start of buffer.
2073 + */
2074 + skb_pull(entry->skb, TXWI_DESC_SIZE);
2075 + skb_trim(entry->skb, rxdesc->size);
2076 +}
2077 +
2078 +/*
2079 + * Interrupt functions.
2080 + */
2081 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2082 +{
2083 + struct data_queue *queue;
2084 + struct queue_entry *entry;
2085 + struct queue_entry *entry_done;
2086 + struct queue_entry_priv_pci *entry_priv;
2087 + struct txdone_entry_desc txdesc;
2088 + u32 word;
2089 + u32 reg;
2090 + u32 old_reg;
2091 + int type;
2092 + int index;
2093 +
2094 + /*
2095 + * During each loop we will compare the freshly read
2096 + * TX_STA_FIFO register value with the value read from
2097 + * the previous loop. If the 2 values are equal then
2098 + * we should stop processing because the chance it
2099 + * quite big that the device has been unplugged and
2100 + * we risk going into an endless loop.
2101 + */
2102 + old_reg = 0;
2103 +
2104 + while (1) {
2105 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2106 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2107 + break;
2108 +
2109 + if (old_reg == reg)
2110 + break;
2111 + old_reg = reg;
2112 +
2113 + /*
2114 + * Skip this entry when it contains an invalid
2115 + * queue identication number.
2116 + */
2117 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2118 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2119 + if (unlikely(!queue))
2120 + continue;
2121 +
2122 + /*
2123 + * Skip this entry when it contains an invalid
2124 + * index number.
2125 + */
2126 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2127 + if (unlikely(index >= queue->limit))
2128 + continue;
2129 +
2130 + entry = &queue->entries[index];
2131 + entry_priv = entry->priv_data;
2132 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2133 +
2134 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2135 + while (entry != entry_done) {
2136 + /*
2137 + * Catch up.
2138 + * Just report any entries we missed as failed.
2139 + */
2140 + WARNING(rt2x00dev,
2141 + "TX status report missed for entry %d\n",
2142 + entry_done->entry_idx);
2143 +
2144 + txdesc.flags = 0;
2145 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2146 + txdesc.retry = 0;
2147 +
2148 + rt2x00lib_txdone(entry_done, &txdesc);
2149 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2150 + }
2151 +
2152 + /*
2153 + * Obtain the status about this packet.
2154 + */
2155 + txdesc.flags = 0;
2156 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2157 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2158 + else
2159 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2160 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2161 +
2162 + rt2x00lib_txdone(entry, &txdesc);
2163 + }
2164 +}
2165 +
2166 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2167 +{
2168 + struct rt2x00_dev *rt2x00dev = dev_instance;
2169 + u32 reg;
2170 +
2171 + /* Read status and ACK all interrupts */
2172 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2173 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2174 +
2175 + if (!reg)
2176 + return IRQ_NONE;
2177 +
2178 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2179 + return IRQ_HANDLED;
2180 +
2181 + /*
2182 + * 1 - Rx ring done interrupt.
2183 + */
2184 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2185 + rt2x00pci_rxdone(rt2x00dev);
2186 +
2187 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2188 + rt2800pci_txdone(rt2x00dev);
2189 +
2190 + return IRQ_HANDLED;
2191 +}
2192 +
2193 +/*
2194 + * Device probe functions.
2195 + */
2196 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2197 +{
2198 + struct eeprom_93cx6 eeprom;
2199 + u32 reg;
2200 + u16 word;
2201 + u8 *mac;
2202 + u8 default_lna_gain;
2203 +
2204 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2205 +
2206 + eeprom.data = rt2x00dev;
2207 + eeprom.register_read = rt2800pci_eepromregister_read;
2208 + eeprom.register_write = rt2800pci_eepromregister_write;
2209 + eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
2210 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2211 + eeprom.reg_data_in = 0;
2212 + eeprom.reg_data_out = 0;
2213 + eeprom.reg_data_clock = 0;
2214 + eeprom.reg_chip_select = 0;
2215 +
2216 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2217 + EEPROM_SIZE / sizeof(u16));
2218 +
2219 + /*
2220 + * Start validation of the data that has been read.
2221 + */
2222 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2223 + if (!is_valid_ether_addr(mac)) {
2224 + DECLARE_MAC_BUF(macbuf);
2225 +
2226 + random_ether_addr(mac);
2227 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2228 + }
2229 +
2230 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2231 + if (word == 0xffff) {
2232 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2233 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2234 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2235 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2236 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2237 + } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2238 + /*
2239 + * There is a max of 2 RX streams for RT2860 series
2240 + */
2241 + if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2242 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2243 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2244 + }
2245 +
2246 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2247 + if (word == 0xffff) {
2248 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2249 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2250 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2251 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2252 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2253 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2254 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2255 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2256 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2257 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2258 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2259 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2260 + }
2261 +
2262 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2263 + if ((word & 0x00ff) == 0x00ff) {
2264 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2265 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2266 + LED_MODE_TXRX_ACTIVITY);
2267 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2268 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2269 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2270 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2271 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2272 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2273 + }
2274 +
2275 + /*
2276 + * During the LNA validation we are going to use
2277 + * lna0 as correct value. Note that EEPROM_LNA
2278 + * is never validated.
2279 + */
2280 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2281 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2282 +
2283 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2284 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2285 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2286 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2287 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2288 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2289 +
2290 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2291 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2292 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2293 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2294 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2295 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2296 + default_lna_gain);
2297 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2298 +
2299 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2300 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2301 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2302 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2303 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2304 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2305 +
2306 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2307 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2308 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2309 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2310 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2311 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2312 + default_lna_gain);
2313 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2314 +
2315 + return 0;
2316 +}
2317 +
2318 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2319 +{
2320 + u32 reg;
2321 + u16 value;
2322 + u16 eeprom;
2323 + u16 device;
2324 +
2325 + /*
2326 + * Read EEPROM word for configuration.
2327 + */
2328 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2329 +
2330 + /*
2331 + * Identify RF chipset.
2332 + * To determine the RT chip we have to read the
2333 + * PCI header of the device.
2334 + */
2335 + pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2336 + PCI_CONFIG_HEADER_DEVICE, &device);
2337 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2338 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2339 + rt2x00_set_chip(rt2x00dev, device, value, reg);
2340 +
2341 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2342 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2343 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2344 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2345 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2346 + !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2347 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2348 + return -ENODEV;
2349 + }
2350 +
2351 + /*
2352 + * Read frequency offset and RF programming sequence.
2353 + */
2354 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2355 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2356 +
2357 + /*
2358 + * Read external LNA informations.
2359 + */
2360 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2361 +
2362 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2363 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2364 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2365 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2366 +
2367 + /*
2368 + * Detect if this device has an hardware controlled radio.
2369 + */
2370 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2371 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2372 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2373 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2374 +
2375 + /*
2376 + * Store led settings, for correct led behaviour.
2377 + */
2378 +#ifdef CONFIG_RT2X00_LIB_LEDS
2379 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2380 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2381 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2382 +
2383 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2384 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2385 +
2386 + return 0;
2387 +}
2388 +
2389 +/*
2390 + * RF value list for rt2860
2391 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2392 + */
2393 +static const struct rf_channel rf_vals[] = {
2394 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2395 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2396 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2397 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2398 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2399 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2400 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2401 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2402 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2403 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2404 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2405 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2406 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2407 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2408 +
2409 + /* 802.11 UNI / HyperLan 2 */
2410 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2411 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2412 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2413 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2414 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2415 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2416 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2417 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2418 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2419 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2420 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2421 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2422 +
2423 + /* 802.11 HyperLan 2 */
2424 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2425 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2426 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2427 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2428 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2429 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2430 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2431 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2432 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2433 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2434 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2435 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2436 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2437 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2438 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2439 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2440 +
2441 + /* 802.11 UNII */
2442 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2443 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2444 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2445 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2446 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2447 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2448 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2449 +
2450 + /* 802.11 Japan */
2451 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2452 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2453 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2454 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2455 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2456 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2457 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2458 +};
2459 +
2460 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2461 +{
2462 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2463 + struct channel_info *info;
2464 + char *tx_power1;
2465 + char *tx_power2;
2466 + unsigned int i;
2467 + u16 eeprom;
2468 +
2469 + /*
2470 + * Initialize all hw fields.
2471 + */
2472 + rt2x00dev->hw->flags =
2473 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2474 + IEEE80211_HW_SIGNAL_DBM |
2475 + IEEE80211_HW_SUPPORTS_PS |
2476 + IEEE80211_HW_PS_NULLFUNC_STACK;
2477 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2478 +
2479 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2480 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2481 + rt2x00_eeprom_addr(rt2x00dev,
2482 + EEPROM_MAC_ADDR_0));
2483 +
2484 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2485 +
2486 + /*
2487 + * Initialize hw_mode information.
2488 + */
2489 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2490 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2491 +
2492 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2493 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2494 + spec->num_channels = 14;
2495 + spec->channels = rf_vals;
2496 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2497 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2498 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2499 + spec->num_channels = ARRAY_SIZE(rf_vals);
2500 + spec->channels = rf_vals;
2501 + }
2502 +
2503 + /*
2504 + * Initialize HT information.
2505 + */
2506 + spec->ht.ht_supported = true;
2507 + spec->ht.cap =
2508 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2509 + IEEE80211_HT_CAP_GRN_FLD |
2510 + IEEE80211_HT_CAP_SGI_20 |
2511 + IEEE80211_HT_CAP_SGI_40 |
2512 + IEEE80211_HT_CAP_TX_STBC |
2513 + IEEE80211_HT_CAP_RX_STBC |
2514 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2515 + spec->ht.ampdu_factor = 3;
2516 + spec->ht.ampdu_density = 4;
2517 + spec->ht.mcs.tx_params =
2518 + IEEE80211_HT_MCS_TX_DEFINED |
2519 + IEEE80211_HT_MCS_TX_RX_DIFF |
2520 + ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2521 + IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2522 +
2523 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2524 + case 3:
2525 + spec->ht.mcs.rx_mask[2] = 0xff;
2526 + case 2:
2527 + spec->ht.mcs.rx_mask[1] = 0xff;
2528 + case 1:
2529 + spec->ht.mcs.rx_mask[0] = 0xff;
2530 + spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2531 + break;
2532 + }
2533 +
2534 + /*
2535 + * Create channel information array
2536 + */
2537 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2538 + if (!info)
2539 + return -ENOMEM;
2540 +
2541 + spec->channels_info = info;
2542 +
2543 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2544 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2545 +
2546 + for (i = 0; i < 14; i++) {
2547 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2548 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2549 + }
2550 +
2551 + if (spec->num_channels > 14) {
2552 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2553 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2554 +
2555 + for (i = 14; i < spec->num_channels; i++) {
2556 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2557 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2558 + }
2559 + }
2560 +
2561 + return 0;
2562 +}
2563 +
2564 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2565 +{
2566 + int retval;
2567 +
2568 + /*
2569 + * Allocate eeprom data.
2570 + */
2571 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2572 + if (retval)
2573 + return retval;
2574 +
2575 + retval = rt2800pci_init_eeprom(rt2x00dev);
2576 + if (retval)
2577 + return retval;
2578 +
2579 + /*
2580 + * Initialize hw specifications.
2581 + */
2582 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2583 + if (retval)
2584 + return retval;
2585 +
2586 + /*
2587 + * This device requires firmware.
2588 + */
2589 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2590 + if (!modparam_nohwcrypt)
2591 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2592 +
2593 + /*
2594 + * Set the rssi offset.
2595 + */
2596 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2597 +
2598 + return 0;
2599 +}
2600 +
2601 +/*
2602 + * IEEE80211 stack callback functions.
2603 + */
2604 +static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2605 + u32 *iv32, u16 *iv16)
2606 +{
2607 + struct rt2x00_dev *rt2x00dev = hw->priv;
2608 + struct mac_iveiv_entry iveiv_entry;
2609 + u32 offset;
2610 +
2611 + offset = MAC_IVEIV_ENTRY(hw_key_idx);
2612 + rt2x00pci_register_multiread(rt2x00dev, offset,
2613 + &iveiv_entry, sizeof(iveiv_entry));
2614 +
2615 + memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2616 + memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2617 +}
2618 +
2619 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2620 +{
2621 + struct rt2x00_dev *rt2x00dev = hw->priv;
2622 + u32 reg;
2623 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2624 +
2625 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2626 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2627 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2628 +
2629 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2630 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2631 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2632 +
2633 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2634 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2635 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2636 +
2637 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2638 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2639 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2640 +
2641 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2642 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2643 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2644 +
2645 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2646 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2647 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2648 +
2649 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2650 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2651 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2652 +
2653 + return 0;
2654 +}
2655 +
2656 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2657 + const struct ieee80211_tx_queue_params *params)
2658 +{
2659 + struct rt2x00_dev *rt2x00dev = hw->priv;
2660 + struct data_queue *queue;
2661 + struct rt2x00_field32 field;
2662 + int retval;
2663 + u32 reg;
2664 + u32 offset;
2665 +
2666 + /*
2667 + * First pass the configuration through rt2x00lib, that will
2668 + * update the queue settings and validate the input. After that
2669 + * we are free to update the registers based on the value
2670 + * in the queue parameter.
2671 + */
2672 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2673 + if (retval)
2674 + return retval;
2675 +
2676 + /*
2677 + * We only need to perform additional register initialization
2678 + * for WMM queues/
2679 + */
2680 + if (queue_idx >= 4)
2681 + return 0;
2682 +
2683 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2684 +
2685 + /* Update WMM TXOP register */
2686 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2687 + field.bit_offset = (queue_idx & 1) * 16;
2688 + field.bit_mask = 0xffff << field.bit_offset;
2689 +
2690 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2691 + rt2x00_set_field32(&reg, field, queue->txop);
2692 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2693 +
2694 + /* Update WMM registers */
2695 + field.bit_offset = queue_idx * 4;
2696 + field.bit_mask = 0xf << field.bit_offset;
2697 +
2698 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2699 + rt2x00_set_field32(&reg, field, queue->aifs);
2700 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2701 +
2702 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2703 + rt2x00_set_field32(&reg, field, queue->cw_min);
2704 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2705 +
2706 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2707 + rt2x00_set_field32(&reg, field, queue->cw_max);
2708 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2709 +
2710 + /* Update EDCA registers */
2711 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2712 +
2713 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2714 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2715 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2716 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2717 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2718 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2719 +
2720 + return 0;
2721 +}
2722 +
2723 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2724 +{
2725 + struct rt2x00_dev *rt2x00dev = hw->priv;
2726 + u64 tsf;
2727 + u32 reg;
2728 +
2729 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2730 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2731 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2732 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2733 +
2734 + return tsf;
2735 +}
2736 +
2737 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2738 + .tx = rt2x00mac_tx,
2739 + .start = rt2x00mac_start,
2740 + .stop = rt2x00mac_stop,
2741 + .add_interface = rt2x00mac_add_interface,
2742 + .remove_interface = rt2x00mac_remove_interface,
2743 + .config = rt2x00mac_config,
2744 + .config_interface = rt2x00mac_config_interface,
2745 + .configure_filter = rt2x00mac_configure_filter,
2746 + .set_key = rt2x00mac_set_key,
2747 + .get_stats = rt2x00mac_get_stats,
2748 + .get_tkip_seq = rt2800pci_get_tkip_seq,
2749 + .set_rts_threshold = rt2800pci_set_rts_threshold,
2750 + .bss_info_changed = rt2x00mac_bss_info_changed,
2751 + .conf_tx = rt2800pci_conf_tx,
2752 + .get_tx_stats = rt2x00mac_get_tx_stats,
2753 + .get_tsf = rt2800pci_get_tsf,
2754 +};
2755 +
2756 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2757 + .irq_handler = rt2800pci_interrupt,
2758 + .probe_hw = rt2800pci_probe_hw,
2759 + .get_firmware_name = rt2800pci_get_firmware_name,
2760 + .check_firmware = rt2800pci_check_firmware,
2761 + .load_firmware = rt2800pci_load_firmware,
2762 + .initialize = rt2x00pci_initialize,
2763 + .uninitialize = rt2x00pci_uninitialize,
2764 + .get_entry_state = rt2800pci_get_entry_state,
2765 + .clear_entry = rt2800pci_clear_entry,
2766 + .set_device_state = rt2800pci_set_device_state,
2767 + .rfkill_poll = rt2800pci_rfkill_poll,
2768 + .link_stats = rt2800pci_link_stats,
2769 + .reset_tuner = rt2800pci_reset_tuner,
2770 + .link_tuner = rt2800pci_link_tuner,
2771 + .write_tx_desc = rt2800pci_write_tx_desc,
2772 + .write_tx_data = rt2x00pci_write_tx_data,
2773 + .write_beacon = rt2800pci_write_beacon,
2774 + .kick_tx_queue = rt2800pci_kick_tx_queue,
2775 + .kill_tx_queue = rt2800pci_kill_tx_queue,
2776 + .fill_rxdone = rt2800pci_fill_rxdone,
2777 + .config_shared_key = rt2800pci_config_shared_key,
2778 + .config_pairwise_key = rt2800pci_config_pairwise_key,
2779 + .config_filter = rt2800pci_config_filter,
2780 + .config_intf = rt2800pci_config_intf,
2781 + .config_erp = rt2800pci_config_erp,
2782 + .config_ant = rt2800pci_config_ant,
2783 + .config = rt2800pci_config,
2784 +};
2785 +
2786 +static const struct data_queue_desc rt2800pci_queue_rx = {
2787 + .entry_num = RX_ENTRIES,
2788 + .data_size = AGGREGATION_SIZE,
2789 + .desc_size = RXD_DESC_SIZE,
2790 + .priv_size = sizeof(struct queue_entry_priv_pci),
2791 +};
2792 +
2793 +static const struct data_queue_desc rt2800pci_queue_tx = {
2794 + .entry_num = TX_ENTRIES,
2795 + .data_size = AGGREGATION_SIZE,
2796 + .desc_size = TXD_DESC_SIZE,
2797 + .priv_size = sizeof(struct queue_entry_priv_pci),
2798 +};
2799 +
2800 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2801 + .entry_num = 8 * BEACON_ENTRIES,
2802 + .data_size = 0, /* No DMA required for beacons */
2803 + .desc_size = TXWI_DESC_SIZE,
2804 + .priv_size = sizeof(struct queue_entry_priv_pci),
2805 +};
2806 +
2807 +static const struct rt2x00_ops rt2800pci_ops = {
2808 + .name = KBUILD_MODNAME,
2809 + .max_sta_intf = 1,
2810 + .max_ap_intf = 8,
2811 + .eeprom_size = EEPROM_SIZE,
2812 + .rf_size = RF_SIZE,
2813 + .tx_queues = NUM_TX_QUEUES,
2814 + .rx = &rt2800pci_queue_rx,
2815 + .tx = &rt2800pci_queue_tx,
2816 + .bcn = &rt2800pci_queue_bcn,
2817 + .lib = &rt2800pci_rt2x00_ops,
2818 + .hw = &rt2800pci_mac80211_ops,
2819 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2820 + .debugfs = &rt2800pci_rt2x00debug,
2821 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2822 +};
2823 +
2824 +/*
2825 + * RT2800pci module information.
2826 + */
2827 +static struct pci_device_id rt2800pci_device_table[] = {
2828 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2829 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2830 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2831 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2832 + { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
2833 + { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
2834 + { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
2835 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2836 + { 0, }
2837 +};
2838 +
2839 +MODULE_AUTHOR(DRV_PROJECT);
2840 +MODULE_VERSION(DRV_VERSION);
2841 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2842 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2843 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2844 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2845 +MODULE_LICENSE("GPL");
2846 +
2847 +static struct pci_driver rt2800pci_driver = {
2848 + .name = KBUILD_MODNAME,
2849 + .id_table = rt2800pci_device_table,
2850 + .probe = rt2x00pci_probe,
2851 + .remove = __devexit_p(rt2x00pci_remove),
2852 + .suspend = rt2x00pci_suspend,
2853 + .resume = rt2x00pci_resume,
2854 +};
2855 +
2856 +static int __init rt2800pci_init(void)
2857 +{
2858 + return pci_register_driver(&rt2800pci_driver);
2859 +}
2860 +
2861 +static void __exit rt2800pci_exit(void)
2862 +{
2863 + pci_unregister_driver(&rt2800pci_driver);
2864 +}
2865 +
2866 +module_init(rt2800pci_init);
2867 +module_exit(rt2800pci_exit);
2868 --- /dev/null
2869 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2870 @@ -0,0 +1,1867 @@
2871 +/*
2872 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
2873 + <http://rt2x00.serialmonkey.com>
2874 +
2875 + This program is free software; you can redistribute it and/or modify
2876 + it under the terms of the GNU General Public License as published by
2877 + the Free Software Foundation; either version 2 of the License, or
2878 + (at your option) any later version.
2879 +
2880 + This program is distributed in the hope that it will be useful,
2881 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2882 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2883 + GNU General Public License for more details.
2884 +
2885 + You should have received a copy of the GNU General Public License
2886 + along with this program; if not, write to the
2887 + Free Software Foundation, Inc.,
2888 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2889 + */
2890 +
2891 +/*
2892 + Module: rt2800pci
2893 + Abstract: Data structures and registers for the rt2800pci module.
2894 + Supported chipsets: RT2800E & RT2800ED.
2895 + */
2896 +
2897 +#ifndef RT2800PCI_H
2898 +#define RT2800PCI_H
2899 +
2900 +/*
2901 + * RF chip defines.
2902 + *
2903 + * RF2820 2.4G 2T3R
2904 + * RF2850 2.4G/5G 2T3R
2905 + * RF2720 2.4G 1T2R
2906 + * RF2750 2.4G/5G 1T2R
2907 + * RF3020 2.4G 1T1R
2908 + * RF2020 2.4G B/G
2909 + */
2910 +#define RF2820 0x0001
2911 +#define RF2850 0x0002
2912 +#define RF2720 0x0003
2913 +#define RF2750 0x0004
2914 +#define RF3020 0x0005
2915 +#define RF2020 0x0006
2916 +
2917 +/*
2918 + * RT2860 version
2919 + */
2920 +#define RT2860C_VERSION 0x28600100
2921 +#define RT2860D_VERSION 0x28600101
2922 +#define RT2880E_VERSION 0x28720200
2923 +#define RT2883_VERSION 0x28830300
2924 +#define RT3070_VERSION 0x30700200
2925 +
2926 +/*
2927 + * Signal information.
2928 + * Defaul offset is required for RSSI <-> dBm conversion.
2929 + */
2930 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2931 +
2932 +/*
2933 + * Register layout information.
2934 + */
2935 +#define CSR_REG_BASE 0x1000
2936 +#define CSR_REG_SIZE 0x0800
2937 +#define EEPROM_BASE 0x0000
2938 +#define EEPROM_SIZE 0x0110
2939 +#define BBP_BASE 0x0000
2940 +#define BBP_SIZE 0x0080
2941 +#define RF_BASE 0x0004
2942 +#define RF_SIZE 0x0010
2943 +
2944 +/*
2945 + * Number of TX queues.
2946 + */
2947 +#define NUM_TX_QUEUES 4
2948 +
2949 +/*
2950 + * PCI registers.
2951 + */
2952 +
2953 +/*
2954 + * PCI Configuration Header
2955 + */
2956 +#define PCI_CONFIG_HEADER_VENDOR 0x0000
2957 +#define PCI_CONFIG_HEADER_DEVICE 0x0002
2958 +
2959 +/*
2960 + * E2PROM_CSR: EEPROM control register.
2961 + * RELOAD: Write 1 to reload eeprom content.
2962 + * TYPE: 0: 93c46, 1:93c66.
2963 + * LOAD_STATUS: 1:loading, 0:done.
2964 + */
2965 +#define E2PROM_CSR 0x0004
2966 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
2967 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
2968 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
2969 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
2970 +#define E2PROM_CSR_TYPE FIELD32(0x00000030)
2971 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
2972 +#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
2973 +
2974 +/*
2975 + * HOST-MCU shared memory
2976 + */
2977 +#define HOST_CMD_CSR 0x0404
2978 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2979 +
2980 +/*
2981 + * INT_SOURCE_CSR: Interrupt source register.
2982 + * Write one to clear corresponding bit.
2983 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2984 + */
2985 +#define INT_SOURCE_CSR 0x0200
2986 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2987 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2988 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2989 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2990 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2991 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2992 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2993 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2994 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2995 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2996 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2997 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2998 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2999 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3000 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3001 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
3002 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
3003 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
3004 +
3005 +/*
3006 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3007 + */
3008 +#define INT_MASK_CSR 0x0204
3009 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
3010 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
3011 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
3012 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3013 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3014 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3015 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3016 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3017 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3018 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
3019 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
3020 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
3021 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
3022 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3023 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3024 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
3025 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
3026 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
3027 +
3028 +/*
3029 + * WPDMA_GLO_CFG
3030 + */
3031 +#define WPDMA_GLO_CFG 0x0208
3032 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
3033 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
3034 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
3035 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
3036 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
3037 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
3038 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
3039 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
3040 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
3041 +
3042 +/*
3043 + * WPDMA_RST_IDX
3044 + */
3045 +#define WPDMA_RST_IDX 0x020c
3046 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
3047 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
3048 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
3049 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
3050 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
3051 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
3052 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
3053 +
3054 +/*
3055 + * DELAY_INT_CFG
3056 + */
3057 +#define DELAY_INT_CFG 0x0210
3058 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
3059 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
3060 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
3061 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
3062 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
3063 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
3064 +
3065 +/*
3066 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3067 + * AIFSN0: AC_BE
3068 + * AIFSN1: AC_BK
3069 + * AIFSN1: AC_VI
3070 + * AIFSN1: AC_VO
3071 + */
3072 +#define WMM_AIFSN_CFG 0x0214
3073 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3074 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3075 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3076 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3077 +
3078 +/*
3079 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3080 + * CWMIN0: AC_BE
3081 + * CWMIN1: AC_BK
3082 + * CWMIN1: AC_VI
3083 + * CWMIN1: AC_VO
3084 + */
3085 +#define WMM_CWMIN_CFG 0x0218
3086 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3087 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3088 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3089 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3090 +
3091 +/*
3092 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3093 + * CWMAX0: AC_BE
3094 + * CWMAX1: AC_BK
3095 + * CWMAX1: AC_VI
3096 + * CWMAX1: AC_VO
3097 + */
3098 +#define WMM_CWMAX_CFG 0x021c
3099 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3100 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3101 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3102 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3103 +
3104 +/*
3105 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3106 + * AC0TXOP: AC_BK in unit of 32us
3107 + * AC1TXOP: AC_BE in unit of 32us
3108 + */
3109 +#define WMM_TXOP0_CFG 0x0220
3110 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3111 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3112 +
3113 +/*
3114 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3115 + * AC2TXOP: AC_VI in unit of 32us
3116 + * AC3TXOP: AC_VO in unit of 32us
3117 + */
3118 +#define WMM_TXOP1_CFG 0x0224
3119 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3120 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3121 +
3122 +/*
3123 + * GPIO_CTRL_CFG:
3124 + */
3125 +#define GPIO_CTRL_CFG 0x0228
3126 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3127 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3128 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3129 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3130 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3131 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3132 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3133 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3134 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3135 +
3136 +/*
3137 + * MCU_CMD_CFG
3138 + */
3139 +#define MCU_CMD_CFG 0x022c
3140 +
3141 +/*
3142 + * AC_BK register offsets
3143 + */
3144 +#define TX_BASE_PTR0 0x0230
3145 +#define TX_MAX_CNT0 0x0234
3146 +#define TX_CTX_IDX0 0x0238
3147 +#define TX_DTX_IDX0 0x023c
3148 +
3149 +/*
3150 + * AC_BE register offsets
3151 + */
3152 +#define TX_BASE_PTR1 0x0240
3153 +#define TX_MAX_CNT1 0x0244
3154 +#define TX_CTX_IDX1 0x0248
3155 +#define TX_DTX_IDX1 0x024c
3156 +
3157 +/*
3158 + * AC_VI register offsets
3159 + */
3160 +#define TX_BASE_PTR2 0x0250
3161 +#define TX_MAX_CNT2 0x0254
3162 +#define TX_CTX_IDX2 0x0258
3163 +#define TX_DTX_IDX2 0x025c
3164 +
3165 +/*
3166 + * AC_VO register offsets
3167 + */
3168 +#define TX_BASE_PTR3 0x0260
3169 +#define TX_MAX_CNT3 0x0264
3170 +#define TX_CTX_IDX3 0x0268
3171 +#define TX_DTX_IDX3 0x026c
3172 +
3173 +/*
3174 + * HCCA register offsets
3175 + */
3176 +#define TX_BASE_PTR4 0x0270
3177 +#define TX_MAX_CNT4 0x0274
3178 +#define TX_CTX_IDX4 0x0278
3179 +#define TX_DTX_IDX4 0x027c
3180 +
3181 +/*
3182 + * MGMT register offsets
3183 + */
3184 +#define TX_BASE_PTR5 0x0280
3185 +#define TX_MAX_CNT5 0x0284
3186 +#define TX_CTX_IDX5 0x0288
3187 +#define TX_DTX_IDX5 0x028c
3188 +
3189 +/*
3190 + * Queue register offset macros
3191 + */
3192 +#define TX_QUEUE_REG_OFFSET 0x10
3193 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3194 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3195 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3196 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3197 +
3198 +/*
3199 + * RX register offsets
3200 + */
3201 +#define RX_BASE_PTR 0x0290
3202 +#define RX_MAX_CNT 0x0294
3203 +#define RX_CRX_IDX 0x0298
3204 +#define RX_DRX_IDX 0x029c
3205 +
3206 +/*
3207 + * PBF_SYS_CTRL
3208 + * HOST_RAM_WRITE: enable Host program ram write selection
3209 + */
3210 +#define PBF_SYS_CTRL 0x0400
3211 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3212 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3213 +
3214 +/*
3215 + * PBF registers
3216 + * Most are for debug. Driver doesn't touch PBF register.
3217 + */
3218 +#define PBF_CFG 0x0408
3219 +#define PBF_MAX_PCNT 0x040c
3220 +#define PBF_CTRL 0x0410
3221 +#define PBF_INT_STA 0x0414
3222 +#define PBF_INT_ENA 0x0418
3223 +
3224 +/*
3225 + * BCN_OFFSET0:
3226 + */
3227 +#define BCN_OFFSET0 0x042c
3228 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3229 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3230 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3231 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3232 +
3233 +/*
3234 + * BCN_OFFSET1:
3235 + */
3236 +#define BCN_OFFSET1 0x0430
3237 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3238 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3239 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3240 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3241 +
3242 +/*
3243 + * PBF registers
3244 + * Most are for debug. Driver doesn't touch PBF register.
3245 + */
3246 +#define TXRXQ_PCNT 0x0438
3247 +#define PBF_DBG 0x043c
3248 +
3249 +/*
3250 + * MAC Control/Status Registers(CSR).
3251 + * Some values are set in TU, whereas 1 TU == 1024 us.
3252 + */
3253 +
3254 +/*
3255 + * MAC_CSR0: ASIC revision number.
3256 + * ASIC_REV: 0
3257 + * ASIC_VER: 2860
3258 + */
3259 +#define MAC_CSR0 0x1000
3260 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3261 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3262 +
3263 +/*
3264 + * MAC_SYS_CTRL:
3265 + */
3266 +#define MAC_SYS_CTRL 0x1004
3267 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3268 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3269 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3270 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3271 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3272 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3273 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3274 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3275 +
3276 +/*
3277 + * MAC_ADDR_DW0: STA MAC register 0
3278 + */
3279 +#define MAC_ADDR_DW0 0x1008
3280 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3281 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3282 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3283 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3284 +
3285 +/*
3286 + * MAC_ADDR_DW1: STA MAC register 1
3287 + * UNICAST_TO_ME_MASK:
3288 + * Used to mask off bits from byte 5 of the MAC address
3289 + * to determine the UNICAST_TO_ME bit for RX frames.
3290 + * The full mask is complemented by BSS_ID_MASK:
3291 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3292 + */
3293 +#define MAC_ADDR_DW1 0x100c
3294 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3295 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3296 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3297 +
3298 +/*
3299 + * MAC_BSSID_DW0: BSSID register 0
3300 + */
3301 +#define MAC_BSSID_DW0 0x1010
3302 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3303 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3304 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3305 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3306 +
3307 +/*
3308 + * MAC_BSSID_DW1: BSSID register 1
3309 + * BSS_ID_MASK:
3310 + * 0: 1-BSSID mode (BSS index = 0)
3311 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3312 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3313 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3314 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3315 + * BSSID. This will make sure that those bits will be ignored
3316 + * when determining the MY_BSS of RX frames.
3317 + */
3318 +#define MAC_BSSID_DW1 0x1014
3319 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3320 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3321 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3322 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3323 +
3324 +/*
3325 + * MAX_LEN_CFG: Maximum frame length register.
3326 + * MAX_MPDU: rt2860b max 16k bytes
3327 + * MAX_PSDU: Maximum PSDU length
3328 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3329 + */
3330 +#define MAX_LEN_CFG 0x1018
3331 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3332 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3333 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3334 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3335 +
3336 +/*
3337 + * BBP_CSR_CFG: BBP serial control register
3338 + * VALUE: Register value to program into BBP
3339 + * REG_NUM: Selected BBP register
3340 + * READ_CONTROL: 0 write BBP, 1 read BBP
3341 + * BUSY: ASIC is busy executing BBP commands
3342 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3343 + * BBP_RW_MODE: 0 serial, 1 paralell
3344 + */
3345 +#define BBP_CSR_CFG 0x101c
3346 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3347 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3348 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3349 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3350 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3351 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3352 +
3353 +/*
3354 + * RF_CSR_CFG0: RF control register
3355 + * REGID_AND_VALUE: Register value to program into RF
3356 + * BITWIDTH: Selected RF register
3357 + * STANDBYMODE: 0 high when standby, 1 low when standby
3358 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3359 + * BUSY: ASIC is busy executing RF commands
3360 + */
3361 +#define RF_CSR_CFG0 0x1020
3362 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3363 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3364 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3365 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3366 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3367 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3368 +
3369 +/*
3370 + * RF_CSR_CFG1: RF control register
3371 + * REGID_AND_VALUE: Register value to program into RF
3372 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3373 + * 0: 3 system clock cycle (37.5usec)
3374 + * 1: 5 system clock cycle (62.5usec)
3375 + */
3376 +#define RF_CSR_CFG1 0x1024
3377 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3378 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3379 +
3380 +/*
3381 + * RF_CSR_CFG2: RF control register
3382 + * VALUE: Register value to program into RF
3383 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3384 + * 0: 3 system clock cycle (37.5usec)
3385 + * 1: 5 system clock cycle (62.5usec)
3386 + */
3387 +#define RF_CSR_CFG2 0x1028
3388 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3389 +
3390 +/*
3391 + * LED_CFG: LED control
3392 + * color LED's:
3393 + * 0: off
3394 + * 1: blinking upon TX2
3395 + * 2: periodic slow blinking
3396 + * 3: always on
3397 + * LED polarity:
3398 + * 0: active low
3399 + * 1: active high
3400 + */
3401 +#define LED_CFG 0x102c
3402 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3403 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3404 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3405 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3406 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3407 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3408 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3409 +
3410 +/*
3411 + * XIFS_TIME_CFG: MAC timing
3412 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3413 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3414 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3415 + * when MAC doesn't reference BBP signal BBRXEND
3416 + * EIFS: unit 1us
3417 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3418 + *
3419 + */
3420 +#define XIFS_TIME_CFG 0x1100
3421 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3422 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3423 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3424 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3425 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3426 +
3427 +/*
3428 + * BKOFF_SLOT_CFG:
3429 + */
3430 +#define BKOFF_SLOT_CFG 0x1104
3431 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3432 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3433 +
3434 +/*
3435 + * NAV_TIME_CFG:
3436 + */
3437 +#define NAV_TIME_CFG 0x1108
3438 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3439 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3440 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3441 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3442 +
3443 +/*
3444 + * CH_TIME_CFG: count as channel busy
3445 + */
3446 +#define CH_TIME_CFG 0x110c
3447 +
3448 +/*
3449 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3450 + */
3451 +#define PBF_LIFE_TIMER 0x1110
3452 +
3453 +/*
3454 + * BCN_TIME_CFG:
3455 + * BEACON_INTERVAL: in unit of 1/16 TU
3456 + * TSF_TICKING: Enable TSF auto counting
3457 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3458 + * BEACON_GEN: Enable beacon generator
3459 + */
3460 +#define BCN_TIME_CFG 0x1114
3461 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3462 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3463 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3464 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3465 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3466 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3467 +
3468 +/*
3469 + * TBTT_SYNC_CFG:
3470 + */
3471 +#define TBTT_SYNC_CFG 0x1118
3472 +
3473 +/*
3474 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3475 + */
3476 +#define TSF_TIMER_DW0 0x111c
3477 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3478 +
3479 +/*
3480 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3481 + */
3482 +#define TSF_TIMER_DW1 0x1120
3483 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3484 +
3485 +/*
3486 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3487 + */
3488 +#define TBTT_TIMER 0x1124
3489 +
3490 +/*
3491 + * INT_TIMER_CFG:
3492 + */
3493 +#define INT_TIMER_CFG 0x1128
3494 +
3495 +/*
3496 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3497 + */
3498 +#define INT_TIMER_EN 0x112c
3499 +
3500 +/*
3501 + * CH_IDLE_STA: channel idle time
3502 + */
3503 +#define CH_IDLE_STA 0x1130
3504 +
3505 +/*
3506 + * CH_BUSY_STA: channel busy time
3507 + */
3508 +#define CH_BUSY_STA 0x1134
3509 +
3510 +/*
3511 + * MAC_STATUS_CFG:
3512 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3513 + * if 1 or higher one of the 2 registers is busy.
3514 + */
3515 +#define MAC_STATUS_CFG 0x1200
3516 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3517 +
3518 +/*
3519 + * PWR_PIN_CFG:
3520 + */
3521 +#define PWR_PIN_CFG 0x1204
3522 +
3523 +/*
3524 + * AUTOWAKEUP_CFG: Manual power control / status register
3525 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3526 + * AUTOWAKE: 0:sleep, 1:awake
3527 + */
3528 +#define AUTOWAKEUP_CFG 0x1208
3529 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3530 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3531 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3532 +
3533 +/*
3534 + * EDCA_AC0_CFG:
3535 + */
3536 +#define EDCA_AC0_CFG 0x1300
3537 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3538 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3539 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3540 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3541 +
3542 +/*
3543 + * EDCA_AC1_CFG:
3544 + */
3545 +#define EDCA_AC1_CFG 0x1304
3546 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3547 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3548 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3549 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3550 +
3551 +/*
3552 + * EDCA_AC2_CFG:
3553 + */
3554 +#define EDCA_AC2_CFG 0x1308
3555 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3556 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3557 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3558 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3559 +
3560 +/*
3561 + * EDCA_AC3_CFG:
3562 + */
3563 +#define EDCA_AC3_CFG 0x130c
3564 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3565 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3566 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3567 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3568 +
3569 +/*
3570 + * EDCA_TID_AC_MAP:
3571 + */
3572 +#define EDCA_TID_AC_MAP 0x1310
3573 +
3574 +/*
3575 + * TX_PWR_CFG_0:
3576 + */
3577 +#define TX_PWR_CFG_0 0x1314
3578 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3579 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3580 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3581 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3582 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3583 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3584 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3585 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3586 +
3587 +/*
3588 + * TX_PWR_CFG_1:
3589 + */
3590 +#define TX_PWR_CFG_1 0x1318
3591 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3592 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3593 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3594 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3595 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3596 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3597 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3598 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3599 +
3600 +/*
3601 + * TX_PWR_CFG_2:
3602 + */
3603 +#define TX_PWR_CFG_2 0x131c
3604 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3605 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3606 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3607 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3608 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3609 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3610 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3611 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3612 +
3613 +/*
3614 + * TX_PWR_CFG_3:
3615 + */
3616 +#define TX_PWR_CFG_3 0x1320
3617 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3618 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3619 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3620 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3621 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3622 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3623 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3624 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3625 +
3626 +/*
3627 + * TX_PWR_CFG_4:
3628 + */
3629 +#define TX_PWR_CFG_4 0x1324
3630 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3631 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3632 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3633 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3634 +
3635 +/*
3636 + * TX_PIN_CFG:
3637 + */
3638 +#define TX_PIN_CFG 0x1328
3639 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3640 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3641 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3642 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3643 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3644 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3645 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3646 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3647 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3648 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3649 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3650 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3651 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3652 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3653 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3654 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3655 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3656 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3657 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3658 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3659 +
3660 +/*
3661 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3662 + */
3663 +#define TX_BAND_CFG 0x132c
3664 +#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
3665 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3666 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3667 +
3668 +/*
3669 + * TX_SW_CFG0:
3670 + */
3671 +#define TX_SW_CFG0 0x1330
3672 +
3673 +/*
3674 + * TX_SW_CFG1:
3675 + */
3676 +#define TX_SW_CFG1 0x1334
3677 +
3678 +/*
3679 + * TX_SW_CFG2:
3680 + */
3681 +#define TX_SW_CFG2 0x1338
3682 +
3683 +/*
3684 + * TXOP_THRES_CFG:
3685 + */
3686 +#define TXOP_THRES_CFG 0x133c
3687 +
3688 +/*
3689 + * TXOP_CTRL_CFG:
3690 + */
3691 +#define TXOP_CTRL_CFG 0x1340
3692 +
3693 +/*
3694 + * TX_RTS_CFG:
3695 + * RTS_THRES: unit:byte
3696 + * RTS_FBK_EN: enable rts rate fallback
3697 + */
3698 +#define TX_RTS_CFG 0x1344
3699 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3700 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3701 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3702 +
3703 +/*
3704 + * TX_TIMEOUT_CFG:
3705 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3706 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3707 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3708 + * it is recommended that:
3709 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3710 + */
3711 +#define TX_TIMEOUT_CFG 0x1348
3712 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3713 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3714 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3715 +
3716 +/*
3717 + * TX_RTY_CFG:
3718 + * SHORT_RTY_LIMIT: short retry limit
3719 + * LONG_RTY_LIMIT: long retry limit
3720 + * LONG_RTY_THRE: Long retry threshoold
3721 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3722 + * 0:expired by retry limit, 1: expired by mpdu life timer
3723 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3724 + * 0:expired by retry limit, 1: expired by mpdu life timer
3725 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3726 + */
3727 +#define TX_RTY_CFG 0x134c
3728 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3729 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3730 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3731 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3732 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3733 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3734 +
3735 +/*
3736 + * TX_LINK_CFG:
3737 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3738 + * MFB_ENABLE: TX apply remote MFB 1:enable
3739 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3740 + * 0: not apply remote remote unsolicit (MFS=7)
3741 + * TX_MRQ_EN: MCS request TX enable
3742 + * TX_RDG_EN: RDG TX enable
3743 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3744 + * REMOTE_MFB: remote MCS feedback
3745 + * REMOTE_MFS: remote MCS feedback sequence number
3746 + */
3747 +#define TX_LINK_CFG 0x1350
3748 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3749 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3750 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3751 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3752 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3753 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3754 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3755 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3756 +
3757 +/*
3758 + * HT_FBK_CFG0:
3759 + */
3760 +#define HT_FBK_CFG0 0x1354
3761 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3762 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3763 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3764 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3765 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3766 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3767 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3768 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3769 +
3770 +/*
3771 + * HT_FBK_CFG1:
3772 + */
3773 +#define HT_FBK_CFG1 0x1358
3774 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3775 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3776 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3777 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3778 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3779 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3780 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3781 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3782 +
3783 +/*
3784 + * LG_FBK_CFG0:
3785 + */
3786 +#define LG_FBK_CFG0 0x135c
3787 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3788 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3789 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3790 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3791 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3792 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3793 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3794 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3795 +
3796 +/*
3797 + * LG_FBK_CFG1:
3798 + */
3799 +#define LG_FBK_CFG1 0x1360
3800 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3801 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3802 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3803 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3804 +
3805 +/*
3806 + * CCK_PROT_CFG: CCK Protection
3807 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3808 + * PROTECT_CTRL: Protection control frame type for CCK TX
3809 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3810 + * PROTECT_NAV: TXOP protection type for CCK TX
3811 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3812 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3813 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3814 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3815 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3816 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3817 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3818 + * RTS_TH_EN: RTS threshold enable on CCK TX
3819 + */
3820 +#define CCK_PROT_CFG 0x1364
3821 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3822 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3823 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3824 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3825 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3826 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3827 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3828 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3829 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3830 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3831 +
3832 +/*
3833 + * OFDM_PROT_CFG: OFDM Protection
3834 + */
3835 +#define OFDM_PROT_CFG 0x1368
3836 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3837 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3838 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3839 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3840 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3841 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3842 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3843 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3844 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3845 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3846 +
3847 +/*
3848 + * MM20_PROT_CFG: MM20 Protection
3849 + */
3850 +#define MM20_PROT_CFG 0x136c
3851 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3852 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3853 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3854 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3855 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3856 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3857 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3858 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3859 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3860 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3861 +
3862 +/*
3863 + * MM40_PROT_CFG: MM40 Protection
3864 + */
3865 +#define MM40_PROT_CFG 0x1370
3866 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3867 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3868 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3869 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3870 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3871 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3872 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3873 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3874 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3875 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3876 +
3877 +/*
3878 + * GF20_PROT_CFG: GF20 Protection
3879 + */
3880 +#define GF20_PROT_CFG 0x1374
3881 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3882 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3883 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3884 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3885 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3886 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3887 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3888 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3889 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3890 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3891 +
3892 +/*
3893 + * GF40_PROT_CFG: GF40 Protection
3894 + */
3895 +#define GF40_PROT_CFG 0x1378
3896 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3897 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3898 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3899 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3900 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3901 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3902 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3903 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3904 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3905 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3906 +
3907 +/*
3908 + * EXP_CTS_TIME:
3909 + */
3910 +#define EXP_CTS_TIME 0x137c
3911 +
3912 +/*
3913 + * EXP_ACK_TIME:
3914 + */
3915 +#define EXP_ACK_TIME 0x1380
3916 +
3917 +/*
3918 + * RX_FILTER_CFG: RX configuration register.
3919 + */
3920 +#define RX_FILTER_CFG 0x1400
3921 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
3922 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
3923 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
3924 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3925 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
3926 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
3927 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
3928 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
3929 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
3930 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
3931 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
3932 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
3933 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
3934 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
3935 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
3936 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
3937 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
3938 +
3939 +/*
3940 + * AUTO_RSP_CFG:
3941 + * AUTORESPONDER: 0: disable, 1: enable
3942 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3943 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3944 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3945 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3946 + * DUAL_CTS_EN: Power bit value in control frame
3947 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3948 + */
3949 +#define AUTO_RSP_CFG 0x1404
3950 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
3951 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
3952 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
3953 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
3954 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
3955 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
3956 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
3957 +
3958 +/*
3959 + * LEGACY_BASIC_RATE:
3960 + */
3961 +#define LEGACY_BASIC_RATE 0x1408
3962 +
3963 +/*
3964 + * HT_BASIC_RATE:
3965 + */
3966 +#define HT_BASIC_RATE 0x140c
3967 +
3968 +/*
3969 + * HT_CTRL_CFG:
3970 + */
3971 +#define HT_CTRL_CFG 0x1410
3972 +
3973 +/*
3974 + * SIFS_COST_CFG:
3975 + */
3976 +#define SIFS_COST_CFG 0x1414
3977 +
3978 +/*
3979 + * RX_PARSER_CFG:
3980 + * Set NAV for all received frames
3981 + */
3982 +#define RX_PARSER_CFG 0x1418
3983 +
3984 +/*
3985 + * TX_SEC_CNT0:
3986 + */
3987 +#define TX_SEC_CNT0 0x1500
3988 +
3989 +/*
3990 + * RX_SEC_CNT0:
3991 + */
3992 +#define RX_SEC_CNT0 0x1504
3993 +
3994 +/*
3995 + * CCMP_FC_MUTE:
3996 + */
3997 +#define CCMP_FC_MUTE 0x1508
3998 +
3999 +/*
4000 + * TXOP_HLDR_ADDR0:
4001 + */
4002 +#define TXOP_HLDR_ADDR0 0x1600
4003 +
4004 +/*
4005 + * TXOP_HLDR_ADDR1:
4006 + */
4007 +#define TXOP_HLDR_ADDR1 0x1604
4008 +
4009 +/*
4010 + * TXOP_HLDR_ET:
4011 + */
4012 +#define TXOP_HLDR_ET 0x1608
4013 +
4014 +/*
4015 + * QOS_CFPOLL_RA_DW0:
4016 + */
4017 +#define QOS_CFPOLL_RA_DW0 0x160c
4018 +
4019 +/*
4020 + * QOS_CFPOLL_RA_DW1:
4021 + */
4022 +#define QOS_CFPOLL_RA_DW1 0x1610
4023 +
4024 +/*
4025 + * QOS_CFPOLL_QC:
4026 + */
4027 +#define QOS_CFPOLL_QC 0x1614
4028 +
4029 +/*
4030 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4031 + */
4032 +#define RX_STA_CNT0 0x1700
4033 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
4034 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
4035 +
4036 +/*
4037 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4038 + */
4039 +#define RX_STA_CNT1 0x1704
4040 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
4041 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
4042 +
4043 +/*
4044 + * RX_STA_CNT2:
4045 + */
4046 +#define RX_STA_CNT2 0x1708
4047 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
4048 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
4049 +
4050 +/*
4051 + * TX_STA_CNT0: TX Beacon count
4052 + */
4053 +#define TX_STA_CNT0 0x170c
4054 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
4055 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
4056 +
4057 +/*
4058 + * TX_STA_CNT1: TX tx count
4059 + */
4060 +#define TX_STA_CNT1 0x1710
4061 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
4062 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
4063 +
4064 +/*
4065 + * TX_STA_CNT2: TX tx count
4066 + */
4067 +#define TX_STA_CNT2 0x1714
4068 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
4069 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
4070 +
4071 +/*
4072 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4073 + */
4074 +#define TX_STA_FIFO 0x1718
4075 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
4076 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
4077 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
4078 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4079 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4080 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4081 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4082 +
4083 +/*
4084 + * TX_AGG_CNT: Debug counter
4085 + */
4086 +#define TX_AGG_CNT 0x171c
4087 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4088 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4089 +
4090 +/*
4091 + * TX_AGG_CNT0:
4092 + */
4093 +#define TX_AGG_CNT0 0x1720
4094 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4095 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4096 +
4097 +/*
4098 + * TX_AGG_CNT1:
4099 + */
4100 +#define TX_AGG_CNT1 0x1724
4101 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4102 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4103 +
4104 +/*
4105 + * TX_AGG_CNT2:
4106 + */
4107 +#define TX_AGG_CNT2 0x1728
4108 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4109 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4110 +
4111 +/*
4112 + * TX_AGG_CNT3:
4113 + */
4114 +#define TX_AGG_CNT3 0x172c
4115 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4116 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4117 +
4118 +/*
4119 + * TX_AGG_CNT4:
4120 + */
4121 +#define TX_AGG_CNT4 0x1730
4122 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4123 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4124 +
4125 +/*
4126 + * TX_AGG_CNT5:
4127 + */
4128 +#define TX_AGG_CNT5 0x1734
4129 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4130 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4131 +
4132 +/*
4133 + * TX_AGG_CNT6:
4134 + */
4135 +#define TX_AGG_CNT6 0x1738
4136 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4137 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4138 +
4139 +/*
4140 + * TX_AGG_CNT7:
4141 + */
4142 +#define TX_AGG_CNT7 0x173c
4143 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4144 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4145 +
4146 +/*
4147 + * MPDU_DENSITY_CNT:
4148 + * TX_ZERO_DEL: TX zero length delimiter count
4149 + * RX_ZERO_DEL: RX zero length delimiter count
4150 + */
4151 +#define MPDU_DENSITY_CNT 0x1740
4152 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4153 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4154 +
4155 +/*
4156 + * Security key table memory.
4157 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4158 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4159 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4160 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4161 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4162 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4163 + */
4164 +#define MAC_WCID_BASE 0x1800
4165 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4166 +#define MAC_IVEIV_TABLE_BASE 0x6000
4167 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4168 +#define SHARED_KEY_TABLE_BASE 0x6c00
4169 +#define SHARED_KEY_MODE_BASE 0x7000
4170 +
4171 +#define MAC_WCID_ENTRY(__idx) \
4172 + ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4173 +#define PAIRWISE_KEY_ENTRY(__idx) \
4174 + ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4175 +#define MAC_IVEIV_ENTRY(__idx) \
4176 + ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4177 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4178 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4179 +#define SHARED_KEY_ENTRY(__idx) \
4180 + ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4181 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4182 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4183 +
4184 +struct mac_wcid_entry {
4185 + u8 mac[6];
4186 + u8 reserved[2];
4187 +} __attribute__ ((packed));
4188 +
4189 +struct hw_key_entry {
4190 + u8 key[16];
4191 + u8 tx_mic[8];
4192 + u8 rx_mic[8];
4193 +} __attribute__ ((packed));
4194 +
4195 +struct mac_iveiv_entry {
4196 + u8 iv[8];
4197 +} __attribute__ ((packed));
4198 +
4199 +/*
4200 + * MAC_WCID_ATTRIBUTE:
4201 + */
4202 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4203 +#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
4204 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4205 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4206 +
4207 +/*
4208 + * SHARED_KEY_MODE:
4209 + */
4210 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4211 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4212 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4213 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4214 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4215 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4216 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4217 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4218 +
4219 +/*
4220 + * HOST-MCU communication
4221 + */
4222 +
4223 +/*
4224 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4225 + */
4226 +#define H2M_MAILBOX_CSR 0x7010
4227 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4228 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4229 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4230 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4231 +
4232 +/*
4233 + * H2M_MAILBOX_CID:
4234 + */
4235 +#define H2M_MAILBOX_CID 0x7014
4236 +
4237 +/*
4238 + * H2M_MAILBOX_STATUS:
4239 + */
4240 +#define H2M_MAILBOX_STATUS 0x701c
4241 +
4242 +/*
4243 + * H2M_INT_SRC:
4244 + */
4245 +#define H2M_INT_SRC 0x7024
4246 +
4247 +/*
4248 + * H2M_BBP_AGENT:
4249 + */
4250 +#define H2M_BBP_AGENT 0x7028
4251 +
4252 +/*
4253 + * MCU_LEDCS: LED control for MCU Mailbox.
4254 + */
4255 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4256 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4257 +
4258 +/*
4259 + * HW_CS_CTS_BASE:
4260 + * Carrier-sense CTS frame base address.
4261 + * It's where mac stores carrier-sense frame for carrier-sense function.
4262 + */
4263 +#define HW_CS_CTS_BASE 0x7700
4264 +
4265 +/*
4266 + * HW_DFS_CTS_BASE:
4267 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4268 + */
4269 +#define HW_DFS_CTS_BASE 0x7780
4270 +
4271 +/*
4272 + * TXRX control registers - base address 0x3000
4273 + */
4274 +
4275 +/*
4276 + * TXRX_CSR1:
4277 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4278 + */
4279 +#define TXRX_CSR1 0x77d0
4280 +
4281 +/*
4282 + * HW_DEBUG_SETTING_BASE:
4283 + * since NULL frame won't be that long (256 byte)
4284 + * We steal 16 tail bytes to save debugging settings
4285 + */
4286 +#define HW_DEBUG_SETTING_BASE 0x77f0
4287 +#define HW_DEBUG_SETTING_BASE2 0x7770
4288 +
4289 +/*
4290 + * HW_BEACON_BASE
4291 + * In order to support maximum 8 MBSS and its maximum length
4292 + * is 512 bytes for each beacon
4293 + * Three section discontinue memory segments will be used.
4294 + * 1. The original region for BCN 0~3
4295 + * 2. Extract memory from FCE table for BCN 4~5
4296 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4297 + * It occupied those memory of wcid 238~253 for BCN 6
4298 + * and wcid 222~237 for BCN 7
4299 + *
4300 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4301 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4302 + */
4303 +#define HW_BEACON_BASE0 0x7800
4304 +#define HW_BEACON_BASE1 0x7a00
4305 +#define HW_BEACON_BASE2 0x7c00
4306 +#define HW_BEACON_BASE3 0x7e00
4307 +#define HW_BEACON_BASE4 0x7200
4308 +#define HW_BEACON_BASE5 0x7400
4309 +#define HW_BEACON_BASE6 0x5dc0
4310 +#define HW_BEACON_BASE7 0x5bc0
4311 +
4312 +#define HW_BEACON_OFFSET(__index) \
4313 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4314 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4315 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4316 +
4317 +/*
4318 + * 8051 firmware image.
4319 + */
4320 +#define FIRMWARE_RT2860 "rt2860.bin"
4321 +#define FIRMWARE_IMAGE_BASE 0x2000
4322 +
4323 +/*
4324 + * BBP registers.
4325 + * The wordsize of the BBP is 8 bits.
4326 + */
4327 +
4328 +/*
4329 + * BBP 1: TX Antenna
4330 + */
4331 +#define BBP1_TX_POWER FIELD8(0x07)
4332 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4333 +
4334 +/*
4335 + * BBP 3: RX Antenna
4336 + */
4337 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4338 +
4339 +/*
4340 + * RF registers
4341 + */
4342 +
4343 +/*
4344 + * RF 2
4345 + */
4346 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4347 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4348 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4349 +
4350 +/*
4351 + * RF 3
4352 + */
4353 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4354 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4355 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4356 +
4357 +/*
4358 + * RF 4
4359 + */
4360 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4361 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4362 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4363 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4364 +#define RF4_HT40 FIELD32(0x00200000)
4365 +
4366 +/*
4367 + * EEPROM content.
4368 + * The wordsize of the EEPROM is 16 bits.
4369 + */
4370 +
4371 +/*
4372 + * EEPROM Version
4373 + */
4374 +#define EEPROM_VERSION 0x0001
4375 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4376 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4377 +
4378 +/*
4379 + * HW MAC address.
4380 + */
4381 +#define EEPROM_MAC_ADDR_0 0x0002
4382 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4383 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4384 +#define EEPROM_MAC_ADDR_1 0x0003
4385 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4386 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4387 +#define EEPROM_MAC_ADDR_2 0x0004
4388 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4389 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4390 +
4391 +/*
4392 + * EEPROM ANTENNA config
4393 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4394 + * TXPATH: 1: 1T, 2: 2T
4395 + */
4396 +#define EEPROM_ANTENNA 0x001a
4397 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4398 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4399 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4400 +
4401 +/*
4402 + * EEPROM NIC config
4403 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4404 + */
4405 +#define EEPROM_NIC 0x001b
4406 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4407 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4408 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4409 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4410 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4411 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4412 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4413 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4414 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4415 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4416 +
4417 +/*
4418 + * EEPROM frequency
4419 + */
4420 +#define EEPROM_FREQ 0x001d
4421 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4422 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4423 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4424 +
4425 +/*
4426 + * EEPROM LED
4427 + * POLARITY_RDY_G: Polarity RDY_G setting.
4428 + * POLARITY_RDY_A: Polarity RDY_A setting.
4429 + * POLARITY_ACT: Polarity ACT setting.
4430 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4431 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4432 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4433 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4434 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4435 + * LED_MODE: Led mode.
4436 + */
4437 +#define EEPROM_LED1 0x001e
4438 +#define EEPROM_LED2 0x001f
4439 +#define EEPROM_LED3 0x0020
4440 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4441 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4442 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4443 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4444 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4445 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4446 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4447 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4448 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4449 +
4450 +/*
4451 + * EEPROM LNA
4452 + */
4453 +#define EEPROM_LNA 0x0022
4454 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4455 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4456 +
4457 +/*
4458 + * EEPROM RSSI BG offset
4459 + */
4460 +#define EEPROM_RSSI_BG 0x0023
4461 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4462 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4463 +
4464 +/*
4465 + * EEPROM RSSI BG2 offset
4466 + */
4467 +#define EEPROM_RSSI_BG2 0x0024
4468 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4469 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4470 +
4471 +/*
4472 + * EEPROM RSSI A offset
4473 + */
4474 +#define EEPROM_RSSI_A 0x0025
4475 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4476 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4477 +
4478 +/*
4479 + * EEPROM RSSI A2 offset
4480 + */
4481 +#define EEPROM_RSSI_A2 0x0026
4482 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4483 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4484 +
4485 +/*
4486 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4487 + * This is delta in 40MHZ.
4488 + * VALUE: Tx Power dalta value (MAX=4)
4489 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4490 + * TXPOWER: Enable:
4491 + */
4492 +#define EEPROM_TXPOWER_DELTA 0x0028
4493 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4494 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4495 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4496 +
4497 +/*
4498 + * EEPROM TXPOWER 802.11BG
4499 + */
4500 +#define EEPROM_TXPOWER_BG1 0x0029
4501 +#define EEPROM_TXPOWER_BG2 0x0030
4502 +#define EEPROM_TXPOWER_BG_SIZE 7
4503 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4504 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4505 +
4506 +/*
4507 + * EEPROM TXPOWER 802.11A
4508 + */
4509 +#define EEPROM_TXPOWER_A1 0x003c
4510 +#define EEPROM_TXPOWER_A2 0x0053
4511 +#define EEPROM_TXPOWER_A_SIZE 6
4512 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4513 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4514 +
4515 +/*
4516 + * EEPROM TXpower byrate: 20MHZ power
4517 + */
4518 +#define EEPROM_TXPOWER_BYRATE 0x006f
4519 +
4520 +/*
4521 + * EEPROM BBP.
4522 + */
4523 +#define EEPROM_BBP_START 0x0078
4524 +#define EEPROM_BBP_SIZE 16
4525 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4526 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4527 +
4528 +/*
4529 + * MCU mailbox commands.
4530 + */
4531 +#define MCU_SLEEP 0x30
4532 +#define MCU_WAKEUP 0x31
4533 +#define MCU_LED 0x50
4534 +#define MCU_LED_STRENGTH 0x51
4535 +#define MCU_LED_1 0x52
4536 +#define MCU_LED_2 0x53
4537 +#define MCU_LED_3 0x54
4538 +#define MCU_RADAR 0x60
4539 +#define MCU_BOOT_SIGNAL 0x72
4540 +
4541 +/*
4542 + * DMA descriptor defines.
4543 + */
4544 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4545 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4546 +#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
4547 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4548 +
4549 +/*
4550 + * TX descriptor format for TX, PRIO and Beacon Ring.
4551 + */
4552 +
4553 +/*
4554 + * Word0
4555 + */
4556 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4557 +
4558 +/*
4559 + * Word1
4560 + */
4561 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4562 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4563 +#define TXD_W1_BURST FIELD32(0x00008000)
4564 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4565 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4566 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4567 +
4568 +/*
4569 + * Word2
4570 + */
4571 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4572 +
4573 +/*
4574 + * Word3
4575 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4576 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4577 + * 0:MGMT, 1:HCCA 2:EDCA
4578 + */
4579 +#define TXD_W3_WIV FIELD32(0x01000000)
4580 +#define TXD_W3_QSEL FIELD32(0x06000000)
4581 +#define TXD_W3_TCO FIELD32(0x20000000)
4582 +#define TXD_W3_UCO FIELD32(0x40000000)
4583 +#define TXD_W3_ICO FIELD32(0x80000000)
4584 +
4585 +/*
4586 + * TX WI structure
4587 + */
4588 +
4589 +/*
4590 + * Word0
4591 + * FRAG: 1 To inform TKIP engine this is a fragment.
4592 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4593 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4594 + * BW: Channel bandwidth 20MHz or 40 MHz
4595 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4596 + */
4597 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4598 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4599 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4600 +#define TXWI_W0_TS FIELD32(0x00000008)
4601 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4602 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4603 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4604 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4605 +#define TXWI_W0_BW FIELD32(0x00800000)
4606 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4607 +#define TXWI_W0_STBC FIELD32(0x06000000)
4608 +#define TXWI_W0_IFS FIELD32(0x08000000)
4609 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4610 +
4611 +/*
4612 + * Word1
4613 + */
4614 +#define TXWI_W1_ACK FIELD32(0x00000001)
4615 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4616 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4617 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4618 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4619 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4620 +
4621 +/*
4622 + * Word2
4623 + */
4624 +#define TXWI_W2_IV FIELD32(0xffffffff)
4625 +
4626 +/*
4627 + * Word3
4628 + */
4629 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4630 +
4631 +/*
4632 + * RX descriptor format for RX Ring.
4633 + */
4634 +
4635 +/*
4636 + * Word0
4637 + */
4638 +#define RXD_W0_SDP0 FIELD32(0xffffffff)
4639 +
4640 +/*
4641 + * Word1
4642 + */
4643 +#define RXD_W1_SDL1 FIELD32(0x00003fff)
4644 +#define RXD_W1_SDL0 FIELD32(0x3fff0000)
4645 +#define RXD_W1_LS0 FIELD32(0x40000000)
4646 +#define RXD_W1_DMA_DONE FIELD32(0x80000000)
4647 +
4648 +/*
4649 + * Word2
4650 + */
4651 +#define RXD_W2_SDP1 FIELD32(0xffffffff)
4652 +
4653 +/*
4654 + * Word3
4655 + * AMSDU: RX with 802.3 header, not 802.11 header.
4656 + * DECRYPTED: This frame is being decrypted.
4657 + */
4658 +#define RXD_W3_BA FIELD32(0x00000001)
4659 +#define RXD_W3_DATA FIELD32(0x00000002)
4660 +#define RXD_W3_NULLDATA FIELD32(0x00000004)
4661 +#define RXD_W3_FRAG FIELD32(0x00000008)
4662 +#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
4663 +#define RXD_W3_MULTICAST FIELD32(0x00000020)
4664 +#define RXD_W3_BROADCAST FIELD32(0x00000040)
4665 +#define RXD_W3_MY_BSS FIELD32(0x00000080)
4666 +#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
4667 +#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
4668 +#define RXD_W3_AMSDU FIELD32(0x00000800)
4669 +#define RXD_W3_HTC FIELD32(0x00001000)
4670 +#define RXD_W3_RSSI FIELD32(0x00002000)
4671 +#define RXD_W3_L2PAD FIELD32(0x00004000)
4672 +#define RXD_W3_AMPDU FIELD32(0x00008000)
4673 +#define RXD_W3_DECRYPTED FIELD32(0x00010000)
4674 +#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
4675 +#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
4676 +
4677 +/*
4678 + * RX WI structure
4679 + */
4680 +
4681 +/*
4682 + * Word0
4683 + */
4684 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4685 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4686 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4687 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4688 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4689 +#define RXWI_W0_TID FIELD32(0xf0000000)
4690 +
4691 +/*
4692 + * Word1
4693 + */
4694 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4695 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4696 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4697 +#define RXWI_W1_BW FIELD32(0x00800000)
4698 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4699 +#define RXWI_W1_STBC FIELD32(0x06000000)
4700 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4701 +
4702 +/*
4703 + * Word2
4704 + */
4705 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4706 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4707 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4708 +
4709 +/*
4710 + * Word3
4711 + */
4712 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4713 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4714 +
4715 +/*
4716 + * Macro's for converting txpower from EEPROM to mac80211 value
4717 + * and from mac80211 value to register value.
4718 + */
4719 +#define MIN_G_TXPOWER 0
4720 +#define MIN_A_TXPOWER -7
4721 +#define MAX_G_TXPOWER 31
4722 +#define MAX_A_TXPOWER 15
4723 +#define DEFAULT_TXPOWER 5
4724 +
4725 +#define TXPOWER_G_FROM_DEV(__txpower) \
4726 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4727 +
4728 +#define TXPOWER_G_TO_DEV(__txpower) \
4729 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4730 +
4731 +#define TXPOWER_A_FROM_DEV(__txpower) \
4732 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4733 +
4734 +#define TXPOWER_A_TO_DEV(__txpower) \
4735 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4736 +
4737 +#endif /* RT2800PCI_H */
4738 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4739 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4740 @@ -138,6 +138,10 @@ struct rt2x00_chip {
4741 #define RT2561 0x0302
4742 #define RT2661 0x0401
4743 #define RT2571 0x1300
4744 +#define RT2860 0x0601 /* 2.4GHz PCI/CB */
4745 +#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
4746 +#define RT2890 0x0701 /* 2.4GHz PCIe */
4747 +#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
4748
4749 u16 rf;
4750 u32 rev;
Personal OpenWRT clone
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