target/linux/danube/files/include/asm-mips/danube/danube.h

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2005 infineon
  17  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
  18  *
  19  */
  20 #ifndef _DANUBE_H__
  21 #define _DANUBE_H__
  22
  23
  24 /*------------ GENERAL */
  25
  26 #define BOARD_SYSTEM_TYPE               "DANUBE"
  27
  28 #define IOPORT_RESOURCE_START   0x10000000
  29 #define IOPORT_RESOURCE_END             0xffffffff
  30 #define IOMEM_RESOURCE_START    0x10000000
  31 #define IOMEM_RESOURCE_END              0xffffffff
  32
  33
  34 /*------------ ASC1 */
  35
  36 #define DANUBE_ASC1_BASE_ADDR   (KSEG1 + 0x1E100C00)
  37
  38 /* FIFO status register */
  39 #define DANUBE_ASC1_FSTAT               ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048))
  40 #define ASCFSTAT_TXFFLMASK              0x3F00
  41 #define ASCFSTAT_TXFFLOFF               8
  42
  43 /* ASC1 transmit buffer */
  44 #define DANUBE_ASC1_TBUF                ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020))
  45
  46 /* channel operating modes */
  47 #define ASCOPT_CSIZE                    0x3
  48 #define ASCOPT_CS7                              0x1
  49 #define ASCOPT_CS8                              0x2
  50 #define ASCOPT_PARENB                   0x4
  51 #define ASCOPT_STOPB                    0x8
  52 #define ASCOPT_PARODD                   0x0
  53 #define ASCOPT_CREAD                    0x20
  54
  55 /* hardware modified control register */
  56 #define DANUBE_ASC1_WHBSTATE    ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018))
  57
  58 /* receive buffer register */
  59 #define DANUBE_ASC1_RBUF                ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024))
  60
  61 /* status register */
  62 #define DANUBE_ASC1_STATE               ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014))
  63
  64 /* interrupt control */
  65 #define DANUBE_ASC1_IRNCR               ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8))
  66
  67 #define ASC_IRNCR_TIR                   0x4
  68 #define ASC_IRNCR_RIR                   0x2
  69 #define ASC_IRNCR_EIR                   0x4
  70
  71 /* clock control */
  72 #define DANUBE_ASC1_CLC                 ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000))
  73
  74 #define DANUBE_ASC1_CLC_DISS    0x2
  75
  76 /* port input select register */
  77 #define DANUBE_ASC1_PISEL               ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004))
  78
  79 /* tx fifo */
  80 #define DANUBE_ASC1_TXFCON              ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044))
  81
  82 /* rx fifo */
  83 #define DANUBE_ASC1_RXFCON              ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040))
  84
  85 /* control */
  86 #define DANUBE_ASC1_CON                 ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010))
  87
  88 /* timer reload */
  89 #define DANUBE_ASC1_BG                  ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050))
  90
  91 /* int enable */
  92 #define DANUBE_ASC1_IRNREN              ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4))
  93
  94 #define ASC_IRNREN_RX_BUF               0x8
  95 #define ASC_IRNREN_TX_BUF               0x4
  96 #define ASC_IRNREN_ERR                  0x2
  97 #define ASC_IRNREN_TX                   0x1
  98
  99
 100 /*------------ RCU */
 101
 102 #define DANUBE_RCU_BASE_ADDR    0xBF203000
 103
 104 /* reset request */
 105 #define DANUBE_RCU_REQ                  ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
 106 #define DANUBE_RST_ALL                  0x40000000
 107
 108
 109 /*------------ MCD */
 110
 111 #define DANUBE_MCD_BASE_ADDR    (KSEG1 + 0x1F106000)
 112
 113 /* chip id */
 114 #define DANUBE_MCD_CHIPID               ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028))
 115
 116
 117 /*------------ GPTU */
 118
 119 #define DANUBE_GPTU_BASE_ADDR   0xB8000300
 120
 121 /* clock control register */
 122 #define DANUBE_GPTU_GPT_CLC             ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000))
 123
 124 /* captur reload register */
 125 #define DANUBE_GPTU_GPT_CAPREL  ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030))
 126
 127 /* timer 6 control register */
 128 #define DANUBE_GPTU_GPT_T6CON   ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020))
 129
 130
 131 /*------------ EBU */
 132
 133 #define DANUBE_EBU_BASE_ADDR    0xBE105300
 134
 135 /* bus configuration register */
 136 #define DANUBE_EBU_BUSCON0              ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060))
 137 #define DANUBE_EBU_PCC_CON              ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090))
 138 #define DANUBE_EBU_PCC_IEN              ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4))
 139 #define DANUBE_EBU_PCC_ISTAT    ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0))
 140
 141
 142 /*------------ CGU */
 143
 144 #define DANUBE_CGU_BASE_ADDR    0xBF103000
 145
 146 /* clock mux */
 147 #define DANUBE_CGU_SYS                  ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010))
 148 #define DANUBE_CGU_IFCCR                ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018))
 149 #define DANUBE_CGU_PCICR                ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034))
 150
 151 #define CLOCK_60M                               60000000
 152 #define CLOCK_83M                               83333333
 153 #define CLOCK_111M                              111111111
 154 #define CLOCK_133M                              133333333
 155 #define CLOCK_167M                              166666667
 156 #define CLOCK_333M                              333333333
 157
 158
 159 /*------------ CGU */
 160
 161 #define DANUBE_PMU_BASE_ADDR    (KSEG1 + 0x1F102000)
 162
 163 /* power down control */
 164 #define DANUBE_PMU_PWDCR                ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
 165 #define DANUBE_PMU_PWDCR_DMA    0x20
 166 #define DANUBE_PMU_PWDCR_GPT    0x1000
 167 #define DANUBE_PMU_PWDCR_PPE    0x2000
 168 #define DANUBE_PMU_PWDCR_FPI    0x4000
 169
 170
 171 /*------------ ICU */
 172
 173 #define DANUBE_ICU_BASE_ADDR    0xBF880200
 174
 175
 176 #define DANUBE_ICU_IM0_ISR              ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000))
 177 #define DANUBE_ICU_IM0_IER              ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008))
 178 #define DANUBE_ICU_IM0_IOSR             ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010))
 179 #define DANUBE_ICU_IM0_IRSR             ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018))
 180 #define DANUBE_ICU_IM0_IMR              ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020))
 181
 182 #define DANUBE_ICU_IM1_ISR              ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028))
 183
 184 #define DANUBE_ICU_OFFSET               (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR)
 185
 186
 187 /*------------ ETOP */
 188
 189 #define DANUBE_PPE32_BASE_ADDR  0xBE180000
 190
 191 #define ETHERNET_PACKET_DMA_BUFFER_SIZE         0x600
 192
 193 #define DANUBE_PPE32_MEM_MAP    (DANUBE_PPE32_BASE_ADDR + 0x10000 )
 194
 195 #define MII_MODE 1
 196
 197 #define REV_MII_MODE 2
 198
 199 /* mdio access */
 200 #define DANUBE_PPE32_MDIO_ACC   ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804))
 201
 202 #define MDIO_ACC_REQUEST                0x80000000
 203 #define MDIO_ACC_READ                   0x40000000
 204 #define MDIO_ACC_ADDR_MASK              0x1f
 205 #define MDIO_ACC_ADDR_OFFSET    0x15
 206 #define MDIO_ACC_REG_MASK               0xff
 207 #define MDIO_ACC_REG_OFFSET             0x10
 208 #define MDIO_ACC_VAL_MASK               0xffff
 209
 210 /* configuration */
 211 #define DANUBE_PPE32_CFG                ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808))
 212
 213 #define PPE32_MII_MASK                  0xfffffffc
 214 #define PPE32_MII_NORMAL                0x8
 215 #define PPE32_MII_REVERSE               0xe
 216
 217 /* packet length */
 218 #define DANUBE_PPE32_IG_PLEN_CTRL       ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820))
 219
 220 #define PPE32_PLEN_OVER                 0x5ee
 221 #define PPE32_PLEN_UNDER                0x400000
 222
 223 /* enet */
 224 #define DANUBE_PPE32_ENET_MAC_CFG       ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840))
 225
 226 #define PPE32_CGEN                              0x800
 227
 228
 229 /*------------ DMA */
 230 #define DANUBE_DMA_BASE_ADDR    0xBE104100
 231
 232 #define DANUBE_DMA_CS                   ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18))
 233 #define DANUBE_DMA_CIE                  ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C))
 234 #define DANUBE_DMA_IRNEN                ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4))
 235 #define DANUBE_DMA_CCTRL                ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C))
 236 #define DANUBE_DMA_CIS                  ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28))
 237 #define DANUBE_DMA_CDLEN                ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24))
 238 #define DANUBE_DMA_PS                   ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40))
 239 #define DANUBE_DMA_PCTRL                ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44))
 240 #define DANUBE_DMA_CTRL                 ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10))
 241 #define DANUBE_DMA_CPOLL                ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14))
 242 #define DANUBE_DMA_CDBA                 ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20))
 243
 244
 245 /*------------ PCI */
 246 #define PCI_CR_PR_BASE_ADDR             (KSEG1 + 0x1E105400)
 247
 248 #define PCI_CR_FCI_ADDR_MAP0    ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
 249 #define PCI_CR_FCI_ADDR_MAP1    ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
 250 #define PCI_CR_FCI_ADDR_MAP2    ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
 251 #define PCI_CR_FCI_ADDR_MAP3    ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
 252 #define PCI_CR_FCI_ADDR_MAP4    ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
 253 #define PCI_CR_FCI_ADDR_MAP5    ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
 254 #define PCI_CR_FCI_ADDR_MAP6    ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
 255 #define PCI_CR_FCI_ADDR_MAP7    ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
 256 #define PCI_CR_CLK_CTRL                 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000))
 257 #define PCI_CR_PCI_MOD                  ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030))
 258 #define PCI_CR_PC_ARB                   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080))
 259 #define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
 260 #define PCI_CR_BAR11MASK                ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044))
 261 #define PCI_CR_BAR12MASK                ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048))
 262 #define PCI_CR_BAR13MASK                ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C))
 263 #define PCI_CS_BASE_ADDR1               ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010))
 264 #define PCI_CR_PCI_ADDR_MAP11   ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
 265 #define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
 266 #define PCI_CR_PCI_EOI                  ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C))
 267
 268 #define PCI_CS_PR_BASE_ADDR             (KSEG1 + 0x17000000)
 269
 270 #define PCI_CS_STS_CMD                  ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004))
 271
 272 #define PCI_MASTER0_REQ_MASK_2BITS      8
 273 #define PCI_MASTER1_REQ_MASK_2BITS      10
 274 #define PCI_MASTER2_REQ_MASK_2BITS      12
 275 #define INTERNAL_ARB_ENABLE_BIT         0
 276
 277
 278 /*------------ GPIO */
 279 #define DANUBE_GPIO_BASE_ADDR   0xBE100B00
 280
 281 #define DANUBE_GPIO_P1_OUT              ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
 282 #define DANUBE_GPIO_P1_OD               ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
 283 #define DANUBE_GPIO_P1_ALTSEL0  ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
 284 #define DANUBE_GPIO_P0_ALTSEL1  ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
 285 #define DANUBE_GPIO_P1_ALTSEL1  ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
 286 #define DANUBE_GPIO_P1_DIR              ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
 287
 288
 289 /*------------ WDT */
 290
 291 #define DANUBE_WDT_BASE_ADDR    (KSEG1 + 0x1F880000)
 292
 293 #define DANUBE_BIU_WDT_CR               ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F0))
 294 #define DANUBE_BIU_WDT_SR               ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F8))
 295
 296 #define DANUBE_BIU_WDT_CR_GEN                           (1 << 31)
 297 #define DANUBE_BIU_WDT_CR_DSEN                          (1 << 30)
 298 #define DANUBE_BIU_WDT_CR_LPEN                          (1 << 29)
 299
 300 #define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
 301 #define DANUBE_BIU_WDT_CR_PWL_GET(value)        (((value) >> 26) & ((1 << 2) - 1))
 302 #define DANUBE_BIU_WDT_CR_PWL_SET(value)        ((((1 << 2) - 1) & (value)) << 26)
 303 #define DANUBE_BIU_WDT_CR_PW_SET(value)         (((( 1 << 8) - 1) & (value)) << 16)
 304 #define DANUBE_BIU_WDT_CR_CLKDIV_SET(value)     (((( 1 << 2) - 1) & (value)) << 24)
 305 #define DANUBE_BIU_WDT_CR_RELOAD_SET(value)     (((( 1 << 16) - 1) & (value)) << 0)
 306
 307 #endif