target/linux/ifxmips/files/include/asm-mips/danube/ifx_peripheral_definitions.h

   1 //*************************************************************************
   2 //* Summary of definitions which are used in each peripheral              *
   3 //*************************************************************************
   4
   5 #ifndef peripheral_definitions_h
   6 #define peripheral_definitions_h
   7
   8 ////#include "cpu.h"
   9 //
  10 ///* These files have to be included by each peripheral */
  11 //#include <sysdefs.h>
  12 //#include <excep.h>
  13 //#include <cpusubsys.h>
  14 //#include <sys_api.h>
  15 //#include <mips.h>
  16 //#include "SRAM_address_map.h"
  17 //
  18 ///* common header files for all CPU's */
  19 //#include "iiu.h"
  20 //#include "bcu.h"
  21 //#include "FPI_address_map.h"
  22 //#include "direct_interrupts.h"
  23
  24 /////////////////////////////////////////////////////////////////////////
  25
  26 //extern  int _clz();
  27 //extern void _nop();
  28 //extern void _sleep();
  29 //extern void sys_enable_int();
  30
  31 typedef unsigned char UINT8;
  32 typedef signed char INT8;
  33 typedef unsigned short UINT16;
  34 typedef signed short INT16;
  35 typedef unsigned int UINT32;
  36 typedef signed int INT32;
  37 typedef unsigned long long UINT64;
  38 typedef signed long long INT64;
  39
  40 #define REG8( addr )              (*(volatile UINT8 *) (addr))
  41 #define REG16( addr )             (*(volatile UINT16 *)(addr))
  42 #define REG32( addr )             (*(volatile UINT32 *)(addr))
  43 #define REG64( addr )             (*(volatile UINT64 *)(addr))
  44
  45 /* define routine to set FPI access in Supervisor Mode */
  46 #define IFX_SUPERVISOR_ON()                         REG32(FB0_CFG) = 0x01
  47 /* Supervisor mode ends, following functions will be done in User mode */
  48 #define IFX_SUPERVISOR_OFF()                        REG32(FB0_CFG) = 0x00
  49 /* Supervisor mode ends, following functions will be done in User mode */
  50 #define IFX_SUPERVISOR_MODE()                       REG32(FB0_CFG)
  51 /* Supervisor mode ends, following functions will be done in User mode */
  52 #define IFX_SUPERVISOR_SET(svm)                     REG32(FB0_CFG) = svm
  53 /* enable all Interrupts in IIU */
  54 //#define IFX_ENABLE_IRQ(irq_mask, im_base)           REG32(im_base | IIU_MASK) = irq_mask
  55 ///* get all high priority interrupt bits in IIU */
  56 //#define IFX_GET_IRQ_MASKED(im_base)                 REG32(im_base | IIU_IRMASKED)
  57 ///* signal ends of interrupt to IIU */
  58 //#define IFX_CLEAR_DIRECT_IRQ(irq_bit, im_base)      REG32(im_base | IIU_IR) = irq_bit
  59 ///* force IIU interrupt register */
  60 //#define IFX_FORCE_IIU_REGISTER(data, im_base)       REG32(im_base | IIU_IRDEBUG) = data
  61 ///* get all bits of interrupt register */
  62 //#define IFX_GET_IRQ_UNMASKED(im_base)               REG32(im_base | IIU_IR)
  63 /* insert a NOP instruction */
  64 #define NOP                                     _nop()
  65 /* CPU goes to power down mode until interrupt occurs */
  66 #define IFX_CPU_SLEEP                               _sleep()
  67 /* enable all interrupts to CPU */
  68 #define IFX_CPU_ENABLE_ALL_INTERRUPT                sys_enable_int()
  69 /* get all low priority interrupt bits in peripheral */
  70 #define IFX_GET_LOW_PRIO_IRQ(int_reg)               REG32(int_reg)
  71 /* clear low priority interrupt bit in peripheral */
  72 #define IFX_CLEAR_LOW_PRIO_IRQ(irq_bit, int_reg)    REG32(int_reg) = irq_bit
  73 /* write FPI bus */
  74 #define WRITE_FPI_BYTE(data, addr)              REG8(addr) = data
  75 #define WRITE_FPI_16BIT(data, addr)             REG16(addr) = data
  76 #define WRITE_FPI_32BIT(data, addr)             REG32(addr) = data
  77 /* read FPI bus */
  78 #define READ_FPI_BYTE(addr)                     REG8(addr)
  79 #define READ_FPI_16BIT(addr)                    REG16(addr)
  80 #define READ_FPI_32BIT(addr)                    REG32(addr)
  81 /* write peripheral register */
  82 #define WRITE_PERIPHERAL_REGISTER(data, addr)   REG32(addr) = data
  83
  84 #ifdef  CONFIG_CPU_LITTLE_ENDIAN
  85 #define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr) = data
  86 #define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr) = data
  87 #else //not CONFIG_CPU_LITTLE_ENDIAN
  88 #define WRITE_PERIPHERAL_REGISTER_16(data, addr) REG16(addr+2) = data
  89 #define WRITE_PERIPHERAL_REGISTER_8(data, addr) REG8(addr+3) = data
  90 #endif //CONFIG_CPU_LITTLE_ENDIAN
  91
  92 /* read peripheral register */
  93 #define READ_PERIPHERAL_REGISTER(addr)          REG32(addr)
  94
  95 /* read/modify(or)/write peripheral register */
  96 #define RMW_OR_PERIPHERAL_REGISTER(data, addr)  REG32(addr) = REG32(addr) | data
  97 /* read/modify(and)/write peripheral register */
  98 #define RMW_AND_PERIPHERAL_REGISTER(data, addr) REG32(addr) = REG32(addr) & (UINT32)data
  99
 100 /* CPU-independent mnemonic constants */
 101 /* CLC register bits */
 102 #define IFX_CLC_ENABLE                0x00000000
 103 #define IFX_CLC_DISABLE               0x00000001
 104 #define IFX_CLC_DISABLE_STATUS        0x00000002
 105 #define IFX_CLC_SUSPEND_ENABLE        0x00000004
 106 #define IFX_CLC_CLOCK_OFF_DISABLE     0x00000008
 107 #define IFX_CLC_OVERWRITE_SPEN_FSOE   0x00000010
 108 #define IFX_CLC_FAST_CLOCK_SWITCH_OFF 0x00000020
 109 #define IFX_CLC_RUN_DIVIDER_MASK      0x0000FF00
 110 #define IFX_CLC_RUN_DIVIDER_OFFSET    8
 111 #define IFX_CLC_SLEEP_DIVIDER_MASK    0x00FF0000
 112 #define IFX_CLC_SLEEP_DIVIDER_OFFSET  16
 113 #define IFX_CLC_SPECIFIC_DIVIDER_MASK 0x00FF0000
 114 #define IFX_CLC_SPECIFIC_DIVIDER_OFFSET 24
 115
 116 /* number of cycles to wait for interrupt service routine to be called */
 117 #define WAIT_CYCLES   50
 118
 119 #endif /* PERIPHERAL_DEFINITIONS_H not yet defined */