target/linux/ar7/files/include/asm-mips/ar7/ar7.h

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2006, 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #ifndef __AR7_H__
  22 #define __AR7_H__
  23
  24 #include <linux/delay.h>
  25 #include <asm/addrspace.h>
  26 #include <asm/io.h>
  27
  28 #define AR7_REGS_BASE 0x08610000
  29
  30 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
  31 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
  32 #define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00) // 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock)
  33 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
  34 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
  35 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
  36 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1a00)
  37 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
  38 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1e00)
  39 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
  40 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
  41
  42 #define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
  43 #define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
  44 #define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
  45
  46 #define AR7_RESET_PEREPHERIAL 0x0
  47 #define AR7_RESET_SOFTWARE    0x4
  48 #define AR7_RESET_STATUS      0x8
  49
  50 #define AR7_RESET_BIT_CPMAC_LO 17
  51 #define AR7_RESET_BIT_CPMAC_HI 21
  52 #define AR7_RESET_BIT_MDIO     22
  53 #define AR7_RESET_BIT_EPHY     26
  54
  55 /* GPIO control registers */
  56 #define AR7_GPIO_INPUT  0x0
  57 #define AR7_GPIO_OUTPUT 0x4
  58 #define AR7_GPIO_DIR    0x8
  59 #define AR7_GPIO_ENABLE 0xc
  60
  61 #define AR7_CHIP_7100 0x18
  62 #define AR7_CHIP_7200 0x2b
  63 #define AR7_CHIP_7300 0x05
  64
  65 /* Interrupts */
  66 #define AR7_IRQ_UART0  15
  67 #define AR7_IRQ_UART1  16
  68
  69 /* Clocks */
  70 #define AR7_AFE_CLOCK  35328000
  71 #define AR7_REF_CLOCK  25000000
  72 #define AR7_XTAL_CLOCK 24000000
  73
  74 struct plat_cpmac_data {
  75         int reset_bit;
  76         int power_bit;
  77         u32 phy_mask;
  78         char dev_addr[6];
  79 };
  80
  81 struct plat_dsl_data {
  82         int reset_bit_dsl;
  83         int reset_bit_sar;
  84 };
  85
  86 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
  87
  88 static inline u16 ar7_chip_id(void)
  89 {
  90         return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
  91 }
  92
  93 static inline u8 ar7_chip_rev(void)
  94 {
  95         return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
  96 }
  97
  98 static inline int ar7_cpu_freq(void)
  99 {
 100         return ar7_cpu_clock;
 101 }
 102
 103 static inline int ar7_bus_freq(void)
 104 {
 105         return ar7_bus_clock;
 106 }
 107
 108 static inline int ar7_vbus_freq(void)
 109 {
 110         return ar7_bus_clock / 2;
 111 }
 112 #define ar7_cpmac_freq ar7_vbus_freq
 113
 114 static inline int ar7_dsp_freq(void)
 115 {
 116         return ar7_dsp_clock;
 117 }
 118
 119 static inline int ar7_has_high_cpmac(void)
 120 {
 121         u16 chip_id = ar7_chip_id();
 122         switch (chip_id) {
 123         case AR7_CHIP_7100:
 124         case AR7_CHIP_7200:
 125                 return 0;
 126         default:
 127                 return 1;
 128         }
 129 }
 130 #define ar7_has_high_vlynq ar7_has_high_cpmac
 131 #define ar7_has_second_uart ar7_has_high_cpmac
 132
 133 static inline void ar7_device_enable(u32 bit)
 134 {
 135         void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 136         writel(readl(reset_reg) | (1 << bit), reset_reg);
 137         mdelay(20);
 138 }
 139
 140 static inline void ar7_device_disable(u32 bit)
 141 {
 142         void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 143         writel(readl(reset_reg) & ~(1 << bit), reset_reg);
 144         mdelay(20);
 145 }
 146
 147 static inline void ar7_device_reset(u32 bit)
 148 {
 149         ar7_device_disable(bit);
 150         ar7_device_enable(bit);
 151 }
 152
 153 static inline void ar7_device_on(u32 bit)
 154 {
 155         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 156         writel(readl(power_reg) | (1 << bit), power_reg);
 157         mdelay(20);
 158 }
 159
 160 static inline void ar7_device_off(u32 bit)
 161 {
 162         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 163         writel(readl(power_reg) & ~(1 << bit), power_reg);
 164         mdelay(20);
 165 }
 166
 167 #endif /* __AR7_H__ */