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[openwrt.git] / target / linux / xburst / files-2.6.32 / arch / mips / jz4740 / gpio.c
1 /*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19
20 #include <linux/spinlock.h>
21 #include <linux/sysdev.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27
28 #define JZ_GPIO_BASE_A (32*0)
29 #define JZ_GPIO_BASE_B (32*1)
30 #define JZ_GPIO_BASE_C (32*2)
31 #define JZ_GPIO_BASE_D (32*3)
32
33 #define JZ_GPIO_NUM_A 32
34 #define JZ_GPIO_NUM_B 32
35 #define JZ_GPIO_NUM_C 31
36 #define JZ_GPIO_NUM_D 32
37
38 #define JZ_IRQ_GPIO_BASE_A (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_A)
39 #define JZ_IRQ_GPIO_BASE_B (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_B)
40 #define JZ_IRQ_GPIO_BASE_C (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_C)
41 #define JZ_IRQ_GPIO_BASE_D (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_D)
42
43 #define JZ_IRQ_GPIO_A(num) (JZ_IRQ_GPIO_BASE_A + num)
44 #define JZ_IRQ_GPIO_B(num) (JZ_IRQ_GPIO_BASE_B + num)
45 #define JZ_IRQ_GPIO_C(num) (JZ_IRQ_GPIO_BASE_C + num)
46 #define JZ_IRQ_GPIO_D(num) (JZ_IRQ_GPIO_BASE_D + num)
47
48 #define JZ_REG_GPIO_PIN 0x00
49 #define JZ_REG_GPIO_DATA 0x10
50 #define JZ_REG_GPIO_DATA_SET 0x14
51 #define JZ_REG_GPIO_DATA_CLEAR 0x18
52 #define JZ_REG_GPIO_MASK 0x20
53 #define JZ_REG_GPIO_MASK_SET 0x24
54 #define JZ_REG_GPIO_MASK_CLEAR 0x28
55 #define JZ_REG_GPIO_PULL 0x30
56 #define JZ_REG_GPIO_PULL_SET 0x34
57 #define JZ_REG_GPIO_PULL_CLEAR 0x38
58 #define JZ_REG_GPIO_FUNC 0x40
59 #define JZ_REG_GPIO_FUNC_SET 0x44
60 #define JZ_REG_GPIO_FUNC_CLEAR 0x48
61 #define JZ_REG_GPIO_SELECT 0x50
62 #define JZ_REG_GPIO_SELECT_SET 0x54
63 #define JZ_REG_GPIO_SELECT_CLEAR 0x58
64 #define JZ_REG_GPIO_DIRECTION 0x60
65 #define JZ_REG_GPIO_DIRECTION_SET 0x64
66 #define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
67 #define JZ_REG_GPIO_TRIGGER 0x70
68 #define JZ_REG_GPIO_TRIGGER_SET 0x74
69 #define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
70 #define JZ_REG_GPIO_FLAG 0x80
71 #define JZ_REG_GPIO_FLAG_CLEAR 0x14
72
73 #define CHIP_TO_REG(chip, reg) (jz_gpio_base + (((chip)->base) << 3) + reg)
74
75 #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
76 #define GPIO_TO_REG(gpio, reg) (jz_gpio_base + ((gpio >> 5) << 8) + reg)
77
78 static void __iomem *jz_gpio_base;
79
80 struct jz_gpio_chip {
81 unsigned int irq;
82 unsigned int irq_base;
83 uint32_t wakeup;
84 uint32_t suspend_mask;
85 uint32_t edge_trigger_both;
86 spinlock_t lock;
87 struct gpio_chip gpio_chip;
88 struct irq_chip irq_chip;
89 };
90
91 static struct jz_gpio_chip *jz_irq_to_chip(unsigned int irq)
92 {
93 return get_irq_chip_data(irq);
94 }
95
96 static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
97 {
98 writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
99 }
100
101 int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
102 {
103 if (function == JZ_GPIO_FUNC_NONE) {
104 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
105 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
106 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
107 } else {
108 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
109 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
110 switch (function) {
111 case JZ_GPIO_FUNC1:
112 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
113 break;
114 case JZ_GPIO_FUNC3:
115 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
116 case JZ_GPIO_FUNC2: /* Falltrough */
117 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
118 break;
119 default:
120 BUG();
121 break;
122 }
123 }
124
125 return 0;
126 }
127 EXPORT_SYMBOL_GPL(jz_gpio_set_function);
128
129 int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
130 {
131 size_t i;
132 int ret;
133
134 for (i = 0; i < num; ++i, ++request) {
135 ret = gpio_request(request->gpio, request->name);
136 if (ret)
137 goto err;
138 jz_gpio_set_function(request->gpio, request->function);
139 }
140
141 return 0;
142 err:
143 for (--request; i > 0; --i, --request)
144 gpio_free(request->gpio);
145
146 return ret;
147 }
148 EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
149
150 void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
151 {
152 size_t i;
153
154 for (i = 0; i < num; ++i, ++request) {
155 gpio_free(request->gpio);
156 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
157 }
158
159 }
160 EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
161
162 void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
163 {
164 size_t i;
165
166 for (i = 0; i < num; ++i, ++request) {
167 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
168 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
169 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
170 }
171 }
172 EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
173
174 void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
175 {
176 size_t i;
177
178 for (i = 0; i < num; ++i, ++request) {
179 jz_gpio_set_function(request->gpio, request->function);
180 }
181 }
182 EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
183
184 void jz_gpio_enable_pullup(unsigned gpio)
185 {
186 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
187 }
188 EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
189
190 void jz_gpio_disable_pullup(unsigned gpio)
191 {
192 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
193 }
194 EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
195
196 static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
197 {
198 return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
199 }
200
201 static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
202 {
203 uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
204 reg += !value;
205 writel(BIT(gpio), reg);
206 }
207
208 static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
209 {
210 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
211 jz_gpio_set_value(chip, gpio, value);
212
213 return 0;
214 }
215
216 static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
217 {
218 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
219
220 return 0;
221 }
222
223 int jz_gpio_port_direction_input(int port, uint32_t mask)
224 {
225 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
226
227 return 0;
228 }
229 EXPORT_SYMBOL(jz_gpio_port_direction_input);
230
231 int jz_gpio_port_direction_output(int port, uint32_t mask)
232 {
233 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
234
235 return 0;
236 }
237 EXPORT_SYMBOL(jz_gpio_port_direction_output);
238
239 void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
240 {
241 writel((~value) & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
242 writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
243 }
244 EXPORT_SYMBOL(jz_gpio_port_set_value);
245
246 uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
247 {
248 uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
249
250 return value & mask;
251 }
252 EXPORT_SYMBOL(jz_gpio_port_get_value);
253
254
255 #define IRQ_TO_GPIO(irq) (irq - JZ_IRQ_GPIO(0))
256 #define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
257
258 #define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
259
260 static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
261 {
262 uint32_t flag;
263 unsigned int gpio_irq;
264 unsigned int gpio_bank;
265 struct jz_gpio_chip *chip = get_irq_desc_data(desc);
266
267 gpio_bank = JZ_IRQ_GPIO0 - irq;
268
269 flag = readl(jz_gpio_base + (gpio_bank << 8) + JZ_REG_GPIO_FLAG);
270
271 gpio_irq = ffs(flag) - 1;
272
273 if (chip->edge_trigger_both & BIT(gpio_irq)) {
274 uint32_t value = readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN));
275 if (value & BIT(gpio_irq)) {
276 writel(BIT(gpio_irq),
277 CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_CLEAR));
278 } else {
279 writel(BIT(gpio_irq),
280 CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_SET));
281 }
282 }
283
284 gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0);
285
286 generic_handle_irq(gpio_irq);
287 };
288
289 static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
290 {
291 writel(IRQ_TO_BIT(irq), IRQ_TO_REG(irq, reg));
292 }
293
294 static void jz_gpio_irq_mask(unsigned int irq)
295 {
296 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
297 };
298
299 static void jz_gpio_irq_unmask(unsigned int irq)
300 {
301 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
302 };
303
304 /* TODO: Check if function is gpio */
305 static unsigned int jz_gpio_irq_startup(unsigned int irq)
306 {
307 struct irq_desc *desc = irq_to_desc(irq);
308
309 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
310
311 jz_gpio_irq_unmask(irq);
312 desc->status &= ~IRQ_MASKED;
313
314 return 0;
315 }
316
317 static void jz_gpio_irq_shutdown(unsigned int irq)
318 {
319 struct irq_desc *desc = irq_to_desc(irq);
320
321 jz_gpio_irq_mask(irq);
322 desc->status |= IRQ_MASKED;
323
324 /* Set direction to input */
325 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
326 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
327 }
328
329 static void jz_gpio_irq_ack(unsigned int irq)
330 {
331 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
332 };
333
334 static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
335 {
336 struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
337 struct irq_desc *desc = irq_to_desc(irq);
338
339 jz_gpio_irq_mask(irq);
340
341 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
342 uint32_t value = readl(IRQ_TO_REG(irq, JZ_REG_GPIO_PIN));
343 if (value & IRQ_TO_BIT(irq))
344 flow_type = IRQ_TYPE_EDGE_FALLING;
345 else
346 flow_type = IRQ_TYPE_EDGE_RISING;
347 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
348 } else {
349 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
350 }
351
352 switch(flow_type) {
353 case IRQ_TYPE_EDGE_RISING:
354 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
355 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
356 break;
357 case IRQ_TYPE_EDGE_FALLING:
358 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
359 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
360 break;
361 case IRQ_TYPE_LEVEL_HIGH:
362 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
363 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
364 break;
365 case IRQ_TYPE_LEVEL_LOW:
366 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
367 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
368 break;
369 default:
370 return -EINVAL;
371 }
372
373 if (!(desc->status & IRQ_MASKED))
374 jz_gpio_irq_unmask(irq);
375
376 return 0;
377 }
378
379 static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
380 {
381 struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
382 spin_lock(&chip->lock);
383 if (on)
384 chip->wakeup |= IRQ_TO_BIT(irq);
385 else
386 chip->wakeup &= ~IRQ_TO_BIT(irq);
387 spin_unlock(&chip->lock);
388
389 set_irq_wake(chip->irq, !!(chip->wakeup));
390 return 0;
391 }
392
393 int gpio_to_irq(unsigned gpio)
394 {
395 return JZ_IRQ_GPIO(0) + gpio;
396 }
397 EXPORT_SYMBOL_GPL(gpio_to_irq);
398
399 int irq_to_gpio(unsigned gpio)
400 {
401 return IRQ_TO_GPIO(gpio);
402 }
403 EXPORT_SYMBOL_GPL(irq_to_gpio);
404
405 #define JZ_GPIO_CHIP(_bank) { \
406 .irq_base = JZ_IRQ_GPIO_BASE_ ## _bank, \
407 .gpio_chip = { \
408 .label = "Bank " # _bank, \
409 .owner = THIS_MODULE, \
410 .set = jz_gpio_set_value, \
411 .get = jz_gpio_get_value, \
412 .direction_output = jz_gpio_direction_output, \
413 .direction_input = jz_gpio_direction_input, \
414 .base = JZ_GPIO_BASE_ ## _bank, \
415 .ngpio = JZ_GPIO_NUM_ ## _bank, \
416 }, \
417 .irq_chip = { \
418 .name = "GPIO Bank " # _bank, \
419 .mask = jz_gpio_irq_mask, \
420 .unmask = jz_gpio_irq_unmask, \
421 .ack = jz_gpio_irq_ack, \
422 .startup = jz_gpio_irq_startup, \
423 .shutdown = jz_gpio_irq_shutdown, \
424 .set_type = jz_gpio_irq_set_type, \
425 .set_wake = jz_gpio_irq_set_wake, \
426 }, \
427 }
428
429 static struct jz_gpio_chip jz_gpio_chips[] = {
430 JZ_GPIO_CHIP(A),
431 JZ_GPIO_CHIP(B),
432 JZ_GPIO_CHIP(C),
433 JZ_GPIO_CHIP(D),
434 };
435
436 int jz_gpio_suspend(void)
437 {
438 struct jz_gpio_chip *chip = jz_gpio_chips;
439 int i, gpio;
440
441 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
442 gpio = chip->gpio_chip.base;
443 chip->suspend_mask = readl(GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK));
444 writel(~(chip->wakeup), GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_SET));
445 }
446
447 chip = jz_gpio_chips;
448 #if 0
449 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
450 printk("GPIO %d: \n", i);
451 printk("\tPin: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN)));
452 printk("\tData: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DATA)));
453 printk("\tPull: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PULL)));
454 printk("\tFunc: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_FUNC)));
455 printk("\tSelect: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_SELECT)));
456 printk("\tDirection: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION)));
457 printk("\tTrigger: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_TRIGGER)));
458 }
459 #endif
460
461 return 0;
462 }
463
464 int jz_gpio_resume(void)
465 {
466 struct jz_gpio_chip *chip = jz_gpio_chips;
467 int i;
468 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
469 writel(~(chip->suspend_mask), GPIO_TO_REG(chip->gpio_chip.base, JZ_REG_GPIO_MASK_CLEAR));
470 }
471
472 return 0;
473 }
474
475 int __init jz_gpiolib_init(void)
476 {
477 struct jz_gpio_chip *chip = jz_gpio_chips;
478 int i, irq;
479
480 jz_gpio_base = ioremap(0x10010000, 0x400);
481
482 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
483 gpiochip_add(&chip->gpio_chip);
484 spin_lock_init(&chip->lock);
485 chip->irq = JZ_IRQ_INTC_GPIO(i);
486 set_irq_data(chip->irq, chip);
487 set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
488 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
489 set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
490 set_irq_chip_data(irq, chip);
491 }
492 }
493
494 printk("JZ GPIO initalized\n");
495
496 return 0;
497 }
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