target/linux/storm/patches/1004-gmac-enable-napi.patch

   1 Index: linux-2.6.23.16/drivers/net/sl351x_gmac.c
   2 ===================================================================
   3 --- linux-2.6.23.16.orig/drivers/net/sl351x_gmac.c      2008-03-15 16:59:23.361457295 +0200
   4 +++ linux-2.6.23.16/drivers/net/sl351x_gmac.c   2008-03-15 17:00:32.365389612 +0200
   5 @@ -68,9 +68,11 @@
   6  #include <linux/ip.h>
   7  #endif
   8
   9 +/* Enables NAPI unconditionally */
  10 +#define CONFIG_SL_NAPI                                 1
  11 +
  12  // #define SL351x_TEST_WORKAROUND
  13  #ifdef CONFIG_SL351x_NAT
  14 -#define CONFIG_SL_NAPI                                 1
  15  #endif
  16  #define GMAX_TX_INTR_DISABLED                  1
  17  #define DO_HW_CHKSUM                                   1
  18 @@ -124,12 +126,17 @@
  19   *************************************************************/
  20  static int     gmac_initialized = 0;
  21  TOE_INFO_T toe_private_data;
  22 -//static int           do_again = 0;
  23 +static int             do_again = 0;
  24  spinlock_t gmac_fq_lock;
  25  unsigned int FLAG_SWITCH;
  26
  27  static unsigned int            next_tick = 3 * HZ;
  28 -static unsigned char           eth_mac[CONFIG_MAC_NUM][6]= {{0x00,0x11,0x11,0x87,0x87,0x87}, {0x00,0x22,0x22,0xab,0xab,0xab}};
  29 +static unsigned char           eth_mac[CONFIG_MAC_NUM][6]= {
  30 +               {0x00,0x11,0x11,0x87,0x87,0x87},
  31 +#if GMAC_NUM != 1
  32 +               {0x00,0x22,0x22,0xab,0xab,0xab}
  33 +#endif
  34 +};
  35
  36  #undef CONFIG_SL351x_RXTOE
  37  extern NAT_CFG_T nat_cfg;
  38 @@ -2443,7 +2450,8 @@
  39         toe = (TOE_INFO_T *)&toe_private_data;
  40  //     handle NAPI
  41  #ifdef CONFIG_SL_NAPI
  42 -if (storlink_ctl.pauseoff == 1)
  43 +       /* XXX: check this, changed from 'storlink_ctl.pauseoff == 1' to if (1) */
  44 +if (1)
  45  {
  46  /* disable GMAC interrupt */
  47      //toe_gmac_disable_interrupt(tp->irq);
  48 @@ -2530,7 +2538,7 @@
  49                                 {
  50                                         if (likely(netif_rx_schedule_prep(dev)))
  51                                 {
  52 -                                       unsigned int data32;
  53 +                                       // unsigned int data32;
  54                                         // disable GMAC-0 rx interrupt
  55                                         // class-Q & TOE-Q are implemented in future
  56                                         //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
  57 @@ -2563,7 +2571,7 @@
  58                         {
  59                                 if (likely(netif_rx_schedule_prep(dev)))
  60                         {
  61 -                               unsigned int data32;
  62 +                               // unsigned int data32;
  63                                 // disable GMAC-0 rx interrupt
  64                                 // class-Q & TOE-Q are implemented in future
  65                                 //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
  66 @@ -4217,7 +4225,7 @@
  67         GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
  68         unsigned int            status4;
  69         volatile DMA_RWPTR_T    fq_rwptr;
  70 -       int                                     max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
  71 +       // int                                  max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
  72         //unsigned long         rx_old_bytes;
  73         struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
  74         //unsigned long long    rx_time;
  75 @@ -4479,7 +4487,7 @@
  76
  77         if (rwptr.bits.rptr == rwptr.bits.wptr)
  78         {
  79 -               unsigned int data32;
  80 +               // unsigned int data32;
  81                         //printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr]   rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
  82
  83             /* Receive descriptor is empty now */