target/linux/brcm47xx-2.6/files/include/linux/ssb/ssb_driver_extif.h

   1 /*
   2  * Hardware-specific External Interface I/O core definitions
   3  * for the BCM47xx family of SiliconBackplane-based chips.
   4  *
   5  * The External Interface core supports a total of three external chip selects
   6  * supporting external interfaces. One of the external chip selects is
   7  * used for Flash, one is used for PCMCIA, and the other may be
   8  * programmed to support either a synchronous interface or an
   9  * asynchronous interface. The asynchronous interface can be used to
  10  * support external devices such as UARTs and the BCM2019 Bluetooth
  11  * baseband processor.
  12  * The external interface core also contains 2 on-chip 16550 UARTs, clock
  13  * frequency control, a watchdog interrupt timer, and a GPIO interface.
  14  *
  15  * Copyright 2005, Broadcom Corporation
  16  * Copyright 2006, Michael Buesch
  17  *
  18  * Licensed under the GPL version 2. See COPYING for details.
  19  */
  20 #ifndef LINUX_SSB_EXTIFCORE_H_
  21 #define LINUX_SSB_EXTIFCORE_H_
  22
  23 #ifdef __KERNEL__
  24
  25 struct ssb_extif {
  26         struct ssb_device *dev;
  27 };
  28
  29 /* external interface address space */
  30 #define SSB_EXTIF_PCMCIA_MEMBASE(x)     (x)
  31 #define SSB_EXTIF_PCMCIA_IOBASE(x)      ((x) + 0x100000)
  32 #define SSB_EXTIF_PCMCIA_CFGBASE(x)     ((x) + 0x200000)
  33 #define SSB_EXTIF_CFGIF_BASE(x)         ((x) + 0x800000)
  34 #define SSB_EXTIF_FLASH_BASE(x)         ((x) + 0xc00000)
  35
  36 #define SSB_EXTIF_NR_GPIOOUT            5
  37 /* GPIO NOTE:
  38  * The multiple instances of output and output enable registers
  39  * are present to allow driver software for multiple cores to control
  40  * gpio outputs without needing to share a single register pair.
  41  * Use the following helper macro to get a register offset value.
  42  */
  43 #define SSB_EXTIF_GPIO_OUT(index)       ({              \
  44         BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);    \
  45         SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8);        \
  46                                         })
  47 #define SSB_EXTIF_GPIO_OUTEN(index)     ({              \
  48         BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);    \
  49         SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8);      \
  50                                         })
  51
  52 /** EXTIF core registers **/
  53
  54 #define SSB_EXTIF_CTL                   0x0000
  55 #define  SSB_EXTIF_CTL_UARTEN           (1 << 0) /* UART enable */
  56 #define SSB_EXTIF_EXTSTAT               0x0004
  57 #define  SSB_EXTIF_EXTSTAT_EMODE        (1 << 0) /* Endian mode (ro) */
  58 #define  SSB_EXTIF_EXTSTAT_EIRQPIN      (1 << 1) /* External interrupt pin (ro) */
  59 #define  SSB_EXTIF_EXTSTAT_GPIOIRQPIN   (1 << 2) /* GPIO interrupt pin (ro) */
  60 #define SSB_EXTIF_PCMCIA_CFG            0x0010
  61 #define SSB_EXTIF_PCMCIA_MEMWAIT        0x0014
  62 #define SSB_EXTIF_PCMCIA_ATTRWAIT       0x0018
  63 #define SSB_EXTIF_PCMCIA_IOWAIT         0x001C
  64 #define SSB_EXTIF_PROG_CFG              0x0020
  65 #define SSB_EXTIF_PROG_WAITCNT          0x0024
  66 #define SSB_EXTIF_FLASH_CFG             0x0028
  67 #define SSB_EXTIF_FLASH_WAITCNT         0x002C
  68 #define SSB_EXTIF_WATCHDOG              0x0040
  69 #define SSB_EXTIF_CLOCK_N               0x0044
  70 #define SSB_EXTIF_CLOCK_SB              0x0048
  71 #define SSB_EXTIF_CLOCK_PCI             0x004C
  72 #define SSB_EXTIF_CLOCK_MII             0x0050
  73 #define SSB_EXTIF_GPIO_IN               0x0060
  74 #define SSB_EXTIF_GPIO_OUT_BASE         0x0064
  75 #define SSB_EXTIF_GPIO_OUTEN_BASE       0x0068
  76 #define SSB_EXTIF_EJTAG_OUTEN           0x0090
  77 #define SSB_EXTIF_GPIO_INTPOL           0x0094
  78 #define SSB_EXTIF_GPIO_INTMASK          0x0098
  79 #define SSB_EXTIF_UART_DATA             0x0300
  80 #define SSB_EXTIF_UART_TIMER            0x0310
  81 #define SSB_EXTIF_UART_FCR              0x0320
  82 #define SSB_EXTIF_UART_LCR              0x0330
  83 #define SSB_EXTIF_UART_MCR              0x0340
  84 #define SSB_EXTIF_UART_LSR              0x0350
  85 #define SSB_EXTIF_UART_MSR              0x0360
  86 #define SSB_EXTIF_UART_SCRATCH          0x0370
  87
  88
  89
  90
  91 /* pcmcia/prog/flash_config */
  92 #define SSB_EXTCFG_EN                   (1 << 0)        /* enable */
  93 #define SSB_EXTCFG_MODE                 0xE             /* mode */
  94 #define SSB_EXTCFG_MODE_SHIFT           1
  95 #define  SSB_EXTCFG_MODE_FLASH          0x0             /* flash/asynchronous mode */
  96 #define  SSB_EXTCFG_MODE_SYNC           0x2             /* synchronous mode */
  97 #define  SSB_EXTCFG_MODE_PCMCIA         0x4             /* pcmcia mode */
  98 #define SSB_EXTCFG_DS16                 (1 << 4)        /* destsize:  0=8bit, 1=16bit */
  99 #define SSB_EXTCFG_BSWAP                (1 << 5)        /* byteswap */
 100 #define SSB_EXTCFG_CLKDIV               0xC0            /* clock divider */
 101 #define SSB_EXTCFG_CLKDIV_SHIFT         6
 102 #define  SSB_EXTCFG_CLKDIV_2            0x0             /* backplane/2 */
 103 #define  SSB_EXTCFG_CLKDIV_3            0x40            /* backplane/3 */
 104 #define  SSB_EXTCFG_CLKDIV_4            0x80            /* backplane/4 */
 105 #define SSB_EXTCFG_CLKEN                (1 << 8)        /* clock enable */
 106 #define SSB_EXTCFG_STROBE               (1 << 9)        /* size/bytestrobe (synch only) */
 107
 108 /* pcmcia_memwait */
 109 #define SSB_PCMCIA_MEMW_0               0x0000003F      /* waitcount0 */
 110 #define SSB_PCMCIA_MEMW_1               0x00001F00      /* waitcount1 */
 111 #define SSB_PCMCIA_MEMW_1_SHIFT         8
 112 #define SSB_PCMCIA_MEMW_2               0x001F0000      /* waitcount2 */
 113 #define SSB_PCMCIA_MEMW_2_SHIFT         16
 114 #define SSB_PCMCIA_MEMW_3               0x1F000000      /* waitcount3 */
 115 #define SSB_PCMCIA_MEMW_3_SHIFT         24
 116
 117 /* pcmcia_attrwait */
 118 #define SSB_PCMCIA_ATTW_0               0x0000003F      /* waitcount0 */
 119 #define SSB_PCMCIA_ATTW_1               0x00001F00      /* waitcount1 */
 120 #define SSB_PCMCIA_ATTW_1_SHIFT         8
 121 #define SSB_PCMCIA_ATTW_2               0x001F0000      /* waitcount2 */
 122 #define SSB_PCMCIA_ATTW_2_SHIFT         16
 123 #define SSB_PCMCIA_ATTW_3               0x1F000000      /* waitcount3 */
 124 #define SSB_PCMCIA_ATTW_3_SHIFT         24
 125
 126 /* pcmcia_iowait */
 127 #define SSB_PCMCIA_IOW_0                0x0000003F      /* waitcount0 */
 128 #define SSB_PCMCIA_IOW_1                0x00001F00      /* waitcount1 */
 129 #define SSB_PCMCIA_IOW_1_SHIFT          8
 130 #define SSB_PCMCIA_IOW_2                0x001F0000      /* waitcount2 */
 131 #define SSB_PCMCIA_IOW_2_SHIFT          16
 132 #define SSB_PCMCIA_IOW_3                0x1F000000      /* waitcount3 */
 133 #define SSB_PCMCIA_IOW_3_SHIFT          24
 134
 135 /* prog_waitcount */
 136 #define SSB_PROG_WCNT_0                 0x0000001F      /* waitcount0 */
 137 #define SSB_PROG_WCNT_1                 0x00001F00      /* waitcount1 */
 138 #define SSB_PROG_WCNT_1_SHIFT           8
 139 #define SSB_PROG_WCNT_2                 0x001F0000      /* waitcount2 */
 140 #define SSB_PROG_WCNT_2_SHIFT           16
 141 #define SSB_PROG_WCNT_3                 0x1F000000      /* waitcount3 */
 142 #define SSB_PROG_WCNT_3_SHIFT           24
 143
 144 #define SSB_PROG_W0                     0x0000000C
 145 #define SSB_PROG_W1                     0x00000A00
 146 #define SSB_PROG_W2                     0x00020000
 147 #define SSB_PROG_W3                     0x01000000
 148
 149 /* flash_waitcount */
 150 #define SSB_FLASH_WCNT_0                0x0000001F      /* waitcount0 */
 151 #define SSB_FLASH_WCNT_1                0x00001F00      /* waitcount1 */
 152 #define SSB_FLASH_WCNT_1_SHIFT          8
 153 #define SSB_FLASH_WCNT_2                0x001F0000      /* waitcount2 */
 154 #define SSB_FLASH_WCNT_2_SHIFT          16
 155 #define SSB_FLASH_WCNT_3                0x1F000000      /* waitcount3 */
 156 #define SSB_FLASH_WCNT_3_SHIFT          24
 157
 158 /* watchdog */
 159 #define SSB_EXTIF_WATCHDOG_CLK          48000000        /* Hz */
 160
 161
 162 /* GPIO functions */
 163 static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif,
 164                                      u32 mask)
 165 {
 166         return ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN) & mask;
 167 }
 168
 169 static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif,
 170                                      u32 mask, u32 value)
 171 {
 172         return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_OUT(0), mask, value);
 173 }
 174
 175 static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif,
 176                                      u32 mask, u32 value)
 177 {
 178         return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_OUTEN(0), mask, value);
 179 }
 180
 181 static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif,
 182                                      u32 mask, u32 value)
 183 {
 184         return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_INTPOL, mask, value);
 185 }
 186
 187 static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif,
 188                                      u32 mask, u32 value)
 189 {
 190         return ssb_write32_masked(extif->dev, SSB_EXTIF_GPIO_INTMASK, mask, value);
 191 }
 192
 193
 194 #endif /* __KERNEL__ */
 195 #endif /* LINUX_SSB_EXTIFCORE_H_ */