package/broadcom-diag/src/gpio.h

   1 #ifndef __DIAG_GPIO_H
   2 #define __DIAG_GPIO_H
   3 #include <linux/interrupt.h>
   4
   5 #ifndef BCMDRIVER
   6 #include <linux/ssb/ssb_embedded.h>
   7
   8 extern struct ssb_bus ssb;
   9
  10
  11 static inline u32 gpio_in(void)
  12 {
  13         return ssb_gpio_in(&ssb, ~0);
  14 }
  15
  16 static inline u32 gpio_out(u32 mask, u32 value)
  17 {
  18         return ssb_gpio_out(&ssb, mask, value);
  19 }
  20
  21 static inline u32 gpio_outen(u32 mask, u32 value)
  22 {
  23         return ssb_gpio_outen(&ssb, mask, value);
  24 }
  25
  26 static inline u32 gpio_control(u32 mask, u32 value)
  27 {
  28         return ssb_gpio_control(&ssb, mask, value);
  29 }
  30
  31 static inline u32 gpio_intmask(u32 mask, u32 value)
  32 {
  33         return ssb_gpio_intmask(&ssb, mask, value);
  34 }
  35
  36 static inline u32 gpio_intpolarity(u32 mask, u32 value)
  37 {
  38         return ssb_gpio_polarity(&ssb, mask, value);
  39 }
  40
  41 static inline u32 __ssb_write32_masked(struct ssb_device *dev, u16 offset,
  42                                        u32 mask, u32 value)
  43 {
  44         value &= mask;
  45         value |= ssb_read32(dev, offset) & ~mask;
  46         ssb_write32(dev, offset, value);
  47         return value;
  48 }
  49
  50 static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *))
  51 {
  52         int irq;
  53
  54         if (ssb.chipco.dev)
  55                 irq = ssb_mips_irq(ssb.chipco.dev) + 2;
  56         else if (ssb.extif.dev)
  57                 irq = ssb_mips_irq(ssb.extif.dev) + 2;
  58         else return;
  59
  60         if (enabled) {
  61                 if (request_irq(irq, handler, IRQF_SHARED | IRQF_SAMPLE_RANDOM, "gpio", handler))
  62                         return;
  63         } else {
  64                 free_irq(irq, handler);
  65         }
  66
  67         if (ssb.chipco.dev)
  68                 __ssb_write32_masked(ssb.chipco.dev, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO, (enabled ? SSB_CHIPCO_IRQ_GPIO : 0));
  69 }
  70
  71 #else
  72
  73 #include <typedefs.h>
  74 #include <osl.h>
  75 #include <bcmdevs.h>
  76 #include <sbutils.h>
  77 #include <sbconfig.h>
  78 #include <sbchipc.h>
  79 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  80 #include <sbmips.h>
  81 #else
  82 #include <hndcpu.h>
  83 #endif
  84
  85 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  86 #define sbh bcm947xx_sbh
  87 #define sbh_lock bcm947xx_sbh_lock
  88 #endif
  89
  90 extern void *sbh;
  91 extern spinlock_t sbh_lock;
  92
  93 #define gpio_in()       sb_gpioin(sbh)
  94 #define gpio_out(mask, value)   sb_gpioout(sbh, mask, ((value) & (mask)), GPIO_DRV_PRIORITY)
  95 #define gpio_outen(mask, value)         sb_gpioouten(sbh, mask, value, GPIO_DRV_PRIORITY)
  96 #define gpio_control(mask, value)       sb_gpiocontrol(sbh, mask, value, GPIO_DRV_PRIORITY)
  97 #define gpio_intmask(mask, value)       sb_gpiointmask(sbh, mask, value, GPIO_DRV_PRIORITY)
  98 #define gpio_intpolarity(mask, value)   sb_gpiointpolarity(sbh, mask, value, GPIO_DRV_PRIORITY)
  99
 100 static void gpio_set_irqenable(int enabled, irqreturn_t (*handler)(int, void *, struct pt_regs *))
 101 {
 102         unsigned int coreidx;
 103         unsigned long flags;
 104         chipcregs_t *cc;
 105         int irq;
 106
 107         spin_lock_irqsave(sbh_lock, flags);
 108         coreidx = sb_coreidx(sbh);
 109
 110         irq = sb_irq(sbh) + 2;
 111         if (enabled)
 112                 request_irq(irq, handler, SA_SHIRQ | SA_SAMPLE_RANDOM, "gpio", handler);
 113         else
 114                 free_irq(irq, handler);
 115
 116         if ((cc = sb_setcore(sbh, SB_CC, 0))) {
 117                 int intmask;
 118
 119                 intmask = readl(&cc->intmask);
 120                 if (enabled)
 121                         intmask |= CI_GPIO;
 122                 else
 123                         intmask &= ~CI_GPIO;
 124                 writel(intmask, &cc->intmask);
 125         }
 126         sb_setcoreidx(sbh, coreidx);
 127         spin_unlock_irqrestore(sbh_lock, flags);
 128 }
 129
 130 #endif /* BCMDRIVER */
 131
 132 #define EXTIF_ADDR 0x1f000000
 133 #define EXTIF_UART (EXTIF_ADDR + 0x00800000)
 134
 135 #define GPIO_TYPE_NORMAL        (0x0 << 24)
 136 #define GPIO_TYPE_EXTIF         (0x1 << 24)
 137 #define GPIO_TYPE_MASK          (0xf << 24)
 138
 139 static inline void gpio_set_extif(int gpio, int value)
 140 {
 141         volatile u8 *addr = (volatile u8 *) KSEG1ADDR(EXTIF_UART) + (gpio & ~GPIO_TYPE_MASK);
 142         if (value)
 143                 *addr = 0xFF;
 144         else
 145                 *addr;
 146 }
 147
 148 #endif /* __DIAG_GPIO_H */