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6e9aaa97a37039721ef6f60c45981a22e88677e2
[openwrt.git] / target / linux / ixp4xx / patches-2.6.23 / 200-npe_driver.patch
1 Index: linux-2.6.23.17/arch/arm/kernel/setup.c
2 ===================================================================
3 --- linux-2.6.23.17.orig/arch/arm/kernel/setup.c
4 +++ linux-2.6.23.17/arch/arm/kernel/setup.c
5 @@ -62,6 +62,7 @@ extern int root_mountflags;
6 extern void _stext, _text, _etext, __data_start, _edata, _end;
7
8 unsigned int processor_id;
9 +EXPORT_SYMBOL(processor_id);
10 unsigned int __machine_arch_type;
11 EXPORT_SYMBOL(__machine_arch_type);
12
13 Index: linux-2.6.23.17/arch/arm/mach-ixp4xx/Kconfig
14 ===================================================================
15 --- linux-2.6.23.17.orig/arch/arm/mach-ixp4xx/Kconfig
16 +++ linux-2.6.23.17/arch/arm/mach-ixp4xx/Kconfig
17 @@ -246,6 +246,20 @@ config IXP4XX_INDIRECT_PCI
18 need to use the indirect method instead. If you don't know
19 what you need, leave this option unselected.
20
21 +config IXP4XX_QMGR
22 + tristate "IXP4xx Queue Manager support"
23 + help
24 + This driver supports IXP4xx built-in hardware queue manager
25 + and is automatically selected by Ethernet and HSS drivers.
26 +
27 +config IXP4XX_NPE
28 + tristate "IXP4xx Network Processor Engine support"
29 + select HOTPLUG
30 + select FW_LOADER
31 + help
32 + This driver supports IXP4xx built-in network coprocessors
33 + and is automatically selected by Ethernet and HSS drivers.
34 +
35 endmenu
36
37 endif
38 Index: linux-2.6.23.17/arch/arm/mach-ixp4xx/Makefile
39 ===================================================================
40 --- linux-2.6.23.17.orig/arch/arm/mach-ixp4xx/Makefile
41 +++ linux-2.6.23.17/arch/arm/mach-ixp4xx/Makefile
42 @@ -44,3 +44,5 @@ obj-$(CONFIG_MACH_SIDEWINDER) += sidewin
43 obj-$(CONFIG_MACH_AP1000) += ap1000-setup.o
44
45 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
46 +obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
47 +obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
48 Index: linux-2.6.23.17/arch/arm/mach-ixp4xx/ixdp425-setup.c
49 ===================================================================
50 --- linux-2.6.23.17.orig/arch/arm/mach-ixp4xx/ixdp425-setup.c
51 +++ linux-2.6.23.17/arch/arm/mach-ixp4xx/ixdp425-setup.c
52 @@ -177,6 +177,31 @@ static struct platform_device ixdp425_ua
53 .resource = ixdp425_uart_resources
54 };
55
56 +/* Built-in 10/100 Ethernet MAC interfaces */
57 +static struct eth_plat_info ixdp425_plat_eth[] = {
58 + {
59 + .phy = 0,
60 + .rxq = 3,
61 + .txreadyq = 20,
62 + }, {
63 + .phy = 1,
64 + .rxq = 4,
65 + .txreadyq = 21,
66 + }
67 +};
68 +
69 +static struct platform_device ixdp425_eth[] = {
70 + {
71 + .name = "ixp4xx_eth",
72 + .id = IXP4XX_ETH_NPEB,
73 + .dev.platform_data = ixdp425_plat_eth,
74 + }, {
75 + .name = "ixp4xx_eth",
76 + .id = IXP4XX_ETH_NPEC,
77 + .dev.platform_data = ixdp425_plat_eth + 1,
78 + }
79 +};
80 +
81 static struct platform_device *ixdp425_devices[] __initdata = {
82 &ixdp425_i2c_gpio,
83 &ixdp425_flash,
84 @@ -184,7 +209,9 @@ static struct platform_device *ixdp425_d
85 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
86 &ixdp425_flash_nand,
87 #endif
88 - &ixdp425_uart
89 + &ixdp425_uart,
90 + &ixdp425_eth[0],
91 + &ixdp425_eth[1],
92 };
93
94 static void __init ixdp425_init(void)
95 Index: linux-2.6.23.17/arch/arm/mach-ixp4xx/ixp4xx_npe.c
96 ===================================================================
97 --- /dev/null
98 +++ linux-2.6.23.17/arch/arm/mach-ixp4xx/ixp4xx_npe.c
99 @@ -0,0 +1,741 @@
100 +/*
101 + * Intel IXP4xx Network Processor Engine driver for Linux
102 + *
103 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
104 + *
105 + * This program is free software; you can redistribute it and/or modify it
106 + * under the terms of version 2 of the GNU General Public License
107 + * as published by the Free Software Foundation.
108 + *
109 + * The code is based on publicly available information:
110 + * - Intel IXP4xx Developer's Manual and other e-papers
111 + * - Intel IXP400 Access Library Software (BSD license)
112 + * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
113 + * Thanks, Christian.
114 + */
115 +
116 +#include <linux/delay.h>
117 +#include <linux/dma-mapping.h>
118 +#include <linux/firmware.h>
119 +#include <linux/io.h>
120 +#include <linux/kernel.h>
121 +#include <linux/module.h>
122 +#include <linux/slab.h>
123 +#include <asm/arch/npe.h>
124 +
125 +#define DEBUG_MSG 0
126 +#define DEBUG_FW 0
127 +
128 +#define NPE_COUNT 3
129 +#define MAX_RETRIES 1000 /* microseconds */
130 +#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
131 +#define NPE_46X_DATA_SIZE 0x1000
132 +#define NPE_A_42X_INSTR_SIZE 0x1000
133 +#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
134 +#define NPE_46X_INSTR_SIZE 0x1000
135 +#define REGS_SIZE 0x1000
136 +
137 +#define NPE_PHYS_REG 32
138 +
139 +#define FW_MAGIC 0xFEEDF00D
140 +#define FW_BLOCK_TYPE_INSTR 0x0
141 +#define FW_BLOCK_TYPE_DATA 0x1
142 +#define FW_BLOCK_TYPE_EOF 0xF
143 +
144 +/* NPE exec status (read) and command (write) */
145 +#define CMD_NPE_STEP 0x01
146 +#define CMD_NPE_START 0x02
147 +#define CMD_NPE_STOP 0x03
148 +#define CMD_NPE_CLR_PIPE 0x04
149 +#define CMD_CLR_PROFILE_CNT 0x0C
150 +#define CMD_RD_INS_MEM 0x10 /* instruction memory */
151 +#define CMD_WR_INS_MEM 0x11
152 +#define CMD_RD_DATA_MEM 0x12 /* data memory */
153 +#define CMD_WR_DATA_MEM 0x13
154 +#define CMD_RD_ECS_REG 0x14 /* exec access register */
155 +#define CMD_WR_ECS_REG 0x15
156 +
157 +#define STAT_RUN 0x80000000
158 +#define STAT_STOP 0x40000000
159 +#define STAT_CLEAR 0x20000000
160 +#define STAT_ECS_K 0x00800000 /* pipeline clean */
161 +
162 +#define NPE_STEVT 0x1B
163 +#define NPE_STARTPC 0x1C
164 +#define NPE_REGMAP 0x1E
165 +#define NPE_CINDEX 0x1F
166 +
167 +#define INSTR_WR_REG_SHORT 0x0000C000
168 +#define INSTR_WR_REG_BYTE 0x00004000
169 +#define INSTR_RD_FIFO 0x0F888220
170 +#define INSTR_RESET_MBOX 0x0FAC8210
171 +
172 +#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
173 +#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
174 +#define ECS_BG_CTXT_REG_2 0x02
175 +#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
176 +#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
177 +#define ECS_PRI_1_CTXT_REG_2 0x06
178 +#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
179 +#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
180 +#define ECS_PRI_2_CTXT_REG_2 0x0A
181 +#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
182 +#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
183 +#define ECS_DBG_CTXT_REG_2 0x0E
184 +#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
185 +
186 +#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
187 +#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
188 +#define ECS_REG_0_LDUR_BITS 8
189 +#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
190 +#define ECS_REG_1_CCTXT_BITS 16
191 +#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
192 +#define ECS_REG_1_SELCTXT_BITS 0
193 +#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
194 +#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
195 +#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
196 +
197 +/* NPE watchpoint_fifo register bit */
198 +#define WFIFO_VALID 0x80000000
199 +
200 +/* NPE messaging_status register bit definitions */
201 +#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
202 +#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
203 +#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
204 +#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
205 +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
206 +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
207 +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
208 +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
209 +
210 +/* NPE messaging_control register bit definitions */
211 +#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
212 +#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
213 +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
214 +#define MSGCTL_IN_FIFO_WRITE 0x02000000
215 +
216 +/* NPE mailbox_status value for reset */
217 +#define RESET_MBOX_STAT 0x0000F0F0
218 +
219 +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
220 +
221 +#define print_npe(pri, npe, fmt, ...) \
222 + printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
223 +
224 +#if DEBUG_MSG
225 +#define debug_msg(npe, fmt, ...) \
226 + print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
227 +#else
228 +#define debug_msg(npe, fmt, ...)
229 +#endif
230 +
231 +static struct {
232 + u32 reg, val;
233 +} ecs_reset[] = {
234 + { ECS_BG_CTXT_REG_0, 0xA0000000 },
235 + { ECS_BG_CTXT_REG_1, 0x01000000 },
236 + { ECS_BG_CTXT_REG_2, 0x00008000 },
237 + { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
238 + { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
239 + { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
240 + { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
241 + { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
242 + { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
243 + { ECS_DBG_CTXT_REG_0, 0x20000000 },
244 + { ECS_DBG_CTXT_REG_1, 0x00000000 },
245 + { ECS_DBG_CTXT_REG_2, 0x001E0000 },
246 + { ECS_INSTRUCT_REG, 0x1003C00F },
247 +};
248 +
249 +static struct npe npe_tab[NPE_COUNT] = {
250 + {
251 + .id = 0,
252 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
253 + .regs_phys = IXP4XX_NPEA_BASE_PHYS,
254 + }, {
255 + .id = 1,
256 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
257 + .regs_phys = IXP4XX_NPEB_BASE_PHYS,
258 + }, {
259 + .id = 2,
260 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
261 + .regs_phys = IXP4XX_NPEC_BASE_PHYS,
262 + }
263 +};
264 +
265 +int npe_running(struct npe *npe)
266 +{
267 + return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
268 +}
269 +
270 +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
271 +{
272 + __raw_writel(data, &npe->regs->exec_data);
273 + __raw_writel(addr, &npe->regs->exec_addr);
274 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
275 +}
276 +
277 +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
278 +{
279 + __raw_writel(addr, &npe->regs->exec_addr);
280 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
281 + /* Iintroduce extra read cycles after issuing read command to NPE
282 + so that we read the register after the NPE has updated it.
283 + This is to overcome race condition between XScale and NPE */
284 + __raw_readl(&npe->regs->exec_data);
285 + __raw_readl(&npe->regs->exec_data);
286 + return __raw_readl(&npe->regs->exec_data);
287 +}
288 +
289 +static void npe_clear_active(struct npe *npe, u32 reg)
290 +{
291 + u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
292 + npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
293 +}
294 +
295 +static void npe_start(struct npe *npe)
296 +{
297 + /* ensure only Background Context Stack Level is active */
298 + npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
299 + npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
300 + npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
301 +
302 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
303 + __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
304 +}
305 +
306 +static void npe_stop(struct npe *npe)
307 +{
308 + __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
309 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
310 +}
311 +
312 +static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
313 + u32 ldur)
314 +{
315 + u32 wc;
316 + int i;
317 +
318 + /* set the Active bit, and the LDUR, in the debug level */
319 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
320 + ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
321 +
322 + /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
323 + the instruction, and set SELCTXT at ECS DEBUG Level to specify
324 + which context store to access.
325 + Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
326 + */
327 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
328 + (ctx << ECS_REG_1_CCTXT_BITS) |
329 + (ctx << ECS_REG_1_SELCTXT_BITS));
330 +
331 + /* clear the pipeline */
332 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
333 +
334 + /* load NPE instruction into the instruction register */
335 + npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
336 +
337 + /* we need this value later to wait for completion of NPE execution
338 + step */
339 + wc = __raw_readl(&npe->regs->watch_count);
340 +
341 + /* issue a Step One command via the Execution Control register */
342 + __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
343 +
344 + /* Watch Count register increments when NPE completes an instruction */
345 + for (i = 0; i < MAX_RETRIES; i++) {
346 + if (wc != __raw_readl(&npe->regs->watch_count))
347 + return 0;
348 + udelay(1);
349 + }
350 +
351 + print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
352 + return -ETIMEDOUT;
353 +}
354 +
355 +static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
356 + u8 val, u32 ctx)
357 +{
358 + /* here we build the NPE assembler instruction: mov8 d0, #0 */
359 + u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
360 + addr << 9 | /* base Operand */
361 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
362 + (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
363 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
364 +}
365 +
366 +static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
367 + u16 val, u32 ctx)
368 +{
369 + /* here we build the NPE assembler instruction: mov16 d0, #0 */
370 + u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
371 + addr << 9 | /* base Operand */
372 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
373 + (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
374 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
375 +}
376 +
377 +static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
378 + u32 val, u32 ctx)
379 +{
380 + /* write in 16 bit steps first the high and then the low value */
381 + if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
382 + return -ETIMEDOUT;
383 + return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
384 +}
385 +
386 +static int npe_reset(struct npe *npe)
387 +{
388 + u32 val, ctl, exec_count, ctx_reg2;
389 + int i;
390 +
391 + ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
392 + 0x3F3FFFFF;
393 +
394 + /* disable parity interrupt */
395 + __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
396 +
397 + /* pre exec - debug instruction */
398 + /* turn off the halt bit by clearing Execution Count register. */
399 + exec_count = __raw_readl(&npe->regs->exec_count);
400 + __raw_writel(0, &npe->regs->exec_count);
401 + /* ensure that IF and IE are on (temporarily), so that we don't end up
402 + stepping forever */
403 + ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
404 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
405 + ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
406 +
407 + /* clear the FIFOs */
408 + while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
409 + ;
410 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
411 + /* read from the outFIFO until empty */
412 + print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
413 + __raw_readl(&npe->regs->in_out_fifo));
414 +
415 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
416 + /* step execution of the NPE intruction to read inFIFO using
417 + the Debug Executing Context stack */
418 + if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
419 + return -ETIMEDOUT;
420 +
421 + /* reset the mailbox reg from the XScale side */
422 + __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
423 + /* from NPE side */
424 + if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
425 + return -ETIMEDOUT;
426 +
427 + /* Reset the physical registers in the NPE register file */
428 + for (val = 0; val < NPE_PHYS_REG; val++) {
429 + if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
430 + return -ETIMEDOUT;
431 + /* address is either 0 or 4 */
432 + if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
433 + return -ETIMEDOUT;
434 + }
435 +
436 + /* Reset the context store = each context's Context Store registers */
437 +
438 + /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
439 + for Background ECS, to set where NPE starts executing code */
440 + val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
441 + val &= ~ECS_REG_0_NEXTPC_MASK;
442 + val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
443 + npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
444 +
445 + for (i = 0; i < 16; i++) {
446 + if (i) { /* Context 0 has no STEVT nor STARTPC */
447 + /* STEVT = off, 0x80 */
448 + if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
449 + return -ETIMEDOUT;
450 + if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
451 + return -ETIMEDOUT;
452 + }
453 + /* REGMAP = d0->p0, d8->p2, d16->p4 */
454 + if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
455 + return -ETIMEDOUT;
456 + if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
457 + return -ETIMEDOUT;
458 + }
459 +
460 + /* post exec */
461 + /* clear active bit in debug level */
462 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
463 + /* clear the pipeline */
464 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
465 + /* restore previous values */
466 + __raw_writel(exec_count, &npe->regs->exec_count);
467 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
468 +
469 + /* write reset values to Execution Context Stack registers */
470 + for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
471 + npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
472 + ecs_reset[val].val);
473 +
474 + /* clear the profile counter */
475 + __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
476 +
477 + __raw_writel(0, &npe->regs->exec_count);
478 + __raw_writel(0, &npe->regs->action_points[0]);
479 + __raw_writel(0, &npe->regs->action_points[1]);
480 + __raw_writel(0, &npe->regs->action_points[2]);
481 + __raw_writel(0, &npe->regs->action_points[3]);
482 + __raw_writel(0, &npe->regs->watch_count);
483 +
484 + val = ixp4xx_read_feature_bits();
485 + /* reset the NPE */
486 + ixp4xx_write_feature_bits(val &
487 + ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
488 + for (i = 0; i < MAX_RETRIES; i++) {
489 + if (!(ixp4xx_read_feature_bits() &
490 + (IXP4XX_FEATURE_RESET_NPEA << npe->id)))
491 + break; /* reset completed */
492 + udelay(1);
493 + }
494 + if (i == MAX_RETRIES)
495 + return -ETIMEDOUT;
496 +
497 + /* deassert reset */
498 + ixp4xx_write_feature_bits(val |
499 + (IXP4XX_FEATURE_RESET_NPEA << npe->id));
500 + for (i = 0; i < MAX_RETRIES; i++) {
501 + if (ixp4xx_read_feature_bits() &
502 + (IXP4XX_FEATURE_RESET_NPEA << npe->id))
503 + break; /* NPE is back alive */
504 + udelay(1);
505 + }
506 + if (i == MAX_RETRIES)
507 + return -ETIMEDOUT;
508 +
509 + npe_stop(npe);
510 +
511 + /* restore NPE configuration bus Control Register - parity settings */
512 + __raw_writel(ctl, &npe->regs->messaging_control);
513 + return 0;
514 +}
515 +
516 +
517 +int npe_send_message(struct npe *npe, const void *msg, const char *what)
518 +{
519 + const u32 *send = msg;
520 + int cycles = 0;
521 +
522 + debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
523 + what, send[0], send[1]);
524 +
525 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
526 + debug_msg(npe, "NPE input FIFO not empty\n");
527 + return -EIO;
528 + }
529 +
530 + __raw_writel(send[0], &npe->regs->in_out_fifo);
531 +
532 + if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
533 + debug_msg(npe, "NPE input FIFO full\n");
534 + return -EIO;
535 + }
536 +
537 + __raw_writel(send[1], &npe->regs->in_out_fifo);
538 +
539 + while ((cycles < MAX_RETRIES) &&
540 + (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
541 + udelay(1);
542 + cycles++;
543 + }
544 +
545 + if (cycles == MAX_RETRIES) {
546 + debug_msg(npe, "Timeout sending message\n");
547 + return -ETIMEDOUT;
548 + }
549 +
550 + debug_msg(npe, "Sending a message took %i cycles\n", cycles);
551 + return 0;
552 +}
553 +
554 +int npe_recv_message(struct npe *npe, void *msg, const char *what)
555 +{
556 + u32 *recv = msg;
557 + int cycles = 0, cnt = 0;
558 +
559 + debug_msg(npe, "Trying to receive message %s\n", what);
560 +
561 + while (cycles < MAX_RETRIES) {
562 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
563 + recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
564 + if (cnt == 2)
565 + break;
566 + } else {
567 + udelay(1);
568 + cycles++;
569 + }
570 + }
571 +
572 + switch(cnt) {
573 + case 1:
574 + debug_msg(npe, "Received [%08X]\n", recv[0]);
575 + break;
576 + case 2:
577 + debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
578 + break;
579 + }
580 +
581 + if (cycles == MAX_RETRIES) {
582 + debug_msg(npe, "Timeout waiting for message\n");
583 + return -ETIMEDOUT;
584 + }
585 +
586 + debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
587 + return 0;
588 +}
589 +
590 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
591 +{
592 + int result;
593 + u32 *send = msg, recv[2];
594 +
595 + if ((result = npe_send_message(npe, msg, what)) != 0)
596 + return result;
597 + if ((result = npe_recv_message(npe, recv, what)) != 0)
598 + return result;
599 +
600 + if ((recv[0] != send[0]) || (recv[1] != send[1])) {
601 + debug_msg(npe, "Message %s: unexpected message received\n",
602 + what);
603 + return -EIO;
604 + }
605 + return 0;
606 +}
607 +
608 +
609 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
610 +{
611 + const struct firmware *fw_entry;
612 +
613 + struct dl_block {
614 + u32 type;
615 + u32 offset;
616 + } *blk;
617 +
618 + struct dl_image {
619 + u32 magic;
620 + u32 id;
621 + u32 size;
622 + union {
623 + u32 data[0];
624 + struct dl_block blocks[0];
625 + };
626 + } *image;
627 +
628 + struct dl_codeblock {
629 + u32 npe_addr;
630 + u32 size;
631 + u32 data[0];
632 + } *cb;
633 +
634 + int i, j, err, data_size, instr_size, blocks, table_end;
635 + u32 cmd;
636 +
637 + if ((err = request_firmware(&fw_entry, name, dev)) != 0)
638 + return err;
639 +
640 + err = -EINVAL;
641 + if (fw_entry->size < sizeof(struct dl_image)) {
642 + print_npe(KERN_ERR, npe, "incomplete firmware file\n");
643 + goto err;
644 + }
645 + image = (struct dl_image*)fw_entry->data;
646 +
647 +#if DEBUG_FW
648 + print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
649 + image->magic, image->id, image->size, image->size * 4);
650 +#endif
651 +
652 + if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
653 + image->id = swab32(image->id);
654 + image->size = swab32(image->size);
655 + } else if (image->magic != FW_MAGIC) {
656 + print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
657 + image->magic);
658 + goto err;
659 + }
660 + if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
661 + print_npe(KERN_ERR, npe,
662 + "inconsistent size of firmware file\n");
663 + goto err;
664 + }
665 + if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
666 + print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
667 + goto err;
668 + }
669 + if (image->magic == swab32(FW_MAGIC))
670 + for (i = 0; i < image->size; i++)
671 + image->data[i] = swab32(image->data[i]);
672 +
673 + if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
674 + print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
675 + "IXP42x\n");
676 + goto err;
677 + }
678 +
679 + if (npe_running(npe)) {
680 + print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
681 + "already running\n");
682 + err = -EBUSY;
683 + goto err;
684 + }
685 +#if 0
686 + npe_stop(npe);
687 + npe_reset(npe);
688 +#endif
689 +
690 + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
691 + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
692 + (image->id >> 8) & 0xFF, image->id & 0xFF);
693 +
694 + if (!cpu_is_ixp46x()) {
695 + if (!npe->id)
696 + instr_size = NPE_A_42X_INSTR_SIZE;
697 + else
698 + instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
699 + data_size = NPE_42X_DATA_SIZE;
700 + } else {
701 + instr_size = NPE_46X_INSTR_SIZE;
702 + data_size = NPE_46X_DATA_SIZE;
703 + }
704 +
705 + for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
706 + blocks++)
707 + if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
708 + break;
709 + if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
710 + print_npe(KERN_INFO, npe, "firmware EOF block marker not "
711 + "found\n");
712 + goto err;
713 + }
714 +
715 +#if DEBUG_FW
716 + print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
717 +#endif
718 +
719 + table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
720 + for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
721 + if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
722 + || blk->offset < table_end) {
723 + print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
724 + "firmware block #%i\n", blk->offset, i);
725 + goto err;
726 + }
727 +
728 + cb = (struct dl_codeblock*)&image->data[blk->offset];
729 + if (blk->type == FW_BLOCK_TYPE_INSTR) {
730 + if (cb->npe_addr + cb->size > instr_size)
731 + goto too_big;
732 + cmd = CMD_WR_INS_MEM;
733 + } else if (blk->type == FW_BLOCK_TYPE_DATA) {
734 + if (cb->npe_addr + cb->size > data_size)
735 + goto too_big;
736 + cmd = CMD_WR_DATA_MEM;
737 + } else {
738 + print_npe(KERN_INFO, npe, "invalid firmware block #%i "
739 + "type 0x%X\n", i, blk->type);
740 + goto err;
741 + }
742 + if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
743 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
744 + "fit in firmware image: type %c, start 0x%X,"
745 + " length 0x%X\n", i,
746 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
747 + cb->npe_addr, cb->size);
748 + goto err;
749 + }
750 +
751 + for (j = 0; j < cb->size; j++)
752 + npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
753 + }
754 +
755 + npe_start(npe);
756 + if (!npe_running(npe))
757 + print_npe(KERN_ERR, npe, "unable to start\n");
758 + release_firmware(fw_entry);
759 + return 0;
760 +
761 +too_big:
762 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
763 + "memory: type %c, start 0x%X, length 0x%X\n", i,
764 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
765 + cb->npe_addr, cb->size);
766 +err:
767 + release_firmware(fw_entry);
768 + return err;
769 +}
770 +
771 +
772 +struct npe *npe_request(int id)
773 +{
774 + if (id < NPE_COUNT)
775 + if (npe_tab[id].valid)
776 + if (try_module_get(THIS_MODULE))
777 + return &npe_tab[id];
778 + return NULL;
779 +}
780 +
781 +void npe_release(struct npe *npe)
782 +{
783 + module_put(THIS_MODULE);
784 +}
785 +
786 +
787 +static int __init npe_init_module(void)
788 +{
789 +
790 + int i, found = 0;
791 +
792 + for (i = 0; i < NPE_COUNT; i++) {
793 + struct npe *npe = &npe_tab[i];
794 + if (!(ixp4xx_read_feature_bits() &
795 + (IXP4XX_FEATURE_RESET_NPEA << i)))
796 + continue; /* NPE already disabled or not present */
797 + if (!(npe->mem_res = request_mem_region(npe->regs_phys,
798 + REGS_SIZE,
799 + npe_name(npe)))) {
800 + print_npe(KERN_ERR, npe,
801 + "failed to request memory region\n");
802 + continue;
803 + }
804 +
805 + if (npe_reset(npe))
806 + continue;
807 + npe->valid = 1;
808 + found++;
809 + }
810 +
811 + if (!found)
812 + return -ENOSYS;
813 + return 0;
814 +}
815 +
816 +static void __exit npe_cleanup_module(void)
817 +{
818 + int i;
819 +
820 + for (i = 0; i < NPE_COUNT; i++)
821 + if (npe_tab[i].mem_res) {
822 + npe_reset(&npe_tab[i]);
823 + release_resource(npe_tab[i].mem_res);
824 + }
825 +}
826 +
827 +module_init(npe_init_module);
828 +module_exit(npe_cleanup_module);
829 +
830 +MODULE_AUTHOR("Krzysztof Halasa");
831 +MODULE_LICENSE("GPL v2");
832 +
833 +EXPORT_SYMBOL(npe_names);
834 +EXPORT_SYMBOL(npe_running);
835 +EXPORT_SYMBOL(npe_request);
836 +EXPORT_SYMBOL(npe_release);
837 +EXPORT_SYMBOL(npe_load_firmware);
838 +EXPORT_SYMBOL(npe_send_message);
839 +EXPORT_SYMBOL(npe_recv_message);
840 +EXPORT_SYMBOL(npe_send_recv_message);
841 Index: linux-2.6.23.17/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
842 ===================================================================
843 --- /dev/null
844 +++ linux-2.6.23.17/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
845 @@ -0,0 +1,274 @@
846 +/*
847 + * Intel IXP4xx Queue Manager driver for Linux
848 + *
849 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
850 + *
851 + * This program is free software; you can redistribute it and/or modify it
852 + * under the terms of version 2 of the GNU General Public License
853 + * as published by the Free Software Foundation.
854 + */
855 +
856 +#include <linux/ioport.h>
857 +#include <linux/interrupt.h>
858 +#include <linux/kernel.h>
859 +#include <linux/module.h>
860 +#include <asm/arch/qmgr.h>
861 +
862 +#define DEBUG 0
863 +
864 +struct qmgr_regs __iomem *qmgr_regs;
865 +static struct resource *mem_res;
866 +static spinlock_t qmgr_lock;
867 +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
868 +static void (*irq_handlers[HALF_QUEUES])(void *pdev);
869 +static void *irq_pdevs[HALF_QUEUES];
870 +
871 +void qmgr_set_irq(unsigned int queue, int src,
872 + void (*handler)(void *pdev), void *pdev)
873 +{
874 + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
875 + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
876 + unsigned long flags;
877 +
878 + src &= 7;
879 + spin_lock_irqsave(&qmgr_lock, flags);
880 + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
881 + irq_handlers[queue] = handler;
882 + irq_pdevs[queue] = pdev;
883 + spin_unlock_irqrestore(&qmgr_lock, flags);
884 +}
885 +
886 +
887 +static irqreturn_t qmgr_irq1(int irq, void *pdev)
888 +{
889 + int i;
890 + u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
891 + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
892 +
893 + for (i = 0; i < HALF_QUEUES; i++)
894 + if (val & (1 << i))
895 + irq_handlers[i](irq_pdevs[i]);
896 +
897 + return val ? IRQ_HANDLED : 0;
898 +}
899 +
900 +
901 +void qmgr_enable_irq(unsigned int queue)
902 +{
903 + unsigned long flags;
904 +
905 + spin_lock_irqsave(&qmgr_lock, flags);
906 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
907 + &qmgr_regs->irqen[0]);
908 + spin_unlock_irqrestore(&qmgr_lock, flags);
909 +}
910 +
911 +void qmgr_disable_irq(unsigned int queue)
912 +{
913 + unsigned long flags;
914 +
915 + spin_lock_irqsave(&qmgr_lock, flags);
916 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
917 + &qmgr_regs->irqen[0]);
918 + spin_unlock_irqrestore(&qmgr_lock, flags);
919 +}
920 +
921 +static inline void shift_mask(u32 *mask)
922 +{
923 + mask[3] = mask[3] << 1 | mask[2] >> 31;
924 + mask[2] = mask[2] << 1 | mask[1] >> 31;
925 + mask[1] = mask[1] << 1 | mask[0] >> 31;
926 + mask[0] <<= 1;
927 +}
928 +
929 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
930 + unsigned int nearly_empty_watermark,
931 + unsigned int nearly_full_watermark)
932 +{
933 + u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
934 + int err;
935 +
936 + if (queue >= HALF_QUEUES)
937 + return -ERANGE;
938 +
939 + if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
940 + return -EINVAL;
941 +
942 + switch (len) {
943 + case 16:
944 + cfg = 0 << 24;
945 + mask[0] = 0x1;
946 + break;
947 + case 32:
948 + cfg = 1 << 24;
949 + mask[0] = 0x3;
950 + break;
951 + case 64:
952 + cfg = 2 << 24;
953 + mask[0] = 0xF;
954 + break;
955 + case 128:
956 + cfg = 3 << 24;
957 + mask[0] = 0xFF;
958 + break;
959 + default:
960 + return -EINVAL;
961 + }
962 +
963 + cfg |= nearly_empty_watermark << 26;
964 + cfg |= nearly_full_watermark << 29;
965 + len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
966 + mask[1] = mask[2] = mask[3] = 0;
967 +
968 + if (!try_module_get(THIS_MODULE))
969 + return -ENODEV;
970 +
971 + spin_lock_irq(&qmgr_lock);
972 + if (__raw_readl(&qmgr_regs->sram[queue])) {
973 + err = -EBUSY;
974 + goto err;
975 + }
976 +
977 + while (1) {
978 + if (!(used_sram_bitmap[0] & mask[0]) &&
979 + !(used_sram_bitmap[1] & mask[1]) &&
980 + !(used_sram_bitmap[2] & mask[2]) &&
981 + !(used_sram_bitmap[3] & mask[3]))
982 + break; /* found free space */
983 +
984 + addr++;
985 + shift_mask(mask);
986 + if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
987 + printk(KERN_ERR "qmgr: no free SRAM space for"
988 + " queue %i\n", queue);
989 + err = -ENOMEM;
990 + goto err;
991 + }
992 + }
993 +
994 + used_sram_bitmap[0] |= mask[0];
995 + used_sram_bitmap[1] |= mask[1];
996 + used_sram_bitmap[2] |= mask[2];
997 + used_sram_bitmap[3] |= mask[3];
998 + __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
999 + spin_unlock_irq(&qmgr_lock);
1000 +
1001 +#if DEBUG
1002 + printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n",
1003 + queue, addr);
1004 +#endif
1005 + return 0;
1006 +
1007 +err:
1008 + spin_unlock_irq(&qmgr_lock);
1009 + module_put(THIS_MODULE);
1010 + return err;
1011 +}
1012 +
1013 +void qmgr_release_queue(unsigned int queue)
1014 +{
1015 + u32 cfg, addr, mask[4];
1016 +
1017 + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
1018 +
1019 + spin_lock_irq(&qmgr_lock);
1020 + cfg = __raw_readl(&qmgr_regs->sram[queue]);
1021 + addr = (cfg >> 14) & 0xFF;
1022 +
1023 + BUG_ON(!addr); /* not requested */
1024 +
1025 + switch ((cfg >> 24) & 3) {
1026 + case 0: mask[0] = 0x1; break;
1027 + case 1: mask[0] = 0x3; break;
1028 + case 2: mask[0] = 0xF; break;
1029 + case 3: mask[0] = 0xFF; break;
1030 + }
1031 +
1032 + while (addr--)
1033 + shift_mask(mask);
1034 +
1035 + __raw_writel(0, &qmgr_regs->sram[queue]);
1036 +
1037 + used_sram_bitmap[0] &= ~mask[0];
1038 + used_sram_bitmap[1] &= ~mask[1];
1039 + used_sram_bitmap[2] &= ~mask[2];
1040 + used_sram_bitmap[3] &= ~mask[3];
1041 + irq_handlers[queue] = NULL; /* catch IRQ bugs */
1042 + spin_unlock_irq(&qmgr_lock);
1043 +
1044 + module_put(THIS_MODULE);
1045 +#if DEBUG
1046 + printk(KERN_DEBUG "qmgr: released queue %i\n", queue);
1047 +#endif
1048 +}
1049 +
1050 +static int qmgr_init(void)
1051 +{
1052 + int i, err;
1053 + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
1054 + IXP4XX_QMGR_REGION_SIZE,
1055 + "IXP4xx Queue Manager");
1056 + if (mem_res == NULL)
1057 + return -EBUSY;
1058 +
1059 + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1060 + if (qmgr_regs == NULL) {
1061 + err = -ENOMEM;
1062 + goto error_map;
1063 + }
1064 +
1065 + /* reset qmgr registers */
1066 + for (i = 0; i < 4; i++) {
1067 + __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
1068 + __raw_writel(0, &qmgr_regs->irqsrc[i]);
1069 + }
1070 + for (i = 0; i < 2; i++) {
1071 + __raw_writel(0, &qmgr_regs->stat2[i]);
1072 + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
1073 + __raw_writel(0, &qmgr_regs->irqen[i]);
1074 + }
1075 +
1076 + for (i = 0; i < QUEUES; i++)
1077 + __raw_writel(0, &qmgr_regs->sram[i]);
1078 +
1079 + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
1080 + "IXP4xx Queue Manager", NULL);
1081 + if (err) {
1082 + printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
1083 + IRQ_IXP4XX_QM1);
1084 + goto error_irq;
1085 + }
1086 +
1087 + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
1088 + spin_lock_init(&qmgr_lock);
1089 +
1090 + printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
1091 + return 0;
1092 +
1093 +error_irq:
1094 + iounmap(qmgr_regs);
1095 +error_map:
1096 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1097 + return err;
1098 +}
1099 +
1100 +static void qmgr_remove(void)
1101 +{
1102 + free_irq(IRQ_IXP4XX_QM1, NULL);
1103 + synchronize_irq(IRQ_IXP4XX_QM1);
1104 + iounmap(qmgr_regs);
1105 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1106 +}
1107 +
1108 +module_init(qmgr_init);
1109 +module_exit(qmgr_remove);
1110 +
1111 +MODULE_LICENSE("GPL v2");
1112 +MODULE_AUTHOR("Krzysztof Halasa");
1113 +
1114 +EXPORT_SYMBOL(qmgr_regs);
1115 +EXPORT_SYMBOL(qmgr_set_irq);
1116 +EXPORT_SYMBOL(qmgr_enable_irq);
1117 +EXPORT_SYMBOL(qmgr_disable_irq);
1118 +EXPORT_SYMBOL(qmgr_request_queue);
1119 +EXPORT_SYMBOL(qmgr_release_queue);
1120 Index: linux-2.6.23.17/drivers/net/arm/Kconfig
1121 ===================================================================
1122 --- linux-2.6.23.17.orig/drivers/net/arm/Kconfig
1123 +++ linux-2.6.23.17/drivers/net/arm/Kconfig
1124 @@ -47,3 +47,13 @@ config EP93XX_ETH
1125 help
1126 This is a driver for the ethernet hardware included in EP93xx CPUs.
1127 Say Y if you are building a kernel for EP93xx based devices.
1128 +
1129 +config IXP4XX_ETH
1130 + tristate "IXP4xx Ethernet support"
1131 + depends on NET_ETHERNET && ARM && ARCH_IXP4XX
1132 + select IXP4XX_NPE
1133 + select IXP4XX_QMGR
1134 + select MII
1135 + help
1136 + Say Y here if you want to use built-in Ethernet ports
1137 + on IXP4xx processor.
1138 Index: linux-2.6.23.17/drivers/net/arm/Makefile
1139 ===================================================================
1140 --- linux-2.6.23.17.orig/drivers/net/arm/Makefile
1141 +++ linux-2.6.23.17/drivers/net/arm/Makefile
1142 @@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3) += ether3.o
1143 obj-$(CONFIG_ARM_ETHER1) += ether1.o
1144 obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
1145 obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
1146 +obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o
1147 Index: linux-2.6.23.17/drivers/net/arm/ixp4xx_eth.c
1148 ===================================================================
1149 --- /dev/null
1150 +++ linux-2.6.23.17/drivers/net/arm/ixp4xx_eth.c
1151 @@ -0,0 +1,1259 @@
1152 +/*
1153 + * Intel IXP4xx Ethernet driver for Linux
1154 + *
1155 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
1156 + *
1157 + * This program is free software; you can redistribute it and/or modify it
1158 + * under the terms of version 2 of the GNU General Public License
1159 + * as published by the Free Software Foundation.
1160 + *
1161 + * Ethernet port config (0x00 is not present on IXP42X):
1162 + *
1163 + * logical port 0x00 0x10 0x20
1164 + * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
1165 + * physical PortId 2 0 1
1166 + * TX queue 23 24 25
1167 + * RX-free queue 26 27 28
1168 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
1169 + *
1170 + *
1171 + * Queue entries:
1172 + * bits 0 -> 1 - NPE ID (RX and TX-done)
1173 + * bits 0 -> 2 - priority (TX, per 802.1D)
1174 + * bits 3 -> 4 - port ID (user-set?)
1175 + * bits 5 -> 31 - physical descriptor address
1176 + */
1177 +
1178 +#include <linux/delay.h>
1179 +#include <linux/dma-mapping.h>
1180 +#include <linux/dmapool.h>
1181 +#include <linux/etherdevice.h>
1182 +#include <linux/io.h>
1183 +#include <linux/kernel.h>
1184 +#include <linux/mii.h>
1185 +#include <linux/platform_device.h>
1186 +#include <asm/arch/npe.h>
1187 +#include <asm/arch/qmgr.h>
1188 +
1189 +#define DEBUG_QUEUES 0
1190 +#define DEBUG_DESC 0
1191 +#define DEBUG_RX 0
1192 +#define DEBUG_TX 0
1193 +#define DEBUG_PKT_BYTES 0
1194 +#define DEBUG_MDIO 0
1195 +#define DEBUG_CLOSE 0
1196 +
1197 +#define DRV_NAME "ixp4xx_eth"
1198 +
1199 +#define MAX_NPES 3
1200 +
1201 +#define RX_DESCS 64 /* also length of all RX queues */
1202 +#define TX_DESCS 16 /* also length of all TX queues */
1203 +#define TXDONE_QUEUE_LEN 64 /* dwords */
1204 +
1205 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
1206 +#define REGS_SIZE 0x1000
1207 +#define MAX_MRU 1536 /* 0x600 */
1208 +
1209 +#define MDIO_INTERVAL (3 * HZ)
1210 +#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
1211 +#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
1212 +#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
1213 +
1214 +#define NPE_ID(port_id) ((port_id) >> 4)
1215 +#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
1216 +#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
1217 +#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
1218 +#define TXDONE_QUEUE 31
1219 +
1220 +/* TX Control Registers */
1221 +#define TX_CNTRL0_TX_EN 0x01
1222 +#define TX_CNTRL0_HALFDUPLEX 0x02
1223 +#define TX_CNTRL0_RETRY 0x04
1224 +#define TX_CNTRL0_PAD_EN 0x08
1225 +#define TX_CNTRL0_APPEND_FCS 0x10
1226 +#define TX_CNTRL0_2DEFER 0x20
1227 +#define TX_CNTRL0_RMII 0x40 /* reduced MII */
1228 +#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
1229 +
1230 +/* RX Control Registers */
1231 +#define RX_CNTRL0_RX_EN 0x01
1232 +#define RX_CNTRL0_PADSTRIP_EN 0x02
1233 +#define RX_CNTRL0_SEND_FCS 0x04
1234 +#define RX_CNTRL0_PAUSE_EN 0x08
1235 +#define RX_CNTRL0_LOOP_EN 0x10
1236 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
1237 +#define RX_CNTRL0_RX_RUNT_EN 0x40
1238 +#define RX_CNTRL0_BCAST_DIS 0x80
1239 +#define RX_CNTRL1_DEFER_EN 0x01
1240 +
1241 +/* Core Control Register */
1242 +#define CORE_RESET 0x01
1243 +#define CORE_RX_FIFO_FLUSH 0x02
1244 +#define CORE_TX_FIFO_FLUSH 0x04
1245 +#define CORE_SEND_JAM 0x08
1246 +#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
1247 +
1248 +#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
1249 + TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
1250 + TX_CNTRL0_2DEFER)
1251 +#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
1252 +#define DEFAULT_CORE_CNTRL CORE_MDC_EN
1253 +
1254 +
1255 +/* NPE message codes */
1256 +#define NPE_GETSTATUS 0x00
1257 +#define NPE_EDB_SETPORTADDRESS 0x01
1258 +#define NPE_EDB_GETMACADDRESSDATABASE 0x02
1259 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
1260 +#define NPE_GETSTATS 0x04
1261 +#define NPE_RESETSTATS 0x05
1262 +#define NPE_SETMAXFRAMELENGTHS 0x06
1263 +#define NPE_VLAN_SETRXTAGMODE 0x07
1264 +#define NPE_VLAN_SETDEFAULTRXVID 0x08
1265 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
1266 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
1267 +#define NPE_VLAN_SETRXQOSENTRY 0x0B
1268 +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
1269 +#define NPE_STP_SETBLOCKINGSTATE 0x0D
1270 +#define NPE_FW_SETFIREWALLMODE 0x0E
1271 +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
1272 +#define NPE_PC_SETAPMACTABLE 0x11
1273 +#define NPE_SETLOOPBACK_MODE 0x12
1274 +#define NPE_PC_SETBSSIDTABLE 0x13
1275 +#define NPE_ADDRESS_FILTER_CONFIG 0x14
1276 +#define NPE_APPENDFCSCONFIG 0x15
1277 +#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
1278 +#define NPE_MAC_RECOVERY_START 0x17
1279 +
1280 +
1281 +#ifdef __ARMEB__
1282 +typedef struct sk_buff buffer_t;
1283 +#define free_buffer dev_kfree_skb
1284 +#define free_buffer_irq dev_kfree_skb_irq
1285 +#else
1286 +typedef void buffer_t;
1287 +#define free_buffer kfree
1288 +#define free_buffer_irq kfree
1289 +#endif
1290 +
1291 +struct eth_regs {
1292 + u32 tx_control[2], __res1[2]; /* 000 */
1293 + u32 rx_control[2], __res2[2]; /* 010 */
1294 + u32 random_seed, __res3[3]; /* 020 */
1295 + u32 partial_empty_threshold, __res4; /* 030 */
1296 + u32 partial_full_threshold, __res5; /* 038 */
1297 + u32 tx_start_bytes, __res6[3]; /* 040 */
1298 + u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */
1299 + u32 tx_2part_deferral[2], __res8[2]; /* 060 */
1300 + u32 slot_time, __res9[3]; /* 070 */
1301 + u32 mdio_command[4]; /* 080 */
1302 + u32 mdio_status[4]; /* 090 */
1303 + u32 mcast_mask[6], __res10[2]; /* 0A0 */
1304 + u32 mcast_addr[6], __res11[2]; /* 0C0 */
1305 + u32 int_clock_threshold, __res12[3]; /* 0E0 */
1306 + u32 hw_addr[6], __res13[61]; /* 0F0 */
1307 + u32 core_control; /* 1FC */
1308 +};
1309 +
1310 +struct port {
1311 + struct resource *mem_res;
1312 + struct eth_regs __iomem *regs;
1313 + struct npe *npe;
1314 + struct net_device *netdev;
1315 + struct net_device_stats stat;
1316 + struct mii_if_info mii;
1317 + struct delayed_work mdio_thread;
1318 + struct eth_plat_info *plat;
1319 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
1320 + struct desc *desc_tab; /* coherent */
1321 + u32 desc_tab_phys;
1322 + int id; /* logical port ID */
1323 + u16 mii_bmcr;
1324 +};
1325 +
1326 +/* NPE message structure */
1327 +struct msg {
1328 +#ifdef __ARMEB__
1329 + u8 cmd, eth_id, byte2, byte3;
1330 + u8 byte4, byte5, byte6, byte7;
1331 +#else
1332 + u8 byte3, byte2, eth_id, cmd;
1333 + u8 byte7, byte6, byte5, byte4;
1334 +#endif
1335 +};
1336 +
1337 +/* Ethernet packet descriptor */
1338 +struct desc {
1339 + u32 next; /* pointer to next buffer, unused */
1340 +
1341 +#ifdef __ARMEB__
1342 + u16 buf_len; /* buffer length */
1343 + u16 pkt_len; /* packet length */
1344 + u32 data; /* pointer to data buffer in RAM */
1345 + u8 dest_id;
1346 + u8 src_id;
1347 + u16 flags;
1348 + u8 qos;
1349 + u8 padlen;
1350 + u16 vlan_tci;
1351 +#else
1352 + u16 pkt_len; /* packet length */
1353 + u16 buf_len; /* buffer length */
1354 + u32 data; /* pointer to data buffer in RAM */
1355 + u16 flags;
1356 + u8 src_id;
1357 + u8 dest_id;
1358 + u16 vlan_tci;
1359 + u8 padlen;
1360 + u8 qos;
1361 +#endif
1362 +
1363 +#ifdef __ARMEB__
1364 + u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
1365 + u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
1366 + u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
1367 +#else
1368 + u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
1369 + u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
1370 + u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
1371 +#endif
1372 +};
1373 +
1374 +
1375 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
1376 + (n) * sizeof(struct desc))
1377 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
1378 +
1379 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
1380 + ((n) + RX_DESCS) * sizeof(struct desc))
1381 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
1382 +
1383 +#ifndef __ARMEB__
1384 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
1385 +{
1386 + int i;
1387 + for (i = 0; i < cnt; i++)
1388 + dest[i] = swab32(src[i]);
1389 +}
1390 +#endif
1391 +
1392 +static spinlock_t mdio_lock;
1393 +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
1394 +static int ports_open;
1395 +static struct port *npe_port_tab[MAX_NPES];
1396 +static struct dma_pool *dma_pool;
1397 +
1398 +
1399 +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
1400 + int write, u16 cmd)
1401 +{
1402 + int cycles = 0;
1403 +
1404 + if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
1405 + printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
1406 + return 0;
1407 + }
1408 +
1409 + if (write) {
1410 + __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
1411 + __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
1412 + }
1413 + __raw_writel(((phy_id << 5) | location) & 0xFF,
1414 + &mdio_regs->mdio_command[2]);
1415 + __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
1416 + &mdio_regs->mdio_command[3]);
1417 +
1418 + while ((cycles < MAX_MDIO_RETRIES) &&
1419 + (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
1420 + udelay(1);
1421 + cycles++;
1422 + }
1423 +
1424 + if (cycles == MAX_MDIO_RETRIES) {
1425 + printk(KERN_ERR "%s: MII write failed\n", dev->name);
1426 + return 0;
1427 + }
1428 +
1429 +#if DEBUG_MDIO
1430 + printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
1431 + cycles);
1432 +#endif
1433 +
1434 + if (write)
1435 + return 0;
1436 +
1437 + if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
1438 + printk(KERN_ERR "%s: MII read failed\n", dev->name);
1439 + return 0;
1440 + }
1441 +
1442 + return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
1443 + (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
1444 +}
1445 +
1446 +static int mdio_read(struct net_device *dev, int phy_id, int location)
1447 +{
1448 + unsigned long flags;
1449 + u16 val;
1450 +
1451 + spin_lock_irqsave(&mdio_lock, flags);
1452 + val = mdio_cmd(dev, phy_id, location, 0, 0);
1453 + spin_unlock_irqrestore(&mdio_lock, flags);
1454 + return val;
1455 +}
1456 +
1457 +static void mdio_write(struct net_device *dev, int phy_id, int location,
1458 + int val)
1459 +{
1460 + unsigned long flags;
1461 +
1462 + spin_lock_irqsave(&mdio_lock, flags);
1463 + mdio_cmd(dev, phy_id, location, 1, val);
1464 + spin_unlock_irqrestore(&mdio_lock, flags);
1465 +}
1466 +
1467 +static void phy_reset(struct net_device *dev, int phy_id)
1468 +{
1469 + struct port *port = netdev_priv(dev);
1470 + int cycles = 0;
1471 +
1472 + mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
1473 +
1474 + while (cycles < MAX_MII_RESET_RETRIES) {
1475 + if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
1476 +#if DEBUG_MDIO
1477 + printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
1478 + dev->name, cycles);
1479 +#endif
1480 + return;
1481 + }
1482 + udelay(1);
1483 + cycles++;
1484 + }
1485 +
1486 + printk(KERN_ERR "%s: MII reset failed\n", dev->name);
1487 +}
1488 +
1489 +static void eth_set_duplex(struct port *port)
1490 +{
1491 + if (port->mii.full_duplex)
1492 + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
1493 + &port->regs->tx_control[0]);
1494 + else
1495 + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
1496 + &port->regs->tx_control[0]);
1497 +}
1498 +
1499 +
1500 +static void phy_check_media(struct port *port, int init)
1501 +{
1502 + if (mii_check_media(&port->mii, 1, init))
1503 + eth_set_duplex(port);
1504 + if (port->mii.force_media) { /* mii_check_media() doesn't work */
1505 + struct net_device *dev = port->netdev;
1506 + int cur_link = mii_link_ok(&port->mii);
1507 + int prev_link = netif_carrier_ok(dev);
1508 +
1509 + if (!prev_link && cur_link) {
1510 + printk(KERN_INFO "%s: link up\n", dev->name);
1511 + netif_carrier_on(dev);
1512 + } else if (prev_link && !cur_link) {
1513 + printk(KERN_INFO "%s: link down\n", dev->name);
1514 + netif_carrier_off(dev);
1515 + }
1516 + }
1517 +}
1518 +
1519 +
1520 +static void mdio_thread(struct work_struct *work)
1521 +{
1522 + struct port *port = container_of(work, struct port, mdio_thread.work);
1523 +
1524 + phy_check_media(port, 0);
1525 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1526 +}
1527 +
1528 +
1529 +static inline void debug_pkt(struct net_device *dev, const char *func,
1530 + u8 *data, int len)
1531 +{
1532 +#if DEBUG_PKT_BYTES
1533 + int i;
1534 +
1535 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
1536 + for (i = 0; i < len; i++) {
1537 + if (i >= DEBUG_PKT_BYTES)
1538 + break;
1539 + printk("%s%02X",
1540 + ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
1541 + data[i]);
1542 + }
1543 + printk("\n");
1544 +#endif
1545 +}
1546 +
1547 +
1548 +static inline void debug_desc(u32 phys, struct desc *desc)
1549 +{
1550 +#if DEBUG_DESC
1551 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
1552 + " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
1553 + phys, desc->next, desc->buf_len, desc->pkt_len,
1554 + desc->data, desc->dest_id, desc->src_id, desc->flags,
1555 + desc->qos, desc->padlen, desc->vlan_tci,
1556 + desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
1557 + desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
1558 + desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
1559 + desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
1560 +#endif
1561 +}
1562 +
1563 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
1564 +{
1565 +#if DEBUG_QUEUES
1566 + static struct {
1567 + int queue;
1568 + char *name;
1569 + } names[] = {
1570 + { TX_QUEUE(0x10), "TX#0 " },
1571 + { TX_QUEUE(0x20), "TX#1 " },
1572 + { TX_QUEUE(0x00), "TX#2 " },
1573 + { RXFREE_QUEUE(0x10), "RX-free#0 " },
1574 + { RXFREE_QUEUE(0x20), "RX-free#1 " },
1575 + { RXFREE_QUEUE(0x00), "RX-free#2 " },
1576 + { TXDONE_QUEUE, "TX-done " },
1577 + };
1578 + int i;
1579 +
1580 + for (i = 0; i < ARRAY_SIZE(names); i++)
1581 + if (names[i].queue == queue)
1582 + break;
1583 +
1584 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1585 + i < ARRAY_SIZE(names) ? names[i].name : "",
1586 + is_get ? "->" : "<-", phys);
1587 +#endif
1588 +}
1589 +
1590 +static inline u32 queue_get_entry(unsigned int queue)
1591 +{
1592 + u32 phys = qmgr_get_entry(queue);
1593 + debug_queue(queue, 1, phys);
1594 + return phys;
1595 +}
1596 +
1597 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1598 + int is_tx)
1599 +{
1600 + u32 phys, tab_phys, n_desc;
1601 + struct desc *tab;
1602 +
1603 + if (!(phys = queue_get_entry(queue)))
1604 + return -1;
1605 +
1606 + phys &= ~0x1F; /* mask out non-address bits */
1607 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1608 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1609 + n_desc = (phys - tab_phys) / sizeof(struct desc);
1610 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1611 + debug_desc(phys, &tab[n_desc]);
1612 + BUG_ON(tab[n_desc].next);
1613 + return n_desc;
1614 +}
1615 +
1616 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1617 + struct desc *desc)
1618 +{
1619 + debug_queue(queue, 0, phys);
1620 + debug_desc(phys, desc);
1621 + BUG_ON(phys & 0x1F);
1622 + qmgr_put_entry(queue, phys);
1623 + BUG_ON(qmgr_stat_overflow(queue));
1624 +}
1625 +
1626 +
1627 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1628 +{
1629 +#ifdef __ARMEB__
1630 + dma_unmap_single(&port->netdev->dev, desc->data,
1631 + desc->buf_len, DMA_TO_DEVICE);
1632 +#else
1633 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1634 + ALIGN((desc->data & 3) + desc->buf_len, 4),
1635 + DMA_TO_DEVICE);
1636 +#endif
1637 +}
1638 +
1639 +
1640 +static void eth_rx_irq(void *pdev)
1641 +{
1642 + struct net_device *dev = pdev;
1643 + struct port *port = netdev_priv(dev);
1644 +
1645 +#if DEBUG_RX
1646 + printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
1647 +#endif
1648 + qmgr_disable_irq(port->plat->rxq);
1649 + netif_rx_schedule(dev);
1650 +}
1651 +
1652 +static int eth_poll(struct net_device *dev, int *budget)
1653 +{
1654 + struct port *port = netdev_priv(dev);
1655 + unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
1656 + int quota = dev->quota, received = 0;
1657 +
1658 +#if DEBUG_RX
1659 + printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
1660 +#endif
1661 +
1662 + while (quota) {
1663 + struct sk_buff *skb;
1664 + struct desc *desc;
1665 + int n;
1666 +#ifdef __ARMEB__
1667 + struct sk_buff *temp;
1668 + u32 phys;
1669 +#endif
1670 +
1671 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1672 + dev->quota -= received; /* No packet received */
1673 + *budget -= received;
1674 + received = 0;
1675 +#if DEBUG_RX
1676 + printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
1677 + dev->name);
1678 +#endif
1679 + netif_rx_complete(dev);
1680 + qmgr_enable_irq(rxq);
1681 + if (!qmgr_stat_empty(rxq) &&
1682 + netif_rx_reschedule(dev, 0)) {
1683 +#if DEBUG_RX
1684 + printk(KERN_DEBUG "%s: eth_poll"
1685 + " netif_rx_reschedule successed\n",
1686 + dev->name);
1687 +#endif
1688 + qmgr_disable_irq(rxq);
1689 + continue;
1690 + }
1691 +#if DEBUG_RX
1692 + printk(KERN_DEBUG "%s: eth_poll all done\n",
1693 + dev->name);
1694 +#endif
1695 + return 0; /* all work done */
1696 + }
1697 +
1698 + desc = rx_desc_ptr(port, n);
1699 +
1700 +#ifdef __ARMEB__
1701 + if ((skb = netdev_alloc_skb(dev, MAX_MRU)) != NULL) {
1702 + phys = dma_map_single(&dev->dev, skb->data,
1703 + MAX_MRU, DMA_FROM_DEVICE);
1704 + if (dma_mapping_error(phys)) {
1705 + dev_kfree_skb(skb);
1706 + skb = NULL;
1707 + }
1708 + }
1709 +#else
1710 + skb = netdev_alloc_skb(dev, desc->pkt_len);
1711 +#endif
1712 +
1713 + if (!skb) {
1714 + port->stat.rx_dropped++;
1715 + /* put the desc back on RX-ready queue */
1716 + desc->buf_len = MAX_MRU;
1717 + desc->pkt_len = 0;
1718 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1719 + continue;
1720 + }
1721 +
1722 + /* process received frame */
1723 +#ifdef __ARMEB__
1724 + temp = skb;
1725 + skb = port->rx_buff_tab[n];
1726 + dma_unmap_single(&dev->dev, desc->data,
1727 + MAX_MRU, DMA_FROM_DEVICE);
1728 +#else
1729 + dma_sync_single(&dev->dev, desc->data,
1730 + MAX_MRU, DMA_FROM_DEVICE);
1731 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1732 + ALIGN(desc->pkt_len, 4) / 4);
1733 +#endif
1734 + skb_put(skb, desc->pkt_len);
1735 +
1736 + debug_pkt(dev, "eth_poll", skb->data, skb->len);
1737 +
1738 + skb->protocol = eth_type_trans(skb, dev);
1739 + dev->last_rx = jiffies;
1740 + port->stat.rx_packets++;
1741 + port->stat.rx_bytes += skb->len;
1742 + netif_receive_skb(skb);
1743 +
1744 + /* put the new buffer on RX-free queue */
1745 +#ifdef __ARMEB__
1746 + port->rx_buff_tab[n] = temp;
1747 + desc->data = phys;
1748 +#endif
1749 + desc->buf_len = MAX_MRU;
1750 + desc->pkt_len = 0;
1751 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1752 + quota--;
1753 + received++;
1754 + }
1755 + dev->quota -= received;
1756 + *budget -= received;
1757 +#if DEBUG_RX
1758 + printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
1759 +#endif
1760 + return 1; /* not all work done */
1761 +}
1762 +
1763 +
1764 +static void eth_txdone_irq(void *unused)
1765 +{
1766 + u32 phys;
1767 +
1768 +#if DEBUG_TX
1769 + printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
1770 +#endif
1771 + while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
1772 + u32 npe_id, n_desc;
1773 + struct port *port;
1774 + struct desc *desc;
1775 + int start;
1776 +
1777 + npe_id = phys & 3;
1778 + BUG_ON(npe_id >= MAX_NPES);
1779 + port = npe_port_tab[npe_id];
1780 + BUG_ON(!port);
1781 + phys &= ~0x1F; /* mask out non-address bits */
1782 + n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
1783 + BUG_ON(n_desc >= TX_DESCS);
1784 + desc = tx_desc_ptr(port, n_desc);
1785 + debug_desc(phys, desc);
1786 +
1787 + if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
1788 + port->stat.tx_packets++;
1789 + port->stat.tx_bytes += desc->pkt_len;
1790 +
1791 + dma_unmap_tx(port, desc);
1792 +#if DEBUG_TX
1793 + printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
1794 + port->netdev->name, port->tx_buff_tab[n_desc]);
1795 +#endif
1796 + free_buffer_irq(port->tx_buff_tab[n_desc]);
1797 + port->tx_buff_tab[n_desc] = NULL;
1798 + }
1799 +
1800 + start = qmgr_stat_empty(port->plat->txreadyq);
1801 + queue_put_desc(port->plat->txreadyq, phys, desc);
1802 + if (start) {
1803 +#if DEBUG_TX
1804 + printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
1805 + port->netdev->name);
1806 +#endif
1807 + netif_wake_queue(port->netdev);
1808 + }
1809 + }
1810 +}
1811 +
1812 +static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
1813 +{
1814 + struct port *port = netdev_priv(dev);
1815 + unsigned int txreadyq = port->plat->txreadyq;
1816 + int len, offset, bytes, n;
1817 + void *mem;
1818 + u32 phys;
1819 + struct desc *desc;
1820 +
1821 +#if DEBUG_TX
1822 + printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
1823 +#endif
1824 +
1825 + if (unlikely(skb->len > MAX_MRU)) {
1826 + dev_kfree_skb(skb);
1827 + port->stat.tx_errors++;
1828 + return NETDEV_TX_OK;
1829 + }
1830 +
1831 + debug_pkt(dev, "eth_xmit", skb->data, skb->len);
1832 +
1833 + len = skb->len;
1834 +#ifdef __ARMEB__
1835 + offset = 0; /* no need to keep alignment */
1836 + bytes = len;
1837 + mem = skb->data;
1838 +#else
1839 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
1840 + bytes = ALIGN(offset + len, 4);
1841 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
1842 + dev_kfree_skb(skb);
1843 + port->stat.tx_dropped++;
1844 + return NETDEV_TX_OK;
1845 + }
1846 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
1847 + dev_kfree_skb(skb);
1848 +#endif
1849 +
1850 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
1851 + if (dma_mapping_error(phys)) {
1852 +#ifdef __ARMEB__
1853 + dev_kfree_skb(skb);
1854 +#else
1855 + kfree(mem);
1856 +#endif
1857 + port->stat.tx_dropped++;
1858 + return NETDEV_TX_OK;
1859 + }
1860 +
1861 + n = queue_get_desc(txreadyq, port, 1);
1862 + BUG_ON(n < 0);
1863 + desc = tx_desc_ptr(port, n);
1864 +
1865 +#ifdef __ARMEB__
1866 + port->tx_buff_tab[n] = skb;
1867 +#else
1868 + port->tx_buff_tab[n] = mem;
1869 +#endif
1870 + desc->data = phys + offset;
1871 + desc->buf_len = desc->pkt_len = len;
1872 +
1873 + /* NPE firmware pads short frames with zeros internally */
1874 + wmb();
1875 + queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
1876 + dev->trans_start = jiffies;
1877 +
1878 + if (qmgr_stat_empty(txreadyq)) {
1879 +#if DEBUG_TX
1880 + printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
1881 +#endif
1882 + netif_stop_queue(dev);
1883 + /* we could miss TX ready interrupt */
1884 + if (!qmgr_stat_empty(txreadyq)) {
1885 +#if DEBUG_TX
1886 + printk(KERN_DEBUG "%s: eth_xmit ready again\n",
1887 + dev->name);
1888 +#endif
1889 + netif_wake_queue(dev);
1890 + }
1891 + }
1892 +
1893 +#if DEBUG_TX
1894 + printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
1895 +#endif
1896 + return NETDEV_TX_OK;
1897 +}
1898 +
1899 +
1900 +static struct net_device_stats *eth_stats(struct net_device *dev)
1901 +{
1902 + struct port *port = netdev_priv(dev);
1903 + return &port->stat;
1904 +}
1905 +
1906 +static void eth_set_mcast_list(struct net_device *dev)
1907 +{
1908 + struct port *port = netdev_priv(dev);
1909 + struct dev_mc_list *mclist = dev->mc_list;
1910 + u8 diffs[ETH_ALEN], *addr;
1911 + int cnt = dev->mc_count, i;
1912 +
1913 + if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
1914 + __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
1915 + &port->regs->rx_control[0]);
1916 + return;
1917 + }
1918 +
1919 + memset(diffs, 0, ETH_ALEN);
1920 + addr = mclist->dmi_addr; /* first MAC address */
1921 +
1922 + while (--cnt && (mclist = mclist->next))
1923 + for (i = 0; i < ETH_ALEN; i++)
1924 + diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
1925 +
1926 + for (i = 0; i < ETH_ALEN; i++) {
1927 + __raw_writel(addr[i], &port->regs->mcast_addr[i]);
1928 + __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
1929 + }
1930 +
1931 + __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
1932 + &port->regs->rx_control[0]);
1933 +}
1934 +
1935 +
1936 +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1937 +{
1938 + struct port *port = netdev_priv(dev);
1939 + unsigned int duplex_chg;
1940 + int err;
1941 +
1942 + if (!netif_running(dev))
1943 + return -EINVAL;
1944 + err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
1945 + if (duplex_chg)
1946 + eth_set_duplex(port);
1947 + return err;
1948 +}
1949 +
1950 +
1951 +static int request_queues(struct port *port)
1952 +{
1953 + int err;
1954 +
1955 + err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
1956 + if (err)
1957 + return err;
1958 +
1959 + err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
1960 + if (err)
1961 + goto rel_rxfree;
1962 +
1963 + err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
1964 + if (err)
1965 + goto rel_rx;
1966 +
1967 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
1968 + if (err)
1969 + goto rel_tx;
1970 +
1971 + /* TX-done queue handles skbs sent out by the NPEs */
1972 + if (!ports_open) {
1973 + err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
1974 + if (err)
1975 + goto rel_txready;
1976 + }
1977 + return 0;
1978 +
1979 +rel_txready:
1980 + qmgr_release_queue(port->plat->txreadyq);
1981 +rel_tx:
1982 + qmgr_release_queue(TX_QUEUE(port->id));
1983 +rel_rx:
1984 + qmgr_release_queue(port->plat->rxq);
1985 +rel_rxfree:
1986 + qmgr_release_queue(RXFREE_QUEUE(port->id));
1987 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1988 + port->netdev->name);
1989 + return err;
1990 +}
1991 +
1992 +static void release_queues(struct port *port)
1993 +{
1994 + qmgr_release_queue(RXFREE_QUEUE(port->id));
1995 + qmgr_release_queue(port->plat->rxq);
1996 + qmgr_release_queue(TX_QUEUE(port->id));
1997 + qmgr_release_queue(port->plat->txreadyq);
1998 +
1999 + if (!ports_open)
2000 + qmgr_release_queue(TXDONE_QUEUE);
2001 +}
2002 +
2003 +static int init_queues(struct port *port)
2004 +{
2005 + int i;
2006 +
2007 + if (!ports_open)
2008 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
2009 + POOL_ALLOC_SIZE, 32, 0)))
2010 + return -ENOMEM;
2011 +
2012 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
2013 + &port->desc_tab_phys)))
2014 + return -ENOMEM;
2015 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
2016 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
2017 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
2018 +
2019 + /* Setup RX buffers */
2020 + for (i = 0; i < RX_DESCS; i++) {
2021 + struct desc *desc = rx_desc_ptr(port, i);
2022 + buffer_t *buff;
2023 + void *data;
2024 +#ifdef __ARMEB__
2025 + if (!(buff = netdev_alloc_skb(port->netdev, MAX_MRU)))
2026 + return -ENOMEM;
2027 + data = buff->data;
2028 +#else
2029 + if (!(buff = kmalloc(MAX_MRU, GFP_KERNEL)))
2030 + return -ENOMEM;
2031 + data = buff;
2032 +#endif
2033 + desc->buf_len = MAX_MRU;
2034 + desc->data = dma_map_single(&port->netdev->dev, data,
2035 + MAX_MRU, DMA_FROM_DEVICE);
2036 + if (dma_mapping_error(desc->data)) {
2037 + free_buffer(buff);
2038 + return -EIO;
2039 + }
2040 + port->rx_buff_tab[i] = buff;
2041 + }
2042 +
2043 + return 0;
2044 +}
2045 +
2046 +static void destroy_queues(struct port *port)
2047 +{
2048 + int i;
2049 +
2050 + if (port->desc_tab) {
2051 + for (i = 0; i < RX_DESCS; i++) {
2052 + struct desc *desc = rx_desc_ptr(port, i);
2053 + buffer_t *buff = port->rx_buff_tab[i];
2054 + if (buff) {
2055 + dma_unmap_single(&port->netdev->dev,
2056 + desc->data, MAX_MRU,
2057 + DMA_FROM_DEVICE);
2058 + free_buffer(buff);
2059 + }
2060 + }
2061 + for (i = 0; i < TX_DESCS; i++) {
2062 + struct desc *desc = tx_desc_ptr(port, i);
2063 + buffer_t *buff = port->tx_buff_tab[i];
2064 + if (buff) {
2065 + dma_unmap_tx(port, desc);
2066 + free_buffer(buff);
2067 + }
2068 + }
2069 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
2070 + port->desc_tab = NULL;
2071 + }
2072 +
2073 + if (!ports_open && dma_pool) {
2074 + dma_pool_destroy(dma_pool);
2075 + dma_pool = NULL;
2076 + }
2077 +}
2078 +
2079 +static int eth_open(struct net_device *dev)
2080 +{
2081 + struct port *port = netdev_priv(dev);
2082 + struct npe *npe = port->npe;
2083 + struct msg msg;
2084 + int i, err;
2085 +
2086 + if (!npe_running(npe)) {
2087 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
2088 + if (err)
2089 + return err;
2090 +
2091 + if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
2092 + printk(KERN_ERR "%s: %s not responding\n", dev->name,
2093 + npe_name(npe));
2094 + return -EIO;
2095 + }
2096 + }
2097 +
2098 + mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
2099 +
2100 + memset(&msg, 0, sizeof(msg));
2101 + msg.cmd = NPE_VLAN_SETRXQOSENTRY;
2102 + msg.eth_id = port->id;
2103 + msg.byte5 = port->plat->rxq | 0x80;
2104 + msg.byte7 = port->plat->rxq << 4;
2105 + for (i = 0; i < 8; i++) {
2106 + msg.byte3 = i;
2107 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
2108 + return -EIO;
2109 + }
2110 +
2111 + msg.cmd = NPE_EDB_SETPORTADDRESS;
2112 + msg.eth_id = PHYSICAL_ID(port->id);
2113 + msg.byte2 = dev->dev_addr[0];
2114 + msg.byte3 = dev->dev_addr[1];
2115 + msg.byte4 = dev->dev_addr[2];
2116 + msg.byte5 = dev->dev_addr[3];
2117 + msg.byte6 = dev->dev_addr[4];
2118 + msg.byte7 = dev->dev_addr[5];
2119 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
2120 + return -EIO;
2121 +
2122 + memset(&msg, 0, sizeof(msg));
2123 + msg.cmd = NPE_FW_SETFIREWALLMODE;
2124 + msg.eth_id = port->id;
2125 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
2126 + return -EIO;
2127 +
2128 + if ((err = request_queues(port)) != 0)
2129 + return err;
2130 +
2131 + if ((err = init_queues(port)) != 0) {
2132 + destroy_queues(port);
2133 + release_queues(port);
2134 + return err;
2135 + }
2136 +
2137 + for (i = 0; i < ETH_ALEN; i++)
2138 + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
2139 + __raw_writel(0x08, &port->regs->random_seed);
2140 + __raw_writel(0x12, &port->regs->partial_empty_threshold);
2141 + __raw_writel(0x30, &port->regs->partial_full_threshold);
2142 + __raw_writel(0x08, &port->regs->tx_start_bytes);
2143 + __raw_writel(0x15, &port->regs->tx_deferral);
2144 + __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
2145 + __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
2146 + __raw_writel(0x80, &port->regs->slot_time);
2147 + __raw_writel(0x01, &port->regs->int_clock_threshold);
2148 +
2149 + /* Populate queues with buffers, no failure after this point */
2150 + for (i = 0; i < TX_DESCS; i++)
2151 + queue_put_desc(port->plat->txreadyq,
2152 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
2153 +
2154 + for (i = 0; i < RX_DESCS; i++)
2155 + queue_put_desc(RXFREE_QUEUE(port->id),
2156 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
2157 +
2158 + __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
2159 + __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
2160 + __raw_writel(0, &port->regs->rx_control[1]);
2161 + __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
2162 +
2163 + phy_check_media(port, 1);
2164 + eth_set_mcast_list(dev);
2165 + netif_start_queue(dev);
2166 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
2167 +
2168 + qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
2169 + eth_rx_irq, dev);
2170 + if (!ports_open) {
2171 + qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
2172 + eth_txdone_irq, NULL);
2173 + qmgr_enable_irq(TXDONE_QUEUE);
2174 + }
2175 + ports_open++;
2176 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
2177 + return 0;
2178 +}
2179 +
2180 +static int eth_close(struct net_device *dev)
2181 +{
2182 + struct port *port = netdev_priv(dev);
2183 + struct msg msg;
2184 + int buffs = RX_DESCS; /* allocated RX buffers */
2185 + int i;
2186 +
2187 + ports_open--;
2188 + qmgr_disable_irq(port->plat->rxq);
2189 + netif_stop_queue(dev);
2190 +
2191 + while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
2192 + buffs--;
2193 +
2194 + memset(&msg, 0, sizeof(msg));
2195 + msg.cmd = NPE_SETLOOPBACK_MODE;
2196 + msg.eth_id = port->id;
2197 + msg.byte3 = 1;
2198 + if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
2199 + printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
2200 +
2201 + i = 0;
2202 + do { /* drain RX buffers */
2203 + while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
2204 + buffs--;
2205 + if (!buffs)
2206 + break;
2207 + if (qmgr_stat_empty(TX_QUEUE(port->id))) {
2208 + /* we have to inject some packet */
2209 + struct desc *desc;
2210 + u32 phys;
2211 + int n = queue_get_desc(port->plat->txreadyq, port, 1);
2212 + BUG_ON(n < 0);
2213 + desc = tx_desc_ptr(port, n);
2214 + phys = tx_desc_phys(port, n);
2215 + desc->buf_len = desc->pkt_len = 1;
2216 + wmb();
2217 + queue_put_desc(TX_QUEUE(port->id), phys, desc);
2218 + }
2219 + udelay(1);
2220 + } while (++i < MAX_CLOSE_WAIT);
2221 +
2222 + if (buffs)
2223 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
2224 + " left in NPE\n", dev->name, buffs);
2225 +#if DEBUG_CLOSE
2226 + if (!buffs)
2227 + printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
2228 +#endif
2229 +
2230 + buffs = TX_DESCS;
2231 + while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
2232 + buffs--; /* cancel TX */
2233 +
2234 + i = 0;
2235 + do {
2236 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
2237 + buffs--;
2238 + if (!buffs)
2239 + break;
2240 + } while (++i < MAX_CLOSE_WAIT);
2241 +
2242 + if (buffs)
2243 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
2244 + "left in NPE\n", dev->name, buffs);
2245 +#if DEBUG_CLOSE
2246 + if (!buffs)
2247 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
2248 +#endif
2249 +
2250 + msg.byte3 = 0;
2251 + if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
2252 + printk(KERN_CRIT "%s: unable to disable loopback\n",
2253 + dev->name);
2254 +
2255 + port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
2256 + ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
2257 + mdio_write(dev, port->plat->phy, MII_BMCR,
2258 + port->mii_bmcr | BMCR_PDOWN);
2259 +
2260 + if (!ports_open)
2261 + qmgr_disable_irq(TXDONE_QUEUE);
2262 + cancel_rearming_delayed_work(&port->mdio_thread);
2263 + destroy_queues(port);
2264 + release_queues(port);
2265 + return 0;
2266 +}
2267 +
2268 +static int __devinit eth_init_one(struct platform_device *pdev)
2269 +{
2270 + struct port *port;
2271 + struct net_device *dev;
2272 + struct eth_plat_info *plat = pdev->dev.platform_data;
2273 + u32 regs_phys;
2274 + int err;
2275 +
2276 + if (!(dev = alloc_etherdev(sizeof(struct port))))
2277 + return -ENOMEM;
2278 +
2279 + SET_MODULE_OWNER(dev);
2280 + SET_NETDEV_DEV(dev, &pdev->dev);
2281 + port = netdev_priv(dev);
2282 + port->netdev = dev;
2283 + port->id = pdev->id;
2284 +
2285 + switch (port->id) {
2286 + case IXP4XX_ETH_NPEA:
2287 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
2288 + regs_phys = IXP4XX_EthA_BASE_PHYS;
2289 + break;
2290 + case IXP4XX_ETH_NPEB:
2291 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
2292 + regs_phys = IXP4XX_EthB_BASE_PHYS;
2293 + break;
2294 + case IXP4XX_ETH_NPEC:
2295 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
2296 + regs_phys = IXP4XX_EthC_BASE_PHYS;
2297 + break;
2298 + default:
2299 + err = -ENOSYS;
2300 + goto err_free;
2301 + }
2302 +
2303 + dev->open = eth_open;
2304 + dev->hard_start_xmit = eth_xmit;
2305 + dev->poll = eth_poll;
2306 + dev->stop = eth_close;
2307 + dev->get_stats = eth_stats;
2308 + dev->do_ioctl = eth_ioctl;
2309 + dev->set_multicast_list = eth_set_mcast_list;
2310 + dev->weight = 16;
2311 + dev->tx_queue_len = 100;
2312 +
2313 + if (!(port->npe = npe_request(NPE_ID(port->id)))) {
2314 + err = -EIO;
2315 + goto err_free;
2316 + }
2317 +
2318 + if (register_netdev(dev)) {
2319 + err = -EIO;
2320 + goto err_npe_rel;
2321 + }
2322 +
2323 + port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
2324 + if (!port->mem_res) {
2325 + err = -EBUSY;
2326 + goto err_unreg;
2327 + }
2328 +
2329 + port->plat = plat;
2330 + npe_port_tab[NPE_ID(port->id)] = port;
2331 + memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
2332 +
2333 + platform_set_drvdata(pdev, dev);
2334 +
2335 + __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
2336 + &port->regs->core_control);
2337 + udelay(50);
2338 + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
2339 + udelay(50);
2340 +
2341 + port->mii.dev = dev;
2342 + port->mii.mdio_read = mdio_read;
2343 + port->mii.mdio_write = mdio_write;
2344 + port->mii.phy_id = plat->phy;
2345 + port->mii.phy_id_mask = 0x1F;
2346 + port->mii.reg_num_mask = 0x1F;
2347 +
2348 + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
2349 + npe_name(port->npe));
2350 +
2351 + phy_reset(dev, plat->phy);
2352 + port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
2353 + ~(BMCR_RESET | BMCR_PDOWN);
2354 + mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
2355 +
2356 + INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
2357 + return 0;
2358 +
2359 +err_unreg:
2360 + unregister_netdev(dev);
2361 +err_npe_rel:
2362 + npe_release(port->npe);
2363 +err_free:
2364 + free_netdev(dev);
2365 + return err;
2366 +}
2367 +
2368 +static int __devexit eth_remove_one(struct platform_device *pdev)
2369 +{
2370 + struct net_device *dev = platform_get_drvdata(pdev);
2371 + struct port *port = netdev_priv(dev);
2372 +
2373 + unregister_netdev(dev);
2374 + npe_port_tab[NPE_ID(port->id)] = NULL;
2375 + platform_set_drvdata(pdev, NULL);
2376 + npe_release(port->npe);
2377 + release_resource(port->mem_res);
2378 + free_netdev(dev);
2379 + return 0;
2380 +}
2381 +
2382 +static struct platform_driver drv = {
2383 + .driver.name = DRV_NAME,
2384 + .probe = eth_init_one,
2385 + .remove = eth_remove_one,
2386 +};
2387 +
2388 +static int __init eth_init_module(void)
2389 +{
2390 + if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
2391 + return -ENOSYS;
2392 +
2393 + /* All MII PHY accesses use NPE-B Ethernet registers */
2394 + spin_lock_init(&mdio_lock);
2395 + mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
2396 + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
2397 +
2398 + return platform_driver_register(&drv);
2399 +}
2400 +
2401 +static void __exit eth_cleanup_module(void)
2402 +{
2403 + platform_driver_unregister(&drv);
2404 +}
2405 +
2406 +MODULE_AUTHOR("Krzysztof Halasa");
2407 +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
2408 +MODULE_LICENSE("GPL v2");
2409 +module_init(eth_init_module);
2410 +module_exit(eth_cleanup_module);
2411 Index: linux-2.6.23.17/drivers/net/wan/Kconfig
2412 ===================================================================
2413 --- linux-2.6.23.17.orig/drivers/net/wan/Kconfig
2414 +++ linux-2.6.23.17/drivers/net/wan/Kconfig
2415 @@ -334,6 +334,15 @@ config DSCC4_PCI_RST
2416
2417 Say Y if your card supports this feature.
2418
2419 +config IXP4XX_HSS
2420 + tristate "IXP4xx HSS (synchronous serial port) support"
2421 + depends on HDLC && ARM && ARCH_IXP4XX
2422 + select IXP4XX_NPE
2423 + select IXP4XX_QMGR
2424 + help
2425 + Say Y here if you want to use built-in HSS ports
2426 + on IXP4xx processor.
2427 +
2428 config DLCI
2429 tristate "Frame Relay DLCI support"
2430 ---help---
2431 Index: linux-2.6.23.17/drivers/net/wan/Makefile
2432 ===================================================================
2433 --- linux-2.6.23.17.orig/drivers/net/wan/Makefile
2434 +++ linux-2.6.23.17/drivers/net/wan/Makefile
2435 @@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o
2436 obj-$(CONFIG_WANXL) += wanxl.o
2437 obj-$(CONFIG_PCI200SYN) += pci200syn.o
2438 obj-$(CONFIG_PC300TOO) += pc300too.o
2439 +obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
2440
2441 clean-files := wanxlfw.inc
2442 $(obj)/wanxl.o: $(obj)/wanxlfw.inc
2443 Index: linux-2.6.23.17/drivers/net/wan/ixp4xx_hss.c
2444 ===================================================================
2445 --- /dev/null
2446 +++ linux-2.6.23.17/drivers/net/wan/ixp4xx_hss.c
2447 @@ -0,0 +1,1270 @@
2448 +/*
2449 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
2450 + *
2451 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
2452 + *
2453 + * This program is free software; you can redistribute it and/or modify it
2454 + * under the terms of version 2 of the GNU General Public License
2455 + * as published by the Free Software Foundation.
2456 + */
2457 +
2458 +#include <linux/dma-mapping.h>
2459 +#include <linux/dmapool.h>
2460 +#include <linux/io.h>
2461 +#include <linux/kernel.h>
2462 +#include <linux/hdlc.h>
2463 +#include <linux/platform_device.h>
2464 +#include <asm/arch/npe.h>
2465 +#include <asm/arch/qmgr.h>
2466 +
2467 +#define DEBUG_QUEUES 0
2468 +#define DEBUG_DESC 0
2469 +#define DEBUG_RX 0
2470 +#define DEBUG_TX 0
2471 +#define DEBUG_PKT_BYTES 0
2472 +#define DEBUG_CLOSE 0
2473 +
2474 +#define DRV_NAME "ixp4xx_hss"
2475 +
2476 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
2477 +#define FRAME_SYNC_OFFSET 0 /* unused, channelized only */
2478 +#define FRAME_SYNC_SIZE 1024
2479 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
2480 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
2481 +
2482 +#define RX_DESCS 16 /* also length of all RX queues */
2483 +#define TX_DESCS 16 /* also length of all TX queues */
2484 +
2485 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
2486 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
2487 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
2488 +
2489 +/* Queue IDs */
2490 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
2491 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
2492 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
2493 +#define HSS0_PKT_TX1_QUEUE 15
2494 +#define HSS0_PKT_TX2_QUEUE 16
2495 +#define HSS0_PKT_TX3_QUEUE 17
2496 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
2497 +#define HSS0_PKT_RXFREE1_QUEUE 19
2498 +#define HSS0_PKT_RXFREE2_QUEUE 20
2499 +#define HSS0_PKT_RXFREE3_QUEUE 21
2500 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
2501 +
2502 +#define HSS1_CHL_RXTRIG_QUEUE 10
2503 +#define HSS1_PKT_RX_QUEUE 0
2504 +#define HSS1_PKT_TX0_QUEUE 5
2505 +#define HSS1_PKT_TX1_QUEUE 6
2506 +#define HSS1_PKT_TX2_QUEUE 7
2507 +#define HSS1_PKT_TX3_QUEUE 8
2508 +#define HSS1_PKT_RXFREE0_QUEUE 1
2509 +#define HSS1_PKT_RXFREE1_QUEUE 2
2510 +#define HSS1_PKT_RXFREE2_QUEUE 3
2511 +#define HSS1_PKT_RXFREE3_QUEUE 4
2512 +#define HSS1_PKT_TXDONE_QUEUE 9
2513 +
2514 +#define NPE_PKT_MODE_HDLC 0
2515 +#define NPE_PKT_MODE_RAW 1
2516 +#define NPE_PKT_MODE_56KMODE 2
2517 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
2518 +
2519 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
2520 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
2521 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
2522 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
2523 +
2524 +
2525 +/* hss_config, PCRs */
2526 +/* Frame sync sampling, default = active low */
2527 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
2528 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
2529 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
2530 +
2531 +/* Frame sync pin: input (default) or output generated off a given clk edge */
2532 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
2533 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
2534 +
2535 +/* Frame and data clock sampling on edge, default = falling */
2536 +#define PCR_FCLK_EDGE_RISING 0x08000000
2537 +#define PCR_DCLK_EDGE_RISING 0x04000000
2538 +
2539 +/* Clock direction, default = input */
2540 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
2541 +
2542 +/* Generate/Receive frame pulses, default = enabled */
2543 +#define PCR_FRM_PULSE_DISABLED 0x01000000
2544 +
2545 + /* Data rate is full (default) or half the configured clk speed */
2546 +#define PCR_HALF_CLK_RATE 0x00200000
2547 +
2548 +/* Invert data between NPE and HSS FIFOs? (default = no) */
2549 +#define PCR_DATA_POLARITY_INVERT 0x00100000
2550 +
2551 +/* TX/RX endianness, default = LSB */
2552 +#define PCR_MSB_ENDIAN 0x00080000
2553 +
2554 +/* Normal (default) / open drain mode (TX only) */
2555 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
2556 +
2557 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
2558 +#define PCR_SOF_NO_FBIT 0x00020000
2559 +
2560 +/* Drive data pins? */
2561 +#define PCR_TX_DATA_ENABLE 0x00010000
2562 +
2563 +/* Voice 56k type: drive the data pins low (default), high, high Z */
2564 +#define PCR_TX_V56K_HIGH 0x00002000
2565 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
2566 +
2567 +/* Unassigned type: drive the data pins low (default), high, high Z */
2568 +#define PCR_TX_UNASS_HIGH 0x00000800
2569 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
2570 +
2571 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
2572 +#define PCR_TX_FB_HIGH_IMP 0x00000400
2573 +
2574 +/* 56k data endiannes - which bit unused: high (default) or low */
2575 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
2576 +
2577 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
2578 +#define PCR_TX_56KS_56K_DATA 0x00000100
2579 +
2580 +/* hss_config, cCR */
2581 +/* Number of packetized clients, default = 1 */
2582 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
2583 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
2584 +
2585 +/* default = no loopback */
2586 +#define CCR_LOOPBACK 0x02000000
2587 +
2588 +/* HSS number, default = 0 (first) */
2589 +#define CCR_SECOND_HSS 0x01000000
2590 +
2591 +
2592 +/* hss_config, clkCR: main:10, num:10, denom:12 */
2593 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
2594 +
2595 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
2596 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
2597 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
2598 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
2599 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
2600 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
2601 +
2602 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
2603 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
2604 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
2605 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
2606 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
2607 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
2608 +
2609 +
2610 +/* hss_config, LUT entries */
2611 +#define TDMMAP_UNASSIGNED 0
2612 +#define TDMMAP_HDLC 1 /* HDLC - packetized */
2613 +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
2614 +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
2615 +
2616 +#define TIMESLOTS 128
2617 +#define LUT_BITS 2
2618 +
2619 +/* offsets into HSS config */
2620 +#define HSS_CONFIG_TX_PCR 0x00
2621 +#define HSS_CONFIG_RX_PCR 0x04
2622 +#define HSS_CONFIG_CORE_CR 0x08
2623 +#define HSS_CONFIG_CLOCK_CR 0x0C
2624 +#define HSS_CONFIG_TX_FCR 0x10
2625 +#define HSS_CONFIG_RX_FCR 0x14
2626 +#define HSS_CONFIG_TX_LUT 0x18
2627 +#define HSS_CONFIG_RX_LUT 0x38
2628 +
2629 +
2630 +/* NPE command codes */
2631 +/* writes the ConfigWord value to the location specified by offset */
2632 +#define PORT_CONFIG_WRITE 0x40
2633 +
2634 +/* triggers the NPE to load the contents of the configuration table */
2635 +#define PORT_CONFIG_LOAD 0x41
2636 +
2637 +/* triggers the NPE to return an HssErrorReadResponse message */
2638 +#define PORT_ERROR_READ 0x42
2639 +
2640 +/* reset NPE internal status and enable the HssChannelized operation */
2641 +#define CHAN_FLOW_ENABLE 0x43
2642 +#define CHAN_FLOW_DISABLE 0x44
2643 +#define CHAN_IDLE_PATTERN_WRITE 0x45
2644 +#define CHAN_NUM_CHANS_WRITE 0x46
2645 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
2646 +#define CHAN_RX_BUF_CFG_WRITE 0x48
2647 +#define CHAN_TX_BLK_CFG_WRITE 0x49
2648 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
2649 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
2650 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
2651 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
2652 +
2653 +/* downloads the gainWord value for a timeslot switching channel associated
2654 + with bypassNum */
2655 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
2656 +
2657 +/* triggers the NPE to reset internal status and enable the HssPacketized
2658 + operation for the flow specified by pPipe */
2659 +#define PKT_PIPE_FLOW_ENABLE 0x50
2660 +#define PKT_PIPE_FLOW_DISABLE 0x51
2661 +#define PKT_NUM_PIPES_WRITE 0x52
2662 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
2663 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
2664 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
2665 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
2666 +#define PKT_PIPE_MODE_WRITE 0x57
2667 +
2668 +/* HDLC packet status values - desc->status */
2669 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
2670 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
2671 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
2672 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
2673 + this packet (if buf_len < pkt_len) */
2674 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
2675 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
2676 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
2677 +
2678 +
2679 +#ifdef __ARMEB__
2680 +typedef struct sk_buff buffer_t;
2681 +#define free_buffer dev_kfree_skb
2682 +#define free_buffer_irq dev_kfree_skb_irq
2683 +#else
2684 +typedef void buffer_t;
2685 +#define free_buffer kfree
2686 +#define free_buffer_irq kfree
2687 +#endif
2688 +
2689 +struct port {
2690 + struct npe *npe;
2691 + struct net_device *netdev;
2692 + struct hss_plat_info *plat;
2693 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
2694 + struct desc *desc_tab; /* coherent */
2695 + u32 desc_tab_phys;
2696 + int id;
2697 + unsigned int clock_type, clock_rate, loopback;
2698 + u8 hdlc_cfg;
2699 +};
2700 +
2701 +/* NPE message structure */
2702 +struct msg {
2703 +#ifdef __ARMEB__
2704 + u8 cmd, unused, hss_port, index;
2705 + union {
2706 + struct { u8 data8a, data8b, data8c, data8d; };
2707 + struct { u16 data16a, data16b; };
2708 + struct { u32 data32; };
2709 + };
2710 +#else
2711 + u8 index, hss_port, unused, cmd;
2712 + union {
2713 + struct { u8 data8d, data8c, data8b, data8a; };
2714 + struct { u16 data16b, data16a; };
2715 + struct { u32 data32; };
2716 + };
2717 +#endif
2718 +};
2719 +
2720 +/* HDLC packet descriptor */
2721 +struct desc {
2722 + u32 next; /* pointer to next buffer, unused */
2723 +
2724 +#ifdef __ARMEB__
2725 + u16 buf_len; /* buffer length */
2726 + u16 pkt_len; /* packet length */
2727 + u32 data; /* pointer to data buffer in RAM */
2728 + u8 status;
2729 + u8 error_count;
2730 + u16 __reserved;
2731 +#else
2732 + u16 pkt_len; /* packet length */
2733 + u16 buf_len; /* buffer length */
2734 + u32 data; /* pointer to data buffer in RAM */
2735 + u16 __reserved;
2736 + u8 error_count;
2737 + u8 status;
2738 +#endif
2739 + u32 __reserved1[4];
2740 +};
2741 +
2742 +
2743 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
2744 + (n) * sizeof(struct desc))
2745 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
2746 +
2747 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
2748 + ((n) + RX_DESCS) * sizeof(struct desc))
2749 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
2750 +
2751 +/*****************************************************************************
2752 + * global variables
2753 + ****************************************************************************/
2754 +
2755 +static int ports_open;
2756 +static struct dma_pool *dma_pool;
2757 +
2758 +static const struct {
2759 + int tx, txdone, rx, rxfree;
2760 +}queue_ids[2] = {{ HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE,
2761 + HSS0_PKT_RX_QUEUE, HSS0_PKT_RXFREE0_QUEUE },
2762 + { HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE,
2763 + HSS1_PKT_RX_QUEUE, HSS1_PKT_RXFREE0_QUEUE },
2764 +};
2765 +
2766 +/*****************************************************************************
2767 + * utility functions
2768 + ****************************************************************************/
2769 +
2770 +static inline struct port* dev_to_port(struct net_device *dev)
2771 +{
2772 + return dev_to_hdlc(dev)->priv;
2773 +}
2774 +
2775 +#ifndef __ARMEB__
2776 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
2777 +{
2778 + int i;
2779 + for (i = 0; i < cnt; i++)
2780 + dest[i] = swab32(src[i]);
2781 +}
2782 +#endif
2783 +
2784 +static inline void debug_pkt(struct net_device *dev, const char *func,
2785 + u8 *data, int len)
2786 +{
2787 +#if DEBUG_PKT_BYTES
2788 + int i;
2789 +
2790 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
2791 + for (i = 0; i < len; i++) {
2792 + if (i >= DEBUG_PKT_BYTES)
2793 + break;
2794 + printk("%s%02X", !(i % 4) ? " " : "", data[i]);
2795 + }
2796 + printk("\n");
2797 +#endif
2798 +}
2799 +
2800 +
2801 +static inline void debug_desc(u32 phys, struct desc *desc)
2802 +{
2803 +#if DEBUG_DESC
2804 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
2805 + phys, desc->next, desc->buf_len, desc->pkt_len,
2806 + desc->data, desc->status, desc->error_count);
2807 +#endif
2808 +}
2809 +
2810 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
2811 +{
2812 +#if DEBUG_QUEUES
2813 + static struct {
2814 + int queue;
2815 + char *name;
2816 + } names[] = {
2817 + { HSS0_PKT_TX0_QUEUE, "TX#0 " },
2818 + { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
2819 + { HSS0_PKT_RX_QUEUE, "RX#0 " },
2820 + { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
2821 + { HSS1_PKT_TX0_QUEUE, "TX#1 " },
2822 + { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
2823 + { HSS1_PKT_RX_QUEUE, "RX#1 " },
2824 + { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
2825 + };
2826 + int i;
2827 +
2828 + for (i = 0; i < ARRAY_SIZE(names); i++)
2829 + if (names[i].queue == queue)
2830 + break;
2831 +
2832 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
2833 + i < ARRAY_SIZE(names) ? names[i].name : "",
2834 + is_get ? "->" : "<-", phys);
2835 +#endif
2836 +}
2837 +
2838 +static inline u32 queue_get_entry(unsigned int queue)
2839 +{
2840 + u32 phys = qmgr_get_entry(queue);
2841 + debug_queue(queue, 1, phys);
2842 + return phys;
2843 +}
2844 +
2845 +static inline int queue_get_desc(unsigned int queue, struct port *port,
2846 + int is_tx)
2847 +{
2848 + u32 phys, tab_phys, n_desc;
2849 + struct desc *tab;
2850 +
2851 + if (!(phys = queue_get_entry(queue)))
2852 + return -1;
2853 +
2854 + BUG_ON(phys & 0x1F);
2855 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
2856 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
2857 + n_desc = (phys - tab_phys) / sizeof(struct desc);
2858 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
2859 + debug_desc(phys, &tab[n_desc]);
2860 + BUG_ON(tab[n_desc].next);
2861 + return n_desc;
2862 +}
2863 +
2864 +static inline void queue_put_desc(unsigned int queue, u32 phys,
2865 + struct desc *desc)
2866 +{
2867 + debug_queue(queue, 0, phys);
2868 + debug_desc(phys, desc);
2869 + BUG_ON(phys & 0x1F);
2870 + qmgr_put_entry(queue, phys);
2871 + BUG_ON(qmgr_stat_overflow(queue));
2872 +}
2873 +
2874 +
2875 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
2876 +{
2877 +#ifdef __ARMEB__
2878 + dma_unmap_single(&port->netdev->dev, desc->data,
2879 + desc->buf_len, DMA_TO_DEVICE);
2880 +#else
2881 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
2882 + ALIGN((desc->data & 3) + desc->buf_len, 4),
2883 + DMA_TO_DEVICE);
2884 +#endif
2885 +}
2886 +
2887 +
2888 +static void hss_hdlc_set_carrier(void *pdev, int carrier)
2889 +{
2890 + struct net_device *dev = pdev;
2891 + if (carrier)
2892 + netif_carrier_on(dev);
2893 + else
2894 + netif_carrier_off(dev);
2895 +}
2896 +
2897 +static void hss_hdlc_rx_irq(void *pdev)
2898 +{
2899 + struct net_device *dev = pdev;
2900 + struct port *port = dev_to_port(dev);
2901 +
2902 +#if DEBUG_RX
2903 + printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
2904 +#endif
2905 + qmgr_disable_irq(queue_ids[port->id].rx);
2906 + netif_rx_schedule(dev);
2907 +}
2908 +
2909 +static int hss_hdlc_poll(struct net_device *dev, int *budget)
2910 +{
2911 + struct port *port = dev_to_port(dev);
2912 + unsigned int rxq = queue_ids[port->id].rx;
2913 + unsigned int rxfreeq = queue_ids[port->id].rxfree;
2914 + struct net_device_stats *stats = hdlc_stats(dev);
2915 + int quota = dev->quota, received = 0;
2916 +
2917 +#if DEBUG_RX
2918 + printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
2919 +#endif
2920 +
2921 + while (quota) {
2922 + struct sk_buff *skb;
2923 + struct desc *desc;
2924 + int n;
2925 +#ifdef __ARMEB__
2926 + struct sk_buff *temp;
2927 + u32 phys;
2928 +#endif
2929 +
2930 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
2931 + dev->quota -= received; /* No packet received */
2932 + *budget -= received;
2933 + received = 0;
2934 +#if DEBUG_RX
2935 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
2936 + " netif_rx_complete\n", dev->name);
2937 +#endif
2938 + netif_rx_complete(dev);
2939 + qmgr_enable_irq(rxq);
2940 + if (!qmgr_stat_empty(rxq) &&
2941 + netif_rx_reschedule(dev, 0)) {
2942 +#if DEBUG_RX
2943 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
2944 + " netif_rx_reschedule successed\n",
2945 + dev->name);
2946 +#endif
2947 + qmgr_disable_irq(rxq);
2948 + continue;
2949 + }
2950 +#if DEBUG_RX
2951 + printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
2952 + dev->name);
2953 +#endif
2954 + return 0; /* all work done */
2955 + }
2956 +
2957 + desc = rx_desc_ptr(port, n);
2958 +
2959 + if (desc->error_count) /* FIXME - remove printk */
2960 + printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
2961 + " errors %u\n", dev->name, desc->status,
2962 + desc->error_count);
2963 +
2964 + skb = NULL;
2965 + switch (desc->status) {
2966 + case 0:
2967 +#ifdef __ARMEB__
2968 + if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
2969 + phys = dma_map_single(&dev->dev, skb->data,
2970 + RX_SIZE,
2971 + DMA_FROM_DEVICE);
2972 + if (dma_mapping_error(phys)) {
2973 + dev_kfree_skb(skb);
2974 + skb = NULL;
2975 + }
2976 + }
2977 +#else
2978 + skb = netdev_alloc_skb(dev, desc->pkt_len);
2979 +#endif
2980 + if (!skb)
2981 + stats->rx_dropped++;
2982 + break;
2983 + case ERR_HDLC_ALIGN:
2984 + case ERR_HDLC_ABORT:
2985 + stats->rx_frame_errors++;
2986 + stats->rx_errors++;
2987 + break;
2988 + case ERR_HDLC_FCS:
2989 + stats->rx_crc_errors++;
2990 + stats->rx_errors++;
2991 + break;
2992 + case ERR_HDLC_TOO_LONG:
2993 + stats->rx_length_errors++;
2994 + stats->rx_errors++;
2995 + break;
2996 + default: /* FIXME - remove printk */
2997 + printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
2998 + " errors %u\n", dev->name, desc->status,
2999 + desc->error_count);
3000 + stats->rx_errors++;
3001 + }
3002 +
3003 + if (!skb) {
3004 + /* put the desc back on RX-ready queue */
3005 + desc->buf_len = RX_SIZE;
3006 + desc->pkt_len = desc->status = 0;
3007 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
3008 + continue;
3009 + }
3010 +
3011 + /* process received frame */
3012 +#ifdef __ARMEB__
3013 + temp = skb;
3014 + skb = port->rx_buff_tab[n];
3015 + dma_unmap_single(&dev->dev, desc->data,
3016 + RX_SIZE, DMA_FROM_DEVICE);
3017 +#else
3018 + dma_sync_single(&dev->dev, desc->data,
3019 + RX_SIZE, DMA_FROM_DEVICE);
3020 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
3021 + ALIGN(desc->pkt_len, 4) / 4);
3022 +#endif
3023 + skb_put(skb, desc->pkt_len);
3024 +
3025 + debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
3026 +
3027 + skb->protocol = hdlc_type_trans(skb, dev);
3028 + dev->last_rx = jiffies;
3029 + stats->rx_packets++;
3030 + stats->rx_bytes += skb->len;
3031 + netif_receive_skb(skb);
3032 +
3033 + /* put the new buffer on RX-free queue */
3034 +#ifdef __ARMEB__
3035 + port->rx_buff_tab[n] = temp;
3036 + desc->data = phys;
3037 +#endif
3038 + desc->buf_len = RX_SIZE;
3039 + desc->pkt_len = 0;
3040 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
3041 + quota--;
3042 + received++;
3043 + }
3044 + dev->quota -= received;
3045 + *budget -= received;
3046 +#if DEBUG_RX
3047 + printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
3048 +#endif
3049 + return 1; /* not all work done */
3050 +}
3051 +
3052 +
3053 +static void hss_hdlc_txdone_irq(void *pdev)
3054 +{
3055 + struct net_device *dev = pdev;
3056 + struct port *port = dev_to_port(dev);
3057 + struct net_device_stats *stats = hdlc_stats(dev);
3058 + int n_desc;
3059 +
3060 +#if DEBUG_TX
3061 + printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
3062 +#endif
3063 + while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
3064 + port, 1)) >= 0) {
3065 + struct desc *desc;
3066 + int start;
3067 +
3068 + desc = tx_desc_ptr(port, n_desc);
3069 +
3070 + stats->tx_packets++;
3071 + stats->tx_bytes += desc->pkt_len;
3072 +
3073 + dma_unmap_tx(port, desc);
3074 +#if DEBUG_TX
3075 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
3076 + port->netdev->name, port->tx_buff_tab[n_desc]);
3077 +#endif
3078 + free_buffer_irq(port->tx_buff_tab[n_desc]);
3079 + port->tx_buff_tab[n_desc] = NULL;
3080 +
3081 + start = qmgr_stat_empty(port->plat->txreadyq);
3082 + queue_put_desc(port->plat->txreadyq,
3083 + tx_desc_phys(port, n_desc), desc);
3084 + if (start) {
3085 +#if DEBUG_TX
3086 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
3087 + " ready\n", port->netdev->name);
3088 +#endif
3089 + netif_wake_queue(port->netdev);
3090 + }
3091 + }
3092 +}
3093 +
3094 +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
3095 +{
3096 + struct port *port = dev_to_port(dev);
3097 + struct net_device_stats *stats = hdlc_stats(dev);
3098 + unsigned int txreadyq = port->plat->txreadyq;
3099 + int len, offset, bytes, n;
3100 + void *mem;
3101 + u32 phys;
3102 + struct desc *desc;
3103 +
3104 +#if DEBUG_TX
3105 + printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
3106 +#endif
3107 +
3108 + if (unlikely(skb->len > HDLC_MAX_MRU)) {
3109 + dev_kfree_skb(skb);
3110 + stats->tx_errors++;
3111 + return NETDEV_TX_OK;
3112 + }
3113 +
3114 + debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
3115 +
3116 + len = skb->len;
3117 +#ifdef __ARMEB__
3118 + offset = 0; /* no need to keep alignment */
3119 + bytes = len;
3120 + mem = skb->data;
3121 +#else
3122 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
3123 + bytes = ALIGN(offset + len, 4);
3124 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
3125 + dev_kfree_skb(skb);
3126 + stats->tx_dropped++;
3127 + return NETDEV_TX_OK;
3128 + }
3129 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
3130 + dev_kfree_skb(skb);
3131 +#endif
3132 +
3133 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
3134 + if (dma_mapping_error(phys)) {
3135 +#ifdef __ARMEB__
3136 + dev_kfree_skb(skb);
3137 +#else
3138 + kfree(mem);
3139 +#endif
3140 + stats->tx_dropped++;
3141 + return NETDEV_TX_OK;
3142 + }
3143 +
3144 + n = queue_get_desc(txreadyq, port, 1);
3145 + BUG_ON(n < 0);
3146 + desc = tx_desc_ptr(port, n);
3147 +
3148 +#ifdef __ARMEB__
3149 + port->tx_buff_tab[n] = skb;
3150 +#else
3151 + port->tx_buff_tab[n] = mem;
3152 +#endif
3153 + desc->data = phys + offset;
3154 + desc->buf_len = desc->pkt_len = len;
3155 +
3156 + wmb();
3157 + queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
3158 + dev->trans_start = jiffies;
3159 +
3160 + if (qmgr_stat_empty(txreadyq)) {
3161 +#if DEBUG_TX
3162 + printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
3163 +#endif
3164 + netif_stop_queue(dev);
3165 + /* we could miss TX ready interrupt */
3166 + if (!qmgr_stat_empty(txreadyq)) {
3167 +#if DEBUG_TX
3168 + printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
3169 + dev->name);
3170 +#endif
3171 + netif_wake_queue(dev);
3172 + }
3173 + }
3174 +
3175 +#if DEBUG_TX
3176 + printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
3177 +#endif
3178 + return NETDEV_TX_OK;
3179 +}
3180 +
3181 +
3182 +static int request_hdlc_queues(struct port *port)
3183 +{
3184 + int err;
3185 +
3186 + err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
3187 + if (err)
3188 + return err;
3189 +
3190 + err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
3191 + if (err)
3192 + goto rel_rxfree;
3193 +
3194 + err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
3195 + if (err)
3196 + goto rel_rx;
3197 +
3198 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
3199 + if (err)
3200 + goto rel_tx;
3201 +
3202 + err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
3203 + if (err)
3204 + goto rel_txready;
3205 + return 0;
3206 +
3207 +rel_txready:
3208 + qmgr_release_queue(port->plat->txreadyq);
3209 +rel_tx:
3210 + qmgr_release_queue(queue_ids[port->id].tx);
3211 +rel_rx:
3212 + qmgr_release_queue(queue_ids[port->id].rx);
3213 +rel_rxfree:
3214 + qmgr_release_queue(queue_ids[port->id].rxfree);
3215 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
3216 + port->netdev->name);
3217 + return err;
3218 +}
3219 +
3220 +static void release_hdlc_queues(struct port *port)
3221 +{
3222 + qmgr_release_queue(queue_ids[port->id].rxfree);
3223 + qmgr_release_queue(queue_ids[port->id].rx);
3224 + qmgr_release_queue(queue_ids[port->id].txdone);
3225 + qmgr_release_queue(queue_ids[port->id].tx);
3226 + qmgr_release_queue(port->plat->txreadyq);
3227 +}
3228 +
3229 +static int init_hdlc_queues(struct port *port)
3230 +{
3231 + int i;
3232 +
3233 + if (!ports_open)
3234 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
3235 + POOL_ALLOC_SIZE, 32, 0)))
3236 + return -ENOMEM;
3237 +
3238 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
3239 + &port->desc_tab_phys)))
3240 + return -ENOMEM;
3241 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
3242 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
3243 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
3244 +
3245 + /* Setup RX buffers */
3246 + for (i = 0; i < RX_DESCS; i++) {
3247 + struct desc *desc = rx_desc_ptr(port, i);
3248 + buffer_t *buff;
3249 + void *data;
3250 +#ifdef __ARMEB__
3251 + if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
3252 + return -ENOMEM;
3253 + data = buff->data;
3254 +#else
3255 + if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
3256 + return -ENOMEM;
3257 + data = buff;
3258 +#endif
3259 + desc->buf_len = RX_SIZE;
3260 + desc->data = dma_map_single(&port->netdev->dev, data,
3261 + RX_SIZE, DMA_FROM_DEVICE);
3262 + if (dma_mapping_error(desc->data)) {
3263 + free_buffer(buff);
3264 + return -EIO;
3265 + }
3266 + port->rx_buff_tab[i] = buff;
3267 + }
3268 +
3269 + return 0;
3270 +}
3271 +
3272 +static void destroy_hdlc_queues(struct port *port)
3273 +{
3274 + int i;
3275 +
3276 + if (port->desc_tab) {
3277 + for (i = 0; i < RX_DESCS; i++) {
3278 + struct desc *desc = rx_desc_ptr(port, i);
3279 + buffer_t *buff = port->rx_buff_tab[i];
3280 + if (buff) {
3281 + dma_unmap_single(&port->netdev->dev,
3282 + desc->data, RX_SIZE,
3283 + DMA_FROM_DEVICE);
3284 + free_buffer(buff);
3285 + }
3286 + }
3287 + for (i = 0; i < TX_DESCS; i++) {
3288 + struct desc *desc = tx_desc_ptr(port, i);
3289 + buffer_t *buff = port->tx_buff_tab[i];
3290 + if (buff) {
3291 + dma_unmap_tx(port, desc);
3292 + free_buffer(buff);
3293 + }
3294 + }
3295 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
3296 + port->desc_tab = NULL;
3297 + }
3298 +
3299 + if (!ports_open && dma_pool) {
3300 + dma_pool_destroy(dma_pool);
3301 + dma_pool = NULL;
3302 + }
3303 +}
3304 +
3305 +static int hss_hdlc_open(struct net_device *dev)
3306 +{
3307 + struct port *port = dev_to_port(dev);
3308 + struct npe *npe = port->npe;
3309 + struct msg msg;
3310 + int i, err;
3311 +
3312 + if (!npe_running(npe)) {
3313 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
3314 + if (err)
3315 + return err;
3316 + }
3317 +
3318 + if ((err = hdlc_open(dev)) != 0)
3319 + return err;
3320 +
3321 + if (port->plat->open)
3322 + if ((err = port->plat->open(port->id, port->netdev,
3323 + hss_hdlc_set_carrier)) != 0)
3324 + goto err_hdlc_close;
3325 +
3326 + /* HSS main configuration */
3327 + memset(&msg, 0, sizeof(msg));
3328 + msg.cmd = PORT_CONFIG_WRITE;
3329 + msg.hss_port = port->id;
3330 + msg.index = 0; /* offset in HSS config */
3331 +
3332 + msg.data32 = PCR_FRM_PULSE_DISABLED |
3333 + PCR_SOF_NO_FBIT |
3334 + PCR_MSB_ENDIAN |
3335 + PCR_TX_DATA_ENABLE;
3336 +
3337 + if (port->clock_type == CLOCK_INT)
3338 + msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
3339 +
3340 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_PCR") != 0))
3341 + goto err_plat_close; /* 0: TX PCR */
3342 +
3343 + msg.index = 4;
3344 + msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
3345 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_PCR") != 0))
3346 + goto err_plat_close; /* 4: RX PCR */
3347 +
3348 + msg.index = 8;
3349 + msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
3350 + (port->id ? CCR_SECOND_HSS : 0);
3351 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CORE_CR") != 0))
3352 + goto err_plat_close; /* 8: Core CR */
3353 +
3354 + msg.index = 12;
3355 + msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
3356 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CLK_CR") != 0))
3357 + goto err_plat_close; /* 12: CLK CR */
3358 +
3359 + msg.data32 = (FRAME_SYNC_OFFSET << 16) | (FRAME_SYNC_SIZE - 1);
3360 + msg.index = 16;
3361 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_FCR") != 0))
3362 + goto err_plat_close; /* 16: TX FCR */
3363 +
3364 + msg.index = 20;
3365 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_FCR") != 0))
3366 + goto err_plat_close; /* 20: RX FCR */
3367 +
3368 + msg.data32 = 0; /* Fill LUT with HDLC timeslots */
3369 + for (i = 0; i < 32 / LUT_BITS; i++)
3370 + msg.data32 |= TDMMAP_HDLC << (LUT_BITS * i);
3371 +
3372 + for (i = 0; i < 2 /* TX and RX */ * TIMESLOTS * LUT_BITS / 8; i += 4) {
3373 + msg.index = 24 + i; /* 24 - 55: TX LUT, 56 - 87: RX LUT */
3374 + if ((err = npe_send_message(npe, &msg, "HSS_SET_LUT") != 0))
3375 + goto err_plat_close;
3376 + }
3377 +
3378 + /* HDLC mode configuration */
3379 + memset(&msg, 0, sizeof(msg));
3380 + msg.cmd = PKT_NUM_PIPES_WRITE;
3381 + msg.hss_port = port->id;
3382 + msg.data8a = PKT_NUM_PIPES;
3383 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_PIPES") != 0))
3384 + goto err_plat_close;
3385 +
3386 + memset(&msg, 0, sizeof(msg));
3387 + msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
3388 + msg.hss_port = port->id;
3389 + msg.data8a = PKT_PIPE_FIFO_SIZEW;
3390 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_FIFO") != 0))
3391 + goto err_plat_close;
3392 +
3393 + memset(&msg, 0, sizeof(msg));
3394 + msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
3395 + msg.hss_port = port->id;
3396 + msg.data32 = 0x7F7F7F7F;
3397 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_IDLE") != 0))
3398 + goto err_plat_close;
3399 +
3400 + memset(&msg, 0, sizeof(msg));
3401 + msg.cmd = PORT_CONFIG_LOAD;
3402 + msg.hss_port = port->id;
3403 + if ((err = npe_send_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
3404 + goto err_plat_close;
3405 + if ((err = npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
3406 + goto err_plat_close;
3407 +
3408 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
3409 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
3410 + printk(KERN_DEBUG "%s: unexpected message received in"
3411 + " response to HSS_LOAD_CONFIG\n", npe_name(npe));
3412 + err = EIO;
3413 + goto err_plat_close;
3414 + }
3415 +
3416 + memset(&msg, 0, sizeof(msg));
3417 + msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
3418 + msg.hss_port = port->id;
3419 + msg.data8a = port->hdlc_cfg; /* rx_cfg */
3420 + msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
3421 + if ((err = npe_send_message(npe, &msg, "HSS_SET_HDLC_CFG") != 0))
3422 + goto err_plat_close;
3423 +
3424 + memset(&msg, 0, sizeof(msg));
3425 + msg.cmd = PKT_PIPE_MODE_WRITE;
3426 + msg.hss_port = port->id;
3427 + msg.data8a = NPE_PKT_MODE_HDLC;
3428 + /* msg.data8b = inv_mask */
3429 + /* msg.data8c = or_mask */
3430 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_MODE") != 0))
3431 + goto err_plat_close;
3432 +
3433 + memset(&msg, 0, sizeof(msg));
3434 + msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
3435 + msg.hss_port = port->id;
3436 + msg.data16a = HDLC_MAX_MRU;
3437 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_RX_SIZE") != 0))
3438 + goto err_plat_close;
3439 +
3440 + if ((err = request_hdlc_queues(port)) != 0)
3441 + goto err_plat_close;
3442 +
3443 + if ((err = init_hdlc_queues(port)) != 0)
3444 + goto err_destroy_queues;
3445 +
3446 + memset(&msg, 0, sizeof(msg));
3447 + msg.cmd = PKT_PIPE_FLOW_ENABLE;
3448 + msg.hss_port = port->id;
3449 + if ((err = npe_send_message(npe, &msg, "HSS_ENABLE_PKT_PIPE") != 0))
3450 + goto err_destroy_queues;
3451 +
3452 + /* Populate queues with buffers, no failure after this point */
3453 + for (i = 0; i < TX_DESCS; i++)
3454 + queue_put_desc(port->plat->txreadyq,
3455 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
3456 +
3457 + for (i = 0; i < RX_DESCS; i++)
3458 + queue_put_desc(queue_ids[port->id].rxfree,
3459 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
3460 +
3461 + netif_start_queue(dev);
3462 +
3463 + qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
3464 + hss_hdlc_rx_irq, dev);
3465 +
3466 + qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
3467 + hss_hdlc_txdone_irq, dev);
3468 + qmgr_enable_irq(queue_ids[port->id].txdone);
3469 +
3470 + ports_open++;
3471 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
3472 + return 0;
3473 +
3474 +err_destroy_queues:
3475 + destroy_hdlc_queues(port);
3476 + release_hdlc_queues(port);
3477 +err_plat_close:
3478 + if (port->plat->close)
3479 + port->plat->close(port->id, port->netdev);
3480 +err_hdlc_close:
3481 + hdlc_close(dev);
3482 + return err;
3483 +}
3484 +
3485 +static int hss_hdlc_close(struct net_device *dev)
3486 +{
3487 + struct port *port = dev_to_port(dev);
3488 + struct npe *npe = port->npe;
3489 + struct msg msg;
3490 + int buffs = RX_DESCS; /* allocated RX buffers */
3491 + int i;
3492 +
3493 + ports_open--;
3494 + qmgr_disable_irq(queue_ids[port->id].rx);
3495 + netif_stop_queue(dev);
3496 +
3497 + memset(&msg, 0, sizeof(msg));
3498 + msg.cmd = PKT_PIPE_FLOW_DISABLE;
3499 + msg.hss_port = port->id;
3500 + if (npe_send_message(npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
3501 + printk(KERN_CRIT "HSS-%i: unable to stop HDLC flow\n",
3502 + port->id);
3503 + /* The upper level would ignore the error anyway */
3504 + }
3505 +
3506 + while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
3507 + buffs--;
3508 + while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
3509 + buffs--;
3510 +
3511 + if (buffs)
3512 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
3513 + " left in NPE\n", dev->name, buffs);
3514 +
3515 + buffs = TX_DESCS;
3516 + while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
3517 + buffs--; /* cancel TX */
3518 +
3519 + i = 0;
3520 + do {
3521 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
3522 + buffs--;
3523 + if (!buffs)
3524 + break;
3525 + } while (++i < MAX_CLOSE_WAIT);
3526 +
3527 + if (buffs)
3528 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
3529 + "left in NPE\n", dev->name, buffs);
3530 +#if DEBUG_CLOSE
3531 + if (!buffs)
3532 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
3533 +#endif
3534 + qmgr_disable_irq(queue_ids[port->id].txdone);
3535 + destroy_hdlc_queues(port);
3536 + release_hdlc_queues(port);
3537 +
3538 + if (port->plat->close)
3539 + port->plat->close(port->id, port->netdev);
3540 + hdlc_close(dev);
3541 + return 0;
3542 +}
3543 +
3544 +
3545 +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
3546 + unsigned short parity)
3547 +{
3548 + struct port *port = dev_to_port(dev);
3549 +
3550 + if (encoding != ENCODING_NRZ)
3551 + return -EINVAL;
3552 +
3553 + switch(parity) {
3554 + case PARITY_CRC16_PR1_CCITT:
3555 + port->hdlc_cfg = 0;
3556 + return 0;
3557 +
3558 + case PARITY_CRC32_PR1_CCITT:
3559 + port->hdlc_cfg = PKT_HDLC_CRC_32;
3560 + return 0;
3561 +
3562 + default:
3563 + return -EINVAL;
3564 + }
3565 +}
3566 +
3567 +
3568 +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3569 +{
3570 + const size_t size = sizeof(sync_serial_settings);
3571 + sync_serial_settings new_line;
3572 + int clk;
3573 + sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
3574 + struct port *port = dev_to_port(dev);
3575 +
3576 + if (cmd != SIOCWANDEV)
3577 + return hdlc_ioctl(dev, ifr, cmd);
3578 +
3579 + switch(ifr->ifr_settings.type) {
3580 + case IF_GET_IFACE:
3581 + ifr->ifr_settings.type = IF_IFACE_V35;
3582 + if (ifr->ifr_settings.size < size) {
3583 + ifr->ifr_settings.size = size; /* data size wanted */
3584 + return -ENOBUFS;
3585 + }
3586 + memset(&new_line, 0, sizeof(new_line));
3587 + new_line.clock_type = port->clock_type;
3588 + new_line.clock_rate = port->clock_rate;
3589 + new_line.loopback = port->loopback;
3590 + if (copy_to_user(line, &new_line, size))
3591 + return -EFAULT;
3592 + return 0;
3593 +
3594 + case IF_IFACE_SYNC_SERIAL:
3595 + case IF_IFACE_V35:
3596 + if(!capable(CAP_NET_ADMIN))
3597 + return -EPERM;
3598 + if (dev->flags & IFF_UP)
3599 + return -EBUSY; /* Cannot change parameters when open */
3600 +
3601 + if (copy_from_user(&new_line, line, size))
3602 + return -EFAULT;
3603 +
3604 + clk = new_line.clock_type;
3605 + if (port->plat->set_clock)
3606 + clk = port->plat->set_clock(port->id, clk);
3607 +
3608 + if (clk != CLOCK_EXT && clk != CLOCK_INT)
3609 + return -EINVAL; /* No such clock setting */
3610 +
3611 + if (new_line.loopback != 0 && new_line.loopback != 1)
3612 + return -EINVAL;
3613 +
3614 + port->clock_type = clk; /* Update settings */
3615 + port->clock_rate = new_line.clock_rate;
3616 + port->loopback = new_line.loopback;
3617 + return 0;
3618 +
3619 + default:
3620 + return hdlc_ioctl(dev, ifr, cmd);
3621 + }
3622 +}
3623 +
3624 +
3625 +static int __devinit hss_init_one(struct platform_device *pdev)
3626 +{
3627 + struct port *port;
3628 + struct net_device *dev;
3629 + hdlc_device *hdlc;
3630 + int err;
3631 +
3632 + if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
3633 + return -ENOMEM;
3634 + platform_set_drvdata(pdev, port);
3635 + port->id = pdev->id;
3636 +
3637 + if ((port->npe = npe_request(0)) == NULL) {
3638 + err = -ENOSYS;
3639 + goto err_free;
3640 + }
3641 +
3642 + port->plat = pdev->dev.platform_data;
3643 + if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
3644 + err = -ENOMEM;
3645 + goto err_plat;
3646 + }
3647 +
3648 + SET_MODULE_OWNER(net);
3649 + SET_NETDEV_DEV(dev, &pdev->dev);
3650 + hdlc = dev_to_hdlc(dev);
3651 + hdlc->attach = hss_hdlc_attach;
3652 + hdlc->xmit = hss_hdlc_xmit;
3653 + dev->open = hss_hdlc_open;
3654 + dev->poll = hss_hdlc_poll;
3655 + dev->stop = hss_hdlc_close;
3656 + dev->do_ioctl = hss_hdlc_ioctl;
3657 + dev->weight = 16;
3658 + dev->tx_queue_len = 100;
3659 + port->clock_type = CLOCK_EXT;
3660 + port->clock_rate = 2048000;
3661 +
3662 + if (register_hdlc_device(dev)) {
3663 + printk(KERN_ERR "HSS-%i: unable to register HDLC device\n",
3664 + port->id);
3665 + err = -ENOBUFS;
3666 + goto err_free_netdev;
3667 + }
3668 + printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
3669 + return 0;
3670 +
3671 +err_free_netdev:
3672 + free_netdev(dev);
3673 +err_plat:
3674 + npe_release(port->npe);
3675 + platform_set_drvdata(pdev, NULL);
3676 +err_free:
3677 + kfree(port);
3678 + return err;
3679 +}
3680 +
3681 +static int __devexit hss_remove_one(struct platform_device *pdev)
3682 +{
3683 + struct port *port = platform_get_drvdata(pdev);
3684 +
3685 + unregister_hdlc_device(port->netdev);
3686 + free_netdev(port->netdev);
3687 + npe_release(port->npe);
3688 + platform_set_drvdata(pdev, NULL);
3689 + kfree(port);
3690 + return 0;
3691 +}
3692 +
3693 +static struct platform_driver drv = {
3694 + .driver.name = DRV_NAME,
3695 + .probe = hss_init_one,
3696 + .remove = hss_remove_one,
3697 +};
3698 +
3699 +static int __init hss_init_module(void)
3700 +{
3701 + if ((ixp4xx_read_feature_bits() &
3702 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
3703 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
3704 + return -ENOSYS;
3705 + return platform_driver_register(&drv);
3706 +}
3707 +
3708 +static void __exit hss_cleanup_module(void)
3709 +{
3710 + platform_driver_unregister(&drv);
3711 +}
3712 +
3713 +MODULE_AUTHOR("Krzysztof Halasa");
3714 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
3715 +MODULE_LICENSE("GPL v2");
3716 +module_init(hss_init_module);
3717 +module_exit(hss_cleanup_module);
3718 Index: linux-2.6.23.17/include/asm-arm/arch-ixp4xx/cpu.h
3719 ===================================================================
3720 --- linux-2.6.23.17.orig/include/asm-arm/arch-ixp4xx/cpu.h
3721 +++ linux-2.6.23.17/include/asm-arm/arch-ixp4xx/cpu.h
3722 @@ -28,4 +28,19 @@ extern unsigned int processor_id;
3723 #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
3724 IXP465_PROCESSOR_ID_VALUE)
3725
3726 +static inline u32 ixp4xx_read_feature_bits(void)
3727 +{
3728 + unsigned int val = ~*IXP4XX_EXP_CFG2;
3729 + val &= ~IXP4XX_FEATURE_RESERVED;
3730 + if (!cpu_is_ixp46x())
3731 + val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
3732 +
3733 + return val;
3734 +}
3735 +
3736 +static inline void ixp4xx_write_feature_bits(u32 value)
3737 +{
3738 + *IXP4XX_EXP_CFG2 = ~value;
3739 +}
3740 +
3741 #endif /* _ASM_ARCH_CPU_H */
3742 Index: linux-2.6.23.17/include/asm-arm/arch-ixp4xx/hardware.h
3743 ===================================================================
3744 --- linux-2.6.23.17.orig/include/asm-arm/arch-ixp4xx/hardware.h
3745 +++ linux-2.6.23.17/include/asm-arm/arch-ixp4xx/hardware.h
3746 @@ -27,13 +27,13 @@
3747
3748 #define pcibios_assign_all_busses() 1
3749
3750 +/* Register locations and bits */
3751 +#include "ixp4xx-regs.h"
3752 +
3753 #ifndef __ASSEMBLER__
3754 #include <asm/arch/cpu.h>
3755 #endif
3756
3757 -/* Register locations and bits */
3758 -#include "ixp4xx-regs.h"
3759 -
3760 /* Platform helper functions and definitions */
3761 #include "platform.h"
3762
3763 Index: linux-2.6.23.17/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3764 ===================================================================
3765 --- linux-2.6.23.17.orig/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3766 +++ linux-2.6.23.17/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3767 @@ -15,10 +15,6 @@
3768 *
3769 */
3770
3771 -#ifndef __ASM_ARCH_HARDWARE_H__
3772 -#error "Do not include this directly, instead #include <asm/hardware.h>"
3773 -#endif
3774 -
3775 #ifndef _ASM_ARM_IXP4XX_H_
3776 #define _ASM_ARM_IXP4XX_H_
3777
3778 @@ -607,4 +603,36 @@
3779
3780 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
3781
3782 +/* "fuse" bits of IXP_EXP_CFG2 */
3783 +#define IXP4XX_FEATURE_RCOMP (1 << 0)
3784 +#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
3785 +#define IXP4XX_FEATURE_HASH (1 << 2)
3786 +#define IXP4XX_FEATURE_AES (1 << 3)
3787 +#define IXP4XX_FEATURE_DES (1 << 4)
3788 +#define IXP4XX_FEATURE_HDLC (1 << 5)
3789 +#define IXP4XX_FEATURE_AAL (1 << 6)
3790 +#define IXP4XX_FEATURE_HSS (1 << 7)
3791 +#define IXP4XX_FEATURE_UTOPIA (1 << 8)
3792 +#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
3793 +#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
3794 +#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
3795 +#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
3796 +#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
3797 +#define IXP4XX_FEATURE_PCI (1 << 14)
3798 +#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
3799 +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
3800 +#define IXP4XX_FEATURE_USB_HOST (1 << 18)
3801 +#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
3802 +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
3803 +#define IXP4XX_FEATURE_RSA (1 << 21)
3804 +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
3805 +#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
3806 +
3807 +#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
3808 + IXP4XX_FEATURE_USB_HOST | \
3809 + IXP4XX_FEATURE_NPEA_ETH | \
3810 + IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
3811 + IXP4XX_FEATURE_RSA | \
3812 + IXP4XX_FEATURE_XSCALE_MAX_FREQ)
3813 +
3814 #endif
3815 Index: linux-2.6.23.17/include/asm-arm/arch-ixp4xx/npe.h
3816 ===================================================================
3817 --- /dev/null
3818 +++ linux-2.6.23.17/include/asm-arm/arch-ixp4xx/npe.h
3819 @@ -0,0 +1,39 @@
3820 +#ifndef __IXP4XX_NPE_H
3821 +#define __IXP4XX_NPE_H
3822 +
3823 +#include <linux/kernel.h>
3824 +
3825 +extern const char *npe_names[];
3826 +
3827 +struct npe_regs {
3828 + u32 exec_addr, exec_data, exec_status_cmd, exec_count;
3829 + u32 action_points[4];
3830 + u32 watchpoint_fifo, watch_count;
3831 + u32 profile_count;
3832 + u32 messaging_status, messaging_control;
3833 + u32 mailbox_status, /*messaging_*/ in_out_fifo;
3834 +};
3835 +
3836 +struct npe {
3837 + struct resource *mem_res;
3838 + struct npe_regs __iomem *regs;
3839 + u32 regs_phys;
3840 + int id;
3841 + int valid;
3842 +};
3843 +
3844 +
3845 +static inline const char *npe_name(struct npe *npe)
3846 +{
3847 + return npe_names[npe->id];
3848 +}
3849 +
3850 +int npe_running(struct npe *npe);
3851 +int npe_send_message(struct npe *npe, const void *msg, const char *what);
3852 +int npe_recv_message(struct npe *npe, void *msg, const char *what);
3853 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
3854 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
3855 +struct npe *npe_request(int id);
3856 +void npe_release(struct npe *npe);
3857 +
3858 +#endif /* __IXP4XX_NPE_H */
3859 Index: linux-2.6.23.17/include/asm-arm/arch-ixp4xx/platform.h
3860 ===================================================================
3861 --- linux-2.6.23.17.orig/include/asm-arm/arch-ixp4xx/platform.h
3862 +++ linux-2.6.23.17/include/asm-arm/arch-ixp4xx/platform.h
3863 @@ -77,8 +77,7 @@ extern unsigned long ixp4xx_exp_bus_size
3864
3865 /*
3866 * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
3867 - * used to
3868 - * Used as platform_data to provide GPIO pin information to the ixp42x
3869 + * used as platform_data to provide GPIO pin information to the ixp42x
3870 * I2C driver.
3871 */
3872 struct ixp4xx_i2c_pins {
3873 @@ -86,6 +85,27 @@ struct ixp4xx_i2c_pins {
3874 unsigned long scl_pin;
3875 };
3876
3877 +#define IXP4XX_ETH_NPEA 0x00
3878 +#define IXP4XX_ETH_NPEB 0x10
3879 +#define IXP4XX_ETH_NPEC 0x20
3880 +
3881 +/* Information about built-in Ethernet MAC interfaces */
3882 +struct eth_plat_info {
3883 + u8 phy; /* MII PHY ID, 0 - 31 */
3884 + u8 rxq; /* configurable, currently 0 - 31 only */
3885 + u8 txreadyq;
3886 + u8 hwaddr[6];
3887 +};
3888 +
3889 +/* Information about built-in HSS (synchronous serial) interfaces */
3890 +struct hss_plat_info {
3891 + int (*set_clock)(int port, unsigned int clock_type);
3892 + int (*open)(int port, void *pdev,
3893 + void (*set_carrier_cb)(void *pdev, int carrier));
3894 + void (*close)(int port, void *pdev);
3895 + u8 txreadyq;
3896 +};
3897 +
3898 /*
3899 * This structure provide a means for the board setup code
3900 * to give information to th pata_ixp4xx driver. It is
3901 Index: linux-2.6.23.17/include/asm-arm/arch-ixp4xx/qmgr.h
3902 ===================================================================
3903 --- /dev/null
3904 +++ linux-2.6.23.17/include/asm-arm/arch-ixp4xx/qmgr.h
3905 @@ -0,0 +1,126 @@
3906 +/*
3907 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3908 + *
3909 + * This program is free software; you can redistribute it and/or modify it
3910 + * under the terms of version 2 of the GNU General Public License
3911 + * as published by the Free Software Foundation.
3912 + */
3913 +
3914 +#ifndef IXP4XX_QMGR_H
3915 +#define IXP4XX_QMGR_H
3916 +
3917 +#include <linux/io.h>
3918 +#include <linux/kernel.h>
3919 +
3920 +#define HALF_QUEUES 32
3921 +#define QUEUES 64 /* only 32 lower queues currently supported */
3922 +#define MAX_QUEUE_LENGTH 4 /* in dwords */
3923 +
3924 +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
3925 +#define QUEUE_STAT1_NEARLY_EMPTY 2
3926 +#define QUEUE_STAT1_NEARLY_FULL 4
3927 +#define QUEUE_STAT1_FULL 8
3928 +#define QUEUE_STAT2_UNDERFLOW 1
3929 +#define QUEUE_STAT2_OVERFLOW 2
3930 +
3931 +#define QUEUE_WATERMARK_0_ENTRIES 0
3932 +#define QUEUE_WATERMARK_1_ENTRY 1
3933 +#define QUEUE_WATERMARK_2_ENTRIES 2
3934 +#define QUEUE_WATERMARK_4_ENTRIES 3
3935 +#define QUEUE_WATERMARK_8_ENTRIES 4
3936 +#define QUEUE_WATERMARK_16_ENTRIES 5
3937 +#define QUEUE_WATERMARK_32_ENTRIES 6
3938 +#define QUEUE_WATERMARK_64_ENTRIES 7
3939 +
3940 +/* queue interrupt request conditions */
3941 +#define QUEUE_IRQ_SRC_EMPTY 0
3942 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
3943 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2
3944 +#define QUEUE_IRQ_SRC_FULL 3
3945 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4
3946 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
3947 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
3948 +#define QUEUE_IRQ_SRC_NOT_FULL 7
3949 +
3950 +struct qmgr_regs {
3951 + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
3952 + u32 stat1[4]; /* 0x400 - 0x40F */
3953 + u32 stat2[2]; /* 0x410 - 0x417 */
3954 + u32 statne_h; /* 0x418 - queue nearly empty */
3955 + u32 statf_h; /* 0x41C - queue full */
3956 + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
3957 + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
3958 + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
3959 + u32 reserved[1776];
3960 + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
3961 +};
3962 +
3963 +void qmgr_set_irq(unsigned int queue, int src,
3964 + void (*handler)(void *pdev), void *pdev);
3965 +void qmgr_enable_irq(unsigned int queue);
3966 +void qmgr_disable_irq(unsigned int queue);
3967 +
3968 +/* request_ and release_queue() must be called from non-IRQ context */
3969 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
3970 + unsigned int nearly_empty_watermark,
3971 + unsigned int nearly_full_watermark);
3972 +void qmgr_release_queue(unsigned int queue);
3973 +
3974 +
3975 +static inline void qmgr_put_entry(unsigned int queue, u32 val)
3976 +{
3977 + extern struct qmgr_regs __iomem *qmgr_regs;
3978 + __raw_writel(val, &qmgr_regs->acc[queue][0]);
3979 +}
3980 +
3981 +static inline u32 qmgr_get_entry(unsigned int queue)
3982 +{
3983 + extern struct qmgr_regs __iomem *qmgr_regs;
3984 + return __raw_readl(&qmgr_regs->acc[queue][0]);
3985 +}
3986 +
3987 +static inline int qmgr_get_stat1(unsigned int queue)
3988 +{
3989 + extern struct qmgr_regs __iomem *qmgr_regs;
3990 + return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
3991 + >> ((queue & 7) << 2)) & 0xF;
3992 +}
3993 +
3994 +static inline int qmgr_get_stat2(unsigned int queue)
3995 +{
3996 + extern struct qmgr_regs __iomem *qmgr_regs;
3997 + return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
3998 + >> ((queue & 0xF) << 1)) & 0x3;
3999 +}
4000 +
4001 +static inline int qmgr_stat_empty(unsigned int queue)
4002 +{
4003 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
4004 +}
4005 +
4006 +static inline int qmgr_stat_nearly_empty(unsigned int queue)
4007 +{
4008 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
4009 +}
4010 +
4011 +static inline int qmgr_stat_nearly_full(unsigned int queue)
4012 +{
4013 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
4014 +}
4015 +
4016 +static inline int qmgr_stat_full(unsigned int queue)
4017 +{
4018 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
4019 +}
4020 +
4021 +static inline int qmgr_stat_underflow(unsigned int queue)
4022 +{
4023 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
4024 +}
4025 +
4026 +static inline int qmgr_stat_overflow(unsigned int queue)
4027 +{
4028 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
4029 +}
4030 +
4031 +#endif
4032 Index: linux-2.6.23.17/include/asm-arm/arch-ixp4xx/uncompress.h
4033 ===================================================================
4034 --- linux-2.6.23.17.orig/include/asm-arm/arch-ixp4xx/uncompress.h
4035 +++ linux-2.6.23.17/include/asm-arm/arch-ixp4xx/uncompress.h
4036 @@ -13,7 +13,7 @@
4037 #ifndef _ARCH_UNCOMPRESS_H_
4038 #define _ARCH_UNCOMPRESS_H_
4039
4040 -#include <asm/hardware.h>
4041 +#include "ixp4xx-regs.h"
4042 #include <asm/mach-types.h>
4043 #include <linux/serial_reg.h>
4044
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