target/linux/adm5120/files/drivers/usb/host/adm5120.h

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 /*
  11  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  12  * __leXX (normally) or __beXX (given OHCI_BIG_ENDIAN), depending on the
  13  * host controller implementation.
  14  */
  15 typedef __u32 __bitwise __hc32;
  16 typedef __u16 __bitwise __hc16;
  17
  18 /*
  19  * OHCI Endpoint Descriptor (ED) ... holds TD queue
  20  * See OHCI spec, section 4.2
  21  *
  22  * This is a "Queue Head" for those transfers, which is why
  23  * both EHCI and UHCI call similar structures a "QH".
  24  */
  25
  26 #define TD_DATALEN_MAX  4096
  27
  28 #define ED_ALIGN        16
  29 #define ED_MASK ((u32)~(ED_ALIGN-1))    /* strip hw status in low addr bits */
  30
  31 struct ed {
  32         /* first fields are hardware-specified */
  33         __hc32                  hwINFO;      /* endpoint config bitmap */
  34         /* info bits defined by hcd */
  35 #define ED_DEQUEUE      (1 << 27)
  36         /* info bits defined by the hardware */
  37 #define ED_MPS_SHIFT    16
  38 #define ED_MPS_MASK     ((1 << 11)-1)
  39 #define ED_MPS_GET(x)   (((x) >> ED_MPS_SHIFT) & ED_MPS_MASK)
  40 #define ED_ISO          (1 << 15)               /* isochronous endpoint */
  41 #define ED_SKIP         (1 << 14)
  42 #define ED_SPEED_FULL   (1 << 13)               /* fullspeed device */
  43 #define ED_INT          (1 << 11)               /* interrupt endpoint */
  44 #define ED_EN_SHIFT     7                       /* endpoint shift */
  45 #define ED_EN_MASK      ((1 << 4)-1)            /* endpoint mask */
  46 #define ED_EN_GET(x)    (((x) >> ED_EN_SHIFT) & ED_EN_MASK)
  47 #define ED_FA_MASK      ((1 << 7)-1)            /* function address mask */
  48 #define ED_FA_GET(x)    ((x) & ED_FA_MASK)
  49         __hc32                  hwTailP;        /* tail of TD list */
  50         __hc32                  hwHeadP;        /* head of TD list (hc r/w) */
  51 #define ED_C            (0x02)                  /* toggle carry */
  52 #define ED_H            (0x01)                  /* halted */
  53         __hc32                  hwNextED;       /* next ED in list */
  54
  55         /* rest are purely for the driver's use */
  56         dma_addr_t              dma;            /* addr of ED */
  57         struct td               *dummy;         /* next TD to activate */
  58
  59         struct urb_priv         *urb_active;    /* active URB */
  60         struct list_head        urb_pending;    /* pending URBs */
  61
  62         struct list_head        ed_list;        /* list of all EDs*/
  63         struct list_head        rm_list;        /* for remove list */
  64
  65         /* host's view of schedule */
  66         struct ed               *ed_next;       /* on schedule list */
  67         struct ed               *ed_prev;       /* for non-interrupt EDs */
  68
  69         /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
  70          * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
  71          */
  72         u8                      state;
  73 #define ED_NEW          0x00            /* just allocated */
  74 #define ED_IDLE         0x01            /* linked into HC, but not running */
  75 #define ED_OPER         0x02            /* linked into HC and running */
  76 #define ED_UNLINK       0x03            /* being unlinked from HC */
  77
  78         u8                      type;           /* PIPE_{BULK,...} */
  79
  80         /* periodic scheduling params (for intr and iso) */
  81         u8                      branch;
  82         u16                     interval;
  83         u16                     load;
  84         u16                     last_iso;       /* iso only */
  85
  86         /* HC may see EDs on rm_list until next frame (frame_no == tick) */
  87         u16                     tick;
  88 } __attribute__ ((aligned(ED_ALIGN)));
  89
  90 /*
  91  * OHCI Transfer Descriptor (TD) ... one per transfer segment
  92  * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
  93  * and 4.3.2 (iso)
  94  */
  95
  96 #define TD_ALIGN        32
  97 #define TD_MASK ((u32)~(TD_ALIGN-1))    /* strip hw status in low addr bits */
  98
  99 struct td {
 100         /* first fields are hardware-specified */
 101         __hc32          hwINFO;         /* transfer info bitmask */
 102
 103         /* hwINFO bits */
 104 #define TD_OWN          (1 << 31)               /* owner of the descriptor */
 105 #define TD_CC_SHIFT     27                      /* condition code */
 106 #define TD_CC_MASK      0xf
 107 #define TD_CC           (TD_CC_MASK << TD_CC_SHIFT)
 108 #define TD_CC_GET(x)    (((x) >> TD_CC_SHIFT) & TD_CC_MASK)
 109
 110 #define TD_EC_SHIFT     25                      /* error count */
 111 #define TD_EC_MASK      0x3
 112 #define TD_EC           (TD_EC_MASK << TD_EC_SHIFT)
 113 #define TD_EC_GET(x)    ((x >> TD_EC_SHIFT) & TD_EC_MASK)
 114 #define TD_T_SHIFT      23                      /* data toggle state */
 115 #define TD_T_MASK       0x3
 116 #define TD_T            (TD_T_MASK << TD_T_SHIFT)
 117 #define TD_T_DATA0      (0x2 << TD_T_SHIFT)     /* DATA0 */
 118 #define TD_T_DATA1      (0x3 << TD_T_SHIFT)     /* DATA1 */
 119 #define TD_T_CARRY      (0x0 << TD_T_SHIFT)     /* uses ED_C */
 120 #define TD_T_GET(x)     (((x) >> TD_T_SHIFT) & TD_T_MASK)
 121 #define TD_DP_SHIFT     21                      /* direction/pid */
 122 #define TD_DP_MASK      0x3
 123 #define TD_DP           (TD_DP_MASK << TD_DP_SHIFT)
 124 #define TD_DP_SETUP     (0x0 << TD_DP_SHIFT)    /* SETUP pid */
 125 #define TD_DP_OUT       (0x1 << TD_DP_SHIFT)    /* OUT pid */
 126 #define TD_DP_IN        (0x2 << TD_DP_SHIFT)    /* IN pid */
 127 #define TD_DP_GET(x)    (((x) >> TD_DP_SHIFT) & TD_DP_MASK)
 128 #define TD_ISI_SHIFT    8                       /* Interrupt Service Interval */
 129 #define TD_ISI_MASK     0x3f
 130 #define TD_ISI_GET(x)   (((x) >> TD_ISI_SHIFT) & TD_ISI_MASK)
 131 #define TD_FN_MASK      0x3f                    /* frame number */
 132 #define TD_FN_GET(x)    ((x) & TD_FN_MASK)
 133
 134         __hc32          hwDBP;          /* Data Buffer Pointer (or 0) */
 135         __hc32          hwCBL;          /* Controller/Buffer Length */
 136
 137         /* hwCBL bits */
 138 #define TD_BL_MASK      0xffff          /* buffer length */
 139 #define TD_BL_GET(x)    ((x) & TD_BL_MASK)
 140 #define TD_IE           (1 << 16)       /* interrupt enable */
 141         __hc32          hwNextTD;       /* Next TD Pointer */
 142
 143         /* rest are purely for the driver's use */
 144         __u8            index;
 145         struct urb      *urb;
 146
 147         dma_addr_t      td_dma;         /* addr of this TD */
 148         dma_addr_t      data_dma;       /* addr of data it points to */
 149
 150 } __attribute__ ((aligned(TD_ALIGN)));  /* c/b/i need 16; only iso needs 32 */
 151
 152 /*
 153  * Hardware transfer status codes -- CC from td->hwINFO
 154  */
 155 #define TD_CC_NOERROR           0x00
 156 #define TD_CC_CRC               0x01
 157 #define TD_CC_BITSTUFFING       0x02
 158 #define TD_CC_DATATOGGLEM       0x03
 159 #define TD_CC_STALL             0x04
 160 #define TD_CC_DEVNOTRESP        0x05
 161 #define TD_CC_PIDCHECKFAIL      0x06
 162 #define TD_CC_UNEXPECTEDPID     0x07
 163 #define TD_CC_DATAOVERRUN       0x08
 164 #define TD_CC_DATAUNDERRUN      0x09
 165     /* 0x0A, 0x0B reserved for hardware */
 166 #define TD_CC_BUFFEROVERRUN     0x0C
 167 #define TD_CC_BUFFERUNDERRUN    0x0D
 168     /* 0x0E, 0x0F reserved for HCD */
 169 #define TD_CC_HCD0              0x0E
 170 #define TD_CC_NOTACCESSED       0x0F
 171
 172 /*
 173  * preshifted status codes
 174  */
 175 #define TD_SCC_NOTACCESSED      (TD_CC_NOTACCESSED << TD_CC_SHIFT)
 176
 177
 178 /* map OHCI TD status codes (CC) to errno values */
 179 static const int cc_to_error [16] = {
 180         /* No  Error  */        0,
 181         /* CRC Error  */        -EILSEQ,
 182         /* Bit Stuff  */        -EPROTO,
 183         /* Data Togg  */        -EILSEQ,
 184         /* Stall      */        -EPIPE,
 185         /* DevNotResp */        -ETIME,
 186         /* PIDCheck   */        -EPROTO,
 187         /* UnExpPID   */        -EPROTO,
 188         /* DataOver   */        -EOVERFLOW,
 189         /* DataUnder  */        -EREMOTEIO,
 190         /* (for hw)   */        -EIO,
 191         /* (for hw)   */        -EIO,
 192         /* BufferOver */        -ECOMM,
 193         /* BuffUnder  */        -ENOSR,
 194         /* (for HCD)  */        -EALREADY,
 195         /* (for HCD)  */        -EALREADY
 196 };
 197
 198 #define NUM_INTS        32
 199
 200 /*
 201  * This is the structure of the OHCI controller's memory mapped I/O region.
 202  * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
 203  * Layout is in section 7 (and appendix B) of the spec.
 204  */
 205 struct admhcd_regs {
 206         __hc32  gencontrol;     /* General Control */
 207         __hc32  int_status;     /* Interrupt Status */
 208         __hc32  int_enable;     /* Interrupt Enable */
 209         __hc32  reserved00;
 210         __hc32  host_control;   /* Host General Control */
 211         __hc32  reserved01;
 212         __hc32  fminterval;     /* Frame Interval */
 213         __hc32  fmnumber;       /* Frame Number */
 214         __hc32  reserved02;
 215         __hc32  reserved03;
 216         __hc32  reserved04;
 217         __hc32  reserved05;
 218         __hc32  reserved06;
 219         __hc32  reserved07;
 220         __hc32  reserved08;
 221         __hc32  reserved09;
 222         __hc32  reserved10;
 223         __hc32  reserved11;
 224         __hc32  reserved12;
 225         __hc32  reserved13;
 226         __hc32  reserved14;
 227         __hc32  reserved15;
 228         __hc32  reserved16;
 229         __hc32  reserved17;
 230         __hc32  reserved18;
 231         __hc32  reserved19;
 232         __hc32  reserved20;
 233         __hc32  reserved21;
 234         __hc32  lsthresh;       /* Low Speed Threshold */
 235         __hc32  rhdesc;         /* Root Hub Descriptor */
 236 #define MAX_ROOT_PORTS  2
 237         __hc32  portstatus[MAX_ROOT_PORTS]; /* Port Status */
 238         __hc32  hosthead;       /* Host Descriptor Head */
 239 } __attribute__ ((aligned(32)));
 240
 241 /*
 242  * General Control register bits
 243  */
 244 #define ADMHC_CTRL_UHFE (1 << 0)        /* USB Host Function Enable */
 245 #define ADMHC_CTRL_SIR  (1 << 1)        /* Software Interrupt request */
 246 #define ADMHC_CTRL_DMAA (1 << 2)        /* DMA Arbitration Control */
 247 #define ADMHC_CTRL_SR   (1 << 3)        /* Software Reset */
 248
 249 /*
 250  * Host General Control register bits
 251  */
 252 #define ADMHC_HC_BUSS           0x3             /* USB bus state */
 253 #define   ADMHC_BUSS_RESET      0x0
 254 #define   ADMHC_BUSS_RESUME     0x1
 255 #define   ADMHC_BUSS_OPER       0x2
 256 #define   ADMHC_BUSS_SUSPEND    0x3
 257 #define ADMHC_HC_DMAE           (1 << 2)        /* DMA enable */
 258
 259 /*
 260  * Interrupt Status/Enable register bits
 261  */
 262 #define ADMHC_INTR_SOFI (1 << 4)        /* start of frame */
 263 #define ADMHC_INTR_RESI (1 << 5)        /* resume detected */
 264 #define ADMHC_INTR_6    (1 << 6)        /* unknown */
 265 #define ADMHC_INTR_7    (1 << 7)        /* unknown */
 266 #define ADMHC_INTR_BABI (1 << 8)        /* babble detected */
 267 #define ADMHC_INTR_INSM (1 << 9)        /* root hub status change */
 268 #define ADMHC_INTR_SO   (1 << 10)       /* scheduling overrun */
 269 #define ADMHC_INTR_FNO  (1 << 11)       /* frame number overflow */
 270 #define ADMHC_INTR_TDC  (1 << 20)       /* transfer descriptor completed */
 271 #define ADMHC_INTR_SWI  (1 << 29)       /* software interrupt */
 272 #define ADMHC_INTR_FATI (1 << 30)       /* fatal error */
 273 #define ADMHC_INTR_INTA (1 << 31)       /* interrupt active */
 274
 275 #define ADMHC_INTR_MIE  (1 << 31)       /* master interrupt enable */
 276
 277 /*
 278  * SOF Frame Interval register bits
 279  */
 280 #define ADMHC_SFI_FI_MASK       ((1 << 14)-1)   /* Frame Interval value */
 281 #define ADMHC_SFI_FSLDP_SHIFT   16
 282 #define ADMHC_SFI_FSLDP_MASK    ((1 << 15)-1)
 283 #define ADMHC_SFI_FIT           (1 << 31)       /* Frame Interval Toggle */
 284
 285 /*
 286  * SOF Frame Number register bits
 287  */
 288 #define ADMHC_SFN_FN_MASK       ((1 << 16)-1)   /* Frame Number Mask */
 289 #define ADMHC_SFN_FR_SHIFT      16              /* Frame Remaining Shift */
 290 #define ADMHC_SFN_FR_MASK       ((1 << 14)-1)   /* Frame Remaining Mask */
 291 #define ADMHC_SFN_FRT           (1 << 31)       /* Frame Remaining Toggle */
 292
 293 /*
 294  * Root Hub Descriptor register bits
 295  */
 296 #define ADMHC_RH_NUMP   0xff            /* number of ports */
 297 #define ADMHC_RH_PSM    (1 << 8)        /* power switching mode */
 298 #define ADMHC_RH_NPS    (1 << 9)        /* no power switching */
 299 #define ADMHC_RH_OCPM   (1 << 10)       /* over current protection mode */
 300 #define ADMHC_RH_NOCP   (1 << 11)       /* no over current protection */
 301 #define ADMHC_RH_PPCM   (0xff << 16)    /* port power control */
 302
 303 #define ADMHC_RH_LPS    (1 << 24)       /* local power switch */
 304 #define ADMHC_RH_OCI    (1 << 25)       /* over current indicator */
 305
 306 /* status change bits */
 307 #define ADMHC_RH_LPSC   (1 << 26)       /* local power switch change */
 308 #define ADMHC_RH_OCIC   (1 << 27)       /* over current indicator change */
 309
 310 #define ADMHC_RH_DRWE   (1 << 28)       /* device remote wakeup enable */
 311 #define ADMHC_RH_CRWE   (1 << 29)       /* clear remote wakeup enable */
 312
 313 #define ADMHC_RH_CGP    (1 << 24)       /* clear global power */
 314 #define ADMHC_RH_SGP    (1 << 26)       /* set global power */
 315
 316 /*
 317  * Port Status register bits
 318  */
 319 #define ADMHC_PS_CCS    (1 << 0)        /* current connect status */
 320 #define ADMHC_PS_PES    (1 << 1)        /* port enable status */
 321 #define ADMHC_PS_PSS    (1 << 2)        /* port suspend status */
 322 #define ADMHC_PS_POCI   (1 << 3)        /* port over current indicator */
 323 #define ADMHC_PS_PRS    (1 << 4)        /* port reset status */
 324 #define ADMHC_PS_PPS    (1 << 8)        /* port power status */
 325 #define ADMHC_PS_LSDA   (1 << 9)        /* low speed device attached */
 326
 327 /* status change bits */
 328 #define ADMHC_PS_CSC    (1 << 16)       /* connect status change */
 329 #define ADMHC_PS_PESC   (1 << 17)       /* port enable status change */
 330 #define ADMHC_PS_PSSC   (1 << 18)       /* port suspend status change */
 331 #define ADMHC_PS_OCIC   (1 << 19)       /* over current indicator change */
 332 #define ADMHC_PS_PRSC   (1 << 20)       /* port reset status change */
 333
 334 /* port feature bits */
 335 #define ADMHC_PS_CPE    (1 << 0)        /* clear port enable */
 336 #define ADMHC_PS_SPE    (1 << 1)        /* set port enable */
 337 #define ADMHC_PS_SPS    (1 << 2)        /* set port suspend */
 338 #define ADMHC_PS_CPS    (1 << 3)        /* clear suspend status */
 339 #define ADMHC_PS_SPR    (1 << 4)        /* set port reset */
 340 #define ADMHC_PS_SPP    (1 << 8)        /* set port power */
 341 #define ADMHC_PS_CPP    (1 << 9)        /* clear port power */
 342
 343 /*
 344  * the POTPGT value is not defined in the ADMHC, so define a dummy value
 345  */
 346 #define ADMHC_POTPGT    2               /* in ms */
 347
 348 /* hcd-private per-urb state */
 349 struct urb_priv {
 350         struct ed               *ed;
 351         struct urb              *urb;
 352         struct list_head        pending;        /* URBs on the same ED */
 353
 354         u32                     td_cnt;         /* # tds in this request */
 355         u32                     td_idx;         /* index of the current td */
 356         struct td               *td[0];         /* all TDs in this request */
 357 };
 358
 359 #define TD_HASH_SIZE    64    /* power'o'two */
 360 /* sizeof (struct td) ~= 64 == 2^6 ... */
 361 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
 362
 363 /*
 364  * This is the full ADMHCD controller description
 365  *
 366  * Note how the "proper" USB information is just
 367  * a subset of what the full implementation needs. (Linus)
 368  */
 369
 370 struct admhcd {
 371         spinlock_t              lock;
 372
 373         /*
 374          * I/O memory used to communicate with the HC (dma-consistent)
 375          */
 376         struct admhcd_regs __iomem *regs;
 377
 378         /*
 379          * hcd adds to schedule for a live hc any time, but removals finish
 380          * only at the start of the next frame.
 381          */
 382         struct ed               *ed_head;
 383         struct ed               *ed_tails[4];
 384
 385 //      struct ed               *periodic[NUM_INTS];    /* shadow int_table */
 386
 387 #if 0   /* TODO: remove? */
 388         /*
 389          * OTG controllers and transceivers need software interaction;
 390          * other external transceivers should be software-transparent
 391          */
 392         struct otg_transceiver  *transceiver;
 393 #endif
 394
 395         /*
 396          * memory management for queue data structures
 397          */
 398         struct dma_pool         *td_cache;
 399         struct dma_pool         *ed_cache;
 400         struct td               *td_hash[TD_HASH_SIZE];
 401
 402         /*
 403          * driver state
 404          */
 405         int                     num_ports;
 406         int                     load[NUM_INTS];
 407         u32                     host_control;   /* copy of the host_control reg */
 408         unsigned long           next_statechange;       /* suspend/resume */
 409         u32                     fminterval;             /* saved register */
 410         unsigned                autostop:1;     /* rh auto stopping/stopped */
 411
 412         unsigned long           flags;          /* for HC bugs */
 413 #define OHCI_QUIRK_AMD756       0x01                    /* erratum #4 */
 414 #define OHCI_QUIRK_SUPERIO      0x02                    /* natsemi */
 415 #define OHCI_QUIRK_INITRESET    0x04                    /* SiS, OPTi, ... */
 416 #define OHCI_QUIRK_BE_DESC      0x08                    /* BE descriptors */
 417 #define OHCI_QUIRK_BE_MMIO      0x10                    /* BE registers */
 418 #define OHCI_QUIRK_ZFMICRO      0x20                    /* Compaq ZFMicro chipset*/
 419         // there are also chip quirks/bugs in init logic
 420 };
 421
 422 /* convert between an hcd pointer and the corresponding ahcd_hcd */
 423 static inline struct admhcd *hcd_to_admhcd(struct usb_hcd *hcd)
 424 {
 425         return (struct admhcd *)(hcd->hcd_priv);
 426 }
 427 static inline struct usb_hcd *admhcd_to_hcd(const struct admhcd *ahcd)
 428 {
 429         return container_of((void *)ahcd, struct usb_hcd, hcd_priv);
 430 }
 431
 432 /*-------------------------------------------------------------------------*/
 433
 434 #ifndef DEBUG
 435 #define STUB_DEBUG_FILES
 436 #endif  /* DEBUG */
 437
 438 #ifdef DEBUG
 439 #       define admhc_dbg(ahcd, fmt, args...) \
 440                 printk(KERN_DEBUG "adm5120-hcd: " fmt , ## args )
 441 #else
 442 #       define admhc_dbg(ahcd, fmt, args...) do { } while (0)
 443 #endif
 444
 445 #define admhc_err(ahcd, fmt, args...) \
 446         printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
 447 #define admhc_info(ahcd, fmt, args...) \
 448         printk(KERN_INFO "adm5120-hcd: " fmt , ## args )
 449 #define admhc_warn(ahcd, fmt, args...) \
 450         printk(KERN_WARNING "adm5120-hcd: " fmt , ## args )
 451
 452 #ifdef ADMHC_VERBOSE_DEBUG
 453 #       define admhc_vdbg admhc_dbg
 454 #else
 455 #       define admhc_vdbg(ahcd, fmt, args...) do { } while (0)
 456 #endif
 457
 458 /*-------------------------------------------------------------------------*/
 459
 460 /*
 461  * While most USB host controllers implement their registers and
 462  * in-memory communication descriptors in little-endian format,
 463  * a minority (notably the IBM STB04XXX and the Motorola MPC5200
 464  * processors) implement them in big endian format.
 465  *
 466  * In addition some more exotic implementations like the Toshiba
 467  * Spider (aka SCC) cell southbridge are "mixed" endian, that is,
 468  * they have a different endianness for registers vs. in-memory
 469  * descriptors.
 470  *
 471  * This attempts to support either format at compile time without a
 472  * runtime penalty, or both formats with the additional overhead
 473  * of checking a flag bit.
 474  *
 475  * That leads to some tricky Kconfig rules howevber. There are
 476  * different defaults based on some arch/ppc platforms, though
 477  * the basic rules are:
 478  *
 479  * Controller type              Kconfig options needed
 480  * ---------------              ----------------------
 481  * little endian                CONFIG_USB_ADMHC_LITTLE_ENDIAN
 482  *
 483  * fully big endian             CONFIG_USB_ADMHC_BIG_ENDIAN_DESC _and_
 484  *                              CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 485  *
 486  * mixed endian                 CONFIG_USB_ADMHC_LITTLE_ENDIAN _and_
 487  *                              CONFIG_USB_OHCI_BIG_ENDIAN_{MMIO,DESC}
 488  *
 489  * (If you have a mixed endian controller, you -must- also define
 490  * CONFIG_USB_ADMHC_LITTLE_ENDIAN or things will not work when building
 491  * both your mixed endian and a fully big endian controller support in
 492  * the same kernel image).
 493  */
 494
 495 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_DESC
 496 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
 497 #define big_endian_desc(ahcd)   (ahcd->flags & OHCI_QUIRK_BE_DESC)
 498 #else
 499 #define big_endian_desc(ahcd)   1               /* only big endian */
 500 #endif
 501 #else
 502 #define big_endian_desc(ahcd)   0               /* only little endian */
 503 #endif
 504
 505 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 506 #ifdef CONFIG_USB_ADMHC_LITTLE_ENDIAN
 507 #define big_endian_mmio(ahcd)   (ahcd->flags & OHCI_QUIRK_BE_MMIO)
 508 #else
 509 #define big_endian_mmio(ahcd)   1               /* only big endian */
 510 #endif
 511 #else
 512 #define big_endian_mmio(ahcd)   0               /* only little endian */
 513 #endif
 514
 515 /*
 516  * Big-endian read/write functions are arch-specific.
 517  * Other arches can be added if/when they're needed.
 518  *
 519  * REVISIT: arch/powerpc now has readl/writel_be, so the
 520  * definition below can die once the STB04xxx support is
 521  * finally ported over.
 522  */
 523 #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
 524 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 525 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 526 #endif
 527
 528 static inline unsigned int admhc_readl(const struct admhcd *ahcd,
 529         __hc32 __iomem *regs)
 530 {
 531 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 532         return big_endian_mmio(ahcd) ?
 533                 readl_be(regs) :
 534                 readl(regs);
 535 #else
 536         return readl(regs);
 537 #endif
 538 }
 539
 540 static inline void admhc_writel(const struct admhcd *ahcd,
 541         const unsigned int val, __hc32 __iomem *regs)
 542 {
 543 #ifdef CONFIG_USB_ADMHC_BIG_ENDIAN_MMIO
 544         big_endian_mmio(ahcd) ?
 545                 writel_be(val, regs) :
 546                 writel(val, regs);
 547 #else
 548                 writel(val, regs);
 549 #endif
 550 }
 551
 552 /*-------------------------------------------------------------------------*/
 553
 554 /* cpu to ahcd */
 555 static inline __hc16 cpu_to_hc16(const struct admhcd *ahcd, const u16 x)
 556 {
 557         return big_endian_desc(ahcd) ?
 558                 (__force __hc16)cpu_to_be16(x) :
 559                 (__force __hc16)cpu_to_le16(x);
 560 }
 561
 562 static inline __hc16 cpu_to_hc16p(const struct admhcd *ahcd, const u16 *x)
 563 {
 564         return big_endian_desc(ahcd) ?
 565                 cpu_to_be16p(x) :
 566                 cpu_to_le16p(x);
 567 }
 568
 569 static inline __hc32 cpu_to_hc32(const struct admhcd *ahcd, const u32 x)
 570 {
 571         return big_endian_desc(ahcd) ?
 572                 (__force __hc32)cpu_to_be32(x) :
 573                 (__force __hc32)cpu_to_le32(x);
 574 }
 575
 576 static inline __hc32 cpu_to_hc32p(const struct admhcd *ahcd, const u32 *x)
 577 {
 578         return big_endian_desc(ahcd) ?
 579                 cpu_to_be32p(x) :
 580                 cpu_to_le32p(x);
 581 }
 582
 583 /* ahcd to cpu */
 584 static inline u16 hc16_to_cpu(const struct admhcd *ahcd, const __hc16 x)
 585 {
 586         return big_endian_desc(ahcd) ?
 587                 be16_to_cpu((__force __be16)x) :
 588                 le16_to_cpu((__force __le16)x);
 589 }
 590
 591 static inline u16 hc16_to_cpup(const struct admhcd *ahcd, const __hc16 *x)
 592 {
 593         return big_endian_desc(ahcd) ?
 594                 be16_to_cpup((__force __be16 *)x) :
 595                 le16_to_cpup((__force __le16 *)x);
 596 }
 597
 598 static inline u32 hc32_to_cpu(const struct admhcd *ahcd, const __hc32 x)
 599 {
 600         return big_endian_desc(ahcd) ?
 601                 be32_to_cpu((__force __be32)x) :
 602                 le32_to_cpu((__force __le32)x);
 603 }
 604
 605 static inline u32 hc32_to_cpup(const struct admhcd *ahcd, const __hc32 *x)
 606 {
 607         return big_endian_desc(ahcd) ?
 608                 be32_to_cpup((__force __be32 *)x) :
 609                 le32_to_cpup((__force __le32 *)x);
 610 }
 611
 612 /*-------------------------------------------------------------------------*/
 613
 614 static inline u16 admhc_frame_no(const struct admhcd *ahcd)
 615 {
 616         u32     t;
 617
 618         t = admhc_readl(ahcd, &ahcd->regs->fmnumber) & ADMHC_SFN_FN_MASK;
 619         return (u16)t;
 620 }
 621
 622 static inline u16 admhc_frame_remain(const struct admhcd *ahcd)
 623 {
 624         u32     t;
 625
 626         t = admhc_readl(ahcd, &ahcd->regs->fmnumber) >> ADMHC_SFN_FR_SHIFT;
 627         t &= ADMHC_SFN_FR_MASK;
 628         return (u16)t;
 629 }
 630
 631 /*-------------------------------------------------------------------------*/
 632
 633 static inline void admhc_disable(struct admhcd *ahcd)
 634 {
 635         admhcd_to_hcd(ahcd)->state = HC_STATE_HALT;
 636 }
 637
 638 #define FI                      0x2edf          /* 12000 bits per frame (-1) */
 639 #define FSLDP(fi)               (0x7fff & ((6 * ((fi) - 1200)) / 7))
 640 #define FIT                     ADMHC_SFI_FIT
 641 #define LSTHRESH                0x628           /* lowspeed bit threshold */
 642
 643 static inline void periodic_reinit(struct admhcd *ahcd)
 644 {
 645         u32     fit = admhc_readl(ahcd, &ahcd->regs->fminterval) & FIT;
 646
 647         /* TODO: adjust FSLargestDataPacket value too? */
 648         admhc_writel(ahcd, (fit ^ FIT) | ahcd->fminterval,
 649                                         &ahcd->regs->fminterval);
 650 }
 651
 652 static inline u32 admhc_read_rhdesc(struct admhcd *ahcd)
 653 {
 654         return admhc_readl(ahcd, &ahcd->regs->rhdesc);
 655 }
 656
 657 static inline u32 admhc_read_portstatus(struct admhcd *ahcd, int port)
 658 {
 659         return admhc_readl(ahcd, &ahcd->regs->portstatus[port]);
 660 }
 661
 662 static inline void admhc_write_portstatus(struct admhcd *ahcd, int port,
 663                 u32 value)
 664 {
 665         admhc_writel(ahcd, value, &ahcd->regs->portstatus[port]);
 666 }
 667
 668 static inline void roothub_write_status(struct admhcd *ahcd, u32 value)
 669 {
 670         /* FIXME: read-only bits must be masked out */
 671         admhc_writel(ahcd, value, &ahcd->regs->rhdesc);
 672 }
 673
 674 static inline void admhc_intr_disable(struct admhcd *ahcd, u32 ints)
 675 {
 676         u32     t;
 677
 678         t = admhc_readl(ahcd, &ahcd->regs->int_enable);
 679         t &= ~(ints);
 680         admhc_writel(ahcd, t, &ahcd->regs->int_enable);
 681         /* TODO: flush writes ?*/
 682 }
 683
 684 static inline void admhc_intr_enable(struct admhcd *ahcd, u32 ints)
 685 {
 686         u32     t;
 687
 688         t = admhc_readl(ahcd, &ahcd->regs->int_enable);
 689         t |= ints;
 690         admhc_writel(ahcd, t, &ahcd->regs->int_enable);
 691         /* TODO: flush writes ?*/
 692 }
 693
 694 static inline void admhc_intr_ack(struct admhcd *ahcd, u32 ints)
 695 {
 696         admhc_writel(ahcd, ints, &ahcd->regs->int_status);
 697 }
 698
 699 static inline void admhc_dma_enable(struct admhcd *ahcd)
 700 {
 701         u32 t;
 702
 703         t = admhc_readl(ahcd, &ahcd->regs->host_control);
 704         if (t & ADMHC_HC_DMAE)
 705                 return;
 706
 707         t |= ADMHC_HC_DMAE;
 708         admhc_writel(ahcd, t, &ahcd->regs->host_control);
 709         admhc_vdbg(ahcd,"DMA enabled\n");
 710 }
 711
 712 static inline void admhc_dma_disable(struct admhcd *ahcd)
 713 {
 714         u32 t;
 715
 716         t = admhc_readl(ahcd, &ahcd->regs->host_control);
 717         if (!(t & ADMHC_HC_DMAE))
 718                 return;
 719
 720         t &= ~ADMHC_HC_DMAE;
 721         admhc_writel(ahcd, t, &ahcd->regs->host_control);
 722         admhc_vdbg(ahcd,"DMA disabled\n");
 723 }