USR8200 changes
[openwrt.git] / target / linux / ppc40x / patches / 004-acadia_cuboot.patch
1 --- a/arch/powerpc/boot/Makefile
2 +++ b/arch/powerpc/boot/Makefile
3 @@ -68,7 +68,8 @@ src-plat := of.c cuboot-52xx.c cuboot-82
4 fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
5 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
6 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
7 - virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c
8 + virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
9 + cuboot-acadia.c
10 src-boot := $(src-wlib) $(src-plat) empty.c
11
12 src-boot := $(addprefix $(obj)/, $(src-boot))
13 @@ -211,6 +212,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImag
14 # Board ports in arch/powerpc/platform/40x/Kconfig
15 image-$(CONFIG_EP405) += dtbImage.ep405
16 image-$(CONFIG_WALNUT) += treeImage.walnut
17 +image-$(CONFIG_ACADIA) += cuImage.acadia
18
19 # Board ports in arch/powerpc/platform/44x/Kconfig
20 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
21 --- /dev/null
22 +++ b/arch/powerpc/boot/cuboot-acadia.c
23 @@ -0,0 +1,174 @@
24 +/*
25 + * Old U-boot compatibility for Acadia
26 + *
27 + * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
28 + *
29 + * Copyright 2008 IBM Corporation
30 + *
31 + * This program is free software; you can redistribute it and/or modify it
32 + * under the terms of the GNU General Public License version 2 as published
33 + * by the Free Software Foundation.
34 + */
35 +
36 +#include "ops.h"
37 +#include "io.h"
38 +#include "dcr.h"
39 +#include "stdio.h"
40 +#include "4xx.h"
41 +#include "44x.h"
42 +#include "cuboot.h"
43 +
44 +#define TARGET_4xx
45 +#include "ppcboot.h"
46 +
47 +static bd_t bd;
48 +
49 +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
50 +
51 +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
52 +
53 +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
54 +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
55 +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
56 +
57 +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
58 +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
59 +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
60 +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
61 +
62 +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
63 +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
64 +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
65 +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
66 +
67 +static void get_clocks(void)
68 +{
69 + unsigned long sysclk, cpr_plld, cpr_pllc, cpr_primad, plloutb, i;
70 + unsigned long pllFwdDiv, pllFwdDivB, pllFbkDiv, pllPlbDiv, pllExtBusDiv;
71 + unsigned long pllOpbDiv, freqEBC, freqUART, freqOPB;
72 + unsigned long div; /* total divisor udiv * bdiv */
73 + unsigned long umin; /* minimum udiv */
74 + unsigned short diff; /* smallest diff */
75 + unsigned long udiv; /* best udiv */
76 + unsigned short idiff; /* current diff */
77 + unsigned short ibdiv; /* current bdiv */
78 + unsigned long est; /* current estimate */
79 + unsigned long baud;
80 + void *np;
81 +
82 + /* read the sysclk value from the CPLD */
83 + sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;
84 +
85 + /*
86 + * Read PLL Mode registers
87 + */
88 + cpr_plld = CPR0_READ(DCRN_CPR0_PLLD);
89 + cpr_pllc = CPR0_READ(DCRN_CPR0_PLLC);
90 +
91 + /*
92 + * Determine forward divider A
93 + */
94 + pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16);
95 +
96 + /*
97 + * Determine forward divider B
98 + */
99 + pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8);
100 + if (pllFwdDivB == 0)
101 + pllFwdDivB = 8;
102 +
103 + /*
104 + * Determine FBK_DIV.
105 + */
106 + pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
107 + if (pllFbkDiv == 0)
108 + pllFbkDiv = 256;
109 +
110 + /*
111 + * Read CPR_PRIMAD register
112 + */
113 + cpr_primad = CPR0_READ(DCRN_CPR0_PRIMAD);
114 +
115 + /*
116 + * Determine PLB_DIV.
117 + */
118 + pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16);
119 + if (pllPlbDiv == 0)
120 + pllPlbDiv = 16;
121 +
122 + /*
123 + * Determine EXTBUS_DIV.
124 + */
125 + pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK);
126 + if (pllExtBusDiv == 0)
127 + pllExtBusDiv = 16;
128 +
129 + /*
130 + * Determine OPB_DIV.
131 + */
132 + pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8);
133 + if (pllOpbDiv == 0)
134 + pllOpbDiv = 16;
135 +
136 + /* There is a bug in U-Boot that prevents us from using
137 + * bd.bi_opbfreq because U-Boot doesn't populate it for
138 + * 405EZ. We get to calculate it, yay!
139 + */
140 + freqOPB = (sysclk *pllFbkDiv) /pllOpbDiv;
141 +
142 + freqEBC = (sysclk * pllFbkDiv) / pllExtBusDiv;
143 +
144 + plloutb = ((sysclk * ((cpr_pllc & PLLC_SRC_MASK) ?
145 + pllFwdDivB : pllFwdDiv) *
146 + pllFbkDiv) / pllFwdDivB);
147 +
148 + np = find_node_by_alias("serial0");
149 + if (getprop(np, "current-speed", &baud, sizeof(baud)) != sizeof(baud))
150 + fatal("no current-speed property\n\r");
151 +
152 + udiv = 256; /* Assume lowest possible serial clk */
153 + div = plloutb / (16 * baud); /* total divisor */
154 + umin = (plloutb / freqOPB) << 1; /* 2 x OPB divisor */
155 + diff = 256; /* highest possible */
156 +
157 + /* i is the test udiv value -- start with the largest
158 + * possible (256) to minimize serial clock and constrain
159 + * search to umin.
160 + */
161 + for (i = 256; i > umin; i--) {
162 + ibdiv = div / i;
163 + est = i * ibdiv;
164 + idiff = (est > div) ? (est-div) : (div-est);
165 + if (idiff == 0) {
166 + udiv = i;
167 + break; /* can't do better */
168 + } else if (idiff < diff) {
169 + udiv = i; /* best so far */
170 + diff = idiff; /* update lowest diff*/
171 + }
172 + }
173 + freqUART = plloutb / udiv;
174 +
175 + dt_fixup_cpu_clocks(bd.bi_procfreq, bd.bi_intfreq, bd.bi_plb_busfreq);
176 + dt_fixup_clock("/plb/ebc", freqEBC);
177 + dt_fixup_clock("/plb/opb", freqOPB);
178 + dt_fixup_clock("/plb/opb/serial@ef600300", freqUART);
179 + dt_fixup_clock("/plb/opb/serial@ef600400", freqUART);
180 +}
181 +
182 +static void acadia_fixups(void)
183 +{
184 + dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
185 + get_clocks();
186 + dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
187 +}
188 +
189 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
190 + unsigned long r6, unsigned long r7)
191 +{
192 + CUBOOT_INIT();
193 + platform_ops.fixups = acadia_fixups;
194 + platform_ops.exit = ibm40x_dbcr_reset;
195 + fdt_init(_dtb_start);
196 + serial_console_init();
197 +}
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