target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h

   1 #ifndef BCM63XX_CPU_H_
   2 #define BCM63XX_CPU_H_
   3
   4 #include <linux/types.h>
   5 #include <linux/init.h>
   6
   7 #include <bcm63xx_regs.h>
   8
   9 /*
  10  * Macro to fetch bcm63xx cpu id and revision, should be optimized at
  11  * compile time if only one CPU support is enabled (idea stolen from
  12  * arm mach-types)
  13  */
  14 #define BCM6338_CPU_ID          0x6338
  15 #define BCM6348_CPU_ID          0x6348
  16 #define BCM6358_CPU_ID          0x6358
  17
  18 void __init bcm63xx_cpu_init(void);
  19 u16 __bcm63xx_get_cpu_id(void);
  20 u16 bcm63xx_get_cpu_rev(void);
  21 unsigned int bcm63xx_get_cpu_freq(void);
  22
  23 #ifdef CONFIG_BCM63XX_CPU_6338
  24 # ifdef bcm63xx_get_cpu_id
  25 #  undef bcm63xx_get_cpu_id
  26 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  27 #  define BCMCPU_RUNTIME_DETECT
  28 # else
  29 #  define bcm63xx_get_cpu_id()  BCM6338_CPU_ID
  30 # endif
  31 # define BCMCPU_IS_6338()       (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
  32 #else
  33 # define BCMCPU_IS_6338()       (0)
  34 #endif
  35
  36 #ifdef CONFIG_BCM63XX_CPU_6348
  37 # ifdef bcm63xx_get_cpu_id
  38 #  undef bcm63xx_get_cpu_id
  39 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  40 #  define BCMCPU_RUNTIME_DETECT
  41 # else
  42 #  define bcm63xx_get_cpu_id()  BCM6348_CPU_ID
  43 # endif
  44 # define BCMCPU_IS_6348()       (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
  45 #else
  46 # define BCMCPU_IS_6348()       (0)
  47 #endif
  48
  49 #ifdef CONFIG_BCM63XX_CPU_6358
  50 # ifdef bcm63xx_get_cpu_id
  51 #  undef bcm63xx_get_cpu_id
  52 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  53 #  define BCMCPU_RUNTIME_DETECT
  54 # else
  55 #  define bcm63xx_get_cpu_id()  BCM6358_CPU_ID
  56 # endif
  57 # define BCMCPU_IS_6358()       (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
  58 #else
  59 # define BCMCPU_IS_6358()       (0)
  60 #endif
  61
  62 #ifndef bcm63xx_get_cpu_id
  63 #error "No CPU support configured"
  64 #endif
  65
  66 /*
  67  * While registers sets are (mostly) the same across 63xx CPU, base
  68  * address of these sets do change.
  69  */
  70 enum bcm63xx_regs_set {
  71         RSET_DSL_LMEM = 0,
  72         RSET_PERF,
  73         RSET_TIMER,
  74         RSET_WDT,
  75         RSET_UART0,
  76         RSET_GPIO,
  77         RSET_SPI,
  78         RSET_UDC0,
  79         RSET_OHCI0,
  80         RSET_OHCI_PRIV,
  81         RSET_USBH_PRIV,
  82         RSET_MPI,
  83         RSET_PCMCIA,
  84         RSET_DSL,
  85         RSET_ENET0,
  86         RSET_ENET1,
  87         RSET_ENETDMA,
  88         RSET_EHCI0,
  89         RSET_SDRAM,
  90         RSET_MEMC,
  91         RSET_DDR,
  92 };
  93
  94 #define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
  95 #define RSET_DSL_SIZE                   4096
  96 #define RSET_WDT_SIZE                   12
  97 #define RSET_ENET_SIZE                  2048
  98 #define RSET_ENETDMA_SIZE               2048
  99 #define RSET_UART_SIZE                  24
 100 #define RSET_SPI_SIZE                   256
 101 #define RSET_UDC_SIZE                   256
 102 #define RSET_OHCI_SIZE                  256
 103 #define RSET_EHCI_SIZE                  256
 104 #define RSET_PCMCIA_SIZE                12
 105
 106 /*
 107  * 6338 register sets base address
 108  */
 109
 110 #define BCM_6338_PERF_BASE              (0xfffe0000)
 111 #define BCM_6338_BB_BASE                (0xfffe0100) /* bus bridge registers */
 112 #define BCM_6338_TIMER_BASE             (0xfffe0200)
 113 #define BCM_6338_WDT_BASE               (0xfffe021c)
 114 #define BCM_6338_UART0_BASE             (0xfffe0300)
 115 #define BCM_6338_GPIO_BASE              (0xfffe0400)
 116 #define BCM_6338_SPI_BASE               (0xfffe0c00)
 117 #define BCM_6338_DSL_BASE               (0xfffe1000)
 118 #define BCM_6338_SAR_BASE               (0xfffe2000)
 119 #define BCM_6338_ENETDMA_BASE           (0xfffe2400)
 120 #define BCM_6338_USBDMA_BASE            (0xfffe2400)
 121 #define BCM_6338_ENET0_BASE             (0xfffe2800)
 122 #define BCM_6338_UDC0_BASE              (0xfffe3000) /* USB_CTL_BASE */
 123 #define BCM_6338_MEMC_BASE              (0xfffe3100)
 124
 125 /*
 126  * 6348 register sets base address
 127  */
 128 #define BCM_6348_DSL_LMEM_BASE          (0xfff00000)
 129 #define BCM_6348_PERF_BASE              (0xfffe0000)
 130 #define BCM_6348_BB_BASE                (0xfffe0100) /* bus bridge registers */
 131 #define BCM_6348_TIMER_BASE             (0xfffe0200)
 132 #define BCM_6348_WDT_BASE               (0xfffe021c)
 133 #define BCM_6348_UART0_BASE             (0xfffe0300)
 134 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 135 #define BCM_6348_SPI_BASE               (0xfffe0c00)
 136 #define BCM_6348_UDC0_BASE              (0xfffe1000)
 137 #define BCM_6348_USBDMA_BASE            (0xfffe1400)
 138 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 139 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
 140 #define BCM_6348_USBH_PRIV_BASE         (0xdeadbeef)
 141 #define BCM_6348_MPI_BASE               (0xfffe2000)
 142 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
 143 #define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
 144 #define BCM_6348_DSL_BASE               (0xfffe3000)
 145 #define BCM_6348_SAR_BASE               (0xfffe4000)
 146 #define BCM_6348_UBUS_BASE              (0xfffe5000)
 147 #define BCM_6348_ENET0_BASE             (0xfffe6000)
 148 #define BCM_6348_ENET1_BASE             (0xfffe6800)
 149 #define BCM_6348_ENETDMA_BASE           (0xfffe7000)
 150 #define BCM_6348_EHCI0_BASE             (0xdeadbeef)
 151 #define BCM_6348_SDRAM_BASE             (0xfffe2300)
 152 #define BCM_6348_MEMC_BASE              (0xdeadbeef)
 153 #define BCM_6348_DDR_BASE               (0xdeadbeef)
 154
 155 /*
 156  * 6358 register sets base address
 157  */
 158 #define BCM_6358_DSL_LMEM_BASE          (0xfff00000)
 159 #define BCM_6358_PERF_BASE              (0xfffe0000)
 160 #define BCM_6358_TIMER_BASE             (0xfffe0040)
 161 #define BCM_6358_WDT_BASE               (0xfffe005c)
 162 #define BCM_6358_GPIO_BASE              (0xfffe0080)
 163 #define BCM_6358_UART0_BASE             (0xfffe0100)
 164 #define BCM_6358_UDC0_BASE              (0xfffe0400)
 165 #define BCM_6358_SPI_BASE               (0xfffe0800)
 166 #define BCM_6358_MPI_BASE               (0xfffe1000)
 167 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
 168 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 169 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
 170 #define BCM_6358_USBH_PRIV_BASE         (0xfffe1500)
 171 #define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
 172 #define BCM_6358_DSL_BASE               (0xfffe3000)
 173 #define BCM_6358_ENET0_BASE             (0xfffe4000)
 174 #define BCM_6358_ENET1_BASE             (0xfffe4800)
 175 #define BCM_6358_ENETDMA_BASE           (0xfffe5000)
 176 #define BCM_6358_EHCI0_BASE             (0xfffe1300)
 177 #define BCM_6358_SDRAM_BASE             (0xdeadbeef)
 178 #define BCM_6358_MEMC_BASE              (0xfffe1200)
 179 #define BCM_6358_DDR_BASE               (0xfffe12a0)
 180
 181
 182 extern const unsigned long *bcm63xx_regs_base;
 183
 184 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 185 {
 186 #ifdef BCMCPU_RUNTIME_DETECT
 187         return bcm63xx_regs_base[set];
 188 #else
 189 #ifdef CONFIG_BCM63XX_CPU_6338
 190         switch (set) {
 191         case RSET_PERF:
 192                 return BCM_6338_PERF_BASE;
 193         case RSET_TIMER:
 194                 return BCM_6338_TIMER_BASE;
 195         case RSET_WDT:
 196                 return BCM_6338_WDT_BASE;
 197         case RSET_UART0:
 198                 return BCM_6338_UART0_BASE;
 199         case RSET_GPIO:
 200                 return BCM_6338_GPIO_BASE;
 201         case RSET_SPI:
 202                 return BCM_6338_SPI_BASE;
 203         case RSET_MEMC:
 204                 return BCM_6338_MEMC_BASE;
 205         }
 206 #endif
 207 #ifdef CONFIG_BCM63XX_CPU_6348
 208         switch (set) {
 209         case RSET_DSL_LMEM:
 210                 return BCM_6348_DSL_LMEM_BASE;
 211         case RSET_PERF:
 212                 return BCM_6348_PERF_BASE;
 213         case RSET_TIMER:
 214                 return BCM_6348_TIMER_BASE;
 215         case RSET_WDT:
 216                 return BCM_6348_WDT_BASE;
 217         case RSET_UART0:
 218                 return BCM_6348_UART0_BASE;
 219         case RSET_GPIO:
 220                 return BCM_6348_GPIO_BASE;
 221         case RSET_SPI:
 222                 return BCM_6348_SPI_BASE;
 223         case RSET_UDC0:
 224                 return BCM_6348_UDC0_BASE;
 225         case RSET_OHCI0:
 226                 return BCM_6348_OHCI0_BASE;
 227         case RSET_OHCI_PRIV:
 228                 return BCM_6348_OHCI_PRIV_BASE;
 229         case RSET_USBH_PRIV:
 230                 return BCM_6348_USBH_PRIV_BASE;
 231         case RSET_MPI:
 232                 return BCM_6348_MPI_BASE;
 233         case RSET_PCMCIA:
 234                 return BCM_6348_PCMCIA_BASE;
 235         case RSET_DSL:
 236                 return BCM_6348_DSL_BASE;
 237         case RSET_ENET0:
 238                 return BCM_6348_ENET0_BASE;
 239         case RSET_ENET1:
 240                 return BCM_6348_ENET1_BASE;
 241         case RSET_ENETDMA:
 242                 return BCM_6348_ENETDMA_BASE;
 243         case RSET_EHCI0:
 244                 return BCM_6348_EHCI0_BASE;
 245         case RSET_SDRAM:
 246                 return BCM_6348_SDRAM_BASE;
 247         case RSET_MEMC:
 248                 return BCM_6348_MEMC_BASE;
 249         case RSET_DDR:
 250                 return BCM_6348_DDR_BASE;
 251         }
 252 #endif
 253 #ifdef CONFIG_BCM63XX_CPU_6358
 254         switch (set) {
 255         case RSET_DSL_LMEM:
 256                 return BCM_6358_DSL_LMEM_BASE;
 257         case RSET_PERF:
 258                 return BCM_6358_PERF_BASE;
 259         case RSET_TIMER:
 260                 return BCM_6358_TIMER_BASE;
 261         case RSET_WDT:
 262                 return BCM_6358_WDT_BASE;
 263         case RSET_UART0:
 264                 return BCM_6358_UART0_BASE;
 265         case RSET_GPIO:
 266                 return BCM_6358_GPIO_BASE;
 267         case RSET_SPI:
 268                 return BCM_6358_SPI_BASE;
 269         case RSET_UDC0:
 270                 return BCM_6358_UDC0_BASE;
 271         case RSET_OHCI0:
 272                 return BCM_6358_OHCI0_BASE;
 273         case RSET_OHCI_PRIV:
 274                 return BCM_6358_OHCI_PRIV_BASE;
 275         case RSET_USBH_PRIV:
 276                 return BCM_6358_USBH_PRIV_BASE;
 277         case RSET_MPI:
 278                 return BCM_6358_MPI_BASE;
 279         case RSET_PCMCIA:
 280                 return BCM_6358_PCMCIA_BASE;
 281         case RSET_ENET0:
 282                 return BCM_6358_ENET0_BASE;
 283         case RSET_ENET1:
 284                 return BCM_6358_ENET1_BASE;
 285         case RSET_ENETDMA:
 286                 return BCM_6358_ENETDMA_BASE;
 287         case RSET_DSL:
 288                 return BCM_6358_DSL_BASE;
 289         case RSET_EHCI0:
 290                 return BCM_6358_EHCI0_BASE;
 291         case RSET_SDRAM:
 292                 return BCM_6358_SDRAM_BASE;
 293         case RSET_MEMC:
 294                 return BCM_6358_MEMC_BASE;
 295         case RSET_DDR:
 296                 return BCM_6358_DDR_BASE;
 297         }
 298 #endif
 299 #endif
 300         /* unreached */
 301         return 0;
 302 }
 303
 304 /*
 305  * SPI register layout is not compatible
 306  * accross CPU versions but it is software
 307  * compatible
 308  */
 309
 310 enum bcm63xx_regs_spi {
 311         SPI_CMD,
 312         SPI_INT_STATUS,
 313         SPI_INT_MASK_ST,
 314         SPI_INT_MASK,
 315         SPI_ST,
 316         SPI_CLK_CFG,
 317         SPI_FILL_BYTE,
 318         SPI_MSG_TAIL,
 319         SPI_RX_TAIL,
 320         SPI_MSG_CTL,
 321         SPI_MSG_DATA,
 322         SPI_RX_DATA,
 323 };
 324
 325 extern const unsigned long *bcm63xx_regs_spi;
 326
 327 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 328 {
 329 #ifdef BCMCPU_RUNTIME_DETECT
 330         return bcm63xx_regs_spi[reg];
 331 #else
 332 #ifdef CONFIG_BCM63XX_CPU_6338
 333 switch (reg) {
 334         case SPI_CMD:
 335                 return SPI_BCM_6338_SPI_CMD;
 336         case SPI_INT_STATUS:
 337                 return SPI_BCM_6338_SPI_INT_STATUS;
 338         case SPI_INT_MASK_ST:
 339                 return SPI_BCM_6338_SPI_MASK_INT_ST;
 340         case SPI_INT_MASK:
 341                 return SPI_BCM_6338_SPI_INT_MASK;
 342         case SPI_ST:
 343                 return SPI_BCM_6338_SPI_ST;
 344         case SPI_CLK_CFG:
 345                 return SPI_BCM_6338_SPI_CLK_CFG;
 346         case SPI_FILL_BYTE:
 347                 return SPI_BCM_6338_SPI_FILL_BYTE;
 348         case SPI_MSG_TAIL:
 349                 return SPI_BCM_6338_SPI_MSG_TAIL;
 350         case SPI_RX_TAIL:
 351                 return SPI_BCM_6338_SPI_RX_TAIL;
 352         case SPI_MSG_CTL:
 353                 return SPI_BCM_6338_SPI_MSG_CTL;
 354         case SPI_MSG_DATA:
 355                 return SPI_BCM_6338_SPI_MSG_DATA;
 356         case SPI_RX_DATA:
 357                 return SPI_BCM_6338_SPI_RX_DATA;
 358 }
 359 #endif
 360 #ifdef CONFIG_BCM63XX_CPU_6348
 361 switch (reg) {
 362         case SPI_CMD:
 363                 return SPI_BCM_6348_SPI_CMD;
 364         case SPI_INT_MASK_ST:
 365                 return SPI_BCM_6348_SPI_MASK_INT_ST;
 366         case SPI_INT_MASK:
 367                 return SPI_BCM_6348_SPI_INT_MASK;
 368         case SPI_INT_STATUS:
 369                 return SPI_BCM_6348_SPI_INT_STATUS;
 370         case SPI_ST:
 371                 return SPI_BCM_6348_SPI_ST;
 372         case SPI_CLK_CFG:
 373                 return SPI_BCM_6348_SPI_CLK_CFG;
 374         case SPI_FILL_BYTE:
 375                 return SPI_BCM_6348_SPI_FILL_BYTE;
 376         case SPI_MSG_TAIL:
 377                 return SPI_BCM_6348_SPI_MSG_TAIL;
 378         case SPI_RX_TAIL:
 379                 return SPI_BCM_6348_SPI_RX_TAIL;
 380         case SPI_MSG_CTL:
 381                 return SPI_BCM_6348_SPI_MSG_CTL;
 382         case SPI_MSG_DATA:
 383                 return SPI_BCM_6348_SPI_MSG_DATA;
 384         case SPI_RX_DATA:
 385                 return SPI_BCM_6348_SPI_RX_DATA;
 386 }
 387 #endif
 388 #ifdef CONFIG_BCM63XX_CPU_6358
 389 switch (reg) {
 390         case SPI_CMD:
 391                 return SPI_BCM_6358_SPI_CMD;
 392         case SPI_INT_STATUS:
 393                 return SPI_BCM_6358_SPI_INT_STATUS;
 394         case SPI_INT_MASK_ST:
 395                 return SPI_BCM_6358_SPI_MASK_INT_ST;
 396         case SPI_INT_MASK:
 397                 return SPI_BCM_6358_SPI_INT_MASK;
 398         case SPI_ST:
 399                 return SPI_BCM_6358_SPI_STATUS;
 400         case SPI_CLK_CFG:
 401                 return SPI_BCM_6358_SPI_CLK_CFG;
 402         case SPI_FILL_BYTE:
 403                 return SPI_BCM_6358_SPI_FILL_BYTE;
 404         case SPI_MSG_TAIL:
 405                 return SPI_BCM_6358_SPI_MSG_TAIL;
 406         case SPI_RX_TAIL:
 407                 return SPI_BCM_6358_SPI_RX_TAIL;
 408         case SPI_MSG_CTL:
 409                 return SPI_BCM_6358_MSG_CTL;
 410         case SPI_MSG_DATA:
 411                 return SPI_BCM_6358_SPI_MSG_DATA;
 412         case SPI_RX_DATA:
 413                 return SPI_BCM_6358_SPI_RX_DATA;
 414 }
 415 #endif
 416 #endif
 417         return 0;
 418 }
 419
 420 /*
 421  * IRQ number changes across CPU too
 422  */
 423 enum bcm63xx_irq {
 424         IRQ_TIMER = 0,
 425         IRQ_UART0,
 426         IRQ_SPI,
 427         IRQ_DSL,
 428         IRQ_UDC0,
 429         IRQ_ENET0,
 430         IRQ_ENET1,
 431         IRQ_ENET_PHY,
 432         IRQ_OHCI0,
 433         IRQ_EHCI0,
 434         IRQ_PCMCIA0,
 435         IRQ_ENET0_RXDMA,
 436         IRQ_ENET0_TXDMA,
 437         IRQ_ENET1_RXDMA,
 438         IRQ_ENET1_TXDMA,
 439         IRQ_PCI,
 440         IRQ_PCMCIA,
 441 };
 442
 443 /*
 444  * 6338 irqs
 445  */
 446 #define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 447 #define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 448 #define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 449 #define BCM_6338_DG_IRQ                 (IRQ_INTERNAL_BASE + 4)
 450 #define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
 451 #define BCM_6338_ATM_IRQ                (IRQ_INTERNAL_BASE + 6)
 452 #define BCM_6338_UDC0_IRQ               (IRQ_INTERNAL_BASE + 7)
 453 #define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 454 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 455 #define BCM_6338_SDRAM_IRQ              (IRQ_INTERNAL_BASE + 10)
 456 #define BCM_6338_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 11)
 457 #define BCM_6338_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 12)
 458 #define BCM_6338_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13)
 459 #define BCM_6338_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 14)
 460 #define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 461 #define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 462 #define BCM_6338_SDIO_IRQ               (IRQ_INTERNAL_BASE + 17)
 463
 464 /*
 465  * 6348 irqs
 466  */
 467 #define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 468 #define BCM_6348_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 469 #define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 470 #define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
 471 #define BCM_6348_UDC0_IRQ               (IRQ_INTERNAL_BASE + 6)
 472 #define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 473 #define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 474 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 475 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
 476 #define BCM_6348_USB_CNTL_RX_DMA        (IRQ_INTERNAL_BASE + 14)
 477 #define BCM_6348_USB_CNTL_TX_DMA        (IRQ_INTERNAL_BASE + 15)
 478 #define BCM_6348_USB_BULK_RX_DMA        (IRQ_INTERNAL_BASE + 16)
 479 #define BCM_6348_USB_BULK_TX_DMA        (IRQ_INTERNAL_BASE + 17)
 480 #define BCM_6348_USB_ISO_RX_DMA         (IRQ_INTERNAL_BASE + 18)
 481 #define BCM_6348_USB_ISO_TX_DMA         (IRQ_INTERNAL_BASE + 19)
 482 #define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
 483 #define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
 484 #define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
 485 #define BCM_6348_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 23)
 486 #define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 487 #define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
 488
 489 /*
 490  * 6358 irqs
 491  */
 492 #define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 493 #define BCM_6358_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 494 #define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 495 #define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 496 #define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
 497 #define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 498 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 499 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
 500 #define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 501 #define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 502 #define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 503 #define BCM_6358_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
 504 #define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 505 #define BCM_6358_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
 506 #define BCM_6358_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 507
 508 extern const int *bcm63xx_irqs;
 509
 510 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 511 {
 512         return bcm63xx_irqs[irq];
 513 }
 514
 515 /*
 516  * return installed memory size
 517  */
 518 unsigned int bcm63xx_get_memory_size(void);
 519
 520 #endif /* !BCM63XX_CPU_H_ */