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75b24b0043a5688639074bef96f1965245c55976
[openwrt.git] / target / linux / ar71xx / files / arch / mips / ar71xx / devices.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ar71xx/ar71xx.h>
24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
25
26 #include "devices.h"
27
28 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
29
30 static struct resource ar71xx_uart_resources[] = {
31 {
32 .start = AR71XX_UART_BASE,
33 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 };
37
38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
39 static struct plat_serial8250_port ar71xx_uart_data[] = {
40 {
41 .mapbase = AR71XX_UART_BASE,
42 .irq = AR71XX_MISC_IRQ_UART,
43 .flags = AR71XX_UART_FLAGS,
44 .iotype = UPIO_MEM32,
45 .regshift = 2,
46 }, {
47 /* terminating entry */
48 }
49 };
50
51 static struct platform_device ar71xx_uart_device = {
52 .name = "serial8250",
53 .id = PLAT8250_DEV_PLATFORM,
54 .resource = ar71xx_uart_resources,
55 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
56 .dev = {
57 .platform_data = ar71xx_uart_data
58 },
59 };
60
61 static struct resource ar933x_uart_resources[] = {
62 {
63 .start = AR933X_UART_BASE,
64 .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
65 .flags = IORESOURCE_MEM,
66 },
67 {
68 .start = AR71XX_MISC_IRQ_UART,
69 .end = AR71XX_MISC_IRQ_UART,
70 .flags = IORESOURCE_IRQ,
71 },
72 };
73
74 static struct ar933x_uart_platform_data ar933x_uart_data;
75 static struct platform_device ar933x_uart_device = {
76 .name = "ar933x-uart",
77 .id = -1,
78 .resource = ar933x_uart_resources,
79 .num_resources = ARRAY_SIZE(ar933x_uart_resources),
80 .dev = {
81 .platform_data = &ar933x_uart_data,
82 },
83 };
84
85 void __init ar71xx_add_device_uart(void)
86 {
87 struct platform_device *pdev;
88
89 switch (ar71xx_soc) {
90 case AR71XX_SOC_AR7130:
91 case AR71XX_SOC_AR7141:
92 case AR71XX_SOC_AR7161:
93 case AR71XX_SOC_AR7240:
94 case AR71XX_SOC_AR7241:
95 case AR71XX_SOC_AR7242:
96 case AR71XX_SOC_AR9130:
97 case AR71XX_SOC_AR9132:
98 pdev = &ar71xx_uart_device;
99 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
100 break;
101
102 case AR71XX_SOC_AR9330:
103 case AR71XX_SOC_AR9331:
104 pdev = &ar933x_uart_device;
105 ar933x_uart_data.uartclk = ar71xx_ref_freq;
106 break;
107
108 case AR71XX_SOC_AR9341:
109 case AR71XX_SOC_AR9342:
110 case AR71XX_SOC_AR9344:
111 pdev = &ar71xx_uart_device;
112 ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
113 break;
114
115 default:
116 BUG();
117 }
118
119 platform_device_register(pdev);
120 }
121
122 static struct resource ar71xx_mdio0_resources[] = {
123 {
124 .name = "mdio_base",
125 .flags = IORESOURCE_MEM,
126 .start = AR71XX_GE0_BASE,
127 .end = AR71XX_GE0_BASE + 0x200 - 1,
128 }
129 };
130
131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
132
133 struct platform_device ar71xx_mdio0_device = {
134 .name = "ag71xx-mdio",
135 .id = 0,
136 .resource = ar71xx_mdio0_resources,
137 .num_resources = ARRAY_SIZE(ar71xx_mdio0_resources),
138 .dev = {
139 .platform_data = &ar71xx_mdio0_data,
140 },
141 };
142
143 static struct resource ar71xx_mdio1_resources[] = {
144 {
145 .name = "mdio_base",
146 .flags = IORESOURCE_MEM,
147 .start = AR71XX_GE1_BASE,
148 .end = AR71XX_GE1_BASE + 0x200 - 1,
149 }
150 };
151
152 static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
153
154 struct platform_device ar71xx_mdio1_device = {
155 .name = "ag71xx-mdio",
156 .id = 1,
157 .resource = ar71xx_mdio1_resources,
158 .num_resources = ARRAY_SIZE(ar71xx_mdio1_resources),
159 .dev = {
160 .platform_data = &ar71xx_mdio1_data,
161 },
162 };
163
164 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
165 {
166 void __iomem *base;
167 u32 t;
168
169 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
170
171 t = __raw_readl(base + cfg_reg);
172 t &= ~(3 << shift);
173 t |= (2 << shift);
174 __raw_writel(t, base + cfg_reg);
175 udelay(100);
176
177 __raw_writel(pll_val, base + pll_reg);
178
179 t |= (3 << shift);
180 __raw_writel(t, base + cfg_reg);
181 udelay(100);
182
183 t &= ~(3 << shift);
184 __raw_writel(t, base + cfg_reg);
185 udelay(100);
186
187 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
188 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
189
190 iounmap(base);
191 }
192
193 static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
194 unsigned int mii_if)
195 {
196 void __iomem *base;
197 u32 t;
198
199 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
200
201 t = __raw_readl(base + reg);
202 t &= ~(MII_CTRL_IF_MASK);
203 t |= (mii_if & MII_CTRL_IF_MASK);
204 __raw_writel(t, base + reg);
205
206 iounmap(base);
207 }
208
209 static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
210 {
211 void __iomem *base;
212 unsigned int mii_speed;
213 u32 t;
214
215 switch (speed) {
216 case SPEED_10:
217 mii_speed = MII_CTRL_SPEED_10;
218 break;
219 case SPEED_100:
220 mii_speed = MII_CTRL_SPEED_100;
221 break;
222 case SPEED_1000:
223 mii_speed = MII_CTRL_SPEED_1000;
224 break;
225 default:
226 BUG();
227 }
228
229 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
230
231 t = __raw_readl(base + reg);
232 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
233 t |= mii_speed << MII_CTRL_SPEED_SHIFT;
234 __raw_writel(t, base + reg);
235
236 iounmap(base);
237 }
238
239 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
240 {
241 struct platform_device *mdio_dev;
242 struct ag71xx_mdio_platform_data *mdio_data;
243 unsigned int max_id;
244
245 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
246 ar71xx_soc == AR71XX_SOC_AR9342 ||
247 ar71xx_soc == AR71XX_SOC_AR9344)
248 max_id = 1;
249 else
250 max_id = 0;
251
252 if (id > max_id) {
253 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
254 return;
255 }
256
257 switch (ar71xx_soc) {
258 case AR71XX_SOC_AR7241:
259 case AR71XX_SOC_AR9330:
260 case AR71XX_SOC_AR9331:
261 mdio_dev = &ar71xx_mdio1_device;
262 mdio_data = &ar71xx_mdio1_data;
263 break;
264
265 case AR71XX_SOC_AR9341:
266 case AR71XX_SOC_AR9342:
267 case AR71XX_SOC_AR9344:
268 if (id == 0) {
269 mdio_dev = &ar71xx_mdio0_device;
270 mdio_data = &ar71xx_mdio0_data;
271 } else {
272 mdio_dev = &ar71xx_mdio1_device;
273 mdio_data = &ar71xx_mdio1_data;
274 }
275 break;
276
277 case AR71XX_SOC_AR7242:
278 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
279 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
280 AR71XX_ETH0_PLL_SHIFT);
281 /* fall through */
282 default:
283 mdio_dev = &ar71xx_mdio0_device;
284 mdio_data = &ar71xx_mdio0_data;
285 break;
286 }
287
288 mdio_data->phy_mask = phy_mask;
289
290 switch (ar71xx_soc) {
291 case AR71XX_SOC_AR7240:
292 case AR71XX_SOC_AR7241:
293 case AR71XX_SOC_AR9330:
294 case AR71XX_SOC_AR9331:
295 mdio_data->is_ar7240 = 1;
296 break;
297
298 case AR71XX_SOC_AR9341:
299 case AR71XX_SOC_AR9342:
300 case AR71XX_SOC_AR9344:
301 if (id == 1)
302 mdio_data->is_ar7240 = 1;
303 break;
304
305 default:
306 break;
307 }
308
309 platform_device_register(mdio_dev);
310 }
311
312 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
313 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
314
315 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
316 {
317 struct ar71xx_eth_pll_data *pll_data;
318 u32 pll_val;
319
320 switch (mac) {
321 case 0:
322 pll_data = &ar71xx_eth0_pll_data;
323 break;
324 case 1:
325 pll_data = &ar71xx_eth1_pll_data;
326 break;
327 default:
328 BUG();
329 }
330
331 switch (speed) {
332 case SPEED_10:
333 pll_val = pll_data->pll_10;
334 break;
335 case SPEED_100:
336 pll_val = pll_data->pll_100;
337 break;
338 case SPEED_1000:
339 pll_val = pll_data->pll_1000;
340 break;
341 default:
342 BUG();
343 }
344
345 return pll_val;
346 }
347
348 static void ar71xx_set_speed_ge0(int speed)
349 {
350 u32 val = ar71xx_get_eth_pll(0, speed);
351
352 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
353 val, AR71XX_ETH0_PLL_SHIFT);
354 ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
355 }
356
357 static void ar71xx_set_speed_ge1(int speed)
358 {
359 u32 val = ar71xx_get_eth_pll(1, speed);
360
361 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
362 val, AR71XX_ETH1_PLL_SHIFT);
363 ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
364 }
365
366 static void ar724x_set_speed_ge0(int speed)
367 {
368 /* TODO */
369 }
370
371 static void ar724x_set_speed_ge1(int speed)
372 {
373 /* TODO */
374 }
375
376 static void ar7242_set_speed_ge0(int speed)
377 {
378 u32 val = ar71xx_get_eth_pll(0, speed);
379 void __iomem *base;
380
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
383 iounmap(base);
384 }
385
386 static void ar91xx_set_speed_ge0(int speed)
387 {
388 u32 val = ar71xx_get_eth_pll(0, speed);
389
390 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
391 val, AR91XX_ETH0_PLL_SHIFT);
392 ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
393 }
394
395 static void ar91xx_set_speed_ge1(int speed)
396 {
397 u32 val = ar71xx_get_eth_pll(1, speed);
398
399 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
400 val, AR91XX_ETH1_PLL_SHIFT);
401 ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
402 }
403
404 static void ar933x_set_speed_ge0(int speed)
405 {
406 /* TODO */
407 }
408
409 static void ar933x_set_speed_ge1(int speed)
410 {
411 /* TODO */
412 }
413
414 static void ar934x_set_speed_ge0(int speed)
415 {
416 /* TODO */
417 }
418
419 static void ar934x_set_speed_ge1(int speed)
420 {
421 /* TODO */
422 }
423
424 static void ar71xx_ddr_flush_ge0(void)
425 {
426 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
427 }
428
429 static void ar71xx_ddr_flush_ge1(void)
430 {
431 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
432 }
433
434 static void ar724x_ddr_flush_ge0(void)
435 {
436 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
437 }
438
439 static void ar724x_ddr_flush_ge1(void)
440 {
441 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
442 }
443
444 static void ar91xx_ddr_flush_ge0(void)
445 {
446 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
447 }
448
449 static void ar91xx_ddr_flush_ge1(void)
450 {
451 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
452 }
453
454 static void ar933x_ddr_flush_ge0(void)
455 {
456 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
457 }
458
459 static void ar933x_ddr_flush_ge1(void)
460 {
461 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
462 }
463
464 static void ar934x_ddr_flush_ge0(void)
465 {
466 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
467 }
468
469 static void ar934x_ddr_flush_ge1(void)
470 {
471 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
472 }
473
474 static struct resource ar71xx_eth0_resources[] = {
475 {
476 .name = "mac_base",
477 .flags = IORESOURCE_MEM,
478 .start = AR71XX_GE0_BASE,
479 .end = AR71XX_GE0_BASE + 0x200 - 1,
480 }, {
481 .name = "mac_irq",
482 .flags = IORESOURCE_IRQ,
483 .start = AR71XX_CPU_IRQ_GE0,
484 .end = AR71XX_CPU_IRQ_GE0,
485 },
486 };
487
488 struct ag71xx_platform_data ar71xx_eth0_data = {
489 .reset_bit = RESET_MODULE_GE0_MAC,
490 };
491
492 struct platform_device ar71xx_eth0_device = {
493 .name = "ag71xx",
494 .id = 0,
495 .resource = ar71xx_eth0_resources,
496 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
497 .dev = {
498 .platform_data = &ar71xx_eth0_data,
499 },
500 };
501
502 static struct resource ar71xx_eth1_resources[] = {
503 {
504 .name = "mac_base",
505 .flags = IORESOURCE_MEM,
506 .start = AR71XX_GE1_BASE,
507 .end = AR71XX_GE1_BASE + 0x200 - 1,
508 }, {
509 .name = "mac_irq",
510 .flags = IORESOURCE_IRQ,
511 .start = AR71XX_CPU_IRQ_GE1,
512 .end = AR71XX_CPU_IRQ_GE1,
513 },
514 };
515
516 struct ag71xx_platform_data ar71xx_eth1_data = {
517 .reset_bit = RESET_MODULE_GE1_MAC,
518 };
519
520 struct platform_device ar71xx_eth1_device = {
521 .name = "ag71xx",
522 .id = 1,
523 .resource = ar71xx_eth1_resources,
524 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
525 .dev = {
526 .platform_data = &ar71xx_eth1_data,
527 },
528 };
529
530 struct ag71xx_switch_platform_data ar71xx_switch_data;
531
532 #define AR71XX_PLL_VAL_1000 0x00110000
533 #define AR71XX_PLL_VAL_100 0x00001099
534 #define AR71XX_PLL_VAL_10 0x00991099
535
536 #define AR724X_PLL_VAL_1000 0x00110000
537 #define AR724X_PLL_VAL_100 0x00001099
538 #define AR724X_PLL_VAL_10 0x00991099
539
540 #define AR7242_PLL_VAL_1000 0x16000000
541 #define AR7242_PLL_VAL_100 0x00000101
542 #define AR7242_PLL_VAL_10 0x00001616
543
544 #define AR91XX_PLL_VAL_1000 0x1a000000
545 #define AR91XX_PLL_VAL_100 0x13000a44
546 #define AR91XX_PLL_VAL_10 0x00441099
547
548 #define AR933X_PLL_VAL_1000 0x00110000
549 #define AR933X_PLL_VAL_100 0x00001099
550 #define AR933X_PLL_VAL_10 0x00991099
551
552 #define AR934X_PLL_VAL_1000 0x00110000
553 #define AR934X_PLL_VAL_100 0x00001099
554 #define AR934X_PLL_VAL_10 0x00991099
555
556 static void __init ar71xx_init_eth_pll_data(unsigned int id)
557 {
558 struct ar71xx_eth_pll_data *pll_data;
559 u32 pll_10, pll_100, pll_1000;
560
561 switch (id) {
562 case 0:
563 pll_data = &ar71xx_eth0_pll_data;
564 break;
565 case 1:
566 pll_data = &ar71xx_eth1_pll_data;
567 break;
568 default:
569 BUG();
570 }
571
572 switch (ar71xx_soc) {
573 case AR71XX_SOC_AR7130:
574 case AR71XX_SOC_AR7141:
575 case AR71XX_SOC_AR7161:
576 pll_10 = AR71XX_PLL_VAL_10;
577 pll_100 = AR71XX_PLL_VAL_100;
578 pll_1000 = AR71XX_PLL_VAL_1000;
579 break;
580
581 case AR71XX_SOC_AR7240:
582 case AR71XX_SOC_AR7241:
583 pll_10 = AR724X_PLL_VAL_10;
584 pll_100 = AR724X_PLL_VAL_100;
585 pll_1000 = AR724X_PLL_VAL_1000;
586 break;
587
588 case AR71XX_SOC_AR7242:
589 pll_10 = AR7242_PLL_VAL_10;
590 pll_100 = AR7242_PLL_VAL_100;
591 pll_1000 = AR7242_PLL_VAL_1000;
592 break;
593
594 case AR71XX_SOC_AR9130:
595 case AR71XX_SOC_AR9132:
596 pll_10 = AR91XX_PLL_VAL_10;
597 pll_100 = AR91XX_PLL_VAL_100;
598 pll_1000 = AR91XX_PLL_VAL_1000;
599 break;
600
601 case AR71XX_SOC_AR9330:
602 case AR71XX_SOC_AR9331:
603 pll_10 = AR933X_PLL_VAL_10;
604 pll_100 = AR933X_PLL_VAL_100;
605 pll_1000 = AR933X_PLL_VAL_1000;
606 break;
607
608 case AR71XX_SOC_AR9341:
609 case AR71XX_SOC_AR9342:
610 case AR71XX_SOC_AR9344:
611 pll_10 = AR934X_PLL_VAL_10;
612 pll_100 = AR934X_PLL_VAL_100;
613 pll_1000 = AR934X_PLL_VAL_1000;
614 break;
615
616 default:
617 BUG();
618 }
619
620 if (!pll_data->pll_10)
621 pll_data->pll_10 = pll_10;
622
623 if (!pll_data->pll_100)
624 pll_data->pll_100 = pll_100;
625
626 if (!pll_data->pll_1000)
627 pll_data->pll_1000 = pll_1000;
628 }
629
630 static int __init ar71xx_setup_phy_if_mode(unsigned int id,
631 struct ag71xx_platform_data *pdata)
632 {
633 unsigned int mii_if;
634
635 switch (id) {
636 case 0:
637 switch (ar71xx_soc) {
638 case AR71XX_SOC_AR7130:
639 case AR71XX_SOC_AR7141:
640 case AR71XX_SOC_AR7161:
641 case AR71XX_SOC_AR9130:
642 case AR71XX_SOC_AR9132:
643 switch (pdata->phy_if_mode) {
644 case PHY_INTERFACE_MODE_MII:
645 mii_if = MII0_CTRL_IF_MII;
646 break;
647 case PHY_INTERFACE_MODE_GMII:
648 mii_if = MII0_CTRL_IF_GMII;
649 break;
650 case PHY_INTERFACE_MODE_RGMII:
651 mii_if = MII0_CTRL_IF_RGMII;
652 break;
653 case PHY_INTERFACE_MODE_RMII:
654 mii_if = MII0_CTRL_IF_RMII;
655 break;
656 default:
657 return -EINVAL;
658 }
659 ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
660 break;
661
662 case AR71XX_SOC_AR7240:
663 case AR71XX_SOC_AR7241:
664 case AR71XX_SOC_AR9330:
665 case AR71XX_SOC_AR9331:
666 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
667 break;
668
669 case AR71XX_SOC_AR7242:
670 /* FIXME */
671
672 case AR71XX_SOC_AR9341:
673 case AR71XX_SOC_AR9342:
674 case AR71XX_SOC_AR9344:
675 switch (pdata->phy_if_mode) {
676 case PHY_INTERFACE_MODE_MII:
677 case PHY_INTERFACE_MODE_GMII:
678 case PHY_INTERFACE_MODE_RGMII:
679 case PHY_INTERFACE_MODE_RMII:
680 break;
681 default:
682 return -EINVAL;
683 }
684 break;
685
686 default:
687 BUG();
688 }
689 break;
690 case 1:
691 switch (ar71xx_soc) {
692 case AR71XX_SOC_AR7130:
693 case AR71XX_SOC_AR7141:
694 case AR71XX_SOC_AR7161:
695 case AR71XX_SOC_AR9130:
696 case AR71XX_SOC_AR9132:
697 switch (pdata->phy_if_mode) {
698 case PHY_INTERFACE_MODE_RMII:
699 mii_if = MII1_CTRL_IF_RMII;
700 break;
701 case PHY_INTERFACE_MODE_RGMII:
702 mii_if = MII1_CTRL_IF_RGMII;
703 break;
704 default:
705 return -EINVAL;
706 }
707 ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
708 break;
709
710 case AR71XX_SOC_AR7240:
711 case AR71XX_SOC_AR7241:
712 case AR71XX_SOC_AR9330:
713 case AR71XX_SOC_AR9331:
714 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
715 break;
716
717 case AR71XX_SOC_AR7242:
718 /* FIXME */
719
720 case AR71XX_SOC_AR9341:
721 case AR71XX_SOC_AR9342:
722 case AR71XX_SOC_AR9344:
723 switch (pdata->phy_if_mode) {
724 case PHY_INTERFACE_MODE_MII:
725 case PHY_INTERFACE_MODE_GMII:
726 break;
727 default:
728 return -EINVAL;
729 }
730 break;
731
732 default:
733 BUG();
734 }
735 break;
736 }
737
738 return 0;
739 }
740
741 static int ar71xx_eth_instance __initdata;
742 void __init ar71xx_add_device_eth(unsigned int id)
743 {
744 struct platform_device *pdev;
745 struct ag71xx_platform_data *pdata;
746 int err;
747
748 if (id > 1) {
749 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
750 return;
751 }
752
753 ar71xx_init_eth_pll_data(id);
754
755 if (id == 0)
756 pdev = &ar71xx_eth0_device;
757 else
758 pdev = &ar71xx_eth1_device;
759
760 pdata = pdev->dev.platform_data;
761
762 err = ar71xx_setup_phy_if_mode(id, pdata);
763 if (err) {
764 printk(KERN_ERR
765 "ar71xx: invalid PHY interface mode for GE%u\n", id);
766 return;
767 }
768
769 switch (ar71xx_soc) {
770 case AR71XX_SOC_AR7130:
771 if (id == 0) {
772 pdata->ddr_flush = ar71xx_ddr_flush_ge0;
773 pdata->set_speed = ar71xx_set_speed_ge0;
774 } else {
775 pdata->ddr_flush = ar71xx_ddr_flush_ge1;
776 pdata->set_speed = ar71xx_set_speed_ge1;
777 }
778 break;
779
780 case AR71XX_SOC_AR7141:
781 case AR71XX_SOC_AR7161:
782 if (id == 0) {
783 pdata->ddr_flush = ar71xx_ddr_flush_ge0;
784 pdata->set_speed = ar71xx_set_speed_ge0;
785 } else {
786 pdata->ddr_flush = ar71xx_ddr_flush_ge1;
787 pdata->set_speed = ar71xx_set_speed_ge1;
788 }
789 pdata->has_gbit = 1;
790 break;
791
792 case AR71XX_SOC_AR7242:
793 if (id == 0) {
794 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
795 RESET_MODULE_GE0_PHY;
796 pdata->ddr_flush = ar724x_ddr_flush_ge0;
797 pdata->set_speed = ar7242_set_speed_ge0;
798 } else {
799 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
800 RESET_MODULE_GE1_PHY;
801 pdata->ddr_flush = ar724x_ddr_flush_ge1;
802 pdata->set_speed = ar724x_set_speed_ge1;
803 }
804 pdata->has_gbit = 1;
805 pdata->is_ar724x = 1;
806
807 if (!pdata->fifo_cfg1)
808 pdata->fifo_cfg1 = 0x0010ffff;
809 if (!pdata->fifo_cfg2)
810 pdata->fifo_cfg2 = 0x015500aa;
811 if (!pdata->fifo_cfg3)
812 pdata->fifo_cfg3 = 0x01f00140;
813 break;
814
815 case AR71XX_SOC_AR7241:
816 if (id == 0)
817 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
818 else
819 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
820 /* fall through */
821 case AR71XX_SOC_AR7240:
822 if (id == 0) {
823 pdata->reset_bit |= RESET_MODULE_GE0_PHY;
824 pdata->ddr_flush = ar724x_ddr_flush_ge0;
825 pdata->set_speed = ar724x_set_speed_ge0;
826
827 pdata->phy_mask = BIT(4);
828 } else {
829 pdata->reset_bit |= RESET_MODULE_GE1_PHY;
830 pdata->ddr_flush = ar724x_ddr_flush_ge1;
831 pdata->set_speed = ar724x_set_speed_ge1;
832
833 pdata->speed = SPEED_1000;
834 pdata->duplex = DUPLEX_FULL;
835 pdata->switch_data = &ar71xx_switch_data;
836 }
837 pdata->has_gbit = 1;
838 pdata->is_ar724x = 1;
839 if (ar71xx_soc == AR71XX_SOC_AR7240)
840 pdata->is_ar7240 = 1;
841
842 if (!pdata->fifo_cfg1)
843 pdata->fifo_cfg1 = 0x0010ffff;
844 if (!pdata->fifo_cfg2)
845 pdata->fifo_cfg2 = 0x015500aa;
846 if (!pdata->fifo_cfg3)
847 pdata->fifo_cfg3 = 0x01f00140;
848 break;
849
850 case AR71XX_SOC_AR9130:
851 if (id == 0) {
852 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
853 pdata->set_speed = ar91xx_set_speed_ge0;
854 } else {
855 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
856 pdata->set_speed = ar91xx_set_speed_ge1;
857 }
858 pdata->is_ar91xx = 1;
859 break;
860
861 case AR71XX_SOC_AR9132:
862 if (id == 0) {
863 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
864 pdata->set_speed = ar91xx_set_speed_ge0;
865 } else {
866 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
867 pdata->set_speed = ar91xx_set_speed_ge1;
868 }
869 pdata->is_ar91xx = 1;
870 pdata->has_gbit = 1;
871 break;
872
873 case AR71XX_SOC_AR9330:
874 case AR71XX_SOC_AR9331:
875 if (id == 0) {
876 pdata->reset_bit = AR933X_RESET_GE0_MAC |
877 AR933X_RESET_GE0_MDIO;
878 pdata->ddr_flush = ar933x_ddr_flush_ge0;
879 pdata->set_speed = ar933x_set_speed_ge0;
880
881 pdata->phy_mask = BIT(4);
882 } else {
883 pdata->reset_bit = AR933X_RESET_GE1_MAC |
884 AR933X_RESET_GE1_MDIO;
885 pdata->ddr_flush = ar933x_ddr_flush_ge1;
886 pdata->set_speed = ar933x_set_speed_ge1;
887
888 pdata->speed = SPEED_1000;
889 pdata->duplex = DUPLEX_FULL;
890 pdata->switch_data = &ar71xx_switch_data;
891 }
892
893 pdata->has_gbit = 1;
894 pdata->is_ar724x = 1;
895
896 if (!pdata->fifo_cfg1)
897 pdata->fifo_cfg1 = 0x0010ffff;
898 if (!pdata->fifo_cfg2)
899 pdata->fifo_cfg2 = 0x015500aa;
900 if (!pdata->fifo_cfg3)
901 pdata->fifo_cfg3 = 0x01f00140;
902 break;
903
904 case AR71XX_SOC_AR9341:
905 case AR71XX_SOC_AR9342:
906 case AR71XX_SOC_AR9344:
907 if (id == 0) {
908 pdata->reset_bit = AR934X_RESET_GE0_MAC |
909 AR934X_RESET_GE0_MDIO;
910 pdata->ddr_flush =ar934x_ddr_flush_ge0;
911 pdata->set_speed = ar934x_set_speed_ge0;
912 } else {
913 pdata->reset_bit = AR934X_RESET_GE1_MAC |
914 AR934X_RESET_GE1_MDIO;
915 pdata->ddr_flush = ar934x_ddr_flush_ge1;
916 pdata->set_speed = ar934x_set_speed_ge1;
917
918 pdata->switch_data = &ar71xx_switch_data;
919 }
920
921 pdata->has_gbit = 1;
922 pdata->is_ar724x = 1;
923
924 if (!pdata->fifo_cfg1)
925 pdata->fifo_cfg1 = 0x0010ffff;
926 if (!pdata->fifo_cfg2)
927 pdata->fifo_cfg2 = 0x015500aa;
928 if (!pdata->fifo_cfg3)
929 pdata->fifo_cfg3 = 0x01f00140;
930 break;
931
932 default:
933 BUG();
934 }
935
936 switch (pdata->phy_if_mode) {
937 case PHY_INTERFACE_MODE_GMII:
938 case PHY_INTERFACE_MODE_RGMII:
939 if (!pdata->has_gbit) {
940 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
941 id);
942 return;
943 }
944 /* fallthrough */
945 default:
946 break;
947 }
948
949 if (!is_valid_ether_addr(pdata->mac_addr)) {
950 random_ether_addr(pdata->mac_addr);
951 printk(KERN_DEBUG
952 "ar71xx: using random MAC address for eth%d\n",
953 ar71xx_eth_instance);
954 }
955
956 if (pdata->mii_bus_dev == NULL) {
957 switch (ar71xx_soc) {
958 case AR71XX_SOC_AR9341:
959 case AR71XX_SOC_AR9342:
960 case AR71XX_SOC_AR9344:
961 if (id == 0)
962 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
963 else
964 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
965 break;
966
967 case AR71XX_SOC_AR7241:
968 case AR71XX_SOC_AR9330:
969 case AR71XX_SOC_AR9331:
970 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
971 break;
972
973 default:
974 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
975 break;
976 }
977 }
978
979 /* Reset the device */
980 ar71xx_device_stop(pdata->reset_bit);
981 mdelay(100);
982
983 ar71xx_device_start(pdata->reset_bit);
984 mdelay(100);
985
986 platform_device_register(pdev);
987 ar71xx_eth_instance++;
988 }
989
990 static struct resource ar71xx_spi_resources[] = {
991 [0] = {
992 .start = AR71XX_SPI_BASE,
993 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
994 .flags = IORESOURCE_MEM,
995 },
996 };
997
998 static struct platform_device ar71xx_spi_device = {
999 .name = "ar71xx-spi",
1000 .id = -1,
1001 .resource = ar71xx_spi_resources,
1002 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
1003 };
1004
1005 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
1006 struct spi_board_info const *info,
1007 unsigned n)
1008 {
1009 spi_register_board_info(info, n);
1010 ar71xx_spi_device.dev.platform_data = pdata;
1011 platform_device_register(&ar71xx_spi_device);
1012 }
1013
1014 void __init ar71xx_add_device_wdt(void)
1015 {
1016 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
1017 }
1018
1019 void __init ar71xx_set_mac_base(unsigned char *mac)
1020 {
1021 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
1022 }
1023
1024 void __init ar71xx_parse_mac_addr(char *mac_str)
1025 {
1026 u8 tmp[ETH_ALEN];
1027 int t;
1028
1029 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1030 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1031
1032 if (t != ETH_ALEN)
1033 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1034 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1035
1036 if (t == ETH_ALEN)
1037 ar71xx_set_mac_base(tmp);
1038 else
1039 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
1040 "\"%s\"\n", mac_str);
1041 }
1042
1043 static int __init ar71xx_ethaddr_setup(char *str)
1044 {
1045 ar71xx_parse_mac_addr(str);
1046 return 1;
1047 }
1048 __setup("ethaddr=", ar71xx_ethaddr_setup);
1049
1050 static int __init ar71xx_kmac_setup(char *str)
1051 {
1052 ar71xx_parse_mac_addr(str);
1053 return 1;
1054 }
1055 __setup("kmac=", ar71xx_kmac_setup);
1056
1057 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
1058 int offset)
1059 {
1060 int t;
1061
1062 if (!is_valid_ether_addr(src)) {
1063 memset(dst, '\0', ETH_ALEN);
1064 return;
1065 }
1066
1067 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1068 t += offset;
1069
1070 dst[0] = src[0];
1071 dst[1] = src[1];
1072 dst[2] = src[2];
1073 dst[3] = (t >> 16) & 0xff;
1074 dst[4] = (t >> 8) & 0xff;
1075 dst[5] = t & 0xff;
1076 }
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