target/linux/orion/patches/006-add_a_separate_BRIDGE_INT_TIMER1_CLR_define.patch

   1 From: Ke Wei <kewei@marvell.com>
   2
   3 Some Feroceon-based SoCs have an MBUS bridge interrupt controller
   4 that requires writing a one instead of a zero to clear edge
   5 interrupt sources such as timer expiry.
   6
   7 This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
   8 code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
   9 BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.
  10
  11 Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
  12 ---
  13  arch/arm/plat-orion/time.c             |    2 +-
  14  include/asm-arm/arch-orion5x/orion5x.h |    1 +
  15  2 files changed, 2 insertions(+), 1 deletions(-)
  16
  17 --- a/arch/arm/plat-orion/time.c
  18 +++ b/arch/arm/plat-orion/time.c
  19 @@ -74,7 +74,7 @@
  20         /*
  21          * Clear and enable clockevent timer interrupt.
  22          */
  23 -       writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
  24 +       writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
  25
  26         u = readl(BRIDGE_MASK);
  27         u |= BRIDGE_INT_TIMER1;
  28 --- a/include/asm-arm/arch-orion5x/orion5x.h
  29 +++ b/include/asm-arm/arch-orion5x/orion5x.h
  30 @@ -152,6 +152,7 @@
  31  #define BRIDGE_MASK            ORION5X_BRIDGE_REG(0x114)
  32  #define  BRIDGE_INT_TIMER0     0x0002
  33  #define  BRIDGE_INT_TIMER1     0x0004
  34 +#define  BRIDGE_INT_TIMER1_CLR ~0x0004
  35  #define MAIN_IRQ_CAUSE         ORION5X_BRIDGE_REG(0x200)
  36  #define MAIN_IRQ_MASK          ORION5X_BRIDGE_REG(0x204)
  37