target/linux/brcm63xx/patches-2.6.33/240-spi.patch

   1 --- a/arch/mips/bcm63xx/cpu.c
   2 +++ b/arch/mips/bcm63xx/cpu.c
   3 @@ -55,6 +55,7 @@ static const unsigned long bcm96338_regs
   4
   5  static const int bcm96338_irqs[] = {
   6         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
   7 +       [IRQ_SPI]               = BCM_6338_SPI_IRQ,
   8         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
   9         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  10         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  11 @@ -127,6 +128,7 @@ static const unsigned long bcm96348_regs
  12
  13  static const int bcm96348_irqs[] = {
  14         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
  15 +       [IRQ_SPI]               = BCM_6348_SPI_IRQ,
  16         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
  17         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
  18         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
  19 @@ -169,6 +171,7 @@ static const unsigned long bcm96358_regs
  20
  21  static const int bcm96358_irqs[] = {
  22         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
  23 +       [IRQ_SPI]               = BCM_6358_SPI_IRQ,
  24         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
  25         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
  26         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
  27 --- /dev/null
  28 +++ b/arch/mips/bcm63xx/dev-spi.c
  29 @@ -0,0 +1,60 @@
  30 +/*
  31 + * This file is subject to the terms and conditions of the GNU General Public
  32 + * License.  See the file "COPYING" in the main directory of this archive
  33 + * for more details.
  34 + *
  35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  36 + */
  37 +
  38 +#include <linux/init.h>
  39 +#include <linux/kernel.h>
  40 +#include <linux/platform_device.h>
  41 +
  42 +#include <bcm63xx_cpu.h>
  43 +#include <bcm63xx_dev_spi.h>
  44 +#include <bcm63xx_regs.h>
  45 +
  46 +static struct resource spi_resources[] = {
  47 +       {
  48 +               .start          = -1, /* filled at runtime */
  49 +               .end            = -1, /* filled at runtime */
  50 +               .flags          = IORESOURCE_MEM,
  51 +       },
  52 +       {
  53 +               .start          = -1, /* filled at runtime */
  54 +               .flags          = IORESOURCE_IRQ,
  55 +       },
  56 +};
  57 +
  58 +static struct bcm63xx_spi_pdata spi_pdata = {
  59 +       .bus_num                = 0,
  60 +       .num_chipselect         = 4,
  61 +       .speed_hz               = 50000000,     /* Fclk */
  62 +};
  63 +
  64 +static struct platform_device bcm63xx_spi_device = {
  65 +       .name           = "bcm63xx-spi",
  66 +       .id             = 0,
  67 +       .num_resources  = ARRAY_SIZE(spi_resources),
  68 +       .resource       = spi_resources,
  69 +       .dev            = {
  70 +               .platform_data = &spi_pdata,
  71 +       },
  72 +};
  73 +
  74 +int __init bcm63xx_spi_register(void)
  75 +{
  76 +       spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
  77 +       spi_resources[0].end = spi_resources[0].start;
  78 +       spi_resources[0].end += RSET_SPI_SIZE - 1;
  79 +       spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
  80 +
  81 +       /* Fill in platform data */
  82 +       if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
  83 +               spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
  84 +
  85 +       if (BCMCPU_IS_6358())
  86 +               spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
  87 +
  88 +       return platform_device_register(&bcm63xx_spi_device);
  89 +}
  90 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  91 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  92 @@ -108,6 +108,7 @@ enum bcm63xx_regs_set {
  93  #define RSET_WDT_SIZE                  12
  94  #define RSET_ENET_SIZE                 2048
  95  #define RSET_ENETDMA_SIZE              2048
  96 +#define RSET_SPI_SIZE                  256
  97  #define RSET_UART_SIZE                 24
  98  #define RSET_UDC_SIZE                  256
  99  #define RSET_OHCI_SIZE                 256
 100 @@ -209,7 +210,7 @@ enum bcm63xx_regs_set {
 101  #define BCM_6358_WDT_BASE              (0xfffe005c)
 102  #define BCM_6358_UART0_BASE            (0xfffe0100)
 103  #define BCM_6358_GPIO_BASE             (0xfffe0080)
 104 -#define BCM_6358_SPI_BASE              (0xdeadbeef)
 105 +#define BCM_6358_SPI_BASE              (0xfffe0800)
 106  #define BCM_6358_UDC0_BASE             (0xfffe0400)
 107  #define BCM_6358_OHCI0_BASE            (0xfffe1400)
 108  #define BCM_6358_OHCI_PRIV_BASE                (0xdeadbeef)
 109 @@ -428,6 +429,7 @@ static inline unsigned long bcm63xx_regs
 110   */
 111  enum bcm63xx_irq {
 112         IRQ_TIMER = 0,
 113 +       IRQ_SPI,
 114         IRQ_UART0,
 115         IRQ_DSL,
 116         IRQ_UDC0,
 117 @@ -493,6 +495,7 @@ enum bcm63xx_irq {
 118   * 6348 irqs
 119   */
 120  #define BCM_6348_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 121 +#define BCM_6348_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 122  #define BCM_6348_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 123  #define BCM_6348_DSL_IRQ               (IRQ_INTERNAL_BASE + 4)
 124  #define BCM_6348_UDC0_IRQ              (IRQ_INTERNAL_BASE + 6)
 125 @@ -517,6 +520,7 @@ enum bcm63xx_irq {
 126   * 6358 irqs
 127   */
 128  #define BCM_6358_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 129 +#define BCM_6358_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)
 130  #define BCM_6358_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 131  #define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 132  #define BCM_6358_ENET1_IRQ             (IRQ_INTERNAL_BASE + 6)
 133 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 134 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 135 @@ -769,5 +769,117 @@
 136  #define DMIPSPLLCFG_N2_SHIFT           29
 137  #define DMIPSPLLCFG_N2_MASK            (0x7 << DMIPSPLLCFG_N2_SHIFT)
 138
 139 +/*************************************************************************
 140 + * _REG relative to RSET_SPI
 141 + *************************************************************************/
 142 +
 143 +/* BCM 6338 SPI core */
 144 +#define SPI_BCM_6338_SPI_CMD           0x00    /* 16-bits register */
 145 +#define SPI_BCM_6338_SPI_INT_STATUS    0x02
 146 +#define SPI_BCM_6338_SPI_MASK_INT_ST   0x03
 147 +#define SPI_BCM_6338_SPI_INT_MASK      0x04
 148 +#define SPI_BCM_6338_SPI_ST            0x05
 149 +#define SPI_BCM_6338_SPI_CLK_CFG       0x06
 150 +#define SPI_BCM_6338_SPI_FILL_BYTE     0x07
 151 +#define SPI_BCM_6338_SPI_MSG_TAIL      0x09
 152 +#define SPI_BCM_6338_SPI_RX_TAIL       0x0b
 153 +#define SPI_BCM_6338_SPI_MSG_CTL       0x40
 154 +#define SPI_BCM_6338_SPI_MSG_DATA      0x41
 155 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
 156 +#define SPI_BCM_6338_SPI_RX_DATA       0x80
 157 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE  0x3f
 158 +
 159 +/* BCM 6348 SPI core */
 160 +#define SPI_BCM_6348_SPI_MASK_INT_ST   0x00
 161 +#define SPI_BCM_6348_SPI_INT_STATUS    0x01
 162 +#define SPI_BCM_6348_SPI_CMD           0x02    /* 16-bits register */
 163 +#define SPI_BCM_6348_SPI_FILL_BYTE     0x04
 164 +#define SPI_BCM_6348_SPI_CLK_CFG       0x05
 165 +#define SPI_BCM_6348_SPI_ST            0x06
 166 +#define SPI_BCM_6348_SPI_INT_MASK      0x07
 167 +#define SPI_BCM_6348_SPI_RX_TAIL       0x08
 168 +#define SPI_BCM_6348_SPI_MSG_TAIL      0x10
 169 +#define SPI_BCM_6348_SPI_MSG_DATA      0x40
 170 +#define SPI_BCM_6348_SPI_MSG_CTL       0x42
 171 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
 172 +#define SPI_BCM_6348_SPI_RX_DATA       0x80
 173 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE  0x3f
 174 +
 175 +/* BCM 6358 SPI core */
 176 +#define SPI_BCM_6358_MSG_CTL           0x00    /* 16-bits register */
 177 +
 178 +#define SPI_BCM_6358_SPI_MSG_DATA      0x02
 179 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
 180 +
 181 +#define SPI_BCM_6358_SPI_RX_DATA       0x400
 182 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE  0x220
 183 +
 184 +#define SPI_BCM_6358_SPI_CMD           0x700   /* 16-bits register */
 185 +
 186 +#define SPI_BCM_6358_SPI_INT_STATUS    0x702
 187 +#define SPI_BCM_6358_SPI_MASK_INT_ST   0x703
 188 +
 189 +#define SPI_BCM_6358_SPI_INT_MASK      0x704
 190 +
 191 +#define SPI_BCM_6358_SPI_STATUS                0x705
 192 +
 193 +#define SPI_BCM_6358_SPI_CLK_CFG       0x706
 194 +
 195 +#define SPI_BCM_6358_SPI_FILL_BYTE     0x707
 196 +#define SPI_BCM_6358_SPI_MSG_TAIL      0x709
 197 +#define SPI_BCM_6358_SPI_RX_TAIL       0x70B
 198 +
 199 +/* Shared SPI definitions */
 200 +
 201 +/* Message configuration */
 202 +#define SPI_FD_RW                      0x00
 203 +#define SPI_HD_W                       0x01
 204 +#define SPI_HD_R                       0x02
 205 +#define SPI_BYTE_CNT_SHIFT             0
 206 +#define SPI_MSG_TYPE_SHIFT             14
 207 +
 208 +/* Command */
 209 +#define SPI_CMD_NOOP                   0x01
 210 +#define SPI_CMD_SOFT_RESET             0x02
 211 +#define SPI_CMD_HARD_RESET             0x04
 212 +#define SPI_CMD_START_IMMEDIATE                0x08
 213 +#define SPI_CMD_COMMAND_SHIFT          0
 214 +#define SPI_CMD_COMMAND_MASK           0x000f
 215 +#define SPI_CMD_DEVICE_ID_SHIFT                4
 216 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
 217 +#define SPI_CMD_ONE_BYTE_SHIFT         11
 218 +#define SPI_CMD_ONE_WIRE_SHIFT         12
 219 +#define SPI_DEV_ID_0                   0
 220 +#define SPI_DEV_ID_1                   1
 221 +#define SPI_DEV_ID_2                   2
 222 +#define SPI_DEV_ID_3                   3
 223 +
 224 +/* Interrupt mask */
 225 +#define SPI_INTR_CMD_DONE              0x01
 226 +#define SPI_INTR_RX_OVERFLOW           0x02
 227 +#define SPI_INTR_TX_UNDERFLOW          0x04
 228 +#define SPI_INTR_TX_OVERFLOW           0x08
 229 +#define SPI_INTR_RX_UNDERFLOW          0x10
 230 +#define SPI_INTR_CLEAR_ALL             0x1f
 231 +
 232 +/* Status */
 233 +#define SPI_RX_EMPTY                   0x02
 234 +#define SPI_CMD_BUSY                   0x04
 235 +#define SPI_SERIAL_BUSY                        0x08
 236 +
 237 +/* Clock configuration */
 238 +#define SPI_CLK_20MHZ                  0x00
 239 +#define SPI_CLK_0_391MHZ               0x01
 240 +#define SPI_CLK_0_781MHZ               0x02 /* default */
 241 +#define SPI_CLK_1_563MHZ               0x03
 242 +#define SPI_CLK_3_125MHZ               0x04
 243 +#define SPI_CLK_6_250MHZ               0x05
 244 +#define SPI_CLK_12_50MHZ               0x06
 245 +#define SPI_CLK_25MHZ                  0x07
 246 +#define SPI_CLK_MASK                   0x07
 247 +#define SPI_SSOFFTIME_MASK             0x38
 248 +#define SPI_SSOFFTIME_SHIFT            3
 249 +#define SPI_BYTE_SWAP                  0x80
 250 +
 251  #endif /* BCM63XX_REGS_H_ */
 252
 253 --- /dev/null
 254 +++ b/drivers/spi/bcm63xx_spi.c
 255 @@ -0,0 +1,628 @@
 256 +/*
 257 + * Broadcom BCM63xx SPI controller support
 258 + *
 259 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
 260 + *
 261 + * This program is free software; you can redistribute it and/or
 262 + * modify it under the terms of the GNU General Public License
 263 + * as published by the Free Software Foundation; either version 2
 264 + * of the License, or (at your option) any later version.
 265 + *
 266 + * This program is distributed in the hope that it will be useful,
 267 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 268 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 269 + * GNU General Public License for more details.
 270 + *
 271 + * You should have received a copy of the GNU General Public License
 272 + * along with this program; if not, write to the
 273 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
 274 + */
 275 +
 276 +#include <linux/kernel.h>
 277 +#include <linux/init.h>
 278 +#include <linux/clk.h>
 279 +#include <linux/module.h>
 280 +#include <linux/platform_device.h>
 281 +#include <linux/delay.h>
 282 +#include <linux/interrupt.h>
 283 +#include <linux/spi/spi.h>
 284 +#include <linux/spi/spi_bitbang.h>
 285 +#include <linux/gpio.h>
 286 +#include <linux/completion.h>
 287 +#include <linux/err.h>
 288 +
 289 +#include <bcm63xx_io.h>
 290 +#include <bcm63xx_regs.h>
 291 +#include <bcm63xx_dev_spi.h>
 292 +
 293 +#define PFX            KBUILD_MODNAME
 294 +#define DRV_VER                "0.1.2"
 295 +
 296 +enum bcm63xx_regs_spi {
 297 +        SPI_CMD,
 298 +        SPI_INT_STATUS,
 299 +        SPI_INT_MASK_ST,
 300 +        SPI_INT_MASK,
 301 +        SPI_ST,
 302 +        SPI_CLK_CFG,
 303 +        SPI_FILL_BYTE,
 304 +        SPI_MSG_TAIL,
 305 +        SPI_RX_TAIL,
 306 +        SPI_MSG_CTL,
 307 +        SPI_MSG_DATA,
 308 +        SPI_RX_DATA,
 309 +};
 310 +
 311 +/*
 312 + * register offsets
 313 + */
 314 +static const unsigned long bcm96338_regs_spi[] = {
 315 +       [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
 316 +       [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
 317 +       [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
 318 +       [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
 319 +       [SPI_ST]                = SPI_BCM_6338_SPI_ST,
 320 +       [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
 321 +       [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
 322 +       [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
 323 +       [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
 324 +       [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
 325 +       [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
 326 +       [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
 327 +};
 328 +
 329 +static const unsigned long bcm96348_regs_spi[] = {
 330 +       [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
 331 +       [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
 332 +       [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
 333 +       [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
 334 +       [SPI_ST]                = SPI_BCM_6348_SPI_ST,
 335 +       [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
 336 +       [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
 337 +       [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
 338 +       [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
 339 +       [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
 340 +       [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
 341 +       [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
 342 +};
 343 +
 344 +static const unsigned long bcm96358_regs_spi[] = {
 345 +       [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
 346 +       [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
 347 +       [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
 348 +       [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
 349 +       [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
 350 +       [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
 351 +       [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
 352 +       [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
 353 +       [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
 354 +       [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
 355 +       [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
 356 +       [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
 357 +};
 358 +
 359 +
 360 +#ifdef BCMCPU_RUNTIME_DETECT
 361 +static const unsigned long *bcm63xx_regs_spi;
 362 +
 363 +static __init void bcm63xx_spi_regs_init(void)
 364 +{
 365 +       if (BCMCPU_IS_6338())
 366 +               bcm63xx_regs_spi = bcm96338_regs_spi;
 367 +       if (BCMCPU_IS_6348())
 368 +               bcm63xx_regs_spi = bcm96348_regs_spi;
 369 +       if (BCMCPU_IS_6358())
 370 +               bcm63xx_regs_spi = bcm96358_regs_spi;
 371 +}
 372 +#else
 373 +static __init void bcm63xx_spi_regs_init(void) { }
 374 +#endif
 375 +
 376 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 377 +{
 378 +#ifdef BCMCPU_RUNTIME_DETECT
 379 +        return bcm63xx_regs_spi[reg];
 380 +#else
 381 +#ifdef CONFIG_BCM63XX_CPU_6338
 382 +switch (reg) {
 383 +       case SPI_CMD:
 384 +               return SPI_BCM_6338_SPI_CMD;
 385 +       case SPI_INT_STATUS:
 386 +               return SPI_BCM_6338_SPI_INT_STATUS;
 387 +       case SPI_INT_MASK_ST:
 388 +               return SPI_BCM_6338_SPI_MASK_INT_ST;
 389 +       case SPI_INT_MASK:
 390 +               return SPI_BCM_6338_SPI_INT_MASK;
 391 +       case SPI_ST:
 392 +               return SPI_BCM_6338_SPI_ST;
 393 +       case SPI_CLK_CFG:
 394 +               return SPI_BCM_6338_SPI_CLK_CFG;
 395 +       case SPI_FILL_BYTE:
 396 +               return SPI_BCM_6338_SPI_FILL_BYTE;
 397 +       case SPI_MSG_TAIL:
 398 +               return SPI_BCM_6338_SPI_MSG_TAIL;
 399 +       case SPI_RX_TAIL:
 400 +               return SPI_BCM_6338_SPI_RX_TAIL;
 401 +       case SPI_MSG_CTL:
 402 +               return SPI_BCM_6338_SPI_MSG_CTL;
 403 +       case SPI_MSG_DATA:
 404 +               return SPI_BCM_6338_SPI_MSG_DATA;
 405 +       case SPI_RX_DATA:
 406 +               return SPI_BCM_6338_SPI_RX_DATA;
 407 +}
 408 +#endif
 409 +#ifdef CONFIG_BCM63XX_CPU_6348
 410 +switch (reg) {
 411 +       case SPI_CMD:
 412 +               return SPI_BCM_6348_SPI_CMD;
 413 +       case SPI_INT_MASK_ST:
 414 +               return SPI_BCM_6348_SPI_MASK_INT_ST;
 415 +       case SPI_INT_MASK:
 416 +               return SPI_BCM_6348_SPI_INT_MASK;
 417 +       case SPI_INT_STATUS:
 418 +               return SPI_BCM_6348_SPI_INT_STATUS;
 419 +       case SPI_ST:
 420 +               return SPI_BCM_6348_SPI_ST;
 421 +       case SPI_CLK_CFG:
 422 +               return SPI_BCM_6348_SPI_CLK_CFG;
 423 +       case SPI_FILL_BYTE:
 424 +               return SPI_BCM_6348_SPI_FILL_BYTE;
 425 +       case SPI_MSG_TAIL:
 426 +               return SPI_BCM_6348_SPI_MSG_TAIL;
 427 +       case SPI_RX_TAIL:
 428 +               return SPI_BCM_6348_SPI_RX_TAIL;
 429 +       case SPI_MSG_CTL:
 430 +               return SPI_BCM_6348_SPI_MSG_CTL;
 431 +       case SPI_MSG_DATA:
 432 +               return SPI_BCM_6348_SPI_MSG_DATA;
 433 +       case SPI_RX_DATA:
 434 +               return SPI_BCM_6348_SPI_RX_DATA;
 435 +}
 436 +#endif
 437 +#ifdef CONFIG_BCM63XX_CPU_6358
 438 +switch (reg) {
 439 +       case SPI_CMD:
 440 +               return SPI_BCM_6358_SPI_CMD;
 441 +       case SPI_INT_STATUS:
 442 +               return SPI_BCM_6358_SPI_INT_STATUS;
 443 +       case SPI_INT_MASK_ST:
 444 +               return SPI_BCM_6358_SPI_MASK_INT_ST;
 445 +       case SPI_INT_MASK:
 446 +               return SPI_BCM_6358_SPI_INT_MASK;
 447 +       case SPI_ST:
 448 +               return SPI_BCM_6358_SPI_STATUS;
 449 +       case SPI_CLK_CFG:
 450 +               return SPI_BCM_6358_SPI_CLK_CFG;
 451 +       case SPI_FILL_BYTE:
 452 +               return SPI_BCM_6358_SPI_FILL_BYTE;
 453 +       case SPI_MSG_TAIL:
 454 +               return SPI_BCM_6358_SPI_MSG_TAIL;
 455 +       case SPI_RX_TAIL:
 456 +               return SPI_BCM_6358_SPI_RX_TAIL;
 457 +       case SPI_MSG_CTL:
 458 +               return SPI_BCM_6358_MSG_CTL;
 459 +       case SPI_MSG_DATA:
 460 +               return SPI_BCM_6358_SPI_MSG_DATA;
 461 +       case SPI_RX_DATA:
 462 +               return SPI_BCM_6358_SPI_RX_DATA;
 463 +}
 464 +#endif
 465 +#endif
 466 +       return 0;
 467 +}
 468 +
 469 +/*
 470 + * helpers for the SPI register sets
 471 + */
 472 +#define bcm_spi_readb(b,o)      bcm_readb((b) + bcm63xx_spireg(o))
 473 +#define bcm_spi_readw(b,o)      bcm_readw((b) + bcm63xx_spireg(o))
 474 +#define bcm_spi_writeb(v,b,o)   bcm_writeb((v), (b) + bcm63xx_spireg(o))
 475 +#define bcm_spi_writew(v,b,o)   bcm_writew((v), (b) + bcm63xx_spireg(o))
 476 +
 477 +struct bcm63xx_spi {
 478 +       /* bitbang has to be first */
 479 +        struct spi_bitbang     bitbang;
 480 +        struct completion      done;
 481 +
 482 +        void __iomem           *regs;
 483 +        int                    irq;
 484 +
 485 +       /* Platform data */
 486 +        u32                    speed_hz;
 487 +       unsigned                fifo_size;
 488 +
 489 +       /* Data buffers */
 490 +       const unsigned char     *tx_ptr;
 491 +       unsigned char           *rx_ptr;
 492 +       int                     remaining_bytes;
 493 +
 494 +       struct clk              *clk;
 495 +       struct resource         *ioarea;
 496 +       struct platform_device  *pdev;
 497 +};
 498 +
 499 +static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on)
 500 +{
 501 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 502 +       u16 val;
 503 +
 504 +       val = bcm_spi_readw(bs->regs, SPI_CMD);
 505 +       if (is_on == BITBANG_CS_INACTIVE)
 506 +               val |= SPI_CMD_NOOP;
 507 +       else if (is_on == BITBANG_CS_ACTIVE)
 508 +               val |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 509 +
 510 +       bcm_spi_writew(val, bs->regs, SPI_CMD);
 511 +}
 512 +
 513 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
 514 +                                       struct spi_transfer *t)
 515 +{
 516 +       u8 bits_per_word;
 517 +       u8 clk_cfg;
 518 +       u32 hz;
 519 +       unsigned int div;
 520 +
 521 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 522 +
 523 +       bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 524 +       hz = (t) ? t->speed_hz : spi->max_speed_hz;
 525 +       if (bits_per_word != 8) {
 526 +               dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 527 +                       __func__, bits_per_word);
 528 +               return -EINVAL;
 529 +        }
 530 +
 531 +       if (spi->chip_select > spi->master->num_chipselect) {
 532 +               dev_err(&spi->dev, "%s, unsupported slave %d\n",
 533 +                       __func__, spi->chip_select);
 534 +               return -EINVAL;
 535 +       }
 536 +
 537 +       /* Check clock setting */
 538 +       div = (bs->speed_hz / hz);
 539 +       switch (div) {
 540 +       case 2:
 541 +               clk_cfg = SPI_CLK_25MHZ;
 542 +               break;
 543 +       case 4:
 544 +               clk_cfg = SPI_CLK_12_50MHZ;
 545 +               break;
 546 +       case 8:
 547 +               clk_cfg = SPI_CLK_6_250MHZ;
 548 +               break;
 549 +       case 16:
 550 +               clk_cfg = SPI_CLK_3_125MHZ;
 551 +               break;
 552 +       case 32:
 553 +               clk_cfg = SPI_CLK_1_563MHZ;
 554 +               break;
 555 +       case 128:
 556 +               clk_cfg = SPI_CLK_0_781MHZ;
 557 +               break;
 558 +       case 64:
 559 +       default:
 560 +               /* Set to slowest mode for compatibility */
 561 +               clk_cfg = SPI_CLK_0_781MHZ;
 562 +               break;
 563 +       }
 564 +
 565 +       bcm_spi_writeb(clk_cfg, bs->regs, SPI_CLK_CFG);
 566 +       dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
 567 +                                                               div, hz, clk_cfg);
 568 +
 569 +       return 0;
 570 +}
 571 +
 572 +/* the spi->mode bits understood by this driver: */
 573 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
 574 +
 575 +static int bcm63xx_spi_setup(struct spi_device *spi)
 576 +{
 577 +       struct spi_bitbang *bitbang;
 578 +       struct bcm63xx_spi *bs;
 579 +       int retval;
 580 +
 581 +       bs = spi_master_get_devdata(spi->master);
 582 +       bitbang = &bs->bitbang;
 583 +
 584 +       if (!spi->bits_per_word)
 585 +               spi->bits_per_word = 8;
 586 +
 587 +       if (spi->mode & ~MODEBITS) {
 588 +               dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
 589 +                       __func__, spi->mode & ~MODEBITS);
 590 +               return -EINVAL;
 591 +       }
 592 +
 593 +       retval = bcm63xx_spi_setup_transfer(spi, NULL);
 594 +       if (retval < 0) {
 595 +               dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
 596 +                       spi->mode & ~MODEBITS);
 597 +               return retval;
 598 +       }
 599 +
 600 +       dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 601 +               __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
 602 +
 603 +       return 0;
 604 +}
 605 +
 606 +/* Fill the TX FIFO with as many bytes as possible */
 607 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
 608 +{
 609 +        u8 tail;
 610 +
 611 +        /* Fill the Tx FIFO with as many bytes as possible */
 612 +       tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
 613 +        while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
 614 +                if (bs->tx_ptr)
 615 +                        bcm_spi_writeb(*bs->tx_ptr++, bs->regs, SPI_MSG_DATA);
 616 +               else
 617 +                       bcm_spi_writeb(0, bs->regs, SPI_MSG_DATA);
 618 +                bs->remaining_bytes--;
 619 +               tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
 620 +        }
 621 +}
 622 +
 623 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 624 +{
 625 +       struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 626 +       u8 msg_ctl;
 627 +       u16 cmd;
 628 +
 629 +       dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 630 +                               t->tx_buf, t->rx_buf, t->len);
 631 +
 632 +       /* Transmitter is inhibited */
 633 +       bs->tx_ptr = t->tx_buf;
 634 +       bs->rx_ptr = t->rx_buf;
 635 +       bs->remaining_bytes = t->len;
 636 +       init_completion(&bs->done);
 637 +
 638 +       bcm63xx_spi_fill_tx_fifo(bs);
 639 +
 640 +       /* Enable the command done interrupt which
 641 +        * we use to determine completion of a command */
 642 +       bcm_spi_writeb(SPI_INTR_CMD_DONE, bs->regs, SPI_INT_MASK);
 643 +
 644 +       /* Fill in the Message control register */
 645 +       msg_ctl = bcm_spi_readb(bs->regs, SPI_MSG_CTL);
 646 +       msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT);
 647 +       msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
 648 +       bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL);
 649 +
 650 +       /* Issue the transfer */
 651 +       cmd = bcm_spi_readw(bs->regs, SPI_CMD);
 652 +       cmd |= SPI_CMD_START_IMMEDIATE;
 653 +       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 654 +       bcm_spi_writew(cmd, bs->regs, SPI_CMD);
 655 +
 656 +       wait_for_completion(&bs->done);
 657 +
 658 +       /* Disable the CMD_DONE interrupt */
 659 +       bcm_spi_writeb(~(SPI_INTR_CMD_DONE), bs->regs, SPI_INT_MASK);
 660 +
 661 +       return t->len - bs->remaining_bytes;
 662 +}
 663 +
 664 +/* This driver supports single master mode only. Hence
 665 + * CMD_DONE is the only interrupt we care about
 666 + */
 667 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 668 +{
 669 +       struct spi_master *master = (struct spi_master *)dev_id;
 670 +       struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 671 +       u8 intr;
 672 +       u16 cmd;
 673 +
 674 +       /* Read interupts and clear them immediately */
 675 +       intr = bcm_spi_readb(bs->regs, SPI_INT_STATUS);
 676 +       bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
 677 +
 678 +       /* A tansfer completed */
 679 +       if (intr & SPI_INTR_CMD_DONE) {
 680 +               u8 rx_empty;
 681 +
 682 +               rx_empty = bcm_spi_readb(bs->regs, SPI_ST);
 683 +               /* Read out all the data */
 684 +               while ((rx_empty & SPI_RX_EMPTY) == 0) {
 685 +                       u8 data;
 686 +
 687 +                       data = bcm_spi_readb(bs->regs, SPI_RX_DATA);
 688 +                       if (bs->rx_ptr)
 689 +                               *bs->rx_ptr++ = data;
 690 +
 691 +                       rx_empty = bcm_spi_readb(bs->regs, SPI_RX_EMPTY);
 692 +               }
 693 +
 694 +               /* See if there is more data to send */
 695 +               if (bs->remaining_bytes > 0) {
 696 +                       bcm63xx_spi_fill_tx_fifo(bs);
 697 +
 698 +                       /* Start the transfer */
 699 +                       cmd = bcm_spi_readw(bs->regs, SPI_CMD);
 700 +                       cmd |= SPI_CMD_START_IMMEDIATE;
 701 +                       cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 702 +                       bcm_spi_writew(cmd, bs->regs, SPI_CMD);
 703 +               } else
 704 +                       complete(&bs->done);
 705 +       }
 706 +
 707 +       return IRQ_HANDLED;
 708 +}
 709 +
 710 +
 711 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
 712 +{
 713 +       struct resource *r;
 714 +       struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 715 +       int irq;
 716 +       struct spi_master *master;
 717 +       struct clk *clk;
 718 +       struct bcm63xx_spi *bs;
 719 +       int ret;
 720 +
 721 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 722 +       if (!r) {
 723 +               ret = -ENXIO;
 724 +               goto out;
 725 +       }
 726 +
 727 +       irq = platform_get_irq(pdev, 0);
 728 +       if (irq < 0) {
 729 +               ret = -ENXIO;
 730 +               goto out;
 731 +       }
 732 +
 733 +       bcm63xx_spi_regs_init();
 734 +
 735 +       clk = clk_get(&pdev->dev, "spi");
 736 +       if (IS_ERR(clk)) {
 737 +               dev_err(&pdev->dev, "No clock for device\n");
 738 +               ret = -ENODEV;
 739 +               goto out;
 740 +       }
 741 +
 742 +       master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi));
 743 +       if (!master) {
 744 +               ret = -ENOMEM;
 745 +               goto out_free;
 746 +       }
 747 +
 748 +       bs = spi_master_get_devdata(master);
 749 +       bs->bitbang.master = spi_master_get(master);
 750 +       bs->bitbang.chipselect = bcm63xx_spi_chipselect;
 751 +       bs->bitbang.setup_transfer = bcm63xx_spi_setup_transfer;
 752 +       bs->bitbang.txrx_bufs = bcm63xx_txrx_bufs;
 753 +       bs->bitbang.master->setup = bcm63xx_spi_setup;
 754 +       init_completion(&bs->done);
 755 +
 756 +       platform_set_drvdata(pdev, master);
 757 +        bs->pdev = pdev;
 758 +
 759 +       if (!request_mem_region(r->start,
 760 +                       r->end - r->start, PFX)) {
 761 +               ret = -ENXIO;
 762 +               goto out_free;
 763 +       }
 764 +
 765 +        bs->regs = ioremap_nocache(r->start, r->end - r->start);
 766 +       if (!bs->regs) {
 767 +               printk(KERN_ERR PFX " unable to ioremap regs\n");
 768 +               ret = -ENOMEM;
 769 +               goto out_free;
 770 +       }
 771 +       bs->irq = irq;
 772 +       bs->clk = clk;
 773 +       bs->fifo_size = pdata->fifo_size;
 774 +
 775 +       ret = request_irq(irq, bcm63xx_spi_interrupt, 0,
 776 +                               pdev->name, master);
 777 +       if (ret) {
 778 +               printk(KERN_ERR PFX " unable to request irq\n");
 779 +               goto out_unmap;
 780 +       }
 781 +
 782 +       master->bus_num = pdata->bus_num;
 783 +       master->num_chipselect = pdata->num_chipselect;
 784 +       bs->speed_hz = pdata->speed_hz;
 785 +
 786 +       /* Initialize hardware */
 787 +       clk_enable(bs->clk);
 788 +       bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
 789 +
 790 +       dev_info(&pdev->dev, " at 0x%08x (irq %d, FIFOs size %d) v%s\n",
 791 +                               r->start, irq, bs->fifo_size, DRV_VER);
 792 +
 793 +       ret = spi_bitbang_start(&bs->bitbang);
 794 +       if (ret) {
 795 +               dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
 796 +               goto out_reset_hw;
 797 +       }
 798 +
 799 +       return ret;
 800 +
 801 +out_reset_hw:
 802 +       clk_disable(clk);
 803 +       free_irq(irq, master);
 804 +out_unmap:
 805 +       iounmap(bs->regs);
 806 +out_free:
 807 +       clk_put(clk);
 808 +       spi_master_put(master);
 809 +out:
 810 +       return ret;
 811 +}
 812 +
 813 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
 814 +{
 815 +       struct spi_master       *master = platform_get_drvdata(pdev);
 816 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 817 +
 818 +       spi_bitbang_stop(&bs->bitbang);
 819 +       clk_disable(bs->clk);
 820 +       clk_put(bs->clk);
 821 +       free_irq(bs->irq, master);
 822 +       iounmap(bs->regs);
 823 +       platform_set_drvdata(pdev, 0);
 824 +       spi_master_put(bs->bitbang.master);
 825 +
 826 +       return 0;
 827 +}
 828 +
 829 +#ifdef CONFIG_PM
 830 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
 831 +{
 832 +       struct spi_master       *master = platform_get_drvdata(pdev);
 833 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 834 +
 835 +        clk_disable(bs->clk);
 836 +
 837 +       return 0;
 838 +}
 839 +
 840 +static int bcm63xx_spi_resume(struct platform_device *pdev)
 841 +{
 842 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 843 +       struct bcm63xx_spi      *bs = spi_master_get_devdata(master);
 844 +
 845 +       clk_enable(bs->clk);
 846 +
 847 +       return 0;
 848 +}
 849 +#else
 850 +#define bcm63xx_spi_suspend    NULL
 851 +#define bcm63xx_spi_resume     NULL
 852 +#endif
 853 +
 854 +static struct platform_driver bcm63xx_spi_driver = {
 855 +       .driver = {
 856 +               .name   = "bcm63xx-spi",
 857 +               .owner  = THIS_MODULE,
 858 +       },
 859 +       .probe          = bcm63xx_spi_probe,
 860 +       .remove         = bcm63xx_spi_remove,
 861 +       .suspend        = bcm63xx_spi_suspend,
 862 +       .resume         = bcm63xx_spi_resume,
 863 +};
 864 +
 865 +
 866 +static int __init bcm63xx_spi_init(void)
 867 +{
 868 +       return platform_driver_register(&bcm63xx_spi_driver);
 869 +}
 870 +
 871 +static void __exit bcm63xx_spi_exit(void)
 872 +{
 873 +       platform_driver_unregister(&bcm63xx_spi_driver);
 874 +}
 875 +
 876 +module_init(bcm63xx_spi_init);
 877 +module_exit(bcm63xx_spi_exit);
 878 +
 879 +MODULE_ALIAS("platform:bcm63xx_spi");
 880 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
 881 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 882 +MODULE_LICENSE("GPL");
 883 +MODULE_VERSION(DRV_VER);
 884 --- a/drivers/spi/Kconfig
 885 +++ b/drivers/spi/Kconfig
 886 @@ -60,6 +60,13 @@ config SPI_ATMEL
 887           This selects a driver for the Atmel SPI Controller, present on
 888           many AT32 (AVR32) and AT91 (ARM) chips.
 889
 890 +config SPI_BCM63XX
 891 +       tristate "Broadcom BCM63xx SPI controller"
 892 +       depends on BCM63XX
 893 +       select SPI_BITBANG
 894 +       help
 895 +         This is the SPI controller master driver for Broadcom BCM63xx SoC.
 896 +
 897  config SPI_BFIN
 898         tristate "SPI controller driver for ADI Blackfin5xx"
 899         depends on BLACKFIN
 900 --- a/drivers/spi/Makefile
 901 +++ b/drivers/spi/Makefile
 902 @@ -43,6 +43,7 @@ obj-$(CONFIG_SPI_SH_SCI)              += spi_sh_sci.
 903  obj-$(CONFIG_SPI_SH_MSIOF)             += spi_sh_msiof.o
 904  obj-$(CONFIG_SPI_STMP3XXX)             += spi_stmp.o
 905  obj-$(CONFIG_SPI_NUC900)               += spi_nuc900.o
 906 +obj-$(CONFIG_SPI_BCM63XX)              += bcm63xx_spi.o
 907
 908  # special build for s3c24xx spi driver with fiq support
 909  spi_s3c24xx_hw-y                       := spi_s3c24xx.o
 910 --- /dev/null
 911 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
 912 @@ -0,0 +1,15 @@
 913 +#ifndef BCM63XX_DEV_SPI_H
 914 +#define BCM63XX_DEV_SPI_H
 915 +
 916 +#include <linux/types.h>
 917 +
 918 +int __init bcm63xx_spi_register(void);
 919 +
 920 +struct bcm63xx_spi_pdata {
 921 +       unsigned int    fifo_size;
 922 +       int             bus_num;
 923 +       int             num_chipselect;
 924 +       u32             speed_hz;
 925 +};
 926 +
 927 +#endif /* BCM63XX_DEV_SPI_H */
 928 --- a/arch/mips/bcm63xx/Makefile
 929 +++ b/arch/mips/bcm63xx/Makefile
 930 @@ -1,6 +1,6 @@
 931  obj-y          += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
 932                    dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
 933 -                  dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
 934 +                  dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
 935  obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 936
 937  obj-y          += boards/
 938 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 939 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
 940 @@ -30,6 +30,7 @@
 941  #include <bcm63xx_dev_usb_ohci.h>
 942  #include <bcm63xx_dev_usb_ehci.h>
 943  #include <bcm63xx_dev_usb_udc.h>
 944 +#include <bcm63xx_dev_spi.h>
 945  #include <board_bcm963xx.h>
 946
 947  #define PFX    "board_bcm963xx: "
 948 @@ -1525,6 +1526,9 @@ int __init board_register_devices(void)
 949         if (board.has_udc0)
 950                 bcm63xx_udc_register();
 951
 952 +       if (!BCMCPU_IS_6345())
 953 +               bcm63xx_spi_register();
 954 +
 955         /* Generate MAC address for WLAN and
 956          * register our SPROM */
 957  #ifdef CONFIG_SSB_PCIHOST