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add XScale support to -ng
[openwrt.git] / target / linux / brcm63xx-2.6 / patches / 020-bcmdrivers.patch
1 diff -urN linux-2.6.17/bcmdrivers/opensource/char/serial/impl1/bcm63xx_cons.c linux-2.6.17-brcm63xx/bcmdrivers/opensource/char/serial/impl1/bcm63xx_cons.c
2 --- linux-2.6.17/bcmdrivers/opensource/char/serial/impl1/bcm63xx_cons.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/char/serial/impl1/bcm63xx_cons.c 2006-08-03 16:42:38.000000000 +0200
4 @@ -0,0 +1,1056 @@
5 +/*
6 +<:copyright-gpl
7 + Copyright 2002 Broadcom Corp. All Rights Reserved.
8 +
9 + This program is free software; you can distribute it and/or modify it
10 + under the terms of the GNU General Public License (Version 2) as
11 + published by the Free Software Foundation.
12 +
13 + This program is distributed in the hope it will be useful, but WITHOUT
14 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 + for more details.
17 +
18 + You should have received a copy of the GNU General Public License along
19 + with this program; if not, write to the Free Software Foundation, Inc.,
20 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 +:>
22 +*/
23 +
24 +/* Description: Serial port driver for the BCM963XX. */
25 +
26 +#define CARDNAME "bcm963xx_serial driver"
27 +#define VERSION "2.0"
28 +#define VER_STR CARDNAME " v" VERSION "\n"
29 +
30 +
31 +#include <linux/kernel.h>
32 +#include <linux/module.h>
33 +#include <linux/version.h>
34 +#include <linux/init.h>
35 +#include <linux/slab.h>
36 +#include <linux/interrupt.h>
37 +#include <linux/spinlock.h>
38 +
39 +/* for definition of struct console */
40 +#include <linux/console.h>
41 +#include <linux/tty.h>
42 +#include <linux/tty_flip.h>
43 +#include <linux/serial.h>
44 +#include <asm/uaccess.h>
45 +
46 +#include <bcmtypes.h>
47 +#include <board.h>
48 +#include <bcm_map_part.h>
49 +#include <bcm_intr.h>
50 +
51 +static DEFINE_SPINLOCK(bcm963xx_serial_lock);
52 +
53 +extern void _putc(char);
54 +extern void _puts(const char *);
55 +
56 +typedef struct bcm_serial {
57 + volatile Uart * port;
58 + int type;
59 + int flags;
60 + int irq;
61 + int baud_base;
62 + int blocked_open;
63 + unsigned short close_delay;
64 + unsigned short closing_wait;
65 + unsigned short line; /* port/line number */
66 + unsigned short cflags; /* line configuration flag */
67 + unsigned short x_char; /* xon/xoff character */
68 + unsigned short read_status_mask; /* mask for read condition */
69 + unsigned short ignore_status_mask; /* mask for ignore condition */
70 + unsigned long event; /* mask used in BH */
71 + int xmit_head; /* Position of the head */
72 + int xmit_tail; /* Position of the tail */
73 + int xmit_cnt; /* Count of the chars in the buffer */
74 + int count; /* indicates how many times it has been opened */
75 + int magic;
76 +
77 + struct async_icount icount; /* keep track of things ... */
78 + struct tty_struct *tty; /* tty associated */
79 + struct termios normal_termios;
80 +
81 + wait_queue_head_t open_wait;
82 + wait_queue_head_t close_wait;
83 +
84 + long session; /* Session of opening process */
85 + long pgrp; /* pgrp of opening process */
86 +
87 + unsigned char is_initialized;
88 +} Context;
89 +
90 +
91 +/*---------------------------------------------------------------------*/
92 +/* Define bits in the Interrupt Enable register */
93 +/*---------------------------------------------------------------------*/
94 +/* Enable receive interrupt */
95 +#define RXINT (RXFIFONE|RXOVFERR)
96 +
97 +/* Enable transmit interrupt */
98 +#define TXINT (TXFIFOEMT|TXUNDERR|TXOVFERR)
99 +
100 +/* Enable receiver line status interrupt */
101 +#define LSINT (RXBRK|RXPARERR|RXFRAMERR)
102 +
103 +#define BCM_NUM_UARTS 1
104 +
105 +#define BD_BCM63XX_TIMER_CLOCK_INPUT (FPERIPH)
106 +
107 +
108 +static struct bcm_serial multi[BCM_NUM_UARTS];
109 +static struct bcm_serial *lines[BCM_NUM_UARTS];
110 +static struct tty_driver serial_driver;
111 +static struct tty_struct *serial_table[BCM_NUM_UARTS];
112 +static struct termios *serial_termios[BCM_NUM_UARTS];
113 +static struct termios *serial_termios_locked[BCM_NUM_UARTS];
114 +static int serial_refcount;
115 +
116 +
117 +static void bcm_stop (struct tty_struct *tty);
118 +static void bcm_start (struct tty_struct *tty);
119 +static inline void receive_chars (struct bcm_serial * info);
120 +static int startup (struct bcm_serial *info);
121 +static void shutdown (struct bcm_serial * info);
122 +static void change_speed( volatile Uart *pUart, tcflag_t cFlag );
123 +static void bcm63xx_cons_flush_chars (struct tty_struct *tty);
124 +static int bcm63xx_cons_write (struct tty_struct *tty, int from_user,
125 + const unsigned char *buf, int count);
126 +static int bcm63xx_cons_write_room (struct tty_struct *tty);
127 +static int bcm_chars_in_buffer (struct tty_struct *tty);
128 +static void bcm_flush_buffer (struct tty_struct *tty);
129 +static void bcm_throttle (struct tty_struct *tty);
130 +static void bcm_unthrottle (struct tty_struct *tty);
131 +static void bcm_send_xchar (struct tty_struct *tty, char ch);
132 +static int get_serial_info(struct bcm_serial *info, struct serial_struct *retinfo);
133 +static int set_serial_info (struct bcm_serial *info, struct serial_struct *new_info);
134 +static int get_lsr_info (struct bcm_serial *info, unsigned int *value);
135 +static void send_break (struct bcm_serial *info, int duration);
136 +static int bcm_ioctl (struct tty_struct * tty, struct file * file,
137 + unsigned int cmd, unsigned long arg);
138 +static void bcm_set_termios (struct tty_struct *tty, struct termios *old_termios);
139 +static void bcm63xx_cons_close (struct tty_struct *tty, struct file *filp);
140 +static void bcm_hangup (struct tty_struct *tty);
141 +static int block_til_ready (struct tty_struct *tty, struct file *filp, struct bcm_serial *info);
142 +static int bcm63xx_cons_open (struct tty_struct * tty, struct file * filp);
143 +static int __init bcm63xx_serialinit(void);
144 +
145 +
146 +/*
147 + * ------------------------------------------------------------
148 + * rs_stop () and rs_start ()
149 + *
150 + * These routines are called before setting or resetting
151 + * tty->stopped. They enable or disable transmitter interrupts,
152 + * as necessary.
153 + * ------------------------------------------------------------
154 + */
155 +static void bcm_stop (struct tty_struct *tty)
156 +{
157 +}
158 +
159 +static void bcm_start (struct tty_struct *tty)
160 +{
161 + _puts(CARDNAME " Start\n");
162 +}
163 +
164 +/*
165 + * ------------------------------------------------------------
166 + * receive_char ()
167 + *
168 + * This routine deals with inputs from any lines.
169 + * ------------------------------------------------------------
170 + */
171 +static inline void receive_chars (struct bcm_serial * info)
172 +{
173 + struct tty_struct *tty = 0;
174 + struct async_icount * icount;
175 + int ignore = 0;
176 + unsigned short status, tmp;
177 + UCHAR ch = 0;
178 + while ((status = info->port->intStatus) & RXINT)
179 + {
180 + char flag_char = 0;
181 +
182 + if (status & RXFIFONE)
183 + ch = info->port->Data; // Read the character
184 + tty = info->tty; /* now tty points to the proper dev */
185 + icount = &info->icount;
186 + if (! tty)
187 + break;
188 + if (!tty_buffer_request_room(tty, 1))
189 + break;
190 + icount->rx++;
191 + if (status & RXBRK)
192 + {
193 + flag_char = TTY_BREAK;
194 + icount->brk++;
195 + }
196 + // keep track of the statistics
197 + if (status & (RXFRAMERR | RXPARERR | RXOVFERR))
198 + {
199 + if (status & RXPARERR) /* parity error */
200 + icount->parity++;
201 + else
202 + if (status & RXFRAMERR) /* frame error */
203 + icount->frame++;
204 + if (status & RXOVFERR)
205 + {
206 + // Overflow. Reset the RX FIFO
207 + info->port->fifoctl |= RSTRXFIFOS;
208 + icount->overrun++;
209 + }
210 + // check to see if we should ignore the character
211 + // and mask off conditions that should be ignored
212 + if (status & info->ignore_status_mask)
213 + {
214 + if (++ignore > 100 )
215 + break;
216 + goto ignore_char;
217 + }
218 + // Mask off the error conditions we want to ignore
219 + tmp = status & info->read_status_mask;
220 + if (tmp & RXPARERR)
221 + {
222 + flag_char = TTY_PARITY;
223 + }
224 + else
225 + if (tmp & RXFRAMERR)
226 + {
227 + flag_char = TTY_FRAME;
228 + }
229 + if (tmp & RXOVFERR)
230 + {
231 + tty_insert_flip_char(tty, ch, flag_char);
232 + ch = 0;
233 + flag_char = TTY_OVERRUN;
234 + if (!tty_buffer_request_room(tty, 1))
235 + break;
236 + }
237 + }
238 + tty_insert_flip_char(tty, ch, flag_char);
239 + }
240 +ignore_char:
241 + if (tty)
242 + tty_flip_buffer_push(tty);
243 +}
244 +
245 +
246 +/*
247 + * ------------------------------------------------------------
248 + * bcm_interrupt ()
249 + *
250 + * this is the main interrupt routine for the chip.
251 + * It deals with the multiple ports.
252 + * ------------------------------------------------------------
253 + */
254 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
255 +static irqreturn_t bcm_interrupt (int irq, void * dev, struct pt_regs * regs)
256 +#else
257 +static void bcm_interrupt (int irq, void * dev, struct pt_regs * regs)
258 +#endif
259 +{
260 + struct bcm_serial * info = lines[0];
261 + UINT16 intStat;
262 +
263 + /* get pending interrupt flags from UART */
264 +
265 + /* Mask with only the serial interrupts that are enabled */
266 + intStat = info->port->intStatus & info->port->intMask;
267 + while (intStat)
268 + {
269 + if (intStat & RXINT)
270 + receive_chars (info);
271 + else
272 + if (intStat & TXINT)
273 + info->port->intStatus = TXINT;
274 + else /* don't know what it was, so let's mask it */
275 + info->port->intMask &= ~intStat;
276 +
277 + intStat = info->port->intStatus & info->port->intMask;
278 + }
279 +
280 + // Clear the interrupt
281 + BcmHalInterruptEnable (INTERRUPT_ID_UART);
282 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
283 + return IRQ_HANDLED;
284 +#endif
285 +}
286 +
287 +/*
288 + * -------------------------------------------------------------------
289 + * startup ()
290 + *
291 + * various initialization tasks
292 + * -------------------------------------------------------------------
293 + */
294 +static int startup (struct bcm_serial *info)
295 +{
296 + // Port is already started...
297 + return 0;
298 +}
299 +
300 +/*
301 + * -------------------------------------------------------------------
302 + * shutdown ()
303 + *
304 + * This routine will shutdown a serial port; interrupts are disabled, and
305 + * DTR is dropped if the hangup on close termio flag is on.
306 + * -------------------------------------------------------------------
307 + */
308 +static void shutdown (struct bcm_serial * info)
309 +{
310 + unsigned long flags;
311 + if (!info->is_initialized)
312 + return;
313 +
314 +
315 + /*save_flags (flags);
316 + cli ();*/
317 + spin_lock_irqsave(&bcm963xx_serial_lock, flags);
318 +
319 + info->port->control &= ~(BRGEN|TXEN|RXEN);
320 + if (info->tty)
321 + set_bit (TTY_IO_ERROR, &info->tty->flags);
322 + info->is_initialized = 0;
323 +
324 + //restore_flags (flags);
325 + spin_unlock_irqrestore(&bcm963xx_serial_lock, flags);
326 +}
327 +/*
328 + * -------------------------------------------------------------------
329 + * change_speed ()
330 + *
331 + * Set the baud rate, character size, parity and stop bits.
332 + * -------------------------------------------------------------------
333 + */
334 +static void change_speed( volatile Uart *pUart, tcflag_t cFlag )
335 +{
336 + unsigned long ulFlags, ulBaud, ulClockFreqHz, ulTmp;
337 + /*save_flags(ulFlags);
338 + cli();*/
339 + spin_lock_irqsave(&bcm963xx_serial_lock, ulFlags);
340 +
341 + switch( cFlag & (CBAUD | CBAUDEX) )
342 + {
343 + case B115200:
344 + ulBaud = 115200;
345 + break;
346 + case B57600:
347 + ulBaud = 57600;
348 + break;
349 + case B38400:
350 + ulBaud = 38400;
351 + break;
352 + case B19200:
353 + ulBaud = 19200;
354 + break;
355 + case B9600:
356 + ulBaud = 9600;
357 + break;
358 + case B4800:
359 + ulBaud = 4800;
360 + break;
361 + case B2400:
362 + ulBaud = 2400;
363 + break;
364 + case B1800:
365 + ulBaud = 1800;
366 + break;
367 + case B1200:
368 + ulBaud = 1200;
369 + break;
370 + case B600:
371 + ulBaud = 600;
372 + break;
373 + case B300:
374 + ulBaud = 300;
375 + break;
376 + case B200:
377 + ulBaud = 200;
378 + break;
379 + case B150:
380 + ulBaud = 150;
381 + break;
382 + case B134:
383 + ulBaud = 134;
384 + break;
385 + case B110:
386 + ulBaud = 110;
387 + break;
388 + case B75:
389 + ulBaud = 75;
390 + break;
391 + case B50:
392 + ulBaud = 50;
393 + break;
394 + default:
395 + ulBaud = 115200;
396 + break;
397 + }
398 +
399 + /* Calculate buad rate. */
400 + ulClockFreqHz = BD_BCM63XX_TIMER_CLOCK_INPUT;
401 + ulTmp = (ulClockFreqHz / ulBaud) / 16;
402 + if( ulTmp & 0x01 )
403 + ulTmp /= 2; /* Rounding up, so sub is already accounted for */
404 + else
405 + ulTmp = (ulTmp / 2) - 1; /* Rounding down so we must sub 1 */
406 + pUart->baudword = ulTmp;
407 +
408 + /* Set character size, stop bits and parity. */
409 + switch( cFlag & CSIZE )
410 + {
411 + case CS5:
412 + ulTmp = BITS5SYM; /* select transmit 5 bit data size */
413 + break;
414 + case CS6:
415 + ulTmp = BITS6SYM; /* select transmit 6 bit data size */
416 + break;
417 + case CS7:
418 + ulTmp = BITS7SYM; /* select transmit 7 bit data size */
419 + break;
420 + /*case CS8:*/
421 + default:
422 + ulTmp = BITS8SYM; /* select transmit 8 bit data size */
423 + break;
424 + }
425 + if( cFlag & CSTOPB )
426 + ulTmp |= TWOSTOP; /* select 2 stop bits */
427 + else
428 + ulTmp |= ONESTOP; /* select one stop bit */
429 +
430 + /* Write these values into the config reg. */
431 + pUart->config = ulTmp;
432 + pUart->control &= ~(RXPARITYEN | TXPARITYEN | RXPARITYEVEN | TXPARITYEVEN);
433 + switch( cFlag & (PARENB | PARODD) )
434 + {
435 + case PARENB|PARODD:
436 + pUart->control |= RXPARITYEN | TXPARITYEN;
437 + break;
438 + case PARENB:
439 + pUart->control |= RXPARITYEN | TXPARITYEN | RXPARITYEVEN | TXPARITYEVEN;
440 + break;
441 + default:
442 + pUart->control |= 0;
443 + break;
444 + }
445 +
446 + /* Reset and flush uart */
447 + pUart->fifoctl = RSTTXFIFOS | RSTRXFIFOS;
448 + //restore_flags( ulFlags );
449 + spin_unlock_irqrestore(&bcm963xx_serial_lock, ulFlags);
450 +}
451 +
452 +
453 +/*
454 + * -------------------------------------------------------------------
455 + * bcm_flush_char ()
456 + *
457 + * Nothing to flush. Polled I/O is used.
458 + * -------------------------------------------------------------------
459 + */
460 +static void bcm63xx_cons_flush_chars (struct tty_struct *tty)
461 +{
462 +}
463 +
464 +
465 +/*
466 + * -------------------------------------------------------------------
467 + * bcm63xx_cons_write ()
468 + *
469 + * Main output routine using polled I/O.
470 + * -------------------------------------------------------------------
471 + */
472 +static int bcm63xx_cons_write (struct tty_struct *tty, int from_user,
473 + const unsigned char *buf, int count)
474 +{
475 + int c;
476 +
477 + for (c = 0; c < count; c++)
478 + _putc(buf[c]);
479 + return count;
480 +}
481 +
482 +/*
483 + * -------------------------------------------------------------------
484 + * bcm63xx_cons_write_room ()
485 + *
486 + * Compute the amount of space available for writing.
487 + * -------------------------------------------------------------------
488 + */
489 +static int bcm63xx_cons_write_room (struct tty_struct *tty)
490 +{
491 + /* Pick a number. Any number. Polled I/O is used. */
492 + return 1024;
493 +}
494 +
495 +/*
496 + * -------------------------------------------------------------------
497 + * bcm_chars_in_buffer ()
498 + *
499 + * compute the amount of char left to be transmitted
500 + * -------------------------------------------------------------------
501 + */
502 +static int bcm_chars_in_buffer (struct tty_struct *tty)
503 +{
504 + return 0;
505 +}
506 +
507 +/*
508 + * -------------------------------------------------------------------
509 + * bcm_flush_buffer ()
510 + *
511 + * Empty the output buffer
512 + * -------------------------------------------------------------------
513 + */
514 +static void bcm_flush_buffer (struct tty_struct *tty)
515 +{
516 +}
517 +
518 +/*
519 + * ------------------------------------------------------------
520 + * bcm_throttle () and bcm_unthrottle ()
521 + *
522 + * This routine is called by the upper-layer tty layer to signal that
523 + * incoming characters should be throttled (or not).
524 + * ------------------------------------------------------------
525 + */
526 +static void bcm_throttle (struct tty_struct *tty)
527 +{
528 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
529 + if (I_IXOFF(tty))
530 + info->x_char = STOP_CHAR(tty);
531 +}
532 +
533 +static void bcm_unthrottle (struct tty_struct *tty)
534 +{
535 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
536 + if (I_IXOFF(tty))
537 + {
538 + if (info->x_char)
539 + info->x_char = 0;
540 + else
541 + info->x_char = START_CHAR(tty);
542 + }
543 +}
544 +
545 +static void bcm_send_xchar (struct tty_struct *tty, char ch)
546 +{
547 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
548 + info->x_char = ch;
549 + if (ch)
550 + bcm_start (info->tty);
551 +}
552 +
553 +/*
554 + * ------------------------------------------------------------
555 + * rs_ioctl () and friends
556 + * ------------------------------------------------------------
557 + */
558 +static int get_serial_info(struct bcm_serial *info, struct serial_struct *retinfo)
559 +{
560 + struct serial_struct tmp;
561 +
562 + if (!retinfo)
563 + return -EFAULT;
564 +
565 + memset (&tmp, 0, sizeof(tmp));
566 + tmp.type = info->type;
567 + tmp.line = info->line;
568 + tmp.port = (int) info->port;
569 + tmp.irq = info->irq;
570 + tmp.flags = 0;
571 + tmp.baud_base = info->baud_base;
572 + tmp.close_delay = info->close_delay;
573 + tmp.closing_wait = info->closing_wait;
574 +
575 + return copy_to_user (retinfo, &tmp, sizeof(*retinfo));
576 +}
577 +
578 +static int set_serial_info (struct bcm_serial *info, struct serial_struct *new_info)
579 +{
580 + struct serial_struct new_serial;
581 + struct bcm_serial old_info;
582 + int retval = 0;
583 +
584 + if (!new_info)
585 + return -EFAULT;
586 +
587 + copy_from_user (&new_serial, new_info, sizeof(new_serial));
588 + old_info = *info;
589 +
590 + if (!capable(CAP_SYS_ADMIN))
591 + return -EPERM;
592 +
593 +
594 + if (info->count > 1)
595 + return -EBUSY;
596 +
597 + /* OK, past this point, all the error checking has been done.
598 + * At this point, we start making changes.....
599 + */
600 + info->baud_base = new_serial.baud_base;
601 + info->type = new_serial.type;
602 + info->close_delay = new_serial.close_delay;
603 + info->closing_wait = new_serial.closing_wait;
604 + retval = startup (info);
605 + return retval;
606 +}
607 +
608 +/*
609 + * get_lsr_info - get line status register info
610 + *
611 + * Purpose: Let user call ioctl() to get info when the UART physically
612 + * is emptied. On bus types like RS485, the transmitter must
613 + * release the bus after transmitting. This must be done when
614 + * the transmit shift register is empty, not be done when the
615 + * transmit holding register is empty. This functionality
616 + * allows an RS485 driver to be written in user space.
617 + */
618 +static int get_lsr_info (struct bcm_serial *info, unsigned int *value)
619 +{
620 + return( 0 );
621 +}
622 +
623 +/*
624 + * This routine sends a break character out the serial port.
625 + */
626 +static void send_break (struct bcm_serial *info, int duration)
627 +{
628 + unsigned long flags;
629 +
630 + if (!info->port)
631 + return;
632 +
633 + current->state = TASK_INTERRUPTIBLE;
634 +
635 + /*save_flags (flags);
636 + cli();*/
637 + spin_lock_irqsave(&bcm963xx_serial_lock, flags);
638 +
639 + info->port->control |= XMITBREAK;
640 + schedule_timeout(duration);
641 + info->port->control &= ~XMITBREAK;
642 +
643 + spin_unlock_irqrestore(&bcm963xx_serial_lock, flags);
644 + //restore_flags (flags);
645 +}
646 +
647 +static int bcm_ioctl (struct tty_struct * tty, struct file * file,
648 + unsigned int cmd, unsigned long arg)
649 +{
650 + int error;
651 + struct bcm_serial * info = (struct bcm_serial *)tty->driver_data;
652 + int retval;
653 +
654 + if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
655 + (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
656 + (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT))
657 + {
658 + if (tty->flags & (1 << TTY_IO_ERROR))
659 + return -EIO;
660 + }
661 + switch (cmd)
662 + {
663 +
664 + case TCSBRK: /* SVID version: non-zero arg --> no break */
665 + retval = tty_check_change (tty);
666 + if (retval)
667 + return retval;
668 + tty_wait_until_sent (tty, 0);
669 + if (!arg)
670 + send_break (info, HZ/4); /* 1/4 second */
671 + return 0;
672 +
673 + case TCSBRKP: /* support for POSIX tcsendbreak() */
674 + retval = tty_check_change (tty);
675 + if (retval)
676 + return retval;
677 + tty_wait_until_sent (tty, 0);
678 + send_break (info, arg ? arg*(HZ/10) : HZ/4);
679 + return 0;
680 +
681 + case TIOCGSOFTCAR:
682 + error = access_ok (VERIFY_WRITE, (void *)arg, sizeof(long));
683 + if (!error)
684 + return -EFAULT;
685 + else
686 + {
687 + put_user (C_CLOCAL(tty) ? 1 : 0, (unsigned long *)arg);
688 + return 0;
689 + }
690 +
691 + case TIOCSSOFTCAR:
692 + error = get_user (arg, (unsigned long *)arg);
693 + if (error)
694 + return error;
695 + tty->termios->c_cflag = ((tty->termios->c_cflag & ~CLOCAL) | (arg ? CLOCAL : 0));
696 + return 0;
697 +
698 + case TIOCGSERIAL:
699 + error = access_ok (VERIFY_WRITE, (void *)arg, sizeof(struct serial_struct));
700 + if (!error)
701 + return -EFAULT;
702 + else
703 + return get_serial_info (info, (struct serial_struct *)arg);
704 +
705 + case TIOCSSERIAL:
706 + return set_serial_info (info, (struct serial_struct *) arg);
707 +
708 + case TIOCSERGETLSR: /* Get line status register */
709 + error = access_ok (VERIFY_WRITE, (void *)arg, sizeof(unsigned int));
710 + if (!error)
711 + return -EFAULT;
712 + else
713 + return get_lsr_info (info, (unsigned int *)arg);
714 +
715 + case TIOCSERGSTRUCT:
716 + error = access_ok (VERIFY_WRITE, (void *)arg, sizeof(struct bcm_serial));
717 + if (!error)
718 + return -EFAULT;
719 + else
720 + {
721 + copy_to_user((struct bcm_serial *)arg, info, sizeof(struct bcm_serial));
722 + return 0;
723 + }
724 +
725 + default:
726 + return -ENOIOCTLCMD;
727 + }
728 + return 0;
729 +}
730 +
731 +static void bcm_set_termios (struct tty_struct *tty, struct termios *old_termios)
732 +{
733 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
734 +
735 + if( tty->termios->c_cflag != old_termios->c_cflag )
736 + change_speed (info->port, tty->termios->c_cflag);
737 +}
738 +
739 +/*
740 + * ------------------------------------------------------------
741 + * bcm63xx_cons_close()
742 + *
743 + * This routine is called when the serial port gets closed. First, we
744 + * wait for the last remaining data to be sent. Then, we turn off
745 + * the transmit enable and receive enable flags.
746 + * ------------------------------------------------------------
747 + */
748 +static void bcm63xx_cons_close (struct tty_struct *tty, struct file *filp)
749 +{
750 + struct bcm_serial * info = (struct bcm_serial *)tty->driver_data;
751 + unsigned long flags;
752 +
753 + if (!info)
754 + return;
755 +
756 + /*save_flags (flags);
757 + cli();*/
758 + spin_lock_irqsave(&bcm963xx_serial_lock, flags);
759 +
760 + if (tty_hung_up_p (filp))
761 + {
762 + spin_unlock_irqrestore(&bcm963xx_serial_lock, flags);
763 + //restore_flags (flags);
764 + return;
765 + }
766 +
767 + if ((tty->count == 1) && (info->count != 1))
768 + {
769 +
770 + /* Uh, oh. tty->count is 1, which means that the tty
771 + * structure will be freed. Info->count should always
772 + * be one in these conditions. If it's greater than
773 + * one, we've got real problems, since it means the
774 + * serial port won't be shutdown.
775 + */
776 + printk("bcm63xx_cons_close: bad serial port count; tty->count is 1, "
777 + "info->count is %d\n", info->count);
778 + info->count = 1;
779 + }
780 +
781 + if (--info->count < 0)
782 + {
783 + printk("ds_close: bad serial port count for ttys%d: %d\n",
784 + info->line, info->count);
785 + info->count = 0;
786 + }
787 +
788 + if (info->count)
789 + {
790 + //restore_flags (flags);
791 + spin_unlock_irqrestore(&bcm963xx_serial_lock, flags);
792 + return;
793 + }
794 +
795 + /* Now we wait for the transmit buffer to clear; and we notify
796 + * the line discipline to only process XON/XOFF characters.
797 + */
798 + tty->closing = 1;
799 +
800 + /* At this point we stop accepting input. To do this, we
801 + * disable the receive line status interrupts.
802 + */
803 + shutdown (info);
804 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
805 + if (tty->driver->flush_buffer)
806 + tty->driver->flush_buffer (tty);
807 +#else
808 + if (tty->driver.flush_buffer)
809 + tty->driver.flush_buffer (tty);
810 +#endif
811 + if (tty->ldisc.flush_buffer)
812 + tty->ldisc.flush_buffer (tty);
813 +
814 + tty->closing = 0;
815 + info->event = 0;
816 + info->tty = 0;
817 + if (tty->ldisc.num != tty_ldisc_get(N_TTY)->num)
818 + {
819 + if (tty->ldisc.close)
820 + (tty->ldisc.close)(tty);
821 + tty->ldisc = *tty_ldisc_get(N_TTY);
822 + tty->termios->c_line = N_TTY;
823 + if (tty->ldisc.open)
824 + (tty->ldisc.open)(tty);
825 + }
826 + if (info->blocked_open)
827 + {
828 + if (info->close_delay)
829 + {
830 + current->state = TASK_INTERRUPTIBLE;
831 + schedule_timeout(info->close_delay);
832 + }
833 + wake_up_interruptible (&info->open_wait);
834 + }
835 + wake_up_interruptible (&info->close_wait);
836 +
837 + //restore_flags (flags);
838 + spin_unlock_irqrestore(&bcm963xx_serial_lock, flags);
839 +}
840 +
841 +/*
842 + * bcm_hangup () --- called by tty_hangup() when a hangup is signaled.
843 + */
844 +static void bcm_hangup (struct tty_struct *tty)
845 +{
846 +
847 + struct bcm_serial *info = (struct bcm_serial *)tty->driver_data;
848 +
849 + shutdown (info);
850 + info->event = 0;
851 + info->count = 0;
852 + info->tty = 0;
853 + wake_up_interruptible (&info->open_wait);
854 +}
855 +
856 +/*
857 + * ------------------------------------------------------------
858 + * rs_open() and friends
859 + * ------------------------------------------------------------
860 + */
861 +static int block_til_ready (struct tty_struct *tty, struct file *filp,
862 + struct bcm_serial *info)
863 +{
864 + return 0;
865 +}
866 +
867 +/*
868 + * This routine is called whenever a serial port is opened. It
869 + * enables interrupts for a serial port. It also performs the
870 + * serial-specific initialization for the tty structure.
871 + */
872 +static int bcm63xx_cons_open (struct tty_struct * tty, struct file * filp)
873 +{
874 + struct bcm_serial *info;
875 + int retval, line;
876 +
877 + // Make sure we're only opening on of the ports we support
878 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
879 + line = MINOR(tty->driver->cdev.dev) - tty->driver->minor_start;
880 +#else
881 + line = MINOR(tty->device) - tty->driver.minor_start;
882 +#endif
883 +
884 + if ((line < 0) || (line >= BCM_NUM_UARTS))
885 + return -ENODEV;
886 +
887 + info = lines[line];
888 +
889 + info->port->intMask = 0; /* Clear any pending interrupts */
890 + info->port->intMask = RXINT; /* Enable RX */
891 +
892 + info->count++;
893 + tty->driver_data = info;
894 + info->tty = tty;
895 + BcmHalInterruptEnable (INTERRUPT_ID_UART);
896 +
897 + // Start up serial port
898 + retval = startup (info);
899 + if (retval)
900 + return retval;
901 +
902 + retval = block_til_ready (tty, filp, info);
903 + if (retval)
904 + return retval;
905 +
906 +
907 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
908 + info->pgrp = process_group(current);
909 + info->session = current->signal->session;
910 +#else
911 + info->session = current->session;
912 + info->pgrp = current->pgrp;
913 +#endif
914 +
915 + return 0;
916 +}
917 +
918 +/* --------------------------------------------------------------------------
919 + Name: bcm63xx_serialinit
920 + Purpose: Initialize our BCM63xx serial driver
921 +-------------------------------------------------------------------------- */
922 +static int __init bcm63xx_serialinit(void)
923 +{
924 + int i, flags;
925 + struct bcm_serial * info;
926 +
927 + // Print the driver version information
928 + printk(VER_STR);
929 +
930 + memset(&serial_driver, 0, sizeof(struct tty_driver));
931 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
932 + serial_driver.owner = THIS_MODULE;
933 + serial_driver.devfs_name = "tts/";
934 +#endif
935 + serial_driver.magic = TTY_DRIVER_MAGIC;
936 + serial_driver.name = "ttyS";
937 + serial_driver.major = TTY_MAJOR;
938 + serial_driver.minor_start = 64;
939 + serial_driver.num = BCM_NUM_UARTS;
940 + serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
941 + serial_driver.subtype = SERIAL_TYPE_NORMAL;
942 + serial_driver.init_termios = tty_std_termios;
943 + serial_driver.init_termios.c_cflag = B115200 | CS8 | CREAD | CLOCAL;
944 + serial_driver.flags = TTY_DRIVER_REAL_RAW;
945 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
946 + serial_driver.refcount = serial_refcount;
947 + serial_driver.ttys = serial_table;
948 +#else
949 + serial_driver.refcount = &serial_refcount;
950 + serial_driver.table = serial_table;
951 +#endif
952 +
953 + serial_driver.termios = serial_termios;
954 + serial_driver.termios_locked = serial_termios_locked;
955 + serial_driver.open = bcm63xx_cons_open;
956 + serial_driver.close = bcm63xx_cons_close;
957 + serial_driver.write = bcm63xx_cons_write;
958 + serial_driver.flush_chars = bcm63xx_cons_flush_chars;
959 + serial_driver.write_room = bcm63xx_cons_write_room;
960 + serial_driver.chars_in_buffer = bcm_chars_in_buffer;
961 + serial_driver.flush_buffer = bcm_flush_buffer;
962 + serial_driver.ioctl = bcm_ioctl;
963 + serial_driver.throttle = bcm_throttle;
964 + serial_driver.unthrottle = bcm_unthrottle;
965 + serial_driver.send_xchar = bcm_send_xchar;
966 + serial_driver.set_termios = bcm_set_termios;
967 + serial_driver.stop = bcm_stop;
968 + serial_driver.start = bcm_start;
969 + serial_driver.hangup = bcm_hangup;
970 +
971 + if (tty_register_driver (&serial_driver))
972 + panic("Couldn't register serial driver\n");
973 +
974 + //save_flags(flags); cli();
975 + spin_lock_irqsave(&bcm963xx_serial_lock, flags);
976 +
977 + for (i = 0; i < BCM_NUM_UARTS; i++)
978 + {
979 + info = &multi[i];
980 + lines[i] = info;
981 + info->port = (Uart *) ((char *)UART_BASE + (i * 0x20));
982 + info->irq = (2 - i) + 8;
983 + info->line = i;
984 + info->tty = 0;
985 + info->close_delay = 50;
986 + info->closing_wait = 3000;
987 + info->x_char = 0;
988 + info->event = 0;
989 + info->count = 0;
990 + info->blocked_open = 0;
991 + info->normal_termios = serial_driver.init_termios;
992 + init_waitqueue_head(&info->open_wait);
993 + init_waitqueue_head(&info->close_wait);
994 +
995 + /* If we are pointing to address zero then punt - not correctly
996 + * set up in setup.c to handle this.
997 + */
998 + if (! info->port)
999 + return 0;
1000 + BcmHalMapInterrupt(bcm_interrupt, 0, INTERRUPT_ID_UART);
1001 + }
1002 +
1003 + /* order matters here... the trick is that flags
1004 + * is updated... in request_irq - to immediatedly obliterate
1005 + * it is unwise.
1006 + */
1007 + //restore_flags(flags);
1008 + spin_unlock_irqrestore(&bcm963xx_serial_lock, flags);
1009 + return 0;
1010 +}
1011 +
1012 +module_init(bcm63xx_serialinit);
1013 +
1014 +/* --------------------------------------------------------------------------
1015 + Name: bcm_console_print
1016 + Purpose: bcm_console_print is registered for printk.
1017 + The console_lock must be held when we get here.
1018 +-------------------------------------------------------------------------- */
1019 +static void bcm_console_print (struct console * cons, const char * str,
1020 + unsigned int count)
1021 +{
1022 + unsigned int i;
1023 + //_puts(str);
1024 + for(i=0; i<count; i++, str++)
1025 + {
1026 + _putc(*str);
1027 + if (*str == 10)
1028 + {
1029 + _putc(13);
1030 + }
1031 + }
1032 +}
1033 +
1034 +static struct tty_driver * bcm_console_device(struct console * c, int *index)
1035 +{
1036 + *index = c->index;
1037 + return &serial_driver;
1038 +}
1039 +
1040 +static int __init bcm_console_setup(struct console * co, char * options)
1041 +{
1042 + return 0;
1043 +}
1044 +
1045 +static struct console bcm_sercons = {
1046 + .name = "ttyS",
1047 + .write = bcm_console_print,
1048 + .device = bcm_console_device,
1049 + .setup = bcm_console_setup,
1050 + .flags = CON_PRINTBUFFER, // CON_CONSDEV, CONSOLE_LINE,
1051 + .index = -1,
1052 +};
1053 +
1054 +static int __init bcm63xx_console_init(void)
1055 +{
1056 + register_console(&bcm_sercons);
1057 + return 0;
1058 +}
1059 +
1060 +console_initcall(bcm63xx_console_init);
1061 diff -urN linux-2.6.17/bcmdrivers/opensource/char/serial/impl1/Makefile linux-2.6.17-brcm63xx/bcmdrivers/opensource/char/serial/impl1/Makefile
1062 --- linux-2.6.17/bcmdrivers/opensource/char/serial/impl1/Makefile 1970-01-01 01:00:00.000000000 +0100
1063 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/char/serial/impl1/Makefile 2006-08-03 16:42:38.000000000 +0200
1064 @@ -0,0 +1,13 @@
1065 +# File: bcmdrivers/opensource/char/serial
1066 +#
1067 +# Makefile for the BCM63xx serial/console driver
1068 +
1069 +obj-$(CONFIG_BCM_SERIAL) += bcm63xx_cons.o
1070 +
1071 +EXTRA_CFLAGS += -I$(INC_BRCMDRIVER_PUB_PATH)/$(BRCM_BOARD)
1072 +
1073 +-include $(TOPDIR)/Rules.make
1074 +
1075 +clean:
1076 + rm -f core *.o *.a *.s
1077 +
1078 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6338_intr.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6338_intr.h
1079 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6338_intr.h 1970-01-01 01:00:00.000000000 +0100
1080 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6338_intr.h 2006-08-03 16:42:38.000000000 +0200
1081 @@ -0,0 +1,64 @@
1082 +/*
1083 +<:copyright-gpl
1084 + Copyright 2003 Broadcom Corp. All Rights Reserved.
1085 +
1086 + This program is free software; you can distribute it and/or modify it
1087 + under the terms of the GNU General Public License (Version 2) as
1088 + published by the Free Software Foundation.
1089 +
1090 + This program is distributed in the hope it will be useful, but WITHOUT
1091 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1092 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1093 + for more details.
1094 +
1095 + You should have received a copy of the GNU General Public License along
1096 + with this program; if not, write to the Free Software Foundation, Inc.,
1097 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1098 +:>
1099 +*/
1100 +
1101 +#ifndef __6338_INTR_H
1102 +#define __6338_INTR_H
1103 +
1104 +/*=====================================================================*/
1105 +/* BCM6338 External Interrupt Level Assignments */
1106 +/*=====================================================================*/
1107 +#define INTERRUPT_ID_EXTERNAL_0 3
1108 +#define INTERRUPT_ID_EXTERNAL_1 4
1109 +#define INTERRUPT_ID_EXTERNAL_2 5
1110 +#define INTERRUPT_ID_EXTERNAL_3 6
1111 +
1112 +/*=====================================================================*/
1113 +/* BCM6338 Timer Interrupt Level Assignments */
1114 +/*=====================================================================*/
1115 +#define MIPS_TIMER_INT 7
1116 +
1117 +/*=====================================================================*/
1118 +/* Peripheral ISR Table Offset */
1119 +/*=====================================================================*/
1120 +#define INTERNAL_ISR_TABLE_OFFSET 8
1121 +
1122 +/*=====================================================================*/
1123 +/* Logical Peripheral Interrupt IDs */
1124 +/*=====================================================================*/
1125 +
1126 +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
1127 +#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1)
1128 +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
1129 +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 4)
1130 +#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 5)
1131 +#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 6)
1132 +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 7)
1133 +#define INTERRUPT_ID_EMAC1 (INTERNAL_ISR_TABLE_OFFSET + 8)
1134 +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 9)
1135 +#define INTERRUPT_ID_SDRAM (INTERNAL_ISR_TABLE_OFFSET + 10)
1136 +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 11)
1137 +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 12)
1138 +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 13)
1139 +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 14)
1140 +#define INTERRUPT_ID_EMAC1_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 15)
1141 +#define INTERRUPT_ID_EMAC1_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 16)
1142 +#define INTERRUPT_ID_SDIO (INTERNAL_ISR_TABLE_OFFSET + 17)
1143 +
1144 +#endif /* __BCM6338_H */
1145 +
1146 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h
1147 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h 1970-01-01 01:00:00.000000000 +0100
1148 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h 2006-08-03 16:42:38.000000000 +0200
1149 @@ -0,0 +1,334 @@
1150 +/*
1151 +<:copyright-gpl
1152 + Copyright 2004 Broadcom Corp. All Rights Reserved.
1153 +
1154 + This program is free software; you can distribute it and/or modify it
1155 + under the terms of the GNU General Public License (Version 2) as
1156 + published by the Free Software Foundation.
1157 +
1158 + This program is distributed in the hope it will be useful, but WITHOUT
1159 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1160 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1161 + for more details.
1162 +
1163 + You should have received a copy of the GNU General Public License along
1164 + with this program; if not, write to the Free Software Foundation, Inc.,
1165 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1166 +:>
1167 +*/
1168 +
1169 +#ifndef __BCM6338_MAP_H
1170 +#define __BCM6338_MAP_H
1171 +
1172 +#include "bcmtypes.h"
1173 +
1174 +#define PERF_BASE 0xfffe0000
1175 +#define TIMR_BASE 0xfffe0200
1176 +#define UART_BASE 0xfffe0300
1177 +#define GPIO_BASE 0xfffe0400
1178 +#define SPI_BASE 0xfffe0c00
1179 +
1180 +typedef struct PerfControl {
1181 + uint32 RevID;
1182 + uint16 testControl;
1183 + uint16 blkEnables;
1184 +#define EMAC_CLK_EN 0x0010
1185 +#define USBS_CLK_EN 0x0010
1186 +#define SAR_CLK_EN 0x0020
1187 +
1188 +#define SPI_CLK_EN 0x0200
1189 +
1190 + uint32 pll_control;
1191 +#define SOFT_RESET 0x00000001
1192 +
1193 + uint32 IrqMask;
1194 + uint32 IrqStatus;
1195 +
1196 + uint32 ExtIrqCfg;
1197 +#define EI_SENSE_SHFT 0
1198 +#define EI_STATUS_SHFT 5
1199 +#define EI_CLEAR_SHFT 10
1200 +#define EI_MASK_SHFT 15
1201 +#define EI_INSENS_SHFT 20
1202 +#define EI_LEVEL_SHFT 25
1203 +
1204 + uint32 unused[4]; /* (18) */
1205 + uint32 BlockSoftReset; /* (28) */
1206 +#define BSR_SPI 0x00000001
1207 +#define BSR_EMAC 0x00000004
1208 +#define BSR_USBH 0x00000008
1209 +#define BSR_USBS 0x00000010
1210 +#define BSR_ADSL 0x00000020
1211 +#define BSR_DMAMEM 0x00000040
1212 +#define BSR_SAR 0x00000080
1213 +#define BSR_ACLC 0x00000100
1214 +#define BSR_ADSL_MIPS_PLL 0x00000400
1215 +#define BSR_ALL_BLOCKS \
1216 + (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
1217 + BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
1218 +} PerfControl;
1219 +
1220 +#define PERF ((volatile PerfControl * const) PERF_BASE)
1221 +
1222 +
1223 +typedef struct Timer {
1224 + uint16 unused0;
1225 + byte TimerMask;
1226 +#define TIMER0EN 0x01
1227 +#define TIMER1EN 0x02
1228 +#define TIMER2EN 0x04
1229 + byte TimerInts;
1230 +#define TIMER0 0x01
1231 +#define TIMER1 0x02
1232 +#define TIMER2 0x04
1233 +#define WATCHDOG 0x08
1234 + uint32 TimerCtl0;
1235 + uint32 TimerCtl1;
1236 + uint32 TimerCtl2;
1237 +#define TIMERENABLE 0x80000000
1238 +#define RSTCNTCLR 0x40000000
1239 + uint32 TimerCnt0;
1240 + uint32 TimerCnt1;
1241 + uint32 TimerCnt2;
1242 + uint32 WatchDogDefCount;
1243 +
1244 + /* Write 0xff00 0x00ff to Start timer
1245 + * Write 0xee00 0x00ee to Stop and re-load default count
1246 + * Read from this register returns current watch dog count
1247 + */
1248 + uint32 WatchDogCtl;
1249 +
1250 + /* Number of 40-MHz ticks for WD Reset pulse to last */
1251 + uint32 WDResetCount;
1252 +} Timer;
1253 +
1254 +#define TIMER ((volatile Timer * const) TIMR_BASE)
1255 +typedef struct UartChannel {
1256 + byte unused0;
1257 + byte control;
1258 +#define BRGEN 0x80 /* Control register bit defs */
1259 +#define TXEN 0x40
1260 +#define RXEN 0x20
1261 +#define LOOPBK 0x10
1262 +#define TXPARITYEN 0x08
1263 +#define TXPARITYEVEN 0x04
1264 +#define RXPARITYEN 0x02
1265 +#define RXPARITYEVEN 0x01
1266 +
1267 + byte config;
1268 +#define XMITBREAK 0x40
1269 +#define BITS5SYM 0x00
1270 +#define BITS6SYM 0x10
1271 +#define BITS7SYM 0x20
1272 +#define BITS8SYM 0x30
1273 +#define ONESTOP 0x07
1274 +#define TWOSTOP 0x0f
1275 + /* 4-LSBS represent STOP bits/char
1276 + * in 1/8 bit-time intervals. Zero
1277 + * represents 1/8 stop bit interval.
1278 + * Fifteen represents 2 stop bits.
1279 + */
1280 + byte fifoctl;
1281 +#define RSTTXFIFOS 0x80
1282 +#define RSTRXFIFOS 0x40
1283 + /* 5-bit TimeoutCnt is in low bits of this register.
1284 + * This count represents the number of characters
1285 + * idle times before setting receive Irq when below threshold
1286 + */
1287 + uint32 baudword;
1288 + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
1289 + */
1290 +
1291 + byte txf_levl; /* Read-only fifo depth */
1292 + byte rxf_levl; /* Read-only fifo depth */
1293 + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
1294 + * RxThreshold. Irq can be asserted
1295 + * when rx fifo> thresh, txfifo<thresh
1296 + */
1297 + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
1298 + * if these bits are also enabled to GPIO_o
1299 + */
1300 +#define DTREN 0x01
1301 +#define RTSEN 0x02
1302 +
1303 + byte unused1;
1304 + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
1305 + * detect irq on rising AND falling
1306 + * edges for corresponding GPIO_i
1307 + * if enabled (edge insensitive)
1308 + */
1309 + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
1310 + * 0 for negedge sense if
1311 + * not configured for edge
1312 + * insensitive (see above)
1313 + * Lower 4 bits: Mask to enable change
1314 + * detection IRQ for corresponding
1315 + * GPIO_i
1316 + */
1317 + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
1318 + * have changed (may set IRQ).
1319 + * read automatically clears bit
1320 + * Lower 4 bits are actual status
1321 + */
1322 +
1323 + uint16 intMask; /* Same Bit defs for Mask and status */
1324 + uint16 intStatus;
1325 +#define DELTAIP 0x0001
1326 +#define TXUNDERR 0x0002
1327 +#define TXOVFERR 0x0004
1328 +#define TXFIFOTHOLD 0x0008
1329 +#define TXREADLATCH 0x0010
1330 +#define TXFIFOEMT 0x0020
1331 +#define RXUNDERR 0x0040
1332 +#define RXOVFERR 0x0080
1333 +#define RXTIMEOUT 0x0100
1334 +#define RXFIFOFULL 0x0200
1335 +#define RXFIFOTHOLD 0x0400
1336 +#define RXFIFONE 0x0800
1337 +#define RXFRAMERR 0x1000
1338 +#define RXPARERR 0x2000
1339 +#define RXBRK 0x4000
1340 +
1341 + uint16 unused2;
1342 + uint16 Data; /* Write to TX, Read from RX */
1343 + /* bits 11:8 are BRK,PAR,FRM errors */
1344 +
1345 + uint32 unused3;
1346 + uint32 unused4;
1347 +} Uart;
1348 +
1349 +#define UART ((volatile Uart * const) UART_BASE)
1350 +
1351 +typedef struct GpioControl {
1352 + uint32 unused0;
1353 + uint32 GPIODir; /* bits 7:0 */
1354 + uint32 unused1;
1355 + uint32 GPIOio; /* bits 7:0 */
1356 + uint32 LEDCtrl;
1357 +#define LED3_STROBE 0x08000000
1358 +#define LED2_STROBE 0x04000000
1359 +#define LED1_STROBE 0x02000000
1360 +#define LED0_STROBE 0x01000000
1361 +#define LED_TEST 0x00010000
1362 +#define LED3_DISABLE_LINK_ACT 0x00008000
1363 +#define LED2_DISABLE_LINK_ACT 0x00004000
1364 +#define LED1_DISABLE_LINK_ACT 0x00002000
1365 +#define LED0_DISABLE_LINK_ACT 0x00001000
1366 +#define LED_INTERVAL_SET_MASK 0x00000f00
1367 +#define LED_INTERVAL_SET_320MS 0x00000500
1368 +#define LED_INTERVAL_SET_160MS 0x00000400
1369 +#define LED_INTERVAL_SET_80MS 0x00000300
1370 +#define LED_INTERVAL_SET_40MS 0x00000200
1371 +#define LED_INTERVAL_SET_20MS 0x00000100
1372 +#define LED3_ON 0x00000080
1373 +#define LED2_ON 0x00000040
1374 +#define LED1_ON 0x00000020
1375 +#define LED0_ON 0x00000010
1376 +#define LED3_ENABLE 0x00000008
1377 +#define LED2_ENABLE 0x00000004
1378 +#define LED1_ENABLE 0x00000002
1379 +#define LED0_ENABLE 0x00000001
1380 + uint32 SpiSlaveCfg;
1381 +#define SPI_SLAVE_RESET 0x00010000
1382 +#define SPI_RESTRICT 0x00000400
1383 +#define SPI_DELAY_DISABLE 0x00000200
1384 +#define SPI_PROBE_MUX_SEL_MASK 0x000001e0
1385 +#define SPI_SER_ADDR_CFG_MASK 0x0000000c
1386 +#define SPI_MODE 0x00000001
1387 + uint32 vRegConfig;
1388 +} GpioControl;
1389 +
1390 +#define GPIO ((volatile GpioControl * const) GPIO_BASE)
1391 +
1392 +/* Number to mask conversion macro used for GPIODir and GPIOio */
1393 +#define GPIO_NUM_MAX_BITS_MASK 0x0f
1394 +#define GPIO_NUM_TO_MASK(X) (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
1395 +
1396 +/*
1397 +** Spi Controller
1398 +*/
1399 +
1400 +typedef struct SpiControl {
1401 + uint16 spiCmd; /* (0x0): SPI command */
1402 +#define SPI_CMD_START_IMMEDIATE 3
1403 +
1404 +#define SPI_CMD_COMMAND_SHIFT 0
1405 +#define SPI_CMD_DEVICE_ID_SHIFT 4
1406 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1407 +
1408 + byte spiIntStatus; /* (0x2): SPI interrupt status */
1409 + byte spiMaskIntStatus; /* (0x3): SPI masked interrupt status */
1410 +
1411 + byte spiIntMask; /* (0x4): SPI interrupt mask */
1412 +#define SPI_INTR_CMD_DONE 0x01
1413 +#define SPI_INTR_CLEAR_ALL 0x1f
1414 +
1415 + byte spiStatus; /* (0x5): SPI status */
1416 +
1417 + byte spiClkCfg; /* (0x6): SPI clock configuration */
1418 +
1419 + byte spiFillByte; /* (0x7): SPI fill byte */
1420 +
1421 + byte unused0;
1422 + byte spiMsgTail; /* (0x9): msgtail */
1423 + byte unused1;
1424 + byte spiRxTail; /* (0xB): rxtail */
1425 +
1426 + uint32 unused2[13]; /* (0x0c - 0x3c) reserved */
1427 +
1428 + byte spiMsgCtl; /* (0x40) control byte */
1429 +#define HALF_DUPLEX_W 1
1430 +#define HALF_DUPLEX_R 2
1431 +#define SPI_MSG_TYPE_SHIFT 6
1432 +#define SPI_BYTE_CNT_SHIFT 0
1433 + byte spiMsgData[63]; /* (0x41 - 0x7f) msg data */
1434 + byte spiRxDataFifo[64]; /* (0x80 - 0xbf) rx data */
1435 + byte unused3[64]; /* (0xc0 - 0xff) reserved */
1436 +} SpiControl;
1437 +
1438 +#define SPI ((volatile SpiControl * const) SPI_BASE)
1439 +
1440 +/*
1441 +** External Bus Interface
1442 +*/
1443 +typedef struct EbiChipSelect {
1444 + uint32 base; /* base address in upper 24 bits */
1445 +#define EBI_SIZE_8K 0
1446 +#define EBI_SIZE_16K 1
1447 +#define EBI_SIZE_32K 2
1448 +#define EBI_SIZE_64K 3
1449 +#define EBI_SIZE_128K 4
1450 +#define EBI_SIZE_256K 5
1451 +#define EBI_SIZE_512K 6
1452 +#define EBI_SIZE_1M 7
1453 +#define EBI_SIZE_2M 8
1454 +#define EBI_SIZE_4M 9
1455 +#define EBI_SIZE_8M 10
1456 +#define EBI_SIZE_16M 11
1457 +#define EBI_SIZE_32M 12
1458 +#define EBI_SIZE_64M 13
1459 +#define EBI_SIZE_128M 14
1460 +#define EBI_SIZE_256M 15
1461 + uint32 config;
1462 +#define EBI_ENABLE 0x00000001 /* .. enable this range */
1463 +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
1464 +#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
1465 +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
1466 +#define EBI_WREN 0x00000020 /* enable posted writes */
1467 +#define EBI_POLARITY 0x00000040 /* .. set to invert something,
1468 + ** don't know what yet */
1469 +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
1470 +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
1471 +#define EBI_FIFO 0x00000200 /* .. use fifo */
1472 +#define EBI_RE 0x00000400 /* .. Reverse Endian */
1473 +} EbiChipSelect;
1474 +
1475 +typedef struct MpiRegisters {
1476 + EbiChipSelect cs[1]; /* size chip select configuration */
1477 +} MpiRegisters;
1478 +
1479 +#define MPI ((volatile MpiRegisters * const) MPI_BASE)
1480 +
1481 +
1482 +#endif
1483 +
1484 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6345_intr.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6345_intr.h
1485 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6345_intr.h 1970-01-01 01:00:00.000000000 +0100
1486 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6345_intr.h 2006-08-03 16:42:38.000000000 +0200
1487 @@ -0,0 +1,72 @@
1488 +/*
1489 +<:copyright-gpl
1490 + Copyright 2002 Broadcom Corp. All Rights Reserved.
1491 +
1492 + This program is free software; you can distribute it and/or modify it
1493 + under the terms of the GNU General Public License (Version 2) as
1494 + published by the Free Software Foundation.
1495 +
1496 + This program is distributed in the hope it will be useful, but WITHOUT
1497 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1498 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1499 + for more details.
1500 +
1501 + You should have received a copy of the GNU General Public License along
1502 + with this program; if not, write to the Free Software Foundation, Inc.,
1503 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1504 +:>
1505 +*/
1506 +
1507 +#ifndef __6345_INTR_H
1508 +#define __6345_INTR_H
1509 +
1510 +
1511 +/*=====================================================================*/
1512 +/* BCM6345 External Interrupt Level Assignments */
1513 +/*=====================================================================*/
1514 +#define INTERRUPT_ID_EXTERNAL_0 3
1515 +#define INTERRUPT_ID_EXTERNAL_1 4
1516 +#define INTERRUPT_ID_EXTERNAL_2 5
1517 +#define INTERRUPT_ID_EXTERNAL_3 6
1518 +
1519 +/*=====================================================================*/
1520 +/* BCM6345 Timer Interrupt Level Assignments */
1521 +/*=====================================================================*/
1522 +#define MIPS_TIMER_INT 7
1523 +
1524 +/*=====================================================================*/
1525 +/* Peripheral ISR Table Offset */
1526 +/*=====================================================================*/
1527 +#define INTERNAL_ISR_TABLE_OFFSET 8
1528 +#define DMA_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 13)
1529 +
1530 +/*=====================================================================*/
1531 +/* Logical Peripheral Interrupt IDs */
1532 +/*=====================================================================*/
1533 +
1534 +/* Internal peripheral interrupt IDs */
1535 +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
1536 +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
1537 +#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 3)
1538 +#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 4)
1539 +#define INTERRUPT_ID_USB (INTERNAL_ISR_TABLE_OFFSET + 5)
1540 +#define INTERRUPT_ID_EMAC (INTERNAL_ISR_TABLE_OFFSET + 8)
1541 +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 12)
1542 +
1543 +/* DMA channel interrupt IDs */
1544 +#define INTERRUPT_ID_EMAC_RX_CHAN (DMA_ISR_TABLE_OFFSET + EMAC_RX_CHAN)
1545 +#define INTERRUPT_ID_EMAC_TX_CHAN (DMA_ISR_TABLE_OFFSET + EMAC_TX_CHAN)
1546 +#define INTERRUPT_ID_EBI_RX_CHAN (DMA_ISR_TABLE_OFFSET + EBI_RX_CHAN)
1547 +#define INTERRUPT_ID_EBI_TX_CHAN (DMA_ISR_TABLE_OFFSET + EBI_TX_CHAN)
1548 +#define INTERRUPT_ID_RESERVED_RX_CHAN (DMA_ISR_TABLE_OFFSET + RESERVED_RX_CHAN)
1549 +#define INTERRUPT_ID_RESERVED_TX_CHAN (DMA_ISR_TABLE_OFFSET + RESERVED_TX_CHAN)
1550 +#define INTERRUPT_ID_USB_BULK_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_BULK_RX_CHAN)
1551 +#define INTERRUPT_ID_USB_BULK_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_BULK_TX_CHAN)
1552 +#define INTERRUPT_ID_USB_CNTL_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_CNTL_RX_CHAN)
1553 +#define INTERRUPT_ID_USB_CNTL_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_CNTL_TX_CHAN)
1554 +#define INTERRUPT_ID_USB_ISO_RX_CHAN (DMA_ISR_TABLE_OFFSET + USB_ISO_RX_CHAN)
1555 +#define INTERRUPT_ID_USB_ISO_TX_CHAN (DMA_ISR_TABLE_OFFSET + USB_ISO_TX_CHAN)
1556 +
1557 +
1558 +#endif /* __BCM6345_H */
1559 +
1560 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h
1561 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h 1970-01-01 01:00:00.000000000 +0100
1562 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6345_map_part.h 2006-08-03 16:42:38.000000000 +0200
1563 @@ -0,0 +1,163 @@
1564 +/*
1565 +<:copyright-gpl
1566 + Copyright 2002 Broadcom Corp. All Rights Reserved.
1567 +
1568 + This program is free software; you can distribute it and/or modify it
1569 + under the terms of the GNU General Public License (Version 2) as
1570 + published by the Free Software Foundation.
1571 +
1572 + This program is distributed in the hope it will be useful, but WITHOUT
1573 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1574 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1575 + for more details.
1576 +
1577 + You should have received a copy of the GNU General Public License along
1578 + with this program; if not, write to the Free Software Foundation, Inc.,
1579 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1580 +:>
1581 +*/
1582 +
1583 +#ifndef __BCM6345_MAP_H
1584 +#define __BCM6345_MAP_H
1585 +
1586 +
1587 +#include "bcmtypes.h"
1588 +#include "6345_intr.h"
1589 +
1590 +typedef struct IntControl {
1591 + uint32 RevID;
1592 + uint16 testControl;
1593 + uint16 blkEnables;
1594 +#define USB_CLK_EN 0x0100
1595 +#define EMAC_CLK_EN 0x0080
1596 +#define UART_CLK_EN 0x0008
1597 +#define CPU_CLK_EN 0x0001
1598 +
1599 + uint32 pll_control;
1600 +#define SOFT_RESET 0x00000001
1601 +
1602 + uint32 IrqMask;
1603 + uint32 IrqStatus;
1604 +
1605 + uint32 ExtIrqCfg;
1606 +#define EI_SENSE_SHFT 0
1607 +#define EI_STATUS_SHFT 4
1608 +#define EI_CLEAR_SHFT 8
1609 +#define EI_MASK_SHFT 12
1610 +#define EI_INSENS_SHFT 16
1611 +#define EI_LEVEL_SHFT 20
1612 +} IntControl;
1613 +
1614 +#define INTC_BASE 0xfffe0000
1615 +#define PERF ((volatile IntControl * const) INTC_BASE)
1616 +
1617 +#define TIMR_BASE 0xfffe0200
1618 +typedef struct Timer {
1619 + uint16 unused0;
1620 + byte TimerMask;
1621 +#define TIMER0EN 0x01
1622 +#define TIMER1EN 0x02
1623 +#define TIMER2EN 0x04
1624 + byte TimerInts;
1625 +#define TIMER0 0x01
1626 +#define TIMER1 0x02
1627 +#define TIMER2 0x04
1628 +#define WATCHDOG 0x08
1629 + uint32 TimerCtl0;
1630 + uint32 TimerCtl1;
1631 + uint32 TimerCtl2;
1632 +#define TIMERENABLE 0x80000000
1633 +#define RSTCNTCLR 0x40000000
1634 + uint32 TimerCnt0;
1635 + uint32 TimerCnt1;
1636 + uint32 TimerCnt2;
1637 + uint32 WatchDogDefCount;
1638 +
1639 + /* Write 0xff00 0x00ff to Start timer
1640 + * Write 0xee00 0x00ee to Stop and re-load default count
1641 + * Read from this register returns current watch dog count
1642 + */
1643 + uint32 WatchDogCtl;
1644 +
1645 + /* Number of 40-MHz ticks for WD Reset pulse to last */
1646 + uint32 WDResetCount;
1647 +} Timer;
1648 +
1649 +#define TIMER ((volatile Timer * const) TIMR_BASE)
1650 +
1651 +typedef struct UartChannel {
1652 + byte unused0;
1653 + byte control;
1654 +#define BRGEN 0x80 /* Control register bit defs */
1655 +#define TXEN 0x40
1656 +#define RXEN 0x20
1657 +#define TXPARITYEN 0x08
1658 +#define TXPARITYEVEN 0x04
1659 +#define RXPARITYEN 0x02
1660 +#define RXPARITYEVEN 0x01
1661 + byte config;
1662 +#define BITS5SYM 0x00
1663 +#define BITS6SYM 0x10
1664 +#define BITS7SYM 0x20
1665 +#define BITS8SYM 0x30
1666 +#define XMITBREAK 0x40
1667 +#define ONESTOP 0x07
1668 +#define TWOSTOP 0x0f
1669 +
1670 + byte fifoctl;
1671 +#define RSTTXFIFOS 0x80
1672 +#define RSTRXFIFOS 0x40
1673 + uint32 baudword;
1674 +
1675 + byte txf_levl;
1676 + byte rxf_levl;
1677 + byte fifocfg;
1678 + byte prog_out;
1679 +
1680 + byte unused1;
1681 + byte DeltaIPEdgeNoSense;
1682 + byte DeltaIPConfig_Mask;
1683 + byte DeltaIP_SyncIP;
1684 + uint16 intMask;
1685 + uint16 intStatus;
1686 +#define TXUNDERR 0x0002
1687 +#define TXOVFERR 0x0004
1688 +#define TXFIFOEMT 0x0020
1689 +#define RXOVFERR 0x0080
1690 +#define RXFIFONE 0x0800
1691 +#define RXFRAMERR 0x1000
1692 +#define RXPARERR 0x2000
1693 +#define RXBRK 0x4000
1694 +
1695 + uint16 unused2;
1696 + uint16 Data;
1697 + uint32 unused3;
1698 + uint32 unused4;
1699 +} Uart;
1700 +
1701 +#define UART_BASE 0xfffe0300
1702 +#define UART ((volatile Uart * const) UART_BASE)
1703 +
1704 +typedef struct GpioControl {
1705 + uint16 unused0;
1706 + byte unused1;
1707 + byte TBusSel;
1708 +
1709 + uint16 unused2;
1710 + uint16 GPIODir;
1711 + byte unused3;
1712 + byte Leds;
1713 + uint16 GPIOio;
1714 +
1715 + uint32 UartCtl;
1716 +} GpioControl;
1717 +
1718 +#define GPIO_BASE 0xfffe0400
1719 +#define GPIO ((volatile GpioControl * const) GPIO_BASE)
1720 +
1721 +#define GPIO_NUM_MAX_BITS_MASK 0x0f
1722 +#define GPIO_NUM_TO_MASK(X) (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
1723 +
1724 +
1725 +#endif
1726 +
1727 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6348_intr.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6348_intr.h
1728 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6348_intr.h 1970-01-01 01:00:00.000000000 +0100
1729 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6348_intr.h 2006-08-03 16:42:38.000000000 +0200
1730 @@ -0,0 +1,74 @@
1731 +/*
1732 +<:copyright-gpl
1733 + Copyright 2003 Broadcom Corp. All Rights Reserved.
1734 +
1735 + This program is free software; you can distribute it and/or modify it
1736 + under the terms of the GNU General Public License (Version 2) as
1737 + published by the Free Software Foundation.
1738 +
1739 + This program is distributed in the hope it will be useful, but WITHOUT
1740 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1741 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1742 + for more details.
1743 +
1744 + You should have received a copy of the GNU General Public License along
1745 + with this program; if not, write to the Free Software Foundation, Inc.,
1746 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1747 +:>
1748 +*/
1749 +
1750 +#ifndef __6348_INTR_H
1751 +#define __6348_INTR_H
1752 +
1753 +
1754 +/*=====================================================================*/
1755 +/* BCM6348 External Interrupt Level Assignments */
1756 +/*=====================================================================*/
1757 +#define INTERRUPT_ID_EXTERNAL_0 3
1758 +#define INTERRUPT_ID_EXTERNAL_1 4
1759 +#define INTERRUPT_ID_EXTERNAL_2 5
1760 +#define INTERRUPT_ID_EXTERNAL_3 6
1761 +
1762 +/*=====================================================================*/
1763 +/* BCM6348 Timer Interrupt Level Assignments */
1764 +/*=====================================================================*/
1765 +#define MIPS_TIMER_INT 7
1766 +
1767 +/*=====================================================================*/
1768 +/* Peripheral ISR Table Offset */
1769 +/*=====================================================================*/
1770 +#define INTERNAL_ISR_TABLE_OFFSET 8
1771 +
1772 +/*=====================================================================*/
1773 +/* Logical Peripheral Interrupt IDs */
1774 +/*=====================================================================*/
1775 +
1776 +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 0)
1777 +#define INTERRUPT_ID_SPI (INTERNAL_ISR_TABLE_OFFSET + 1)
1778 +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 2)
1779 +#define INTERRUPT_ID_ADSL (INTERNAL_ISR_TABLE_OFFSET + 4)
1780 +#define INTERRUPT_ID_ATM (INTERNAL_ISR_TABLE_OFFSET + 5)
1781 +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 6)
1782 +#define INTERRUPT_ID_EMAC2 (INTERNAL_ISR_TABLE_OFFSET + 7)
1783 +#define INTERRUPT_ID_EMAC1 (INTERNAL_ISR_TABLE_OFFSET + 8)
1784 +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 9)
1785 +#define INTERRUPT_ID_M2M (INTERNAL_ISR_TABLE_OFFSET + 10)
1786 +#define INTERRUPT_ID_ACLC (INTERNAL_ISR_TABLE_OFFSET + 11)
1787 +#define INTERRUPT_ID_USBH (INTERNAL_ISR_TABLE_OFFSET + 12)
1788 +#define INTERRUPT_ID_SDRAM (INTERNAL_ISR_TABLE_OFFSET + 13)
1789 +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 14)
1790 +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 15)
1791 +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 16)
1792 +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 17)
1793 +#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 18)
1794 +#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 19)
1795 +#define INTERRUPT_ID_EMAC1_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 20)
1796 +#define INTERRUPT_ID_EMAC1_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 21)
1797 +#define INTERRUPT_ID_EMAC2_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 22)
1798 +#define INTERRUPT_ID_EMAC2_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 23)
1799 +#define INTERRUPT_ID_MPI (INTERNAL_ISR_TABLE_OFFSET + 24)
1800 +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 25)
1801 +
1802 +
1803 +#endif /* __BCM6348_H */
1804 +
1805 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6348_map_part.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6348_map_part.h
1806 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/6348_map_part.h 1970-01-01 01:00:00.000000000 +0100
1807 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/6348_map_part.h 2006-08-03 16:42:38.000000000 +0200
1808 @@ -0,0 +1,500 @@
1809 +/*
1810 +<:copyright-gpl
1811 + Copyright 2002 Broadcom Corp. All Rights Reserved.
1812 +
1813 + This program is free software; you can distribute it and/or modify it
1814 + under the terms of the GNU General Public License (Version 2) as
1815 + published by the Free Software Foundation.
1816 +
1817 + This program is distributed in the hope it will be useful, but WITHOUT
1818 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1819 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1820 + for more details.
1821 +
1822 + You should have received a copy of the GNU General Public License along
1823 + with this program; if not, write to the Free Software Foundation, Inc.,
1824 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1825 +:>
1826 +*/
1827 +
1828 +#ifndef __BCM6348_MAP_H
1829 +#define __BCM6348_MAP_H
1830 +
1831 +#include "bcmtypes.h"
1832 +
1833 +#define PERF_BASE 0xfffe0000
1834 +#define TIMR_BASE 0xfffe0200
1835 +#define UART_BASE 0xfffe0300
1836 +#define GPIO_BASE 0xfffe0400
1837 +#define MPI_BASE 0xfffe2000 /* MPI control registers */
1838 +#define USB_HOST_BASE 0xfffe1b00 /* USB host registers */
1839 +#define USB_HOST_NON_OHCI 0xfffe1c00 /* USB host non-OHCI registers */
1840 +
1841 +typedef struct PerfControl {
1842 + uint32 RevID;
1843 + uint16 testControl;
1844 + uint16 blkEnables;
1845 +#define EMAC_CLK_EN 0x0010
1846 +#define SAR_CLK_EN 0x0020
1847 +#define USBS_CLK_EN 0x0040
1848 +#define USBH_CLK_EN 0x0100
1849 +
1850 + uint32 pll_control;
1851 +#define SOFT_RESET 0x00000001
1852 +
1853 + uint32 IrqMask;
1854 + uint32 IrqStatus;
1855 +
1856 + uint32 ExtIrqCfg;
1857 +#define EI_SENSE_SHFT 0
1858 +#define EI_STATUS_SHFT 5
1859 +#define EI_CLEAR_SHFT 10
1860 +#define EI_MASK_SHFT 15
1861 +#define EI_INSENS_SHFT 20
1862 +#define EI_LEVEL_SHFT 25
1863 +
1864 + uint32 unused[4]; /* (18) */
1865 + uint32 BlockSoftReset; /* (28) */
1866 +#define BSR_SPI 0x00000001
1867 +#define BSR_EMAC 0x00000004
1868 +#define BSR_USBH 0x00000008
1869 +#define BSR_USBS 0x00000010
1870 +#define BSR_ADSL 0x00000020
1871 +#define BSR_DMAMEM 0x00000040
1872 +#define BSR_SAR 0x00000080
1873 +#define BSR_ACLC 0x00000100
1874 +#define BSR_ADSL_MIPS_PLL 0x00000400
1875 +#define BSR_ALL_BLOCKS \
1876 + (BSR_SPI | BSR_EMAC | BSR_USBH | BSR_USBS | BSR_ADSL | BSR_DMAMEM | \
1877 + BSR_SAR | BSR_ACLC | BSR_ADSL_MIPS_PLL)
1878 + uint32 unused2[2]; /* (2c) */
1879 + uint32 PllStrap; /* (34) */
1880 +#define PLL_N1_SHFT 20
1881 +#define PLL_N1_MASK (7<<PLL_N1_SHFT)
1882 +#define PLL_N2_SHFT 15
1883 +#define PLL_N2_MASK (0x1f<<PLL_N2_SHFT)
1884 +#define PLL_M1_REF_SHFT 12
1885 +#define PLL_M1_REF_MASK (7<<PLL_M1_REF_SHFT)
1886 +#define PLL_M2_REF_SHFT 9
1887 +#define PLL_M2_REF_MASK (7<<PLL_M2_REF_SHFT)
1888 +#define PLL_M1_CPU_SHFT 6
1889 +#define PLL_M1_CPU_MASK (7<<PLL_M1_CPU_SHFT)
1890 +#define PLL_M1_BUS_SHFT 3
1891 +#define PLL_M1_BUS_MASK (7<<PLL_M1_BUS_SHFT)
1892 +#define PLL_M2_BUS_SHFT 0
1893 +#define PLL_M2_BUS_MASK (7<<PLL_M2_BUS_SHFT)
1894 +} PerfControl;
1895 +
1896 +#define PERF ((volatile PerfControl * const) PERF_BASE)
1897 +
1898 +typedef struct Timer {
1899 + uint16 unused0;
1900 + byte TimerMask;
1901 +#define TIMER0EN 0x01
1902 +#define TIMER1EN 0x02
1903 +#define TIMER2EN 0x04
1904 + byte TimerInts;
1905 +#define TIMER0 0x01
1906 +#define TIMER1 0x02
1907 +#define TIMER2 0x04
1908 +#define WATCHDOG 0x08
1909 + uint32 TimerCtl0;
1910 + uint32 TimerCtl1;
1911 + uint32 TimerCtl2;
1912 +#define TIMERENABLE 0x80000000
1913 +#define RSTCNTCLR 0x40000000
1914 + uint32 TimerCnt0;
1915 + uint32 TimerCnt1;
1916 + uint32 TimerCnt2;
1917 + uint32 WatchDogDefCount;
1918 +
1919 + /* Write 0xff00 0x00ff to Start timer
1920 + * Write 0xee00 0x00ee to Stop and re-load default count
1921 + * Read from this register returns current watch dog count
1922 + */
1923 + uint32 WatchDogCtl;
1924 +
1925 + /* Number of 40-MHz ticks for WD Reset pulse to last */
1926 + uint32 WDResetCount;
1927 +} Timer;
1928 +
1929 +#define TIMER ((volatile Timer * const) TIMR_BASE)
1930 +
1931 +typedef struct UartChannel {
1932 + byte unused0;
1933 + byte control;
1934 +#define BRGEN 0x80 /* Control register bit defs */
1935 +#define TXEN 0x40
1936 +#define RXEN 0x20
1937 +#define LOOPBK 0x10
1938 +#define TXPARITYEN 0x08
1939 +#define TXPARITYEVEN 0x04
1940 +#define RXPARITYEN 0x02
1941 +#define RXPARITYEVEN 0x01
1942 +
1943 + byte config;
1944 +#define XMITBREAK 0x40
1945 +#define BITS5SYM 0x00
1946 +#define BITS6SYM 0x10
1947 +#define BITS7SYM 0x20
1948 +#define BITS8SYM 0x30
1949 +#define ONESTOP 0x07
1950 +#define TWOSTOP 0x0f
1951 + /* 4-LSBS represent STOP bits/char
1952 + * in 1/8 bit-time intervals. Zero
1953 + * represents 1/8 stop bit interval.
1954 + * Fifteen represents 2 stop bits.
1955 + */
1956 + byte fifoctl;
1957 +#define RSTTXFIFOS 0x80
1958 +#define RSTRXFIFOS 0x40
1959 + /* 5-bit TimeoutCnt is in low bits of this register.
1960 + * This count represents the number of characters
1961 + * idle times before setting receive Irq when below threshold
1962 + */
1963 + uint32 baudword;
1964 + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
1965 + */
1966 +
1967 + byte txf_levl; /* Read-only fifo depth */
1968 + byte rxf_levl; /* Read-only fifo depth */
1969 + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
1970 + * RxThreshold. Irq can be asserted
1971 + * when rx fifo> thresh, txfifo<thresh
1972 + */
1973 + byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
1974 + * if these bits are also enabled to GPIO_o
1975 + */
1976 +#define DTREN 0x01
1977 +#define RTSEN 0x02
1978 +
1979 + byte unused1;
1980 + byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
1981 + * detect irq on rising AND falling
1982 + * edges for corresponding GPIO_i
1983 + * if enabled (edge insensitive)
1984 + */
1985 + byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
1986 + * 0 for negedge sense if
1987 + * not configured for edge
1988 + * insensitive (see above)
1989 + * Lower 4 bits: Mask to enable change
1990 + * detection IRQ for corresponding
1991 + * GPIO_i
1992 + */
1993 + byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
1994 + * have changed (may set IRQ).
1995 + * read automatically clears bit
1996 + * Lower 4 bits are actual status
1997 + */
1998 +
1999 + uint16 intMask; /* Same Bit defs for Mask and status */
2000 + uint16 intStatus;
2001 +#define DELTAIP 0x0001
2002 +#define TXUNDERR 0x0002
2003 +#define TXOVFERR 0x0004
2004 +#define TXFIFOTHOLD 0x0008
2005 +#define TXREADLATCH 0x0010
2006 +#define TXFIFOEMT 0x0020
2007 +#define RXUNDERR 0x0040
2008 +#define RXOVFERR 0x0080
2009 +#define RXTIMEOUT 0x0100
2010 +#define RXFIFOFULL 0x0200
2011 +#define RXFIFOTHOLD 0x0400
2012 +#define RXFIFONE 0x0800
2013 +#define RXFRAMERR 0x1000
2014 +#define RXPARERR 0x2000
2015 +#define RXBRK 0x4000
2016 +
2017 + uint16 unused2;
2018 + uint16 Data; /* Write to TX, Read from RX */
2019 + /* bits 11:8 are BRK,PAR,FRM errors */
2020 +
2021 + uint32 unused3;
2022 + uint32 unused4;
2023 +} Uart;
2024 +
2025 +#define UART ((volatile Uart * const) UART_BASE)
2026 +
2027 +typedef struct GpioControl {
2028 + uint32 GPIODir_high; /* bits 36:32 */
2029 + uint32 GPIODir; /* bits 31:00 */
2030 + uint32 GPIOio_high; /* bits 36:32 */
2031 + uint32 GPIOio; /* bits 31:00 */
2032 + uint32 LEDCtrl;
2033 +#define LED3_STROBE 0x08000000
2034 +#define LED2_STROBE 0x04000000
2035 +#define LED1_STROBE 0x02000000
2036 +#define LED0_STROBE 0x01000000
2037 +#define LED_TEST 0x00010000
2038 +#define LED3_DISABLE_LINK_ACT 0x00008000
2039 +#define LED2_DISABLE_LINK_ACT 0x00004000
2040 +#define LED1_DISABLE_LINK_ACT 0x00002000
2041 +#define LED0_DISABLE_LINK_ACT 0x00001000
2042 +#define LED_INTERVAL_SET_MASK 0x00000f00
2043 +#define LED_INTERVAL_SET_320MS 0x00000500
2044 +#define LED_INTERVAL_SET_160MS 0x00000400
2045 +#define LED_INTERVAL_SET_80MS 0x00000300
2046 +#define LED_INTERVAL_SET_40MS 0x00000200
2047 +#define LED_INTERVAL_SET_20MS 0x00000100
2048 +#define LED3_ON 0x00000080
2049 +#define LED2_ON 0x00000040
2050 +#define LED1_ON 0x00000020
2051 +#define LED0_ON 0x00000010
2052 +#define LED3_ENABLE 0x00000008
2053 +#define LED2_ENABLE 0x00000004
2054 +#define LED1_ENABLE 0x00000002
2055 +#define LED0_ENABLE 0x00000001
2056 + uint32 SpiSlaveCfg;
2057 +#define SPI_SLAVE_RESET 0x00010000
2058 +#define SPI_RESTRICT 0x00000400
2059 +#define SPI_DELAY_DISABLE 0x00000200
2060 +#define SPI_PROBE_MUX_SEL_MASK 0x000001e0
2061 +#define SPI_SER_ADDR_CFG_MASK 0x0000000c
2062 +#define SPI_MODE 0x00000001
2063 + uint32 GPIOMode;
2064 +#define GROUP4_DIAG 0x00090000
2065 +#define GROUP4_UTOPIA 0x00080000
2066 +#define GROUP4_LEGACY_LED 0x00030000
2067 +#define GROUP4_MII_SNOOP 0x00020000
2068 +#define GROUP4_EXT_EPHY 0x00010000
2069 +#define GROUP3_DIAG 0x00009000
2070 +#define GROUP3_UTOPIA 0x00008000
2071 +#define GROUP3_EXT_MII 0x00007000
2072 +#define GROUP2_DIAG 0x00000900
2073 +#define GROUP2_PCI 0x00000500
2074 +#define GROUP1_DIAG 0x00000090
2075 +#define GROUP1_UTOPIA 0x00000080
2076 +#define GROUP1_SPI_UART 0x00000060
2077 +#define GROUP1_SPI_MASTER 0x00000060
2078 +#define GROUP1_MII_PCCARD 0x00000040
2079 +#define GROUP1_MII_SNOOP 0x00000020
2080 +#define GROUP1_EXT_EPHY 0x00000010
2081 +#define GROUP0_DIAG 0x00000009
2082 +#define GROUP0_EXT_MII 0x00000007
2083 +
2084 +} GpioControl;
2085 +
2086 +#define GPIO ((volatile GpioControl * const) GPIO_BASE)
2087 +
2088 +/* Number to mask conversion macro used for GPIODir and GPIOio */
2089 +#define GPIO_NUM_TOTAL_BITS_MASK 0x3f
2090 +#define GPIO_NUM_MAX_BITS_MASK 0x1f
2091 +#define GPIO_NUM_TO_MASK(X) ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) < 32) ? (1 << ((X) & GPIO_NUM_MAX_BITS_MASK)) : (0) )
2092 +
2093 +/* Number to mask conversion macro used for GPIODir_high and GPIOio_high */
2094 +#define GPIO_NUM_MAX_BITS_MASK_HIGH 0x07
2095 +#define GPIO_NUM_TO_MASK_HIGH(X) ( (((X) & GPIO_NUM_TOTAL_BITS_MASK) >= 32) ? (1 << ((X-32) & GPIO_NUM_MAX_BITS_MASK_HIGH)) : (0) )
2096 +
2097 +
2098 +/*
2099 +** External Bus Interface
2100 +*/
2101 +typedef struct EbiChipSelect {
2102 + uint32 base; /* base address in upper 24 bits */
2103 +#define EBI_SIZE_8K 0
2104 +#define EBI_SIZE_16K 1
2105 +#define EBI_SIZE_32K 2
2106 +#define EBI_SIZE_64K 3
2107 +#define EBI_SIZE_128K 4
2108 +#define EBI_SIZE_256K 5
2109 +#define EBI_SIZE_512K 6
2110 +#define EBI_SIZE_1M 7
2111 +#define EBI_SIZE_2M 8
2112 +#define EBI_SIZE_4M 9
2113 +#define EBI_SIZE_8M 10
2114 +#define EBI_SIZE_16M 11
2115 +#define EBI_SIZE_32M 12
2116 +#define EBI_SIZE_64M 13
2117 +#define EBI_SIZE_128M 14
2118 +#define EBI_SIZE_256M 15
2119 + uint32 config;
2120 +#define EBI_ENABLE 0x00000001 /* .. enable this range */
2121 +#define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
2122 +#define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
2123 +#define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
2124 +#define EBI_WREN 0x00000020 /* enable posted writes */
2125 +#define EBI_POLARITY 0x00000040 /* .. set to invert something,
2126 + ** don't know what yet */
2127 +#define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
2128 +#define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
2129 +#define EBI_FIFO 0x00000200 /* .. use fifo */
2130 +#define EBI_RE 0x00000400 /* .. Reverse Endian */
2131 +} EbiChipSelect;
2132 +
2133 +typedef struct MpiRegisters {
2134 + EbiChipSelect cs[7]; /* size chip select configuration */
2135 +#define EBI_CS0_BASE 0
2136 +#define EBI_CS1_BASE 1
2137 +#define EBI_CS2_BASE 2
2138 +#define EBI_CS3_BASE 3
2139 +#define PCMCIA_COMMON_BASE 4
2140 +#define PCMCIA_ATTRIBUTE_BASE 5
2141 +#define PCMCIA_IO_BASE 6
2142 + uint32 unused0[2]; /* reserved */
2143 + uint32 ebi_control; /* ebi control */
2144 + uint32 unused1[4]; /* reserved */
2145 +#define EBI_ACCESS_TIMEOUT 0x000007FF
2146 + uint32 pcmcia_cntl1; /* pcmcia control 1 */
2147 +#define PCCARD_CARD_RESET 0x00040000
2148 +#define CARDBUS_ENABLE 0x00008000
2149 +#define PCMCIA_ENABLE 0x00004000
2150 +#define PCMCIA_GPIO_ENABLE 0x00002000
2151 +#define CARDBUS_IDSEL 0x00001F00
2152 +#define VS2_OEN 0x00000080
2153 +#define VS1_OEN 0x00000040
2154 +#define VS2_OUT 0x00000020
2155 +#define VS1_OUT 0x00000010
2156 +#define VS2_IN 0x00000008
2157 +#define VS1_IN 0x00000004
2158 +#define CD2_IN 0x00000002
2159 +#define CD1_IN 0x00000001
2160 +#define VS_MASK 0x0000000C
2161 +#define CD_MASK 0x00000003
2162 + uint32 unused2; /* reserved */
2163 + uint32 pcmcia_cntl2; /* pcmcia control 2 */
2164 +#define PCMCIA_BYTESWAP_DIS 0x00000002
2165 +#define PCMCIA_HALFWORD_EN 0x00000001
2166 +#define RW_ACTIVE_CNT_BIT 2
2167 +#define INACTIVE_CNT_BIT 8
2168 +#define CE_SETUP_CNT_BIT 16
2169 +#define CE_HOLD_CNT_BIT 24
2170 + uint32 unused3[40]; /* reserved */
2171 +
2172 + uint32 sp0range; /* PCI to internal system bus address space */
2173 + uint32 sp0remap;
2174 + uint32 sp0cfg;
2175 + uint32 sp1range;
2176 + uint32 sp1remap;
2177 + uint32 sp1cfg;
2178 +
2179 + uint32 EndianCfg;
2180 +
2181 + uint32 l2pcfgctl; /* internal system bus to PCI IO/Cfg control */
2182 +#define DIR_CFG_SEL 0x80000000 /* change from PCI I/O access to PCI config access */
2183 +#define DIR_CFG_USEREG 0x40000000 /* use this register info for PCI configuration access */
2184 +#define DEVICE_NUMBER 0x00007C00 /* device number for the PCI configuration access */
2185 +#define FUNC_NUMBER 0x00000300 /* function number for the PCI configuration access */
2186 +#define REG_NUMBER 0x000000FC /* register number for the PCI configuration access */
2187 +#define CONFIG_TYPE 0x00000003 /* configuration type for the PCI configuration access */
2188 +
2189 + uint32 l2pmrange1; /* internal system bus to PCI memory space */
2190 +#define PCI_SIZE_64K 0xFFFF0000
2191 +#define PCI_SIZE_128K 0xFFFE0000
2192 +#define PCI_SIZE_256K 0xFFFC0000
2193 +#define PCI_SIZE_512K 0xFFF80000
2194 +#define PCI_SIZE_1M 0xFFF00000
2195 +#define PCI_SIZE_2M 0xFFE00000
2196 +#define PCI_SIZE_4M 0xFFC00000
2197 +#define PCI_SIZE_8M 0xFF800000
2198 +#define PCI_SIZE_16M 0xFF000000
2199 +#define PCI_SIZE_32M 0xFE000000
2200 + uint32 l2pmbase1; /* kseg0 or kseg1 address & 0x1FFFFFFF */
2201 + uint32 l2pmremap1;
2202 +#define CARDBUS_MEM 0x00000004
2203 +#define MEM_WINDOW_EN 0x00000001
2204 + uint32 l2pmrange2;
2205 + uint32 l2pmbase2;
2206 + uint32 l2pmremap2;
2207 + uint32 l2piorange; /* internal system bus to PCI I/O space */
2208 + uint32 l2piobase;
2209 + uint32 l2pioremap;
2210 +
2211 + uint32 pcimodesel;
2212 +#define PCI2_INT_BUS_RD_PREFECH 0x000000F0
2213 +#define PCI_BAR2_NOSWAP 0x00000002 /* BAR at offset 0x20 */
2214 +#define PCI_BAR1_NOSWAP 0x00000001 /* BAR at affset 0x1c */
2215 +
2216 + uint32 pciintstat; /* PCI interrupt mask/status */
2217 +#define MAILBOX1_SENT 0x08
2218 +#define MAILBOX0_SENT 0x04
2219 +#define MAILBOX1_MSG_RCV 0x02
2220 +#define MAILBOX0_MSG_RCV 0x01
2221 + uint32 locbuscntrl; /* internal system bus control */
2222 +#define DIR_U2P_NOSWAP 0x00000002
2223 +#define EN_PCI_GPIO 0x00000001
2224 + uint32 locintstat; /* internal system bus interrupt mask/status */
2225 +#define CSERR 0x0200
2226 +#define SERR 0x0100
2227 +#define EXT_PCI_INT 0x0080
2228 +#define DIR_FAILED 0x0040
2229 +#define DIR_COMPLETE 0x0020
2230 +#define PCI_CFG 0x0010
2231 + uint32 unused5[7];
2232 +
2233 + uint32 mailbox0;
2234 + uint32 mailbox1;
2235 +
2236 + uint32 pcicfgcntrl; /* internal system bus PCI configuration control */
2237 +#define PCI_CFG_REG_WRITE_EN 0x00000080
2238 +#define PCI_CFG_ADDR 0x0000003C
2239 + uint32 pcicfgdata; /* internal system bus PCI configuration data */
2240 +
2241 + uint32 locch2ctl; /* PCI to interrnal system bus DMA (downstream) local control */
2242 +#define MPI_DMA_HALT 0x00000008 /* idle after finish current memory burst */
2243 +#define MPI_DMA_PKT_HALT 0x00000004 /* idle after an EOP flag is detected */
2244 +#define MPI_DMA_STALL 0x00000002 /* idle after an EOP flag is detected */
2245 +#define MPI_DMA_ENABLE 0x00000001 /* set to enable channel */
2246 + uint32 locch2intStat;
2247 +#define MPI_DMA_NO_DESC 0x00000004 /* no valid descriptors */
2248 +#define MPI_DMA_DONE 0x00000002 /* packet xfer complete */
2249 +#define MPI_DMA_BUFF_DONE 0x00000001 /* buffer done */
2250 + uint32 locch2intMask;
2251 + uint32 unused6;
2252 + uint32 locch2descaddr;
2253 + uint32 locch2status1;
2254 +#define LOCAL_DESC_STATE 0xE0000000
2255 +#define PCI_DESC_STATE 0x1C000000
2256 +#define BYTE_DONE 0x03FFC000
2257 +#define RING_ADDR 0x00003FFF
2258 + uint32 locch2status2;
2259 +#define BUFPTR_OFFSET 0x1FFF0000
2260 +#define PCI_MASTER_STATE 0x000000C0
2261 +#define LOC_MASTER_STATE 0x00000038
2262 +#define CONTROL_STATE 0x00000007
2263 + uint32 unused7;
2264 +
2265 + uint32 locch1Ctl; /*internal system bus to PCI DMA (upstream) local control */
2266 +#define DMA_U2P_LE 0x00000200 /* local bus is little endian */
2267 +#define DMA_U2P_NOSWAP 0x00000100 /* lccal bus is little endian but no data swapped */
2268 + uint32 locch1intstat;
2269 + uint32 locch1intmask;
2270 + uint32 unused8;
2271 + uint32 locch1descaddr;
2272 + uint32 locch1status1;
2273 + uint32 locch1status2;
2274 + uint32 unused9;
2275 +
2276 + uint32 pcich1ctl; /* internal system bus to PCI DMA PCI control */
2277 + uint32 pcich1intstat;
2278 + uint32 pcich1intmask;
2279 + uint32 pcich1descaddr;
2280 + uint32 pcich1status1;
2281 + uint32 pcich1status2;
2282 +
2283 + uint32 pcich2Ctl; /* PCI to internal system bus DMA PCI control */
2284 + uint32 pcich2intstat;
2285 + uint32 pcich2intmask;
2286 + uint32 pcich2descaddr;
2287 + uint32 pcich2status1;
2288 + uint32 pcich2status2;
2289 +
2290 + uint32 perm_id; /* permanent device and vendor id */
2291 + uint32 perm_rev; /* permanent revision id */
2292 +} MpiRegisters;
2293 +
2294 +#define MPI ((volatile MpiRegisters * const) MPI_BASE)
2295 +
2296 +/* PCI configuration address space start offset 0x40 */
2297 +#define BRCM_PCI_CONFIG_TIMER 0x40
2298 +#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK 0x0000FF00
2299 +#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK 0x000000FF
2300 +
2301 +/* USB host non-Open HCI register, USB_HOST_NON_OHCI, bit definitions. */
2302 +#define NON_OHCI_ENABLE_PORT1 0x00000001 /* Use USB port 1 for host, not dev */
2303 +#define NON_OHCI_BYTE_SWAP 0x00000008 /* Swap USB host registers */
2304 +
2305 +#define USBH_NON_OHCI ((volatile unsigned long * const) USB_HOST_NON_OHCI)
2306 +
2307 +#endif
2308 +
2309 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcm_intr.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcm_intr.h
2310 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcm_intr.h 1970-01-01 01:00:00.000000000 +0100
2311 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcm_intr.h 2006-08-03 16:42:38.000000000 +0200
2312 @@ -0,0 +1,59 @@
2313 +/*
2314 +<:copyright-gpl
2315 + Copyright 2003 Broadcom Corp. All Rights Reserved.
2316 +
2317 + This program is free software; you can distribute it and/or modify it
2318 + under the terms of the GNU General Public License (Version 2) as
2319 + published by the Free Software Foundation.
2320 +
2321 + This program is distributed in the hope it will be useful, but WITHOUT
2322 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2323 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2324 + for more details.
2325 +
2326 + You should have received a copy of the GNU General Public License along
2327 + with this program; if not, write to the Free Software Foundation, Inc.,
2328 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2329 +:>
2330 +*/
2331 +
2332 +#ifndef __BCM_INTR_H
2333 +#define __BCM_INTR_H
2334 +
2335 +#ifdef __cplusplus
2336 + extern "C" {
2337 +#endif
2338 +
2339 +#if defined(CONFIG_BCM96338)
2340 +#include <6338_intr.h>
2341 +#endif
2342 +#if defined(CONFIG_BCM96345)
2343 +#include <6345_intr.h>
2344 +#endif
2345 +#if defined(CONFIG_BCM96348)
2346 +#include <6348_intr.h>
2347 +#endif
2348 +
2349 +/* defines */
2350 +struct pt_regs;
2351 +typedef int (*FN_HANDLER) (int, void *, struct pt_regs *);
2352 +
2353 +/* prototypes */
2354 +extern void enable_brcm_irq(unsigned int irq);
2355 +extern void disable_brcm_irq(unsigned int irq);
2356 +extern int request_external_irq(unsigned int irq,
2357 + FN_HANDLER handler, unsigned long irqflags,
2358 + const char * devname, void *dev_id);
2359 +extern unsigned int BcmHalMapInterrupt(FN_HANDLER isr, unsigned int param,
2360 + unsigned int interruptId);
2361 +extern void dump_intr_regs(void);
2362 +
2363 +/* compatibility definitions */
2364 +#define BcmHalInterruptEnable(irq) enable_brcm_irq( irq )
2365 +#define BcmHalInterruptDisable(irq) disable_brcm_irq( irq )
2366 +
2367 +#ifdef __cplusplus
2368 + }
2369 +#endif
2370 +
2371 +#endif
2372 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcm_map_part.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcm_map_part.h
2373 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcm_map_part.h 1970-01-01 01:00:00.000000000 +0100
2374 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcm_map_part.h 2006-08-03 16:42:38.000000000 +0200
2375 @@ -0,0 +1,34 @@
2376 +/*
2377 +<:copyright-gpl
2378 + Copyright 2004 Broadcom Corp. All Rights Reserved.
2379 +
2380 + This program is free software; you can distribute it and/or modify it
2381 + under the terms of the GNU General Public License (Version 2) as
2382 + published by the Free Software Foundation.
2383 +
2384 + This program is distributed in the hope it will be useful, but WITHOUT
2385 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2386 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2387 + for more details.
2388 +
2389 + You should have received a copy of the GNU General Public License along
2390 + with this program; if not, write to the Free Software Foundation, Inc.,
2391 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2392 +:>
2393 +*/
2394 +
2395 +#ifndef __BCM_MAP_PART_H
2396 +#define __BCM_MAP_PART_H
2397 +
2398 +#if defined(CONFIG_BCM96338)
2399 +#include <6338_map_part.h>
2400 +#endif
2401 +#if defined(CONFIG_BCM96345)
2402 +#include <6345_map_part.h>
2403 +#endif
2404 +#if defined(CONFIG_BCM96348)
2405 +#include <6348_map_part.h>
2406 +#endif
2407 +
2408 +#endif
2409 +
2410 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcmpci.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcmpci.h
2411 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcmpci.h 1970-01-01 01:00:00.000000000 +0100
2412 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcmpci.h 2006-08-03 16:42:38.000000000 +0200
2413 @@ -0,0 +1,87 @@
2414 +/*
2415 +<:copyright-gpl
2416 + Copyright 2004 Broadcom Corp. All Rights Reserved.
2417 +
2418 + This program is free software; you can distribute it and/or modify it
2419 + under the terms of the GNU General Public License (Version 2) as
2420 + published by the Free Software Foundation.
2421 +
2422 + This program is distributed in the hope it will be useful, but WITHOUT
2423 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2424 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2425 + for more details.
2426 +
2427 + You should have received a copy of the GNU General Public License along
2428 + with this program; if not, write to the Free Software Foundation, Inc.,
2429 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2430 +:>
2431 +*/
2432 +
2433 +//
2434 +// bcmpci.h - bcm96348 PCI, Cardbus, and PCMCIA definition
2435 +//
2436 +#ifndef BCMPCI_H
2437 +#define BCMPCI_H
2438 +
2439 +/* Memory window in internal system bus address space */
2440 +#define BCM_PCI_MEM_BASE 0x08000000
2441 +/* IO window in internal system bus address space */
2442 +#define BCM_PCI_IO_BASE 0x0C000000
2443 +
2444 +#define BCM_PCI_ADDR_MASK 0x1fffffff
2445 +
2446 +/* Memory window size (range) */
2447 +#define BCM_PCI_MEM_SIZE_16MB 0x01000000
2448 +/* IO window size (range) */
2449 +#define BCM_PCI_IO_SIZE_64KB 0x00010000
2450 +
2451 +/* PCI Configuration and I/O space acesss */
2452 +#define BCM_PCI_CFG(d, f, o) ( (d << 11) | (f << 8) | (o/4 << 2) )
2453 +
2454 +/* fake USB PCI slot */
2455 +#define USB_HOST_SLOT 9
2456 +#define USB_BAR0_MEM_SIZE 0x0800
2457 +
2458 +#define BCM_HOST_MEM_SPACE1 0x10000000
2459 +#define BCM_HOST_MEM_SPACE2 0x00000000
2460 +
2461 +/*
2462 + * EBI bus clock is 33MHz and share with PCI bus
2463 + * each clock cycle is 30ns.
2464 + */
2465 +/* attribute memory access wait cnt for 4306 */
2466 +#define PCMCIA_ATTR_CE_HOLD 3 // data hold time 70ns
2467 +#define PCMCIA_ATTR_CE_SETUP 3 // data setup time 50ns
2468 +#define PCMCIA_ATTR_INACTIVE 6 // time between read/write cycles 180ns. For the total cycle time 600ns (cnt1+cnt2+cnt3+cnt4)
2469 +#define PCMCIA_ATTR_ACTIVE 10 // OE/WE pulse width 300ns
2470 +
2471 +/* common memory access wait cnt for 4306 */
2472 +#define PCMCIA_MEM_CE_HOLD 1 // data hold time 30ns
2473 +#define PCMCIA_MEM_CE_SETUP 1 // data setup time 30ns
2474 +#define PCMCIA_MEM_INACTIVE 2 // time between read/write cycles 40ns. For the total cycle time 250ns (cnt1+cnt2+cnt3+cnt4)
2475 +#define PCMCIA_MEM_ACTIVE 5 // OE/WE pulse width 150ns
2476 +
2477 +#define PCCARD_VCC_MASK 0x00070000 // Mask Reset also
2478 +#define PCCARD_VCC_33V 0x00010000
2479 +#define PCCARD_VCC_50V 0x00020000
2480 +
2481 +typedef enum {
2482 + MPI_CARDTYPE_NONE, // No Card in slot
2483 + MPI_CARDTYPE_PCMCIA, // 16-bit PCMCIA card in slot
2484 + MPI_CARDTYPE_CARDBUS, // 32-bit CardBus card in slot
2485 +} CardType;
2486 +
2487 +#define CARDBUS_SLOT 0 // Slot 0 is default for CardBus
2488 +
2489 +#define pcmciaAttrOffset 0x00200000
2490 +#define pcmciaMemOffset 0x00000000
2491 +// Needs to be right above PCI I/O space. Give 0x8000 (32K) to PCMCIA.
2492 +#define pcmciaIoOffset (BCM_PCI_IO_BASE + 0x80000)
2493 +// Base Address is that mapped into the MPI ChipSelect registers.
2494 +// UBUS bridge MemoryWindow 0 outputs a 0x00 for the base.
2495 +#define pcmciaBase 0xbf000000
2496 +#define pcmciaAttr (pcmciaAttrOffset | pcmciaBase)
2497 +#define pcmciaMem (pcmciaMemOffset | pcmciaBase)
2498 +#define pcmciaIo (pcmciaIoOffset | pcmciaBase)
2499 +
2500 +#endif
2501 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcmTag.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcmTag.h
2502 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcmTag.h 1970-01-01 01:00:00.000000000 +0100
2503 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcmTag.h 2006-08-03 16:42:38.000000000 +0200
2504 @@ -0,0 +1,153 @@
2505 +/*
2506 +<:copyright-gpl
2507 + Copyright 2002 Broadcom Corp. All Rights Reserved.
2508 +
2509 + This program is free software; you can distribute it and/or modify it
2510 + under the terms of the GNU General Public License (Version 2) as
2511 + published by the Free Software Foundation.
2512 +
2513 + This program is distributed in the hope it will be useful, but WITHOUT
2514 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2515 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2516 + for more details.
2517 +
2518 + You should have received a copy of the GNU General Public License along
2519 + with this program; if not, write to the Free Software Foundation, Inc.,
2520 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2521 +:>
2522 +*/
2523 +//**************************************************************************************
2524 +// File Name : bcmTag.h
2525 +//
2526 +// Description: add tag with validation system to the firmware image file to be uploaded
2527 +// via http
2528 +//
2529 +// Created : 02/28/2002 seanl
2530 +//**************************************************************************************
2531 +
2532 +#ifndef _BCMTAG_H_
2533 +#define _BCMTAG_H_
2534 +
2535 +
2536 +#define BCM_SIG_1 "Broadcom Corporation"
2537 +#define BCM_SIG_2 "ver. 2.0" // was "firmware version 2.0" now it is split 6 char out for chip id.
2538 +
2539 +#define BCM_TAG_VER "6"
2540 +#define BCM_TAG_VER_LAST "26"
2541 +
2542 +// file tag (head) structure all is in clear text except validationTokens (crc, md5, sha1, etc). Total: 128 unsigned chars
2543 +#define TAG_LEN 256
2544 +#define TAG_VER_LEN 4
2545 +#define SIG_LEN 20
2546 +#define SIG_LEN_2 14 // Original second SIG = 20 is now devided into 14 for SIG_LEN_2 and 6 for CHIP_ID
2547 +#define CHIP_ID_LEN 6
2548 +#define IMAGE_LEN 10
2549 +#define ADDRESS_LEN 12
2550 +#define FLAG_LEN 2
2551 +#define TOKEN_LEN 20
2552 +#define BOARD_ID_LEN 16
2553 +#define RESERVED_LEN (TAG_LEN - TAG_VER_LEN - SIG_LEN - SIG_LEN_2 - CHIP_ID_LEN - BOARD_ID_LEN - \
2554 + (4*IMAGE_LEN) - (3*ADDRESS_LEN) - (3*FLAG_LEN) - (2*TOKEN_LEN))
2555 +
2556 +
2557 +// TAG for downloadable image (kernel plus file system)
2558 +typedef struct _FILE_TAG
2559 +{
2560 + unsigned char tagVersion[TAG_VER_LEN]; // tag version. Will be 2 here.
2561 + unsigned char signiture_1[SIG_LEN]; // text line for company info
2562 + unsigned char signiture_2[SIG_LEN_2]; // additional info (can be version number)
2563 + unsigned char chipId[CHIP_ID_LEN]; // chip id
2564 + unsigned char boardId[BOARD_ID_LEN]; // board id
2565 + unsigned char bigEndian[FLAG_LEN]; // if = 1 - big, = 0 - little endia of the host
2566 + unsigned char totalImageLen[IMAGE_LEN]; // the sum of all the following length
2567 + unsigned char cfeAddress[ADDRESS_LEN]; // if non zero, cfe starting address
2568 + unsigned char cfeLen[IMAGE_LEN]; // if non zero, cfe size in clear ASCII text.
2569 + unsigned char rootfsAddress[ADDRESS_LEN]; // if non zero, filesystem starting address
2570 + unsigned char rootfsLen[IMAGE_LEN]; // if non zero, filesystem size in clear ASCII text.
2571 + unsigned char kernelAddress[ADDRESS_LEN]; // if non zero, kernel starting address
2572 + unsigned char kernelLen[IMAGE_LEN]; // if non zero, kernel size in clear ASCII text.
2573 + unsigned char dualImage[FLAG_LEN]; // if 1, dual image
2574 + unsigned char inactiveLen[FLAG_LEN]; // if 1, the image is INACTIVE; if 0, active
2575 + unsigned char reserved[RESERVED_LEN]; // reserved for later use
2576 + unsigned char imageValidationToken[TOKEN_LEN];// image validation token - can be crc, md5, sha; for
2577 + // now will be 4 unsigned char crc
2578 + unsigned char tagValidationToken[TOKEN_LEN]; // validation token for tag(from signiture_1 to end of // mageValidationToken)
2579 +} FILE_TAG, *PFILE_TAG;
2580 +
2581 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
2582 +#define CRC_LEN 4
2583 +
2584 +// only included if for bcmTag.exe program
2585 +#ifdef BCMTAG_EXE_USE
2586 +
2587 +static unsigned long Crc32_table[256] = {
2588 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
2589 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
2590 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
2591 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
2592 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
2593 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
2594 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
2595 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
2596 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
2597 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
2598 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
2599 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
2600 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
2601 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
2602 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
2603 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
2604 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
2605 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
2606 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
2607 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
2608 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
2609 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
2610 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
2611 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
2612 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
2613 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
2614 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
2615 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
2616 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
2617 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
2618 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
2619 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
2620 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
2621 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
2622 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
2623 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
2624 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
2625 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
2626 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
2627 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
2628 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
2629 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
2630 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
2631 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
2632 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
2633 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
2634 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
2635 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
2636 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
2637 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
2638 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
2639 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
2640 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
2641 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
2642 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
2643 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
2644 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
2645 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
2646 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
2647 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
2648 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
2649 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
2650 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
2651 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
2652 +};
2653 +#endif // BCMTAG_USE
2654 +
2655 +
2656 +#endif // _BCMTAG_H_
2657 +
2658 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcmtypes.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcmtypes.h
2659 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/bcmtypes.h 1970-01-01 01:00:00.000000000 +0100
2660 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/bcmtypes.h 2006-08-03 16:42:38.000000000 +0200
2661 @@ -0,0 +1,163 @@
2662 +/*
2663 +<:copyright-gpl
2664 + Copyright 2002 Broadcom Corp. All Rights Reserved.
2665 +
2666 + This program is free software; you can distribute it and/or modify it
2667 + under the terms of the GNU General Public License (Version 2) as
2668 + published by the Free Software Foundation.
2669 +
2670 + This program is distributed in the hope it will be useful, but WITHOUT
2671 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2672 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2673 + for more details.
2674 +
2675 + You should have received a copy of the GNU General Public License along
2676 + with this program; if not, write to the Free Software Foundation, Inc.,
2677 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2678 +:>
2679 +*/
2680 +
2681 +//
2682 +// bcmtypes.h - misc useful typedefs
2683 +//
2684 +#ifndef BCMTYPES_H
2685 +#define BCMTYPES_H
2686 +
2687 +// These are also defined in typedefs.h in the application area, so I need to
2688 +// protect against re-definition.
2689 +
2690 +#ifndef _TYPEDEFS_H_
2691 +typedef unsigned char uint8;
2692 +typedef unsigned short uint16;
2693 +typedef unsigned long uint32;
2694 +typedef signed char int8;
2695 +typedef signed short int16;
2696 +typedef signed long int32;
2697 +#if !defined(__cplusplus)
2698 +typedef int bool;
2699 +#endif
2700 +#endif
2701 +
2702 +typedef unsigned char byte;
2703 +// typedef unsigned long sem_t;
2704 +
2705 +typedef unsigned long HANDLE,*PULONG,DWORD,*PDWORD;
2706 +typedef signed long LONG,*PLONG;
2707 +
2708 +typedef unsigned int *PUINT;
2709 +typedef signed int INT;
2710 +
2711 +typedef unsigned short *PUSHORT;
2712 +typedef signed short SHORT,*PSHORT;
2713 +typedef unsigned short WORD,*PWORD;
2714 +
2715 +typedef unsigned char *PUCHAR;
2716 +typedef signed char *PCHAR;
2717 +
2718 +typedef void *PVOID;
2719 +
2720 +typedef unsigned char BOOLEAN, *PBOOL, *PBOOLEAN;
2721 +
2722 +typedef unsigned char BYTE,*PBYTE;
2723 +
2724 +//#ifndef __GNUC__
2725 +//The following has been defined in Vxworks internally: vxTypesOld.h
2726 +//redefine under vxworks will cause error
2727 +typedef signed int *PINT;
2728 +
2729 +typedef signed char INT8;
2730 +typedef signed short INT16;
2731 +typedef signed long INT32;
2732 +
2733 +typedef unsigned char UINT8;
2734 +typedef unsigned short UINT16;
2735 +typedef unsigned long UINT32;
2736 +
2737 +typedef unsigned char UCHAR;
2738 +typedef unsigned short USHORT;
2739 +typedef unsigned int UINT;
2740 +typedef unsigned long ULONG;
2741 +
2742 +typedef void VOID;
2743 +typedef unsigned char BOOL;
2744 +
2745 +//#endif /* __GNUC__ */
2746 +
2747 +
2748 +// These are also defined in typedefs.h in the application area, so I need to
2749 +// protect against re-definition.
2750 +#ifndef TYPEDEFS_H
2751 +
2752 +// Maximum and minimum values for a signed 16 bit integer.
2753 +#define MAX_INT16 32767
2754 +#define MIN_INT16 -32768
2755 +
2756 +// Useful for true/false return values. This uses the
2757 +// Taligent notation (k for constant).
2758 +typedef enum
2759 +{
2760 + kFalse = 0,
2761 + kTrue = 1
2762 +} Bool;
2763 +
2764 +#endif
2765 +
2766 +/* macros to protect against unaligned accesses */
2767 +
2768 +#if 0
2769 +/* first arg is an address, second is a value */
2770 +#define PUT16( a, d ) { \
2771 + *((byte *)a) = (byte)((d)>>8); \
2772 + *(((byte *)a)+1) = (byte)(d); \
2773 +}
2774 +
2775 +#define PUT32( a, d ) { \
2776 + *((byte *)a) = (byte)((d)>>24); \
2777 + *(((byte *)a)+1) = (byte)((d)>>16); \
2778 + *(((byte *)a)+2) = (byte)((d)>>8); \
2779 + *(((byte *)a)+3) = (byte)(d); \
2780 +}
2781 +
2782 +/* first arg is an address, returns a value */
2783 +#define GET16( a ) ( \
2784 + (*((byte *)a) << 8) | \
2785 + (*(((byte *)a)+1)) \
2786 +)
2787 +
2788 +#define GET32( a ) ( \
2789 + (*((byte *)a) << 24) | \
2790 + (*(((byte *)a)+1) << 16) | \
2791 + (*(((byte *)a)+2) << 8) | \
2792 + (*(((byte *)a)+3)) \
2793 +)
2794 +#endif
2795 +
2796 +#ifndef YES
2797 +#define YES 1
2798 +#endif
2799 +
2800 +#ifndef NO
2801 +#define NO 0
2802 +#endif
2803 +
2804 +#ifndef IN
2805 +#define IN
2806 +#endif
2807 +
2808 +#ifndef OUT
2809 +#define OUT
2810 +#endif
2811 +
2812 +#ifndef TRUE
2813 +#define TRUE 1
2814 +#endif
2815 +
2816 +#ifndef FALSE
2817 +#define FALSE 0
2818 +#endif
2819 +
2820 +#define READ32(addr) (*(volatile UINT32 *)((ULONG)&addr))
2821 +#define READ16(addr) (*(volatile UINT16 *)((ULONG)&addr))
2822 +#define READ8(addr) (*(volatile UINT8 *)((ULONG)&addr))
2823 +
2824 +#endif
2825 diff -urN linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/board.h linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/board.h
2826 --- linux-2.6.17/bcmdrivers/opensource/include/bcm963xx/board.h 1970-01-01 01:00:00.000000000 +0100
2827 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/include/bcm963xx/board.h 2006-08-03 16:42:46.000000000 +0200
2828 @@ -0,0 +1,374 @@
2829 +/*
2830 +<:copyright-gpl
2831 + Copyright 2002 Broadcom Corp. All Rights Reserved.
2832 +
2833 + This program is free software; you can distribute it and/or modify it
2834 + under the terms of the GNU General Public License (Version 2) as
2835 + published by the Free Software Foundation.
2836 +
2837 + This program is distributed in the hope it will be useful, but WITHOUT
2838 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2839 + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2840 + for more details.
2841 +
2842 + You should have received a copy of the GNU General Public License along
2843 + with this program; if not, write to the Free Software Foundation, Inc.,
2844 + 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2845 +:>
2846 +*/
2847 +/***********************************************************************/
2848 +/* */
2849 +/* MODULE: board.h */
2850 +/* DATE: 97/02/18 */
2851 +/* PURPOSE: Board specific information. This module should include */
2852 +/* all base device addresses and board specific macros. */
2853 +/* */
2854 +/***********************************************************************/
2855 +#ifndef _BOARD_H
2856 +#define _BOARD_H
2857 +
2858 +/*****************************************************************************/
2859 +/* Misc board definitions */
2860 +/*****************************************************************************/
2861 +
2862 +#define DYING_GASP_API
2863 +
2864 +/*****************************************************************************/
2865 +/* Physical Memory Map */
2866 +/*****************************************************************************/
2867 +
2868 +#define PHYS_DRAM_BASE 0x00000000 /* Dynamic RAM Base */
2869 +#define PHYS_FLASH_BASE 0x1FC00000 /* Flash Memory */
2870 +
2871 +/*****************************************************************************/
2872 +/* Note that the addresses above are physical addresses and that programs */
2873 +/* have to use converted addresses defined below: */
2874 +/*****************************************************************************/
2875 +#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */
2876 +#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */
2877 +#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */
2878 +
2879 +/*****************************************************************************/
2880 +/* Select the PLL value to get the desired CPU clock frequency. */
2881 +/* */
2882 +/* */
2883 +/*****************************************************************************/
2884 +#define FPERIPH 50000000
2885 +
2886 +#define ONEK 1024
2887 +#define BLK64K (64*ONEK)
2888 +#define FLASH45_BLKS_BOOT_ROM 1
2889 +#define FLASH45_LENGTH_BOOT_ROM (FLASH45_BLKS_BOOT_ROM * BLK64K)
2890 +#define FLASH_RESERVED_AT_END (64*ONEK) /*reserved for PSI, scratch pad*/
2891 +
2892 +/*****************************************************************************/
2893 +/* Note that the addresses above are physical addresses and that programs */
2894 +/* have to use converted addresses defined below: */
2895 +/*****************************************************************************/
2896 +#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */
2897 +#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */
2898 +#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */
2899 +
2900 +/*****************************************************************************/
2901 +/* Select the PLL value to get the desired CPU clock frequency. */
2902 +/* */
2903 +/* */
2904 +/*****************************************************************************/
2905 +#define FPERIPH 50000000
2906 +
2907 +#define SDRAM_TYPE_ADDRESS_OFFSET 16
2908 +#define NVRAM_DATA_OFFSET 0x0580
2909 +#define NVRAM_DATA_ID 0x0f1e2d3c
2910 +#define BOARD_SDRAM_TYPE *(unsigned long *) \
2911 + (FLASH_BASE + SDRAM_TYPE_ADDRESS_OFFSET)
2912 +
2913 +#define ONEK 1024
2914 +#define BLK64K (64*ONEK)
2915 +
2916 +// nvram and psi flash definitions for 45
2917 +#define FLASH45_LENGTH_NVRAM ONEK // 1k nvram
2918 +#define NVRAM_PSI_DEFAULT 24 // default psi in K byes
2919 +
2920 +/*****************************************************************************/
2921 +/* NVRAM Offset and definition */
2922 +/*****************************************************************************/
2923 +
2924 +#define NVRAM_VERSION_NUMBER 2
2925 +#define NVRAM_VERSION_NUMBER_ADDRESS 0
2926 +
2927 +#define NVRAM_BOOTLINE_LEN 256
2928 +#define NVRAM_BOARD_ID_STRING_LEN 16
2929 +#define NVRAM_MAC_ADDRESS_LEN 6
2930 +#define NVRAM_MAC_COUNT_MAX 32
2931 +
2932 +/*****************************************************************************/
2933 +/* Misc Offsets */
2934 +/*****************************************************************************/
2935 +
2936 +#define CFE_VERSION_OFFSET 0x0570
2937 +#define CFE_VERSION_MARK_SIZE 5
2938 +#define CFE_VERSION_SIZE 5
2939 +
2940 +typedef struct
2941 +{
2942 + unsigned long ulVersion;
2943 + char szBootline[NVRAM_BOOTLINE_LEN];
2944 + char szBoardId[NVRAM_BOARD_ID_STRING_LEN];
2945 + unsigned long ulReserved1[2];
2946 + unsigned long ulNumMacAddrs;
2947 + unsigned char ucaBaseMacAddr[NVRAM_MAC_ADDRESS_LEN];
2948 + char chReserved[2];
2949 + unsigned long ulCheckSum;
2950 +} NVRAM_DATA, *PNVRAM_DATA;
2951 +
2952 +
2953 +/*****************************************************************************/
2954 +/* board ioctl calls for flash, led and some other utilities */
2955 +/*****************************************************************************/
2956 +
2957 +
2958 +/* Defines. for board driver */
2959 +#define BOARD_IOCTL_MAGIC 'B'
2960 +#define BOARD_DRV_MAJOR 206
2961 +
2962 +#define MAC_ADDRESS_ANY (unsigned long) -1
2963 +
2964 +#define BOARD_IOCTL_FLASH_INIT \
2965 + _IOWR(BOARD_IOCTL_MAGIC, 0, BOARD_IOCTL_PARMS)
2966 +
2967 +#define BOARD_IOCTL_FLASH_WRITE \
2968 + _IOWR(BOARD_IOCTL_MAGIC, 1, BOARD_IOCTL_PARMS)
2969 +
2970 +#define BOARD_IOCTL_FLASH_READ \
2971 + _IOWR(BOARD_IOCTL_MAGIC, 2, BOARD_IOCTL_PARMS)
2972 +
2973 +#define BOARD_IOCTL_GET_NR_PAGES \
2974 + _IOWR(BOARD_IOCTL_MAGIC, 3, BOARD_IOCTL_PARMS)
2975 +
2976 +#define BOARD_IOCTL_DUMP_ADDR \
2977 + _IOWR(BOARD_IOCTL_MAGIC, 4, BOARD_IOCTL_PARMS)
2978 +
2979 +#define BOARD_IOCTL_SET_MEMORY \
2980 + _IOWR(BOARD_IOCTL_MAGIC, 5, BOARD_IOCTL_PARMS)
2981 +
2982 +#define BOARD_IOCTL_MIPS_SOFT_RESET \
2983 + _IOWR(BOARD_IOCTL_MAGIC, 6, BOARD_IOCTL_PARMS)
2984 +
2985 +#define BOARD_IOCTL_LED_CTRL \
2986 + _IOWR(BOARD_IOCTL_MAGIC, 7, BOARD_IOCTL_PARMS)
2987 +
2988 +#define BOARD_IOCTL_GET_ID \
2989 + _IOWR(BOARD_IOCTL_MAGIC, 8, BOARD_IOCTL_PARMS)
2990 +
2991 +#define BOARD_IOCTL_GET_MAC_ADDRESS \
2992 + _IOWR(BOARD_IOCTL_MAGIC, 9, BOARD_IOCTL_PARMS)
2993 +
2994 +#define BOARD_IOCTL_RELEASE_MAC_ADDRESS \
2995 + _IOWR(BOARD_IOCTL_MAGIC, 10, BOARD_IOCTL_PARMS)
2996 +
2997 +#define BOARD_IOCTL_GET_PSI_SIZE \
2998 + _IOWR(BOARD_IOCTL_MAGIC, 11, BOARD_IOCTL_PARMS)
2999 +
3000 +#define BOARD_IOCTL_GET_SDRAM_SIZE \
3001 + _IOWR(BOARD_IOCTL_MAGIC, 12, BOARD_IOCTL_PARMS)
3002 +
3003 +#define BOARD_IOCTL_SET_MONITOR_FD \
3004 + _IOWR(BOARD_IOCTL_MAGIC, 13, BOARD_IOCTL_PARMS)
3005 +
3006 +#define BOARD_IOCTL_WAKEUP_MONITOR_TASK \
3007 + _IOWR(BOARD_IOCTL_MAGIC, 14, BOARD_IOCTL_PARMS)
3008 +
3009 +#define BOARD_IOCTL_GET_BOOTLINE \
3010 + _IOWR(BOARD_IOCTL_MAGIC, 15, BOARD_IOCTL_PARMS)
3011 +
3012 +#define BOARD_IOCTL_SET_BOOTLINE \
3013 + _IOWR(BOARD_IOCTL_MAGIC, 16, BOARD_IOCTL_PARMS)
3014 +
3015 +#define BOARD_IOCTL_GET_BASE_MAC_ADDRESS \
3016 + _IOWR(BOARD_IOCTL_MAGIC, 17, BOARD_IOCTL_PARMS)
3017 +
3018 +#define BOARD_IOCTL_GET_CHIP_ID \
3019 + _IOWR(BOARD_IOCTL_MAGIC, 18, BOARD_IOCTL_PARMS)
3020 +
3021 +#define BOARD_IOCTL_GET_NUM_ENET \
3022 + _IOWR(BOARD_IOCTL_MAGIC, 19, BOARD_IOCTL_PARMS)
3023 +
3024 +#define BOARD_IOCTL_GET_CFE_VER \
3025 + _IOWR(BOARD_IOCTL_MAGIC, 20, BOARD_IOCTL_PARMS)
3026 +
3027 +#define BOARD_IOCTL_GET_ENET_CFG \
3028 + _IOWR(BOARD_IOCTL_MAGIC, 21, BOARD_IOCTL_PARMS)
3029 +
3030 +#define BOARD_IOCTL_GET_WLAN_ANT_INUSE \
3031 + _IOWR(BOARD_IOCTL_MAGIC, 22, BOARD_IOCTL_PARMS)
3032 +
3033 +#define BOARD_IOCTL_SET_TRIGGER_EVENT \
3034 + _IOWR(BOARD_IOCTL_MAGIC, 23, BOARD_IOCTL_PARMS)
3035 +
3036 +#define BOARD_IOCTL_GET_TRIGGER_EVENT \
3037 + _IOWR(BOARD_IOCTL_MAGIC, 24, BOARD_IOCTL_PARMS)
3038 +
3039 +#define BOARD_IOCTL_UNSET_TRIGGER_EVENT \
3040 + _IOWR(BOARD_IOCTL_MAGIC, 25, BOARD_IOCTL_PARMS)
3041 +
3042 +#define BOARD_IOCTL_SET_SES_LED \
3043 + _IOWR(BOARD_IOCTL_MAGIC, 26, BOARD_IOCTL_PARMS)
3044 +
3045 +//<<JUNHON, 2004/09/15, get reset button status , tim hou , 05/04/12
3046 +#define RESET_BUTTON_UP 1
3047 +#define RESET_BUTTON_PRESSDOWN 0
3048 +#define BOARD_IOCTL_GET_RESETHOLD \
3049 + _IOWR(BOARD_IOCTL_MAGIC, 27, BOARD_IOCTL_PARMS)
3050 +//>>JUNHON, 2004/09/15
3051 +
3052 +// for the action in BOARD_IOCTL_PARMS for flash operation
3053 +typedef enum
3054 +{
3055 + PERSISTENT,
3056 + NVRAM,
3057 + BCM_IMAGE_CFE,
3058 + BCM_IMAGE_FS,
3059 + BCM_IMAGE_KERNEL,
3060 + BCM_IMAGE_WHOLE,
3061 + SCRATCH_PAD,
3062 + FLASH_SIZE,
3063 +} BOARD_IOCTL_ACTION;
3064 +
3065 +
3066 +typedef struct boardIoctParms
3067 +{
3068 + char *string;
3069 + char *buf;
3070 + int strLen;
3071 + int offset;
3072 + BOARD_IOCTL_ACTION action; /* flash read/write: nvram, persistent, bcm image */
3073 + int result;
3074 +} BOARD_IOCTL_PARMS;
3075 +
3076 +
3077 +// LED defines
3078 +typedef enum
3079 +{
3080 + kLedAdsl,
3081 + kLedWireless,
3082 + kLedUsb,
3083 + kLedHpna,
3084 + kLedWanData,
3085 + kLedPPP,
3086 + kLedVoip,
3087 + kLedSes,
3088 + kLedLan,
3089 + kLedSelfTest,
3090 + kLedEnd, // NOTE: Insert the new led name before this one. Alway stay at the end.
3091 +} BOARD_LED_NAME;
3092 +
3093 +typedef enum
3094 +{
3095 + kLedStateOff, /* turn led off */
3096 + kLedStateOn, /* turn led on */
3097 + kLedStateFail, /* turn led on red */
3098 + kLedStateBlinkOnce, /* blink once, ~100ms and ignore the same call during the 100ms period */
3099 + kLedStateSlowBlinkContinues, /* slow blink continues at ~600ms interval */
3100 + kLedStateFastBlinkContinues, /* fast blink continues at ~200ms interval */
3101 +} BOARD_LED_STATE;
3102 +
3103 +
3104 +// virtual and physical map pair defined in board.c
3105 +typedef struct ledmappair
3106 +{
3107 + BOARD_LED_NAME ledName; // virtual led name
3108 + BOARD_LED_STATE ledInitState; // initial led state when the board boots.
3109 + unsigned short ledMask; // physical GPIO pin mask
3110 + unsigned short ledActiveLow; // reset bit to turn on LED
3111 + unsigned short ledMaskFail; // physical GPIO pin mask for state failure
3112 + unsigned short ledActiveLowFail;// reset bit to turn on LED
3113 +} LED_MAP_PAIR, *PLED_MAP_PAIR;
3114 +
3115 +typedef void (*HANDLE_LED_FUNC)(BOARD_LED_NAME ledName, BOARD_LED_STATE ledState);
3116 +
3117 +/* Flash storage address information that is determined by the flash driver. */
3118 +typedef struct flashaddrinfo
3119 +{
3120 + int flash_persistent_start_blk;
3121 + int flash_persistent_number_blk;
3122 + int flash_persistent_length;
3123 + unsigned long flash_persistent_blk_offset;
3124 + int flash_scratch_pad_start_blk; // start before psi (SP_BUF_LEN)
3125 + int flash_scratch_pad_number_blk;
3126 + int flash_scratch_pad_length;
3127 + unsigned long flash_scratch_pad_blk_offset;
3128 + int flash_nvram_start_blk;
3129 + int flash_nvram_number_blk;
3130 + int flash_nvram_length;
3131 + unsigned long flash_nvram_blk_offset;
3132 +} FLASH_ADDR_INFO, *PFLASH_ADDR_INFO;
3133 +
3134 +// scratch pad defines
3135 +/* SP - Persisten Scratch Pad format:
3136 + sp header : 32 bytes
3137 + tokenId-1 : 8 bytes
3138 + tokenId-1 len : 4 bytes
3139 + tokenId-1 data
3140 + ....
3141 + tokenId-n : 8 bytes
3142 + tokenId-n len : 4 bytes
3143 + tokenId-n data
3144 +*/
3145 +
3146 +#define MAGIC_NUM_LEN 8
3147 +#define MAGIC_NUMBER "gOGoBrCm"
3148 +#define TOKEN_NAME_LEN 16
3149 +#define SP_VERSION 1
3150 +#define SP_MAX_LEN 8 * 1024 // 8k buf before psi
3151 +#define SP_RESERVERD 16
3152 +
3153 +typedef struct _SP_HEADER
3154 +{
3155 + char SPMagicNum[MAGIC_NUM_LEN]; // 8 bytes of magic number
3156 + int SPVersion; // version number
3157 + int SPUsedLen; // used sp len
3158 + char SPReserved[SP_RESERVERD]; // reservied, total 32 bytes
3159 +} SP_HEADER, *PSP_HEADER;
3160 +
3161 +typedef struct _TOKEN_DEF
3162 +{
3163 + char tokenName[TOKEN_NAME_LEN];
3164 + int tokenLen;
3165 +} SP_TOKEN, *PSP_TOKEN;
3166 +
3167 +
3168 +/*****************************************************************************/
3169 +/* Function Prototypes */
3170 +/*****************************************************************************/
3171 +#if !defined(__ASM_ASM_H)
3172 +void dumpaddr( unsigned char *pAddr, int nLen );
3173 +
3174 +void kerSysFlashAddrInfoGet(PFLASH_ADDR_INFO pflash_addr_info);
3175 +int kerSysNvRamGet(char *string, int strLen, int offset);
3176 +int kerSysNvRamSet(char *string, int strLen, int offset);
3177 +int kerSysPersistentGet(char *string, int strLen, int offset);
3178 +int kerSysPersistentSet(char *string, int strLen, int offset);
3179 +int kerSysScratchPadGet(char *tokName, char *tokBuf, int tokLen);
3180 +int kerSysScratchPadSet(char *tokName, char *tokBuf, int tokLen);
3181 +int kerSysBcmImageSet( int flash_start_addr, char *string, int size);
3182 +int kerSysGetMacAddress( unsigned char *pucaAddr, unsigned long ulId );
3183 +int kerSysReleaseMacAddress( unsigned char *pucaAddr );
3184 +int kerSysGetSdramSize( void );
3185 +void kerSysGetBootline(char *string, int strLen);
3186 +void kerSysSetBootline(char *string, int strLen);
3187 +void kerSysMipsSoftReset(void);
3188 +void kerSysLedCtrl(BOARD_LED_NAME, BOARD_LED_STATE);
3189 +void kerSysLedRegisterHwHandler( BOARD_LED_NAME, HANDLE_LED_FUNC, int );
3190 +int kerSysFlashSizeGet(void);
3191 +void kerSysRegisterDyingGaspHandler(char *devname, void *cbfn, void *context);
3192 +void kerSysDeregisterDyingGaspHandler(char *devname);
3193 +void kerSysWakeupMonitorTask( void );
3194 +#endif
3195 +
3196 +#define BOOT_CFE 0
3197 +#define BOOT_REDBOOT 1
3198 +
3199 +extern int boot_loader_type;
3200 +
3201 +#endif /* _BOARD_H */
3202 +
3203 diff -urN linux-2.6.17/bcmdrivers/opensource/Makefile linux-2.6.17-brcm63xx/bcmdrivers/opensource/Makefile
3204 --- linux-2.6.17/bcmdrivers/opensource/Makefile 1970-01-01 01:00:00.000000000 +0100
3205 +++ linux-2.6.17-brcm63xx/bcmdrivers/opensource/Makefile 2006-08-03 16:42:38.000000000 +0200
3206 @@ -0,0 +1,20 @@
3207 +# File: modules/drivers/Makefile
3208 +#
3209 +# Makefile for the GPLed Linux kernel modules.
3210 +#
3211 +
3212 +LN_NAME=bcm9$(BRCM_CHIP)
3213 +LN_DRIVER_DIRS =
3214 +
3215 +-include $(KERNEL_DIR)/.config
3216 +
3217 +ifneq ($(CONFIG_BCM_SERIAL),)
3218 + LN_DRIVER_DIRS +=ln -sn impl$(CONFIG_BCM_SERIAL_IMPL) char/serial/$(LN_NAME);
3219 +endif
3220 +
3221 +obj-$(CONFIG_BCM_SERIAL) += char/serial/impl$(CONFIG_BCM_SERIAL_IMPL)/
3222 +
3223 +
3224 +symlinks:
3225 + find . -lname "*" -name "$(LN_NAME)" -print -exec rm -f "{}" ";"
3226 + $(CONFIG_SHELL) -c "$(LN_DRIVER_DIRS)"
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