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78b1aef13430b0534321400a5ec31a3f55bfa5ef
[openwrt.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * ADM5120 HCD (Host Controller Driver) for USB
3 *
4 * Copyright (C) 2007,2008 Gabor Juhos <juhosg at openwrt.org>
5 *
6 * This file was derived from: drivers/usb/host/ohci-hcd.c
7 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
8 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
9 *
10 * [ Initialisation is based on Linus' ]
11 * [ uhci code and gregs ahcd fragments ]
12 * [ (C) Copyright 1999 Linus Torvalds ]
13 * [ (C) Copyright 1999 Gregory P. Smith]
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published
17 * by the Free Software Foundation.
18 *
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
44
45 #include "../core/hcd.h"
46 #include "../core/hub.h"
47
48 #define DRIVER_VERSION "0.24.0"
49 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
50 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #undef ADMHC_VERBOSE_DEBUG /* not always helpful */
55
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58
59 #define ADMHC_INTR_INIT \
60 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
61 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
62
63 /*-------------------------------------------------------------------------*/
64
65 static const char hcd_name [] = "admhc-hcd";
66
67 #define STATECHANGE_DELAY msecs_to_jiffies(300)
68
69 #include "adm5120.h"
70
71 static void admhc_dump(struct admhcd *ahcd, int verbose);
72 static int admhc_init(struct admhcd *ahcd);
73 static void admhc_stop(struct usb_hcd *hcd);
74
75 #include "adm5120-dbg.c"
76 #include "adm5120-mem.c"
77 #include "adm5120-pm.c"
78 #include "adm5120-hub.c"
79 #include "adm5120-q.c"
80
81 /*-------------------------------------------------------------------------*/
82
83 /*
84 * queue up an urb for anything except the root hub
85 */
86 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
87 gfp_t mem_flags)
88 {
89 struct admhcd *ahcd = hcd_to_admhcd(hcd);
90 struct ed *ed;
91 struct urb_priv *urb_priv;
92 unsigned int pipe = urb->pipe;
93 int td_cnt = 0;
94 unsigned long flags;
95 int ret = 0;
96
97 #ifdef ADMHC_VERBOSE_DEBUG
98 spin_lock_irqsave(&ahcd->lock, flags);
99 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe), -EINPROGRESS);
100 spin_unlock_irqrestore(&ahcd->lock, flags);
101 #endif
102
103 /* every endpoint has an ed, locate and maybe (re)initialize it */
104 ed = ed_get(ahcd, urb->ep, urb->dev, pipe, urb->interval);
105 if (!ed)
106 return -ENOMEM;
107
108 /* for the private part of the URB we need the number of TDs */
109 switch (ed->type) {
110 case PIPE_CONTROL:
111 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
112 /* td_submit_urb() doesn't yet handle these */
113 return -EMSGSIZE;
114
115 /* 1 TD for setup, 1 for ACK, plus ... */
116 td_cnt = 2;
117 /* FALLTHROUGH */
118 case PIPE_BULK:
119 /* one TD for every 4096 Bytes (can be upto 8K) */
120 td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
121 /* ... and for any remaining bytes ... */
122 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
123 td_cnt++;
124 /* ... and maybe a zero length packet to wrap it up */
125 if (td_cnt == 0)
126 td_cnt++;
127 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
128 && (urb->transfer_buffer_length
129 % usb_maxpacket(urb->dev, pipe,
130 usb_pipeout (pipe))) == 0)
131 td_cnt++;
132 break;
133 case PIPE_INTERRUPT:
134 /*
135 * for Interrupt IN/OUT transactions, each ED contains
136 * only 1 TD.
137 * TODO: check transfer_buffer_length?
138 */
139 td_cnt = 1;
140 break;
141 case PIPE_ISOCHRONOUS:
142 /* number of packets from URB */
143 td_cnt = urb->number_of_packets;
144 break;
145 }
146
147 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
148 if (!urb_priv)
149 return -ENOMEM;
150
151 urb_priv->ed = ed;
152
153 spin_lock_irqsave(&ahcd->lock, flags);
154 /* don't submit to a dead HC */
155 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
156 ret = -ENODEV;
157 goto fail;
158 }
159 if (!HC_IS_RUNNING(hcd->state)) {
160 ret = -ENODEV;
161 goto fail;
162 }
163
164 ret = usb_hcd_link_urb_to_ep(hcd, urb);
165 if (ret)
166 goto fail;
167
168 /* schedule the ed if needed */
169 if (ed->state == ED_IDLE) {
170 ret = ed_schedule(ahcd, ed);
171 if (ret < 0) {
172 usb_hcd_unlink_urb_from_ep(hcd, urb);
173 goto fail;
174 }
175 if (ed->type == PIPE_ISOCHRONOUS) {
176 u16 frame = admhc_frame_no(ahcd);
177
178 /* delay a few frames before the first TD */
179 frame += max_t (u16, 8, ed->interval);
180 frame &= ~(ed->interval - 1);
181 frame |= ed->branch;
182 urb->start_frame = frame;
183
184 /* yes, only URB_ISO_ASAP is supported, and
185 * urb->start_frame is never used as input.
186 */
187 }
188 } else if (ed->type == PIPE_ISOCHRONOUS)
189 urb->start_frame = ed->last_iso + ed->interval;
190
191 /* fill the TDs and link them to the ed; and
192 * enable that part of the schedule, if needed
193 * and update count of queued periodic urbs
194 */
195 urb->hcpriv = urb_priv;
196 td_submit_urb(ahcd, urb);
197
198 #ifdef ADMHC_VERBOSE_DEBUG
199 admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
200 #endif
201
202 fail:
203 if (ret)
204 urb_priv_free(ahcd, urb_priv);
205
206 spin_unlock_irqrestore(&ahcd->lock, flags);
207 return ret;
208 }
209
210 /*
211 * decouple the URB from the HC queues (TDs, urb_priv);
212 * reporting is always done
213 * asynchronously, and we might be dealing with an urb that's
214 * partially transferred, or an ED with other urbs being unlinked.
215 */
216 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
217 int status)
218 {
219 struct admhcd *ahcd = hcd_to_admhcd(hcd);
220 unsigned long flags;
221 int ret;
222
223 spin_lock_irqsave(&ahcd->lock, flags);
224
225 #ifdef ADMHC_VERBOSE_DEBUG
226 urb_print(ahcd, urb, "DEQUEUE", 1, status);
227 #endif
228 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
229 if (ret) {
230 /* Do nothing */
231 ;
232 } else if (HC_IS_RUNNING(hcd->state)) {
233 struct urb_priv *urb_priv;
234
235 /* Unless an IRQ completed the unlink while it was being
236 * handed to us, flag it for unlink and giveback, and force
237 * some upcoming INTR_SF to call finish_unlinks()
238 */
239 urb_priv = urb->hcpriv;
240 if (urb_priv) {
241 if (urb_priv->ed->state == ED_OPER)
242 start_ed_unlink(ahcd, urb_priv->ed);
243 }
244 } else {
245 /*
246 * with HC dead, we won't respect hc queue pointers
247 * any more ... just clean up every urb's memory.
248 */
249 if (urb->hcpriv)
250 finish_urb(ahcd, urb, status);
251 }
252 spin_unlock_irqrestore(&ahcd->lock, flags);
253
254 return ret;
255 }
256
257 /*-------------------------------------------------------------------------*/
258
259 /* frees config/altsetting state for endpoints,
260 * including ED memory, dummy TD, and bulk/intr data toggle
261 */
262
263 static void admhc_endpoint_disable(struct usb_hcd *hcd,
264 struct usb_host_endpoint *ep)
265 {
266 struct admhcd *ahcd = hcd_to_admhcd(hcd);
267 unsigned long flags;
268 struct ed *ed = ep->hcpriv;
269 unsigned limit = 1000;
270
271 /* ASSERT: any requests/urbs are being unlinked */
272 /* ASSERT: nobody can be submitting urbs for this any more */
273
274 if (!ed)
275 return;
276
277 #ifdef ADMHC_VERBOSE_DEBUG
278 spin_lock_irqsave(&ahcd->lock, flags);
279 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
280 spin_unlock_irqrestore(&ahcd->lock, flags);
281 #endif
282
283 rescan:
284 spin_lock_irqsave(&ahcd->lock, flags);
285
286 if (!HC_IS_RUNNING(hcd->state)) {
287 sanitize:
288 ed->state = ED_IDLE;
289 finish_unlinks(ahcd, 0);
290 }
291
292 switch (ed->state) {
293 case ED_UNLINK: /* wait for hw to finish? */
294 /* major IRQ delivery trouble loses INTR_SOFI too... */
295 if (limit-- == 0) {
296 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
297 goto sanitize;
298 }
299 spin_unlock_irqrestore(&ahcd->lock, flags);
300 schedule_timeout_uninterruptible(1);
301 goto rescan;
302 case ED_IDLE: /* fully unlinked */
303 if (list_empty(&ed->td_list)) {
304 td_free (ahcd, ed->dummy);
305 ed_free (ahcd, ed);
306 break;
307 }
308 /* else FALL THROUGH */
309 default:
310 /* caller was supposed to have unlinked any requests;
311 * that's not our job. can't recover; must leak ed.
312 */
313 admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
314 ed, ep->desc.bEndpointAddress, ed->state,
315 list_empty(&ed->td_list) ? "" : " (has tds)");
316 td_free(ahcd, ed->dummy);
317 break;
318 }
319
320 ep->hcpriv = NULL;
321
322 spin_unlock_irqrestore(&ahcd->lock, flags);
323 return;
324 }
325
326 static int admhc_get_frame_number(struct usb_hcd *hcd)
327 {
328 struct admhcd *ahcd = hcd_to_admhcd(hcd);
329
330 return admhc_frame_no(ahcd);
331 }
332
333 static void admhc_usb_reset(struct admhcd *ahcd)
334 {
335 #if 0
336 ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
337 ahcd->hc_control &= OHCI_CTRL_RWC;
338 admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
339 #else
340 /* FIXME */
341 ahcd->host_control = ADMHC_BUSS_RESET;
342 admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
343 #endif
344 }
345
346 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
347 * other cases where the next software may expect clean state from the
348 * "firmware". this is bus-neutral, unlike shutdown() methods.
349 */
350 static void
351 admhc_shutdown(struct usb_hcd *hcd)
352 {
353 struct admhcd *ahcd;
354
355 ahcd = hcd_to_admhcd(hcd);
356 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
357 admhc_dma_disable(ahcd);
358 admhc_usb_reset(ahcd);
359 /* flush the writes */
360 admhc_writel_flush(ahcd);
361 }
362
363 /*-------------------------------------------------------------------------*
364 * HC functions
365 *-------------------------------------------------------------------------*/
366
367 static void admhc_eds_cleanup(struct admhcd *ahcd)
368 {
369 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
370 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
371 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
372 }
373
374 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
375 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
376 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
377 }
378
379 if (ahcd->ed_tails[PIPE_CONTROL]) {
380 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
381 ahcd->ed_tails[PIPE_CONTROL] = NULL;
382 }
383
384 if (ahcd->ed_tails[PIPE_BULK]) {
385 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
386 ahcd->ed_tails[PIPE_BULK] = NULL;
387 }
388
389 ahcd->ed_head = NULL;
390 }
391
392 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
393
394 static int admhc_eds_init(struct admhcd *ahcd)
395 {
396 struct ed *ed;
397
398 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
399 if (!ed)
400 goto err;
401
402 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
403
404 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
405 if (!ed)
406 goto err;
407
408 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
409 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
410 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
411 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
412
413 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
414 if (!ed)
415 goto err;
416
417 ahcd->ed_tails[PIPE_CONTROL] = ed;
418 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
419 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
420 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
421
422 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
423 if (!ed)
424 goto err;
425
426 ahcd->ed_tails[PIPE_BULK] = ed;
427 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
428 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
429 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
430
431 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
432
433 #ifdef ADMHC_VERBOSE_DEBUG
434 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
435 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
436 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
437 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
438 #endif
439
440 return 0;
441
442 err:
443 admhc_eds_cleanup(ahcd);
444 return -ENOMEM;
445 }
446
447 /* init memory, and kick BIOS/SMM off */
448
449 static int admhc_init(struct admhcd *ahcd)
450 {
451 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
452 int ret;
453
454 admhc_disable(ahcd);
455 ahcd->regs = hcd->regs;
456
457 /* Disable HC interrupts */
458 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
459
460 /* Read the number of ports unless overridden */
461 if (ahcd->num_ports == 0)
462 ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
463
464 ret = admhc_mem_init(ahcd);
465 if (ret)
466 goto err;
467
468 /* init dummy endpoints */
469 ret = admhc_eds_init(ahcd);
470 if (ret)
471 goto err;
472
473 create_debug_files(ahcd);
474
475 return 0;
476
477 err:
478 admhc_stop(hcd);
479 return ret;
480 }
481
482 /*-------------------------------------------------------------------------*/
483
484 /* Start an OHCI controller, set the BUS operational
485 * resets USB and controller
486 * enable interrupts
487 */
488 static int admhc_run(struct admhcd *ahcd)
489 {
490 u32 temp;
491 int first = ahcd->fminterval == 0;
492 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
493
494 admhc_disable(ahcd);
495
496 /* boot firmware should have set this up (5.1.1.3.1) */
497 if (first) {
498 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
499 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
500 if (ahcd->fminterval != FI)
501 admhc_dbg(ahcd, "fminterval delta %d\n",
502 ahcd->fminterval - FI);
503 ahcd->fminterval |=
504 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
505 /* also: power/overcurrent flags in rhdesc */
506 }
507
508 #if 0 /* TODO: not applicable */
509 /* Reset USB nearly "by the book". RemoteWakeupConnected was
510 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
511 * or if bus glue did the same (e.g. for PCI add-in cards with
512 * PCI PM support).
513 */
514 if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
515 && !device_may_wakeup(hcd->self.controller))
516 device_init_wakeup(hcd->self.controller, 1);
517 #endif
518
519 switch (ahcd->host_control & ADMHC_HC_BUSS) {
520 case ADMHC_BUSS_OPER:
521 temp = 0;
522 break;
523 case ADMHC_BUSS_SUSPEND:
524 /* FALLTHROUGH ? */
525 case ADMHC_BUSS_RESUME:
526 ahcd->host_control = ADMHC_BUSS_RESUME;
527 temp = 10 /* msec wait */;
528 break;
529 /* case ADMHC_BUSS_RESET: */
530 default:
531 ahcd->host_control = ADMHC_BUSS_RESET;
532 temp = 50 /* msec wait */;
533 break;
534 }
535 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
536
537 /* flush the writes */
538 admhc_writel_flush(ahcd);
539
540 msleep(temp);
541 temp = admhc_read_rhdesc(ahcd);
542 if (!(temp & ADMHC_RH_NPS)) {
543 /* power down each port */
544 for (temp = 0; temp < ahcd->num_ports; temp++)
545 admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
546 }
547 /* flush those writes */
548 admhc_writel_flush(ahcd);
549
550 /* 2msec timelimit here means no irqs/preempt */
551 spin_lock_irq(&ahcd->lock);
552
553 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
554 temp = 30; /* ... allow extra time */
555 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
556 if (--temp == 0) {
557 spin_unlock_irq(&ahcd->lock);
558 admhc_err(ahcd, "USB HC reset timed out!\n");
559 return -1;
560 }
561 udelay(1);
562 }
563
564 /* enable HOST mode, before access any host specific register */
565 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
566
567 /* Tell the controller where the descriptor list is */
568 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
569
570 periodic_reinit(ahcd);
571
572 /* use rhsc irqs after khubd is fully initialized */
573 hcd->poll_rh = 1;
574 hcd->uses_new_polling = 1;
575
576 #if 0
577 /* wake on ConnectStatusChange, matching external hubs */
578 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
579 #else
580 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
581 #endif
582
583 /* Choose the interrupts we care about now, others later on demand */
584 admhc_intr_ack(ahcd, ~0);
585 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
586
587 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
588
589 /* flush those writes */
590 admhc_writel_flush(ahcd);
591
592 /* start controller operations */
593 ahcd->host_control = ADMHC_BUSS_OPER;
594 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
595
596 temp = 20;
597 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
598 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
599 if (--temp == 0) {
600 spin_unlock_irq(&ahcd->lock);
601 admhc_err(ahcd, "unable to setup operational mode!\n");
602 return -1;
603 }
604 mdelay(1);
605 }
606
607 hcd->state = HC_STATE_RUNNING;
608
609 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
610
611 #if 0
612 /* FIXME: enabling DMA is always failed here for an unknown reason */
613 admhc_dma_enable(ahcd);
614
615 temp = 200;
616 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
617 & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
618 if (--temp == 0) {
619 spin_unlock_irq(&ahcd->lock);
620 admhc_err(ahcd, "unable to enable DMA!\n");
621 admhc_dump(ahcd, 1);
622 return -1;
623 }
624 mdelay(1);
625 }
626
627 #endif
628
629 spin_unlock_irq(&ahcd->lock);
630
631 mdelay(ADMHC_POTPGT);
632
633 return 0;
634 }
635
636 /*-------------------------------------------------------------------------*/
637
638 /* an interrupt happens */
639
640 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
641 {
642 struct admhcd *ahcd = hcd_to_admhcd(hcd);
643 struct admhcd_regs __iomem *regs = ahcd->regs;
644 u32 ints;
645
646 ints = admhc_readl(ahcd, &regs->int_status);
647 if ((ints & ADMHC_INTR_INTA) == 0) {
648 /* no unmasked interrupt status is set */
649 return IRQ_NONE;
650 }
651
652 ints &= admhc_readl(ahcd, &regs->int_enable);
653
654 if (ints & ADMHC_INTR_FATI) {
655 /* e.g. due to PCI Master/Target Abort */
656 admhc_disable(ahcd);
657 admhc_err(ahcd, "Fatal Error, controller disabled\n");
658 admhc_dump(ahcd, 1);
659 admhc_usb_reset(ahcd);
660 }
661
662 if (ints & ADMHC_INTR_BABI) {
663 admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
664 admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
665 admhc_err(ahcd, "Babble Detected\n");
666 }
667
668 if (ints & ADMHC_INTR_INSM) {
669 admhc_vdbg(ahcd, "Root Hub Status Change\n");
670 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
671 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
672
673 /* NOTE: Vendors didn't always make the same implementation
674 * choices for RHSC. Many followed the spec; RHSC triggers
675 * on an edge, like setting and maybe clearing a port status
676 * change bit. With others it's level-triggered, active
677 * until khubd clears all the port status change bits. We'll
678 * always disable it here and rely on polling until khubd
679 * re-enables it.
680 */
681 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
682 usb_hcd_poll_rh_status(hcd);
683 } else if (ints & ADMHC_INTR_RESI) {
684 /* For connect and disconnect events, we expect the controller
685 * to turn on RHSC along with RD. But for remote wakeup events
686 * this might not happen.
687 */
688 admhc_vdbg(ahcd, "Resume Detect\n");
689 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
690 hcd->poll_rh = 1;
691 if (ahcd->autostop) {
692 spin_lock(&ahcd->lock);
693 admhc_rh_resume(ahcd);
694 spin_unlock(&ahcd->lock);
695 } else
696 usb_hcd_resume_root_hub(hcd);
697 }
698
699 if (ints & ADMHC_INTR_TDC) {
700 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
701 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
702 if (HC_IS_RUNNING(hcd->state))
703 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
704 spin_lock(&ahcd->lock);
705 admhc_td_complete(ahcd);
706 spin_unlock(&ahcd->lock);
707 if (HC_IS_RUNNING(hcd->state))
708 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
709 }
710
711 if (ints & ADMHC_INTR_SO) {
712 /* could track INTR_SO to reduce available PCI/... bandwidth */
713 admhc_vdbg(ahcd, "Schedule Overrun\n");
714 }
715
716 #if 1
717 spin_lock(&ahcd->lock);
718 if (ahcd->ed_rm_list)
719 finish_unlinks(ahcd, admhc_frame_no(ahcd));
720
721 if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
722 && HC_IS_RUNNING(hcd->state))
723 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
724 spin_unlock(&ahcd->lock);
725 #else
726 if (ints & ADMHC_INTR_SOFI) {
727 admhc_vdbg(ahcd, "Start Of Frame\n");
728 spin_lock(&ahcd->lock);
729
730 /* handle any pending ED removes */
731 finish_unlinks(ahcd, admhc_frameno(ahcd));
732
733 /* leaving INTR_SOFI enabled when there's still unlinking
734 * to be done in the (next frame).
735 */
736 if ((ahcd->ed_rm_list == NULL) ||
737 HC_IS_RUNNING(hcd->state) == 0)
738 /*
739 * disable INTR_SOFI if there are no unlinking to be
740 * done (in the next frame)
741 */
742 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
743
744 spin_unlock(&ahcd->lock);
745 }
746 #endif
747
748 if (HC_IS_RUNNING(hcd->state)) {
749 admhc_intr_ack(ahcd, ints);
750 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
751 admhc_writel_flush(ahcd);
752 }
753
754 return IRQ_HANDLED;
755 }
756
757 /*-------------------------------------------------------------------------*/
758
759 static void admhc_stop(struct usb_hcd *hcd)
760 {
761 struct admhcd *ahcd = hcd_to_admhcd(hcd);
762
763 admhc_dump(ahcd, 1);
764
765 flush_scheduled_work();
766
767 admhc_usb_reset(ahcd);
768 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
769
770 free_irq(hcd->irq, hcd);
771 hcd->irq = -1;
772
773 remove_debug_files(ahcd);
774 admhc_eds_cleanup(ahcd);
775 admhc_mem_cleanup(ahcd);
776 }
777
778 /*-------------------------------------------------------------------------*/
779
780 #ifdef CONFIG_MIPS_ADM5120
781 #include "adm5120-drv.c"
782 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
783 #endif
784
785 #if !defined(PLATFORM_DRIVER)
786 #error "missing bus glue for admhc-hcd"
787 #endif
788
789 #define DRIVER_INFO DRIVER_DESC " version " DRIVER_VERSION
790
791 static int __init admhc_hcd_mod_init(void)
792 {
793 int ret = 0;
794
795 if (usb_disabled())
796 return -ENODEV;
797
798 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
799 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
800 sizeof (struct ed), sizeof (struct td));
801
802 #ifdef PLATFORM_DRIVER
803 ret = platform_driver_register(&PLATFORM_DRIVER);
804 if (ret < 0)
805 goto error_platform;
806 #endif
807
808 return ret;
809
810 #ifdef PLATFORM_DRIVER
811 platform_driver_unregister(&PLATFORM_DRIVER);
812 error_platform:
813 #endif
814 return ret;
815 }
816 module_init(admhc_hcd_mod_init);
817
818 static void __exit admhc_hcd_mod_exit(void)
819 {
820 platform_driver_unregister(&PLATFORM_DRIVER);
821 }
822 module_exit(admhc_hcd_mod_exit);
823
824 MODULE_AUTHOR(DRIVER_AUTHOR);
825 MODULE_DESCRIPTION(DRIVER_INFO);
826 MODULE_VERSION(DRIVER_VERSION);
827 MODULE_LICENSE("GPL v2");
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