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[openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
24 #define RTL8366RB_DRIVER_VER "0.2.2"
25
26 #define RTL8366RB_PHY_NO_MAX 4
27 #define RTL8366RB_PHY_PAGE_MAX 7
28 #define RTL8366RB_PHY_ADDR_MAX 31
29
30 /* Switch Global Configuration register */
31 #define RTL8366RB_SGCR 0x0000
32 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
40 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41
42 /* Port Enable Control register */
43 #define RTL8366RB_PECR 0x0001
44
45 /* Switch Security Control registers */
46 #define RTL8366RB_SSCR0 0x0002
47 #define RTL8366RB_SSCR1 0x0003
48 #define RTL8366RB_SSCR2 0x0004
49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50
51 #define RTL8366RB_RESET_CTRL_REG 0x0100
52 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
53 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
54
55 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
56 #define RTL8366RB_CHIP_VERSION_MASK 0xf
57 #define RTL8366RB_CHIP_ID_REG 0x0509
58 #define RTL8366RB_CHIP_ID_8366 0x5937
59
60 /* PHY registers control */
61 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
62 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
63
64 #define RTL8366RB_PHY_CTRL_READ 1
65 #define RTL8366RB_PHY_CTRL_WRITE 0
66
67 #define RTL8366RB_PHY_REG_MASK 0x1f
68 #define RTL8366RB_PHY_PAGE_OFFSET 5
69 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
70 #define RTL8366RB_PHY_NO_OFFSET 9
71 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
72
73 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
74
75 /* LED control registers */
76 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
77 #define RTL8366RB_LED_BLINKRATE_BIT 0
78 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
79
80 #define RTL8366RB_LED_CTRL_REG 0x0431
81 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
82 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
83
84 #define RTL8366RB_MIB_COUNT 33
85 #define RTL8366RB_GLOBAL_MIB_COUNT 1
86 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
87 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
88 #define RTL8366RB_MIB_CTRL_REG 0x13F0
89 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
90 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
91 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
92 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
93 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
94
95 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
96 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
97 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
98 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
99 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
100
101
102 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
103 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
104
105
106 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
107 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
108 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
109
110 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
111
112
113 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
114 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
115 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
116 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
117 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
118 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
119 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
120
121
122 #define RTL8366RB_PORT_NUM_CPU 5
123 #define RTL8366RB_NUM_PORTS 6
124 #define RTL8366RB_NUM_VLANS 16
125 #define RTL8366RB_NUM_LEDGROUPS 4
126 #define RTL8366RB_NUM_VIDS 4096
127 #define RTL8366RB_PRIORITYMAX 7
128 #define RTL8366RB_FIDMAX 7
129
130
131 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
132 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
133 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
134 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
135 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
136
137 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
138
139 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
140 RTL8366RB_PORT_2 | \
141 RTL8366RB_PORT_3 | \
142 RTL8366RB_PORT_4 | \
143 RTL8366RB_PORT_5 | \
144 RTL8366RB_PORT_CPU)
145
146 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
147 RTL8366RB_PORT_2 | \
148 RTL8366RB_PORT_3 | \
149 RTL8366RB_PORT_4 | \
150 RTL8366RB_PORT_5)
151
152 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
153 RTL8366RB_PORT_2 | \
154 RTL8366RB_PORT_3 | \
155 RTL8366RB_PORT_4)
156
157 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
158
159 #define RTL8366RB_VLAN_VID_MASK 0xfff
160 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
161 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
162 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
163 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
164 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
165 #define RTL8366RB_VLAN_FID_MASK 0x7
166
167
168 /* Port ingress bandwidth control */
169 #define RTL8366RB_IB_BASE 0x0200
170 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
171 #define RTL8366RB_IB_BDTH_MASK 0x3fff
172 #define RTL8366RB_IB_PREIFG_OFFSET 14
173 #define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
174
175 /* Port egress bandwidth control */
176 #define RTL8366RB_EB_BASE 0x02d1
177 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
178 #define RTL8366RB_EB_BDTH_MASK 0x3fff
179 #define RTL8366RB_EB_PREIFG_REG 0x02f8
180 #define RTL8366RB_EB_PREIFG_OFFSET 9
181 #define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
182
183 #define RTL8366RB_BDTH_SW_MAX 1048512
184 #define RTL8366RB_BDTH_BASE 64
185 #define RTL8366RB_BDTH_REG_DEFAULT 16383
186
187 /* QOS */
188 #define RTL8366RB_QOS_BIT 15
189 #define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
190 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
191 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
192
193
194 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
195 { 0, 0, 4, "IfInOctets" },
196 { 0, 4, 4, "EtherStatsOctets" },
197 { 0, 8, 2, "EtherStatsUnderSizePkts" },
198 { 0, 10, 2, "EtherFragments" },
199 { 0, 12, 2, "EtherStatsPkts64Octets" },
200 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
201 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
202 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
203 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
204 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
205 { 0, 24, 2, "EtherOversizeStats" },
206 { 0, 26, 2, "EtherStatsJabbers" },
207 { 0, 28, 2, "IfInUcastPkts" },
208 { 0, 30, 2, "EtherStatsMulticastPkts" },
209 { 0, 32, 2, "EtherStatsBroadcastPkts" },
210 { 0, 34, 2, "EtherStatsDropEvents" },
211 { 0, 36, 2, "Dot3StatsFCSErrors" },
212 { 0, 38, 2, "Dot3StatsSymbolErrors" },
213 { 0, 40, 2, "Dot3InPauseFrames" },
214 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
215 { 0, 44, 4, "IfOutOctets" },
216 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
217 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
218 { 0, 52, 2, "Dot3sDeferredTransmissions" },
219 { 0, 54, 2, "Dot3StatsLateCollisions" },
220 { 0, 56, 2, "EtherStatsCollisions" },
221 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
222 { 0, 60, 2, "Dot3OutPauseFrames" },
223 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
224 { 0, 64, 2, "Dot1dTpPortInDiscards" },
225 { 0, 66, 2, "IfOutUcastPkts" },
226 { 0, 68, 2, "IfOutMulticastPkts" },
227 { 0, 70, 2, "IfOutBroadcastPkts" },
228 };
229
230 #define REG_WR(_smi, _reg, _val) \
231 do { \
232 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
233 if (err) \
234 return err; \
235 } while (0)
236
237 #define REG_RMW(_smi, _reg, _mask, _val) \
238 do { \
239 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
240 if (err) \
241 return err; \
242 } while (0)
243
244 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
245 {
246 int timeout = 10;
247 u32 data;
248
249 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
250 RTL8366RB_CHIP_CTRL_RESET_HW);
251 do {
252 msleep(1);
253 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
254 return -EIO;
255
256 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
257 break;
258 } while (--timeout);
259
260 if (!timeout) {
261 printk("Timeout waiting for the switch to reset\n");
262 return -EIO;
263 }
264
265 return 0;
266 }
267
268 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
269 {
270 int err;
271
272 /* set maximum packet length to 1536 bytes */
273 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
274 RTL8366RB_SGCR_MAX_LENGTH_1536);
275
276 /* enable all ports */
277 REG_WR(smi, RTL8366RB_PECR, 0);
278
279 /* enable learning for all ports */
280 REG_WR(smi, RTL8366RB_SSCR0, 0);
281
282 /* enable auto ageing for all ports */
283 REG_WR(smi, RTL8366RB_SSCR1, 0);
284
285 /*
286 * discard VLAN tagged packets if the port is not a member of
287 * the VLAN with which the packets is associated.
288 */
289 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
290
291 /* don't drop packets whose DA has not been learned */
292 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
293
294 return 0;
295 }
296
297 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
298 u32 phy_no, u32 page, u32 addr, u32 *data)
299 {
300 u32 reg;
301 int ret;
302
303 if (phy_no > RTL8366RB_PHY_NO_MAX)
304 return -EINVAL;
305
306 if (page > RTL8366RB_PHY_PAGE_MAX)
307 return -EINVAL;
308
309 if (addr > RTL8366RB_PHY_ADDR_MAX)
310 return -EINVAL;
311
312 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
313 RTL8366RB_PHY_CTRL_READ);
314 if (ret)
315 return ret;
316
317 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
318 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
319 (addr & RTL8366RB_PHY_REG_MASK);
320
321 ret = rtl8366_smi_write_reg(smi, reg, 0);
322 if (ret)
323 return ret;
324
325 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
326 if (ret)
327 return ret;
328
329 return 0;
330 }
331
332 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
333 u32 phy_no, u32 page, u32 addr, u32 data)
334 {
335 u32 reg;
336 int ret;
337
338 if (phy_no > RTL8366RB_PHY_NO_MAX)
339 return -EINVAL;
340
341 if (page > RTL8366RB_PHY_PAGE_MAX)
342 return -EINVAL;
343
344 if (addr > RTL8366RB_PHY_ADDR_MAX)
345 return -EINVAL;
346
347 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
348 RTL8366RB_PHY_CTRL_WRITE);
349 if (ret)
350 return ret;
351
352 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
353 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
354 (addr & RTL8366RB_PHY_REG_MASK);
355
356 ret = rtl8366_smi_write_reg(smi, reg, data);
357 if (ret)
358 return ret;
359
360 return 0;
361 }
362
363 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
364 int port, unsigned long long *val)
365 {
366 int i;
367 int err;
368 u32 addr, data;
369 u64 mibvalue;
370
371 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
372 return -EINVAL;
373
374 addr = RTL8366RB_MIB_COUNTER_BASE +
375 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
376 rtl8366rb_mib_counters[counter].offset;
377
378 /*
379 * Writing access counter address first
380 * then ASIC will prepare 64bits counter wait for being retrived
381 */
382 data = 0; /* writing data will be discard by ASIC */
383 err = rtl8366_smi_write_reg(smi, addr, data);
384 if (err)
385 return err;
386
387 /* read MIB control register */
388 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
389 if (err)
390 return err;
391
392 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
393 return -EBUSY;
394
395 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
396 return -EIO;
397
398 mibvalue = 0;
399 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
400 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
401 if (err)
402 return err;
403
404 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
405 }
406
407 *val = mibvalue;
408 return 0;
409 }
410
411 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
412 struct rtl8366_vlan_4k *vlan4k)
413 {
414 u32 data[3];
415 int err;
416 int i;
417
418 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
419
420 if (vid >= RTL8366RB_NUM_VIDS)
421 return -EINVAL;
422
423 /* write VID */
424 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
425 vid & RTL8366RB_VLAN_VID_MASK);
426 if (err)
427 return err;
428
429 /* write table access control word */
430 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
431 RTL8366RB_TABLE_VLAN_READ_CTRL);
432 if (err)
433 return err;
434
435 for (i = 0; i < 3; i++) {
436 err = rtl8366_smi_read_reg(smi,
437 RTL8366RB_VLAN_TABLE_READ_BASE + i,
438 &data[i]);
439 if (err)
440 return err;
441 }
442
443 vlan4k->vid = vid;
444 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
445 RTL8366RB_VLAN_UNTAG_MASK;
446 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
447 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
448
449 return 0;
450 }
451
452 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
453 const struct rtl8366_vlan_4k *vlan4k)
454 {
455 u32 data[3];
456 int err;
457 int i;
458
459 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
460 vlan4k->member > RTL8366RB_PORT_ALL ||
461 vlan4k->untag > RTL8366RB_PORT_ALL ||
462 vlan4k->fid > RTL8366RB_FIDMAX)
463 return -EINVAL;
464
465 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
466 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
467 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
468 RTL8366RB_VLAN_UNTAG_SHIFT);
469 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
470
471 for (i = 0; i < 3; i++) {
472 err = rtl8366_smi_write_reg(smi,
473 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
474 data[i]);
475 if (err)
476 return err;
477 }
478
479 /* write table access control word */
480 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
481 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
482
483 return err;
484 }
485
486 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
487 struct rtl8366_vlan_mc *vlanmc)
488 {
489 u32 data[3];
490 int err;
491 int i;
492
493 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
494
495 if (index >= RTL8366RB_NUM_VLANS)
496 return -EINVAL;
497
498 for (i = 0; i < 3; i++) {
499 err = rtl8366_smi_read_reg(smi,
500 RTL8366RB_VLAN_MC_BASE(index) + i,
501 &data[i]);
502 if (err)
503 return err;
504 }
505
506 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
507 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
508 RTL8366RB_VLAN_PRIORITY_MASK;
509 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
510 RTL8366RB_VLAN_UNTAG_MASK;
511 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
512 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
513
514 return 0;
515 }
516
517 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
518 const struct rtl8366_vlan_mc *vlanmc)
519 {
520 u32 data[3];
521 int err;
522 int i;
523
524 if (index >= RTL8366RB_NUM_VLANS ||
525 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
526 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
527 vlanmc->member > RTL8366RB_PORT_ALL ||
528 vlanmc->untag > RTL8366RB_PORT_ALL ||
529 vlanmc->fid > RTL8366RB_FIDMAX)
530 return -EINVAL;
531
532 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
533 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
534 RTL8366RB_VLAN_PRIORITY_SHIFT);
535 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
536 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
537 RTL8366RB_VLAN_UNTAG_SHIFT);
538 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
539
540 for (i = 0; i < 3; i++) {
541 err = rtl8366_smi_write_reg(smi,
542 RTL8366RB_VLAN_MC_BASE(index) + i,
543 data[i]);
544 if (err)
545 return err;
546 }
547
548 return 0;
549 }
550
551 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
552 {
553 u32 data;
554 int err;
555
556 if (port >= RTL8366RB_NUM_PORTS)
557 return -EINVAL;
558
559 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
560 &data);
561 if (err)
562 return err;
563
564 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
565 RTL8366RB_PORT_VLAN_CTRL_MASK;
566
567 return 0;
568
569 }
570
571 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
572 {
573 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
574 return -EINVAL;
575
576 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
577 RTL8366RB_PORT_VLAN_CTRL_MASK <<
578 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
579 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
580 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
581 }
582
583 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
584 {
585 unsigned max = RTL8366RB_NUM_VLANS;
586
587 if (smi->vlan4k_enabled)
588 max = RTL8366RB_NUM_VIDS - 1;
589
590 if (vlan == 0 || vlan >= max)
591 return 0;
592
593 return 1;
594 }
595
596 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
597 {
598 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
599 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
600 }
601
602 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
603 {
604 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
605 RTL8366RB_SGCR_EN_VLAN_4KTB,
606 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
607 }
608
609 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
610 const struct switch_attr *attr,
611 struct switch_val *val)
612 {
613 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
614
615 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
616 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
617 }
618
619 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
620 const struct switch_attr *attr,
621 struct switch_val *val)
622 {
623 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
624 u32 data;
625
626 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
627
628 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
629
630 return 0;
631 }
632
633 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
634 const struct switch_attr *attr,
635 struct switch_val *val)
636 {
637 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
638
639 if (val->value.i >= 6)
640 return -EINVAL;
641
642 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
643 RTL8366RB_LED_BLINKRATE_MASK,
644 val->value.i);
645 }
646
647 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
648 const struct switch_attr *attr,
649 struct switch_val *val)
650 {
651 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
652 u32 data;
653
654 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
655 val->value.i = !data;
656
657 return 0;
658 }
659
660
661 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
662 const struct switch_attr *attr,
663 struct switch_val *val)
664 {
665 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
666 u32 portmask = 0;
667 int err = 0;
668
669 if (!val->value.i)
670 portmask = RTL8366RB_PORT_ALL;
671
672 /* set learning for all ports */
673 REG_WR(smi, RTL8366RB_SSCR0, portmask);
674
675 /* set auto ageing for all ports */
676 REG_WR(smi, RTL8366RB_SSCR1, portmask);
677
678 return 0;
679 }
680
681
682 static const char *rtl8366rb_speed_str(unsigned speed)
683 {
684 switch (speed) {
685 case 0:
686 return "10baseT";
687 case 1:
688 return "100baseT";
689 case 2:
690 return "1000baseT";
691 }
692
693 return "unknown";
694 }
695
696 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
697 const struct switch_attr *attr,
698 struct switch_val *val)
699 {
700 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
701 u32 len = 0, data = 0;
702
703 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
704 return -EINVAL;
705
706 memset(smi->buf, '\0', sizeof(smi->buf));
707 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
708 (val->port_vlan / 2), &data);
709
710 if (val->port_vlan % 2)
711 data = data >> 8;
712
713 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
714 len = snprintf(smi->buf, sizeof(smi->buf),
715 "port:%d link:up speed:%s %s-duplex %s%s%s",
716 val->port_vlan,
717 rtl8366rb_speed_str(data &
718 RTL8366RB_PORT_STATUS_SPEED_MASK),
719 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
720 "full" : "half",
721 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
722 "tx-pause ": "",
723 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
724 "rx-pause " : "",
725 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
726 "nway ": "");
727 } else {
728 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
729 val->port_vlan);
730 }
731
732 val->value.s = smi->buf;
733 val->len = len;
734
735 return 0;
736 }
737
738 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
739 const struct switch_attr *attr,
740 struct switch_val *val)
741 {
742 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
743 u32 data;
744 u32 mask;
745 u32 reg;
746
747 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
748 return -EINVAL;
749
750 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
751 reg = RTL8366RB_LED_BLINKRATE_REG;
752 mask = 0xF << 4;
753 data = val->value.i << 4;
754 } else {
755 reg = RTL8366RB_LED_CTRL_REG;
756 mask = 0xF << (val->port_vlan * 4),
757 data = val->value.i << (val->port_vlan * 4);
758 }
759
760 return rtl8366_smi_rmwr(smi, reg, mask, data);
761 }
762
763 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
764 const struct switch_attr *attr,
765 struct switch_val *val)
766 {
767 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
768 u32 data = 0;
769
770 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
771 return -EINVAL;
772
773 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
774 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
775
776 return 0;
777 }
778
779 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
780 const struct switch_attr *attr,
781 struct switch_val *val)
782 {
783 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
784 u32 mask, data;
785
786 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
787 return -EINVAL;
788
789 mask = 1 << val->port_vlan ;
790 if (val->value.i)
791 data = mask;
792 else
793 data = 0;
794
795 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
796 }
797
798 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
799 const struct switch_attr *attr,
800 struct switch_val *val)
801 {
802 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
803 u32 data;
804
805 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
806 return -EINVAL;
807
808 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
809 if (data & (1 << val->port_vlan))
810 val->value.i = 1;
811 else
812 val->value.i = 0;
813
814 return 0;
815 }
816
817 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
818 const struct switch_attr *attr,
819 struct switch_val *val)
820 {
821 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
822
823 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
824 return -EINVAL;
825
826 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
827 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_BASE;
828 else
829 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
830
831 return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
832 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
833 val->value.i |
834 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
835
836 }
837
838 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
839 const struct switch_attr *attr,
840 struct switch_val *val)
841 {
842 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
843 u32 data;
844
845 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
846 return -EINVAL;
847
848 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
849 data &= RTL8366RB_IB_BDTH_MASK;
850 if (data < RTL8366RB_IB_BDTH_MASK)
851 data += 1;
852
853 val->value.i = (int)data * RTL8366RB_BDTH_BASE;
854
855 return 0;
856 }
857
858 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
859 const struct switch_attr *attr,
860 struct switch_val *val)
861 {
862 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
863
864 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
865 return -EINVAL;
866
867 rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
868 RTL8366RB_EB_PREIFG_MASK,
869 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
870
871 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
872 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_BASE;
873 else
874 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
875
876 return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
877 RTL8366RB_EB_BDTH_MASK, val->value.i );
878
879 }
880
881 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
882 const struct switch_attr *attr,
883 struct switch_val *val)
884 {
885 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
886 u32 data;
887
888 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
889 return -EINVAL;
890
891 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
892 data &= RTL8366RB_EB_BDTH_MASK;
893 if (data < RTL8366RB_EB_BDTH_MASK)
894 data += 1;
895
896 val->value.i = (int)data * RTL8366RB_BDTH_BASE;
897
898 return 0;
899 }
900
901 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
902 const struct switch_attr *attr,
903 struct switch_val *val)
904 {
905 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
906 u32 data;
907
908 if (val->value.i)
909 data = RTL8366RB_QOS_MASK;
910 else
911 data = 0;
912
913 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
914 }
915
916 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
917 const struct switch_attr *attr,
918 struct switch_val *val)
919 {
920 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
921 u32 data;
922
923 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
924 if (data & RTL8366RB_QOS_MASK)
925 val->value.i = 1;
926 else
927 val->value.i = 0;
928
929 return 0;
930 }
931
932 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
933 const struct switch_attr *attr,
934 struct switch_val *val)
935 {
936 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
937
938 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
939 return -EINVAL;
940
941 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
942 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
943 }
944
945 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
946 {
947 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
948 int err;
949
950 err = rtl8366rb_reset_chip(smi);
951 if (err)
952 return err;
953
954 err = rtl8366rb_hw_init(smi);
955 if (err)
956 return err;
957
958 return rtl8366_reset_vlan(smi);
959 }
960
961 static struct switch_attr rtl8366rb_globals[] = {
962 {
963 .type = SWITCH_TYPE_INT,
964 .name = "enable_learning",
965 .description = "Enable learning, enable aging",
966 .set = rtl8366rb_sw_set_learning_enable,
967 .get = rtl8366rb_sw_get_learning_enable,
968 .max = 1
969 }, {
970 .type = SWITCH_TYPE_INT,
971 .name = "enable_vlan",
972 .description = "Enable VLAN mode",
973 .set = rtl8366_sw_set_vlan_enable,
974 .get = rtl8366_sw_get_vlan_enable,
975 .max = 1,
976 .ofs = 1
977 }, {
978 .type = SWITCH_TYPE_INT,
979 .name = "enable_vlan4k",
980 .description = "Enable VLAN 4K mode",
981 .set = rtl8366_sw_set_vlan_enable,
982 .get = rtl8366_sw_get_vlan_enable,
983 .max = 1,
984 .ofs = 2
985 }, {
986 .type = SWITCH_TYPE_NOVAL,
987 .name = "reset_mibs",
988 .description = "Reset all MIB counters",
989 .set = rtl8366rb_sw_reset_mibs,
990 }, {
991 .type = SWITCH_TYPE_INT,
992 .name = "blinkrate",
993 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
994 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
995 .set = rtl8366rb_sw_set_blinkrate,
996 .get = rtl8366rb_sw_get_blinkrate,
997 .max = 5
998 }, {
999 .type = SWITCH_TYPE_INT,
1000 .name = "enable_qos",
1001 .description = "Enable QOS",
1002 .set = rtl8366rb_sw_set_qos_enable,
1003 .get = rtl8366rb_sw_get_qos_enable,
1004 .max = 1
1005 },
1006 };
1007
1008 static struct switch_attr rtl8366rb_port[] = {
1009 {
1010 .type = SWITCH_TYPE_STRING,
1011 .name = "link",
1012 .description = "Get port link information",
1013 .max = 1,
1014 .set = NULL,
1015 .get = rtl8366rb_sw_get_port_link,
1016 }, {
1017 .type = SWITCH_TYPE_NOVAL,
1018 .name = "reset_mib",
1019 .description = "Reset single port MIB counters",
1020 .set = rtl8366rb_sw_reset_port_mibs,
1021 }, {
1022 .type = SWITCH_TYPE_STRING,
1023 .name = "mib",
1024 .description = "Get MIB counters for port",
1025 .max = 33,
1026 .set = NULL,
1027 .get = rtl8366_sw_get_port_mib,
1028 }, {
1029 .type = SWITCH_TYPE_INT,
1030 .name = "led",
1031 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1032 .max = 15,
1033 .set = rtl8366rb_sw_set_port_led,
1034 .get = rtl8366rb_sw_get_port_led,
1035 }, {
1036 .type = SWITCH_TYPE_INT,
1037 .name = "disable",
1038 .description = "Get/Set port state (enabled or disabled)",
1039 .max = 1,
1040 .set = rtl8366rb_sw_set_port_disable,
1041 .get = rtl8366rb_sw_get_port_disable,
1042 }, {
1043 .type = SWITCH_TYPE_INT,
1044 .name = "rate_in",
1045 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1046 .max = RTL8366RB_BDTH_SW_MAX,
1047 .set = rtl8366rb_sw_set_port_rate_in,
1048 .get = rtl8366rb_sw_get_port_rate_in,
1049 }, {
1050 .type = SWITCH_TYPE_INT,
1051 .name = "rate_out",
1052 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1053 .max = RTL8366RB_BDTH_SW_MAX,
1054 .set = rtl8366rb_sw_set_port_rate_out,
1055 .get = rtl8366rb_sw_get_port_rate_out,
1056 },
1057 };
1058
1059 static struct switch_attr rtl8366rb_vlan[] = {
1060 {
1061 .type = SWITCH_TYPE_STRING,
1062 .name = "info",
1063 .description = "Get vlan information",
1064 .max = 1,
1065 .set = NULL,
1066 .get = rtl8366_sw_get_vlan_info,
1067 },
1068 };
1069
1070 static const struct switch_dev_ops rtl8366_ops = {
1071 .attr_global = {
1072 .attr = rtl8366rb_globals,
1073 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1074 },
1075 .attr_port = {
1076 .attr = rtl8366rb_port,
1077 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1078 },
1079 .attr_vlan = {
1080 .attr = rtl8366rb_vlan,
1081 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1082 },
1083
1084 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1085 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1086 .get_port_pvid = rtl8366_sw_get_port_pvid,
1087 .set_port_pvid = rtl8366_sw_set_port_pvid,
1088 .reset_switch = rtl8366rb_sw_reset_switch,
1089 };
1090
1091 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1092 {
1093 struct switch_dev *dev = &smi->sw_dev;
1094 int err;
1095
1096 dev->name = "RTL8366RB";
1097 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1098 dev->ports = RTL8366RB_NUM_PORTS;
1099 dev->vlans = RTL8366RB_NUM_VIDS;
1100 dev->ops = &rtl8366_ops;
1101 dev->devname = dev_name(smi->parent);
1102
1103 err = register_switch(dev, NULL);
1104 if (err)
1105 dev_err(smi->parent, "switch registration failed\n");
1106
1107 return err;
1108 }
1109
1110 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1111 {
1112 unregister_switch(&smi->sw_dev);
1113 }
1114
1115 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1116 {
1117 struct rtl8366_smi *smi = bus->priv;
1118 u32 val = 0;
1119 int err;
1120
1121 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1122 if (err)
1123 return 0xffff;
1124
1125 return val;
1126 }
1127
1128 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1129 {
1130 struct rtl8366_smi *smi = bus->priv;
1131 u32 t;
1132 int err;
1133
1134 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1135 /* flush write */
1136 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1137
1138 return err;
1139 }
1140
1141 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1142 {
1143 return (bus->read == rtl8366rb_mii_read &&
1144 bus->write == rtl8366rb_mii_write);
1145 }
1146
1147 static int rtl8366rb_setup(struct rtl8366_smi *smi)
1148 {
1149 int ret;
1150
1151 ret = rtl8366rb_reset_chip(smi);
1152 if (ret)
1153 return ret;
1154
1155 ret = rtl8366rb_hw_init(smi);
1156 return ret;
1157 }
1158
1159 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1160 {
1161 u32 chip_id = 0;
1162 u32 chip_ver = 0;
1163 int ret;
1164
1165 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1166 if (ret) {
1167 dev_err(smi->parent, "unable to read chip id\n");
1168 return ret;
1169 }
1170
1171 switch (chip_id) {
1172 case RTL8366RB_CHIP_ID_8366:
1173 break;
1174 default:
1175 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1176 return -ENODEV;
1177 }
1178
1179 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1180 &chip_ver);
1181 if (ret) {
1182 dev_err(smi->parent, "unable to read chip version\n");
1183 return ret;
1184 }
1185
1186 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1187 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1188
1189 return 0;
1190 }
1191
1192 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1193 .detect = rtl8366rb_detect,
1194 .setup = rtl8366rb_setup,
1195
1196 .mii_read = rtl8366rb_mii_read,
1197 .mii_write = rtl8366rb_mii_write,
1198
1199 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1200 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1201 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1202 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1203 .get_mc_index = rtl8366rb_get_mc_index,
1204 .set_mc_index = rtl8366rb_set_mc_index,
1205 .get_mib_counter = rtl8366rb_get_mib_counter,
1206 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1207 .enable_vlan = rtl8366rb_enable_vlan,
1208 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1209 };
1210
1211 static int __init rtl8366rb_probe(struct platform_device *pdev)
1212 {
1213 static int rtl8366_smi_version_printed;
1214 struct rtl8366rb_platform_data *pdata;
1215 struct rtl8366_smi *smi;
1216 int err;
1217
1218 if (!rtl8366_smi_version_printed++)
1219 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1220 " version " RTL8366RB_DRIVER_VER"\n");
1221
1222 pdata = pdev->dev.platform_data;
1223 if (!pdata) {
1224 dev_err(&pdev->dev, "no platform data specified\n");
1225 err = -EINVAL;
1226 goto err_out;
1227 }
1228
1229 smi = rtl8366_smi_alloc(&pdev->dev);
1230 if (!smi) {
1231 err = -ENOMEM;
1232 goto err_out;
1233 }
1234
1235 smi->gpio_sda = pdata->gpio_sda;
1236 smi->gpio_sck = pdata->gpio_sck;
1237 smi->ops = &rtl8366rb_smi_ops;
1238 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1239 smi->num_ports = RTL8366RB_NUM_PORTS;
1240 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1241 smi->mib_counters = rtl8366rb_mib_counters;
1242 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1243
1244 err = rtl8366_smi_init(smi);
1245 if (err)
1246 goto err_free_smi;
1247
1248 platform_set_drvdata(pdev, smi);
1249
1250 err = rtl8366rb_switch_init(smi);
1251 if (err)
1252 goto err_clear_drvdata;
1253
1254 return 0;
1255
1256 err_clear_drvdata:
1257 platform_set_drvdata(pdev, NULL);
1258 rtl8366_smi_cleanup(smi);
1259 err_free_smi:
1260 kfree(smi);
1261 err_out:
1262 return err;
1263 }
1264
1265 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1266 {
1267 if (!rtl8366rb_mii_bus_match(phydev->bus))
1268 return -EINVAL;
1269
1270 return 0;
1271 }
1272
1273 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1274 {
1275 return 0;
1276 }
1277
1278 static struct phy_driver rtl8366rb_phy_driver = {
1279 .phy_id = 0x001cc960,
1280 .name = "Realtek RTL8366RB",
1281 .phy_id_mask = 0x1ffffff0,
1282 .features = PHY_GBIT_FEATURES,
1283 .config_aneg = rtl8366rb_phy_config_aneg,
1284 .config_init = rtl8366rb_phy_config_init,
1285 .read_status = genphy_read_status,
1286 .driver = {
1287 .owner = THIS_MODULE,
1288 },
1289 };
1290
1291 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1292 {
1293 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1294
1295 if (smi) {
1296 rtl8366rb_switch_cleanup(smi);
1297 platform_set_drvdata(pdev, NULL);
1298 rtl8366_smi_cleanup(smi);
1299 kfree(smi);
1300 }
1301
1302 return 0;
1303 }
1304
1305 static struct platform_driver rtl8366rb_driver = {
1306 .driver = {
1307 .name = RTL8366RB_DRIVER_NAME,
1308 .owner = THIS_MODULE,
1309 },
1310 .probe = rtl8366rb_probe,
1311 .remove = __devexit_p(rtl8366rb_remove),
1312 };
1313
1314 static int __init rtl8366rb_module_init(void)
1315 {
1316 int ret;
1317 ret = platform_driver_register(&rtl8366rb_driver);
1318 if (ret)
1319 return ret;
1320
1321 ret = phy_driver_register(&rtl8366rb_phy_driver);
1322 if (ret)
1323 goto err_platform_unregister;
1324
1325 return 0;
1326
1327 err_platform_unregister:
1328 platform_driver_unregister(&rtl8366rb_driver);
1329 return ret;
1330 }
1331 module_init(rtl8366rb_module_init);
1332
1333 static void __exit rtl8366rb_module_exit(void)
1334 {
1335 phy_driver_unregister(&rtl8366rb_phy_driver);
1336 platform_driver_unregister(&rtl8366rb_driver);
1337 }
1338 module_exit(rtl8366rb_module_exit);
1339
1340 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1341 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1342 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1343 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1344 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1345 MODULE_LICENSE("GPL v2");
1346 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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