target/linux/xburst/patches-2.6.35/005-timer.patch

   1 From ad817ad0a57d0fa6041071395d4cf0d2e9a44635 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 19 Jun 2010 04:08:09 +0000
   4 Subject: [PATCH] MIPS: JZ4740: Add timer support
   5
   6 Add support for the timer/counter unit on a JZ4740 SoC.  This code is used
   7 as a common base for the JZ4740 clocksource/clockevent implementation and
   8 PWM support.
   9
  10 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
  11 Cc: linux-mips@linux-mips.org
  12 Cc: linux-kernel@vger.kernel.org
  13 Patchwork: https://patchwork.linux-mips.org/patch/1396/
  14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  15 ---
  16  arch/mips/include/asm/mach-jz4740/timer.h |   22 +++++
  17  arch/mips/jz4740/timer.c                  |   48 ++++++++++
  18  arch/mips/jz4740/timer.h                  |  136 +++++++++++++++++++++++++++++
  19  3 files changed, 206 insertions(+), 0 deletions(-)
  20  create mode 100644 arch/mips/include/asm/mach-jz4740/timer.h
  21  create mode 100644 arch/mips/jz4740/timer.c
  22  create mode 100644 arch/mips/jz4740/timer.h
  23
  24 --- /dev/null
  25 +++ b/arch/mips/include/asm/mach-jz4740/timer.h
  26 @@ -0,0 +1,22 @@
  27 +/*
  28 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  29 + *  JZ4740 platform timer support
  30 + *
  31 + *  This program is free software; you can redistribute it and/or modify it
  32 + *  under  the terms of the GNU General  Public License as published by the
  33 + *  Free Software Foundation;  either version 2 of the License, or (at your
  34 + *  option) any later version.
  35 + *
  36 + *  You should have received a copy of the GNU General Public License along
  37 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  38 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  39 + *
  40 + */
  41 +
  42 +#ifndef __ASM_MACH_JZ4740_TIMER
  43 +#define __ASM_MACH_JZ4740_TIMER
  44 +
  45 +void jz4740_timer_enable_watchdog(void);
  46 +void jz4740_timer_disable_watchdog(void);
  47 +
  48 +#endif
  49 --- /dev/null
  50 +++ b/arch/mips/jz4740/timer.c
  51 @@ -0,0 +1,48 @@
  52 +/*
  53 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  54 + *  JZ4740 platform timer support
  55 + *
  56 + *  This program is free software; you can redistribute it and/or modify it
  57 + *  under  the terms of the GNU General  Public License as published by the
  58 + *  Free Software Foundation;  either version 2 of the License, or (at your
  59 + *  option) any later version.
  60 + *
  61 + *  You should have received a copy of the GNU General Public License along
  62 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  63 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  64 + *
  65 + */
  66 +
  67 +#include <linux/io.h>
  68 +#include <linux/kernel.h>
  69 +#include <linux/module.h>
  70 +
  71 +#include "timer.h"
  72 +
  73 +#include <asm/mach-jz4740/base.h>
  74 +
  75 +void __iomem *jz4740_timer_base;
  76 +
  77 +void jz4740_timer_enable_watchdog(void)
  78 +{
  79 +       writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
  80 +}
  81 +
  82 +void jz4740_timer_disable_watchdog(void)
  83 +{
  84 +       writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
  85 +}
  86 +
  87 +void __init jz4740_timer_init(void)
  88 +{
  89 +       jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
  90 +
  91 +       if (!jz4740_timer_base)
  92 +               panic("Failed to ioremap timer registers");
  93 +
  94 +       /* Disable all timer clocks except for those used as system timers */
  95 +       writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
  96 +
  97 +       /* Timer irqs are unmasked by default, mask them */
  98 +       writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
  99 +}
 100 --- /dev/null
 101 +++ b/arch/mips/jz4740/timer.h
 102 @@ -0,0 +1,136 @@
 103 +/*
 104 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 105 + *  JZ4740 platform timer support
 106 + *
 107 + *  This program is free software; you can redistribute it and/or modify it
 108 + *  under  the terms of the GNU General  Public License as published by the
 109 + *  Free Software Foundation;  either version 2 of the License, or (at your
 110 + *  option) any later version.
 111 + *
 112 + *  You should have received a copy of the GNU General Public License along
 113 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 114 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 115 + *
 116 + */
 117 +
 118 +#ifndef __MIPS_JZ4740_TIMER_H__
 119 +#define __MIPS_JZ4740_TIMER_H__
 120 +
 121 +#include <linux/module.h>
 122 +#include <linux/io.h>
 123 +
 124 +#define JZ_REG_TIMER_STOP              0x0C
 125 +#define JZ_REG_TIMER_STOP_SET          0x1C
 126 +#define JZ_REG_TIMER_STOP_CLEAR                0x2C
 127 +#define JZ_REG_TIMER_ENABLE            0x00
 128 +#define JZ_REG_TIMER_ENABLE_SET                0x04
 129 +#define JZ_REG_TIMER_ENABLE_CLEAR      0x08
 130 +#define JZ_REG_TIMER_FLAG              0x10
 131 +#define JZ_REG_TIMER_FLAG_SET          0x14
 132 +#define JZ_REG_TIMER_FLAG_CLEAR                0x18
 133 +#define JZ_REG_TIMER_MASK              0x20
 134 +#define JZ_REG_TIMER_MASK_SET          0x24
 135 +#define JZ_REG_TIMER_MASK_CLEAR                0x28
 136 +
 137 +#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
 138 +#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
 139 +#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
 140 +#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
 141 +
 142 +#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
 143 +#define JZ_TIMER_IRQ_FULL(x) BIT(x)
 144 +
 145 +#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN     BIT(9)
 146 +#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW           BIT(8)
 147 +#define JZ_TIMER_CTRL_PWM_ENABLE               BIT(7)
 148 +#define JZ_TIMER_CTRL_PRESCALE_MASK            0x1c
 149 +#define JZ_TIMER_CTRL_PRESCALE_OFFSET          0x3
 150 +#define JZ_TIMER_CTRL_PRESCALE_1               (0 << 3)
 151 +#define JZ_TIMER_CTRL_PRESCALE_4               (1 << 3)
 152 +#define JZ_TIMER_CTRL_PRESCALE_16              (2 << 3)
 153 +#define JZ_TIMER_CTRL_PRESCALE_64              (3 << 3)
 154 +#define JZ_TIMER_CTRL_PRESCALE_256             (4 << 3)
 155 +#define JZ_TIMER_CTRL_PRESCALE_1024            (5 << 3)
 156 +
 157 +#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
 158 +
 159 +#define JZ_TIMER_CTRL_SRC_EXT          BIT(2)
 160 +#define JZ_TIMER_CTRL_SRC_RTC          BIT(1)
 161 +#define JZ_TIMER_CTRL_SRC_PCLK         BIT(0)
 162 +
 163 +extern void __iomem *jz4740_timer_base;
 164 +void __init jz4740_timer_init(void);
 165 +
 166 +static inline void jz4740_timer_stop(unsigned int timer)
 167 +{
 168 +       writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
 169 +}
 170 +
 171 +static inline void jz4740_timer_start(unsigned int timer)
 172 +{
 173 +       writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
 174 +}
 175 +
 176 +static inline bool jz4740_timer_is_enabled(unsigned int timer)
 177 +{
 178 +       return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
 179 +}
 180 +
 181 +static inline void jz4740_timer_enable(unsigned int timer)
 182 +{
 183 +       writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
 184 +}
 185 +
 186 +static inline void jz4740_timer_disable(unsigned int timer)
 187 +{
 188 +       writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
 189 +}
 190 +
 191 +
 192 +static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
 193 +{
 194 +       writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
 195 +}
 196 +
 197 +static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
 198 +{
 199 +       writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
 200 +}
 201 +
 202 +static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
 203 +{
 204 +       writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
 205 +}
 206 +
 207 +static inline uint16_t jz4740_timer_get_count(unsigned int timer)
 208 +{
 209 +       return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
 210 +}
 211 +
 212 +static inline void jz4740_timer_ack_full(unsigned int timer)
 213 +{
 214 +       writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
 215 +}
 216 +
 217 +static inline void jz4740_timer_irq_full_enable(unsigned int timer)
 218 +{
 219 +       writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
 220 +       writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
 221 +}
 222 +
 223 +static inline void jz4740_timer_irq_full_disable(unsigned int timer)
 224 +{
 225 +       writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
 226 +}
 227 +
 228 +static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
 229 +{
 230 +       writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
 231 +}
 232 +
 233 +static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
 234 +{
 235 +       return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
 236 +}
 237 +
 238 +#endif