projects / openwrt.git / blob
? search:


833e455dd00588c2cc275b733b3c13faac476d43
[openwrt.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/phy.h>
20 #include <linux/rtl8366s.h>
21
22 #include "rtl8366_smi.h"
23
24 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
25 #include <linux/debugfs.h>
26 #endif
27
28 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
29 #define RTL8366S_DRIVER_VER "0.2.0"
30
31 #define RTL8366S_PHY_NO_MAX 4
32 #define RTL8366S_PHY_PAGE_MAX 7
33 #define RTL8366S_PHY_ADDR_MAX 31
34
35 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
36 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
37
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
41
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0105
45 #define RTL8366S_CHIP_ID_8366 0x8366
46
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
50
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
53
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
59
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0420
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
64
65 #define RTL8366_LED_CTRL_REG 0x0421
66 #define RTL8366_LED_0_1_CTRL_REG 0x0422
67 #define RTL8366_LED_2_3_CTRL_REG 0x0423
68
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x11F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
77
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
81
82
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
88
89
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s {
150 struct device *parent;
151 struct rtl8366_smi smi;
152 struct mii_bus *mii_bus;
153 int mii_irq[PHY_MAX_ADDR];
154 struct switch_dev dev;
155 char buf[4096];
156 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
157 struct dentry *debugfs_root;
158 #endif
159 };
160
161 struct rtl8366s_vlanconfig {
162 u16 reserved2:1;
163 u16 priority:3;
164 u16 vid:12;
165
166 u16 reserved1:1;
167 u16 fid:3;
168 u16 untag:6;
169 u16 member:6;
170 };
171
172 struct rtl8366s_vlan4kentry {
173 u16 reserved1:4;
174 u16 vid:12;
175
176 u16 reserved2:1;
177 u16 fid:3;
178 u16 untag:6;
179 u16 member:6;
180 };
181
182 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
183 u16 g_dbg_reg;
184 #endif
185
186 struct mib_counter {
187 unsigned offset;
188 unsigned length;
189 const char *name;
190 };
191
192 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
193 { 0, 4, "IfInOctets " },
194 { 4, 4, "EtherStatsOctets " },
195 { 8, 2, "EtherStatsUnderSizePkts " },
196 { 10, 2, "EtherFregament " },
197 { 12, 2, "EtherStatsPkts64Octets " },
198 { 14, 2, "EtherStatsPkts65to127Octets " },
199 { 16, 2, "EtherStatsPkts128to255Octets " },
200 { 18, 2, "EtherStatsPkts256to511Octets " },
201 { 20, 2, "EtherStatsPkts512to1023Octets " },
202 { 22, 2, "EtherStatsPkts1024to1518Octets " },
203 { 24, 2, "EtherOversizeStats " },
204 { 26, 2, "EtherStatsJabbers " },
205 { 28, 2, "IfInUcastPkts " },
206 { 30, 2, "EtherStatsMulticastPkts " },
207 { 32, 2, "EtherStatsBroadcastPkts " },
208 { 34, 2, "EtherStatsDropEvents " },
209 { 36, 2, "Dot3StatsFCSErrors " },
210 { 38, 2, "Dot3StatsSymbolErrors " },
211 { 40, 2, "Dot3InPauseFrames " },
212 { 42, 2, "Dot3ControlInUnknownOpcodes " },
213 { 44, 2, "IfOutOctets " },
214 { 46, 2, "Dot3StatsSingleCollisionFrames " },
215 { 48, 2, "Dot3StatMultipleCollisionFrames " },
216 { 50, 2, "Dot3sDeferredTransmissions " },
217 { 52, 2, "Dot3StatsLateCollisions " },
218 { 54, 2, "EtherStatsCollisions " },
219 { 56, 2, "Dot3StatsExcessiveCollisions " },
220 { 58, 2, "Dot3OutPauseFrames " },
221 { 60, 2, "Dot1dBasePortDelayExceededDiscards" },
222 { 62, 2, "Dot1dTpPortInDiscards " },
223 { 64, 2, "IfOutUcastPkts " },
224 { 66, 2, "IfOutMulticastPkts " },
225 { 68, 2, "IfOutBroadcastPkts " },
226 };
227
228 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
229 {
230 return container_of(sw, struct rtl8366s, dev);
231 }
232
233 static int rtl8366s_read_phy_reg(struct rtl8366s *rtl,
234 u32 phy_no, u32 page, u32 addr, u32 *data)
235 {
236 struct rtl8366_smi *smi = &rtl->smi;
237 u32 reg;
238 int ret;
239
240 if (phy_no > RTL8366S_PHY_NO_MAX)
241 return -EINVAL;
242
243 if (page > RTL8366S_PHY_PAGE_MAX)
244 return -EINVAL;
245
246 if (addr > RTL8366S_PHY_ADDR_MAX)
247 return -EINVAL;
248
249 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
250 RTL8366S_PHY_CTRL_READ);
251 if (ret)
252 return ret;
253
254 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
255 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
256 (addr & RTL8366S_PHY_REG_MASK);
257
258 ret = rtl8366_smi_write_reg(smi, reg, 0);
259 if (ret)
260 return ret;
261
262 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
263 if (ret)
264 return ret;
265
266 return 0;
267 }
268
269 static int rtl8366s_write_phy_reg(struct rtl8366s *rtl,
270 u32 phy_no, u32 page, u32 addr, u32 data)
271 {
272 struct rtl8366_smi *smi = &rtl->smi;
273 u32 reg;
274 int ret;
275
276 if (phy_no > RTL8366S_PHY_NO_MAX)
277 return -EINVAL;
278
279 if (page > RTL8366S_PHY_PAGE_MAX)
280 return -EINVAL;
281
282 if (addr > RTL8366S_PHY_ADDR_MAX)
283 return -EINVAL;
284
285 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
286 RTL8366S_PHY_CTRL_WRITE);
287 if (ret)
288 return ret;
289
290 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
291 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
292 (addr & RTL8366S_PHY_REG_MASK);
293
294 ret = rtl8366_smi_write_reg(smi, reg, data);
295 if (ret)
296 return ret;
297
298 return 0;
299 }
300
301 static int rtl8366_get_mib_counter(struct rtl8366s *rtl, int counter,
302 int port, unsigned long long *val)
303 {
304 struct rtl8366_smi *smi = &rtl->smi;
305 int i;
306 int err;
307 u32 addr, data;
308 u64 mibvalue;
309
310 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
311 return -EINVAL;
312
313 addr = RTL8366S_MIB_COUNTER_BASE +
314 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
315 rtl8366s_mib_counters[counter].offset;
316
317 /*
318 * Writing access counter address first
319 * then ASIC will prepare 64bits counter wait for being retrived
320 */
321 data = 0; /* writing data will be discard by ASIC */
322 err = rtl8366_smi_write_reg(smi, addr, data);
323 if (err)
324 return err;
325
326 /* read MIB control register */
327 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
328 if (err)
329 return err;
330
331 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
332 return -EBUSY;
333
334 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
335 return -EIO;
336
337 mibvalue = 0;
338 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
339 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
340 if (err)
341 return err;
342
343 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
344 }
345
346 *val = mibvalue;
347 return 0;
348 }
349
350 static int rtl8366s_get_vlan_4k_entry(struct rtl8366s *rtl, u32 vid,
351 struct rtl8366s_vlan4kentry *vlan4k)
352 {
353 struct rtl8366_smi *smi = &rtl->smi;
354 int err;
355 u32 data;
356 u16 *tableaddr;
357
358 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
359 vlan4k->vid = vid;
360
361 if (vid >= RTL8366_NUM_VIDS)
362 return -EINVAL;
363
364 tableaddr = (u16 *)vlan4k;
365
366 /* write VID */
367 data = *tableaddr;
368 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
369 if (err)
370 return err;
371
372 /* write table access control word */
373 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
374 RTL8366S_TABLE_VLAN_READ_CTRL);
375 if (err)
376 return err;
377
378 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
379 if (err)
380 return err;
381
382 *tableaddr = data;
383 tableaddr++;
384
385 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
386 &data);
387 if (err)
388 return err;
389
390 *tableaddr = data;
391 vlan4k->vid = vid;
392
393 return 0;
394 }
395
396 static int rtl8366s_set_vlan_4k_entry(struct rtl8366s *rtl,
397 const struct rtl8366s_vlan4kentry *vlan4k)
398 {
399 struct rtl8366_smi *smi = &rtl->smi;
400 int err;
401 u32 data;
402 u16 *tableaddr;
403
404 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
405 vlan4k->member > RTL8366_PORT_ALL ||
406 vlan4k->untag > RTL8366_PORT_ALL ||
407 vlan4k->fid > RTL8366S_FIDMAX)
408 return -EINVAL;
409
410 tableaddr = (u16 *)vlan4k;
411
412 data = *tableaddr;
413
414 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
415 if (err)
416 return err;
417
418 tableaddr++;
419
420 data = *tableaddr;
421
422 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
423 data);
424 if (err)
425 return err;
426
427 /* write table access control word */
428 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
429 RTL8366S_TABLE_VLAN_WRITE_CTRL);
430
431 return err;
432 }
433
434 static int rtl8366s_get_vlan_member_config(struct rtl8366s *rtl, u32 index,
435 struct rtl8366s_vlanconfig *vlanmc)
436 {
437 struct rtl8366_smi *smi = &rtl->smi;
438 int err;
439 u32 addr;
440 u32 data;
441 u16 *tableaddr;
442
443 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
444
445 if (index >= RTL8366_NUM_VLANS)
446 return -EINVAL;
447
448 tableaddr = (u16 *)vlanmc;
449
450 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
451 err = rtl8366_smi_read_reg(smi, addr, &data);
452 if (err)
453 return err;
454
455 *tableaddr = data;
456 tableaddr++;
457
458 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
459 err = rtl8366_smi_read_reg(smi, addr, &data);
460 if (err)
461 return err;
462
463 *tableaddr = data;
464
465 return 0;
466 }
467
468 static int rtl8366s_set_vlan_member_config(struct rtl8366s *rtl, u32 index,
469 const struct rtl8366s_vlanconfig
470 *vlanmc)
471 {
472 struct rtl8366_smi *smi = &rtl->smi;
473 int err;
474 u32 addr;
475 u32 data;
476 u16 *tableaddr;
477
478 if (index >= RTL8366_NUM_VLANS ||
479 vlanmc->vid >= RTL8366_NUM_VIDS ||
480 vlanmc->priority > RTL8366S_PRIORITYMAX ||
481 vlanmc->member > RTL8366_PORT_ALL ||
482 vlanmc->untag > RTL8366_PORT_ALL ||
483 vlanmc->fid > RTL8366S_FIDMAX)
484 return -EINVAL;
485
486 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
487
488 tableaddr = (u16 *)vlanmc;
489 data = *tableaddr;
490
491 err = rtl8366_smi_write_reg(smi, addr, data);
492 if (err)
493 return err;
494
495 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
496
497 tableaddr++;
498 data = *tableaddr;
499
500 err = rtl8366_smi_write_reg(smi, addr, data);
501 if (err)
502 return err;
503
504 return 0;
505 }
506
507 static int rtl8366s_get_port_vlan_index(struct rtl8366s *rtl, int port,
508 int *val)
509 {
510 struct rtl8366_smi *smi = &rtl->smi;
511 u32 data;
512 int err;
513
514 if (port >= RTL8366_NUM_PORTS)
515 return -EINVAL;
516
517 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
518 &data);
519 if (err)
520 return err;
521
522 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
523 RTL8366S_PORT_VLAN_CTRL_MASK;
524
525 return 0;
526
527 }
528
529 static int rtl8366s_get_vlan_port_pvid(struct rtl8366s *rtl, int port,
530 int *val)
531 {
532 struct rtl8366s_vlanconfig vlanmc;
533 int err;
534 int index;
535
536 err = rtl8366s_get_port_vlan_index(rtl, port, &index);
537 if (err)
538 return err;
539
540 err = rtl8366s_get_vlan_member_config(rtl, index, &vlanmc);
541 if (err)
542 return err;
543
544 *val = vlanmc.vid;
545 return 0;
546 }
547
548 static int rtl8366s_set_port_vlan_index(struct rtl8366s *rtl, int port,
549 int index)
550 {
551 struct rtl8366_smi *smi = &rtl->smi;
552 u32 data;
553 int err;
554
555 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
556 return -EINVAL;
557
558 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
559 &data);
560 if (err)
561 return err;
562
563 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
564 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
565 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
566 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
567
568 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
569 data);
570 return err;
571 }
572
573 static int rtl8366s_set_vlan_port_pvid(struct rtl8366s *rtl, int port, int val)
574 {
575 int i;
576 struct rtl8366s_vlanconfig vlanmc;
577 struct rtl8366s_vlan4kentry vlan4k;
578
579 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
580 return -EINVAL;
581
582 /* Updating the 4K entry; lookup it and change the port member set */
583 rtl8366s_get_vlan_4k_entry(rtl, val, &vlan4k);
584 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
585 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
586 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
587
588 /*
589 * For the 16 entries more work needs to be done. First see if such
590 * VID is already there and change it
591 */
592 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
593 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
594
595 /* Try to find an existing vid and update port member set */
596 if (val == vlanmc.vid) {
597 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
598 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
599
600 /* Now update PVID register settings */
601 rtl8366s_set_port_vlan_index(rtl, port, i);
602
603 return 0;
604 }
605 }
606
607 /*
608 * PVID could not be found from vlan table. Replace unused (one that
609 * has no member ports) with new one
610 */
611 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
612 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
613
614 /*
615 * See if this vlan member configuration is unused. It is
616 * unused if member set contains no ports or CPU port only
617 */
618 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
619 vlanmc.vid = val;
620 vlanmc.priority = 0;
621 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
622 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
623 vlanmc.fid = 0;
624
625 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
626
627 /* Now update PVID register settings */
628 rtl8366s_set_port_vlan_index(rtl, port, i);
629
630 return 0;
631 }
632 }
633
634 dev_err(rtl->parent,
635 "All 16 vlan member configurations are in use\n");
636
637 return -EINVAL;
638 }
639
640
641 static int rtl8366s_vlan_set_vlan(struct rtl8366s *rtl, int enable)
642 {
643 struct rtl8366_smi *smi = &rtl->smi;
644 u32 data = 0;
645
646 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
647
648 if (enable)
649 data |= RTL8366_CHIP_CTRL_VLAN;
650 else
651 data &= ~RTL8366_CHIP_CTRL_VLAN;
652
653 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
654 }
655
656 static int rtl8366s_vlan_set_4ktable(struct rtl8366s *rtl, int enable)
657 {
658 struct rtl8366_smi *smi = &rtl->smi;
659 u32 data = 0;
660
661 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
662
663 if (enable)
664 data |= 1;
665 else
666 data &= ~1;
667
668 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
669 }
670
671 static int rtl8366s_reset_vlan(struct rtl8366s *rtl)
672 {
673 struct rtl8366s_vlan4kentry vlan4k;
674 struct rtl8366s_vlanconfig vlanmc;
675 int err;
676 int i;
677
678 /* clear 16 VLAN member configuration */
679 vlanmc.vid = 0;
680 vlanmc.priority = 0;
681 vlanmc.member = 0;
682 vlanmc.untag = 0;
683 vlanmc.fid = 0;
684 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
685 err = rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
686 if (err)
687 return err;
688 }
689
690 /* Set a default VLAN with vid 1 to 4K table for all ports */
691 vlan4k.vid = 1;
692 vlan4k.member = RTL8366_PORT_ALL;
693 vlan4k.untag = RTL8366_PORT_ALL;
694 vlan4k.fid = 0;
695 err = rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
696 if (err)
697 return err;
698
699 /* Set all ports PVID to default VLAN */
700 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
701 err = rtl8366s_set_vlan_port_pvid(rtl, i, 0);
702 if (err)
703 return err;
704 }
705
706 return 0;
707 }
708
709 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
710 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
711 {
712 file->private_data = inode->i_private;
713 return 0;
714 }
715
716 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
717 char __user *user_buf,
718 size_t count, loff_t *ppos)
719 {
720 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
721 int i, j, len = 0;
722 char *buf = rtl->buf;
723
724 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
725 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
726 " "
727 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
728 "Port 4\n");
729
730 for (i = 0; i < 33; ++i) {
731 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
732 i, rtl8366s_mib_counters[i].name);
733 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
734 unsigned long long counter = 0;
735
736 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
737 len += snprintf(buf + len,
738 sizeof(rtl->buf) - len,
739 "[%llu]", counter);
740 else
741 len += snprintf(buf + len,
742 sizeof(rtl->buf) - len,
743 "[error]");
744
745 if (j != RTL8366_NUM_PORTS - 1) {
746 if (counter < 100000)
747 len += snprintf(buf + len,
748 sizeof(rtl->buf) - len,
749 "\t");
750
751 len += snprintf(buf + len,
752 sizeof(rtl->buf) - len,
753 "\t");
754 }
755 }
756 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
757 }
758
759 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
760
761 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
762 }
763
764 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
765 char __user *user_buf,
766 size_t count, loff_t *ppos)
767 {
768 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
769 int i, j, len = 0;
770 char *buf = rtl->buf;
771
772 len += snprintf(buf + len, sizeof(rtl->buf) - len,
773 "VLAN Member Config:\n");
774 len += snprintf(buf + len, sizeof(rtl->buf) - len,
775 "\t id \t vid \t prio \t member \t untag \t fid "
776 "\tports\n");
777
778 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
779 struct rtl8366s_vlanconfig vlanmc;
780
781 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
782
783 len += snprintf(buf + len, sizeof(rtl->buf) - len,
784 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
785 "\t", i, vlanmc.vid, vlanmc.priority,
786 vlanmc.member, vlanmc.untag, vlanmc.fid);
787
788 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
789 int index = 0;
790 if (!rtl8366s_get_port_vlan_index(rtl, j, &index)) {
791 if (index == i)
792 len += snprintf(buf + len,
793 sizeof(rtl->buf) - len,
794 "%d", j);
795 }
796 }
797 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
798 }
799
800 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
801 }
802
803 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
804 char __user *user_buf,
805 size_t count, loff_t *ppos)
806 {
807 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
808 struct rtl8366_smi *smi = &rtl->smi;
809 u32 t, reg = g_dbg_reg;
810 int err, len = 0;
811 char *buf = rtl->buf;
812
813 memset(buf, '\0', sizeof(rtl->buf));
814
815 err = rtl8366_smi_read_reg(smi, reg, &t);
816 if (err) {
817 len += snprintf(buf, sizeof(rtl->buf),
818 "Read failed (reg: 0x%04x)\n", reg);
819 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
820 }
821
822 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
823 reg, t);
824
825 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
826 }
827
828 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
829 const char __user *user_buf,
830 size_t count, loff_t *ppos)
831 {
832 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
833 struct rtl8366_smi *smi = &rtl->smi;
834 unsigned long data;
835 u32 reg = g_dbg_reg;
836 int err;
837 size_t len;
838 char *buf = rtl->buf;
839
840 len = min(count, sizeof(rtl->buf) - 1);
841 if (copy_from_user(buf, user_buf, len)) {
842 dev_err(rtl->parent, "copy from user failed\n");
843 return -EFAULT;
844 }
845
846 buf[len] = '\0';
847 if (len > 0 && buf[len - 1] == '\n')
848 buf[len - 1] = '\0';
849
850
851 if (strict_strtoul(buf, 16, &data)) {
852 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
853 } else {
854 err = rtl8366_smi_write_reg(smi, reg, data);
855 if (err) {
856 dev_err(rtl->parent,
857 "writing reg 0x%04x val 0x%04lx failed\n",
858 reg, data);
859 }
860 }
861
862 return count;
863 }
864
865 static const struct file_operations fops_rtl8366s_regs = {
866 .read = rtl8366s_read_debugfs_reg,
867 .write = rtl8366s_write_debugfs_reg,
868 .open = rtl8366s_debugfs_open,
869 .owner = THIS_MODULE
870 };
871
872 static const struct file_operations fops_rtl8366s_vlan = {
873 .read = rtl8366s_read_debugfs_vlan,
874 .open = rtl8366s_debugfs_open,
875 .owner = THIS_MODULE
876 };
877
878 static const struct file_operations fops_rtl8366s_mibs = {
879 .read = rtl8366s_read_debugfs_mibs,
880 .open = rtl8366s_debugfs_open,
881 .owner = THIS_MODULE
882 };
883
884 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
885 {
886 struct dentry *node;
887 struct dentry *root;
888
889 if (!rtl->debugfs_root)
890 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
891
892 if (!rtl->debugfs_root) {
893 dev_err(rtl->parent, "Unable to create debugfs dir\n");
894 return;
895 }
896 root = rtl->debugfs_root;
897
898 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
899 if (!node) {
900 dev_err(rtl->parent, "Creating debugfs file reg failed\n");
901 return;
902 }
903
904 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
905 &fops_rtl8366s_regs);
906 if (!node) {
907 dev_err(rtl->parent, "Creating debugfs file val failed\n");
908 return;
909 }
910
911 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
912 &fops_rtl8366s_vlan);
913 if (!node) {
914 dev_err(rtl->parent,
915 "Creating debugfs file vlan failed\n");
916 return;
917 }
918
919 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
920 &fops_rtl8366s_mibs);
921 if (!node) {
922 dev_err(rtl->parent,
923 "Creating debugfs file mibs failed\n");
924 return;
925 }
926 }
927
928 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
929 {
930 if (rtl->debugfs_root) {
931 debugfs_remove_recursive(rtl->debugfs_root);
932 rtl->debugfs_root = NULL;
933 }
934 }
935
936 #else
937 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
938 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
939 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
940
941 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
942 const struct switch_attr *attr,
943 struct switch_val *val)
944 {
945 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
946 struct rtl8366_smi *smi = &rtl->smi;
947 u32 data = 0;
948
949 if (val->value.i == 1) {
950 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
951 data |= (1 << 2);
952 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
953 }
954
955 return 0;
956 }
957
958 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
959 const struct switch_attr *attr,
960 struct switch_val *val)
961 {
962 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
963 struct rtl8366_smi *smi = &rtl->smi;
964 u32 data;
965
966 if (attr->ofs == 1) {
967 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
968
969 if (data & RTL8366_CHIP_CTRL_VLAN)
970 val->value.i = 1;
971 else
972 val->value.i = 0;
973 } else if (attr->ofs == 2) {
974 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
975
976 if (data & 0x0001)
977 val->value.i = 1;
978 else
979 val->value.i = 0;
980 }
981
982 return 0;
983 }
984
985 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
986 const struct switch_attr *attr,
987 struct switch_val *val)
988 {
989 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
990 struct rtl8366_smi *smi = &rtl->smi;
991 u32 data;
992
993 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
994
995 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
996
997 return 0;
998 }
999
1000 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1001 const struct switch_attr *attr,
1002 struct switch_val *val)
1003 {
1004 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1005 struct rtl8366_smi *smi = &rtl->smi;
1006 u32 data;
1007
1008 if (val->value.i >= 6)
1009 return -EINVAL;
1010
1011 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1012
1013 data &= ~RTL8366_LED_BLINKRATE_MASK;
1014 data |= val->value.i;
1015
1016 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1017
1018 return 0;
1019 }
1020
1021 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1022 const struct switch_attr *attr,
1023 struct switch_val *val)
1024 {
1025 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1026
1027 if (attr->ofs == 1)
1028 return rtl8366s_vlan_set_vlan(rtl, val->value.i);
1029 else
1030 return rtl8366s_vlan_set_4ktable(rtl, val->value.i);
1031 }
1032
1033 static const char *rtl8366s_speed_str(unsigned speed)
1034 {
1035 switch (speed) {
1036 case 0:
1037 return "10baseT";
1038 case 1:
1039 return "100baseT";
1040 case 2:
1041 return "1000baseT";
1042 }
1043
1044 return "unknown";
1045 }
1046
1047 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1048 const struct switch_attr *attr,
1049 struct switch_val *val)
1050 {
1051 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1052 struct rtl8366_smi *smi = &rtl->smi;
1053 u32 len = 0, data = 0;
1054
1055 if (val->port_vlan >= RTL8366_NUM_PORTS)
1056 return -EINVAL;
1057
1058 memset(rtl->buf, '\0', sizeof(rtl->buf));
1059 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1060 (val->port_vlan / 2), &data);
1061
1062 if (val->port_vlan % 2)
1063 data = data >> 8;
1064
1065 len = snprintf(rtl->buf, sizeof(rtl->buf),
1066 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1067 val->port_vlan,
1068 (data & RTL8366S_PORT_STATUS_LINK_MASK) ? "up" : "down",
1069 rtl8366s_speed_str(data &
1070 RTL8366S_PORT_STATUS_SPEED_MASK),
1071 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1072 "full" : "half",
1073 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1074 "tx-pause ": "",
1075 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1076 "rx-pause " : "",
1077 (data & RTL8366S_PORT_STATUS_AN_MASK) ? "nway ": "");
1078
1079 val->value.s = rtl->buf;
1080 val->len = len;
1081
1082 return 0;
1083 }
1084
1085 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1086 const struct switch_attr *attr,
1087 struct switch_val *val)
1088 {
1089 int i;
1090 u32 len = 0;
1091 struct rtl8366s_vlanconfig vlanmc;
1092 struct rtl8366s_vlan4kentry vlan4k;
1093 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1094 char *buf = rtl->buf;
1095
1096 if (val->port_vlan >= RTL8366_NUM_VLANS)
1097 return -EINVAL;
1098
1099 memset(buf, '\0', sizeof(rtl->buf));
1100
1101 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1102 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1103
1104 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1105 val->port_vlan);
1106
1107 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1108 int index = 0;
1109 if (!rtl8366s_get_port_vlan_index(rtl, i, &index) &&
1110 index == val->port_vlan)
1111 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1112 "%d", i);
1113 }
1114 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1115
1116 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1117 "\t\t vid \t prio \t member \t untag \t fid\n");
1118 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1119 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1120 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1121 vlanmc.vid, vlanmc.priority, vlanmc.member,
1122 vlanmc.untag, vlanmc.fid);
1123 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1124 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1125 "%d \t \t 0x%04x \t 0x%04x \t %d",
1126 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1127
1128 val->value.s = buf;
1129 val->len = len;
1130
1131 return 0;
1132 }
1133
1134 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1135 const struct switch_attr *attr,
1136 struct switch_val *val)
1137 {
1138 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1139 struct rtl8366_smi *smi = &rtl->smi;
1140 u32 data = 0;
1141
1142 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1143 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1144 return -EINVAL;
1145
1146 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1147 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1148 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1149 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1150 } else {
1151 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1152 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1153 (val->value.i << (val->port_vlan * 4));
1154 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1155 }
1156
1157 return 0;
1158 }
1159
1160 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1161 const struct switch_attr *attr,
1162 struct switch_val *val)
1163 {
1164 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1165 struct rtl8366_smi *smi = &rtl->smi;
1166 u32 data = 0;
1167
1168 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1169 return -EINVAL;
1170
1171 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1172 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1173
1174 return 0;
1175 }
1176
1177 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1178 const struct switch_attr *attr,
1179 struct switch_val *val)
1180 {
1181 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1182 struct rtl8366_smi *smi = &rtl->smi;
1183 u32 data = 0;
1184
1185 if (val->port_vlan >= RTL8366_NUM_PORTS)
1186 return -EINVAL;
1187
1188 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1189 data |= (1 << (val->port_vlan + 3));
1190 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1191
1192 return 0;
1193 }
1194
1195 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1196 const struct switch_attr *attr,
1197 struct switch_val *val)
1198 {
1199 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1200 int i, len = 0;
1201 unsigned long long counter = 0;
1202 char *buf = rtl->buf;
1203
1204 if (val->port_vlan >= RTL8366_NUM_PORTS)
1205 return -EINVAL;
1206
1207 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1208 "Port %d MIB counters\n",
1209 val->port_vlan);
1210
1211 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1212 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1213 "%d:%s\t", i, rtl8366s_mib_counters[i].name);
1214 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1215 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1216 "[%llu]\n", counter);
1217 else
1218 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1219 "[error]\n");
1220 }
1221
1222 val->value.s = buf;
1223 val->len = len;
1224 return 0;
1225 }
1226
1227 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1228 struct switch_val *val)
1229 {
1230 struct rtl8366s_vlanconfig vlanmc;
1231 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1232 struct switch_port *port;
1233 int i;
1234
1235 if (val->port_vlan >= RTL8366_NUM_VLANS)
1236 return -EINVAL;
1237
1238 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1239
1240 port = &val->value.ports[0];
1241 val->len = 0;
1242 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1243 if (!(vlanmc.member & BIT(i)))
1244 continue;
1245
1246 port->id = i;
1247 port->flags = (vlanmc.untag & BIT(i)) ?
1248 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1249 val->len++;
1250 port++;
1251 }
1252 return 0;
1253 }
1254
1255 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1256 struct switch_val *val)
1257 {
1258 struct rtl8366s_vlanconfig vlanmc;
1259 struct rtl8366s_vlan4kentry vlan4k;
1260 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1261 struct switch_port *port;
1262 int i;
1263
1264 if (val->port_vlan >= RTL8366_NUM_VLANS)
1265 return -EINVAL;
1266
1267 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1268 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1269
1270 vlanmc.untag = 0;
1271 vlanmc.member = 0;
1272
1273 port = &val->value.ports[0];
1274 for (i = 0; i < val->len; i++, port++) {
1275 vlanmc.member |= BIT(port->id);
1276
1277 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1278 vlanmc.untag |= BIT(port->id);
1279 }
1280
1281 vlan4k.member = vlanmc.member;
1282 vlan4k.untag = vlanmc.untag;
1283
1284 rtl8366s_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1285 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
1286 return 0;
1287 }
1288
1289 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1290 {
1291 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1292 return rtl8366s_get_vlan_port_pvid(rtl, port, val);
1293 }
1294
1295 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1296 {
1297 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1298 return rtl8366s_set_vlan_port_pvid(rtl, port, val);
1299 }
1300
1301 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1302 {
1303 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1304 struct rtl8366_smi *smi = &rtl->smi;
1305 int timeout = 10;
1306 u32 data;
1307
1308 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1309 RTL8366_CHIP_CTRL_RESET_HW);
1310 do {
1311 msleep(1);
1312 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1313 return -EIO;
1314
1315 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1316 break;
1317 } while (--timeout);
1318
1319 if (!timeout) {
1320 printk("Timeout waiting for the switch to reset\n");
1321 return -EIO;
1322 }
1323
1324 return rtl8366s_reset_vlan(rtl);
1325 }
1326
1327 static struct switch_attr rtl8366s_globals[] = {
1328 {
1329 .type = SWITCH_TYPE_INT,
1330 .name = "enable_vlan",
1331 .description = "Enable VLAN mode",
1332 .set = rtl8366s_sw_set_vlan_enable,
1333 .get = rtl8366s_sw_get_vlan_enable,
1334 .max = 1,
1335 .ofs = 1
1336 }, {
1337 .type = SWITCH_TYPE_INT,
1338 .name = "enable_vlan4k",
1339 .description = "Enable VLAN 4K mode",
1340 .set = rtl8366s_sw_set_vlan_enable,
1341 .get = rtl8366s_sw_get_vlan_enable,
1342 .max = 1,
1343 .ofs = 2
1344 }, {
1345 .type = SWITCH_TYPE_INT,
1346 .name = "reset_mibs",
1347 .description = "Reset all MIB counters",
1348 .set = rtl8366s_sw_reset_mibs,
1349 .get = NULL,
1350 .max = 1
1351 }, {
1352 .type = SWITCH_TYPE_INT,
1353 .name = "blinkrate",
1354 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1355 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1356 .set = rtl8366s_sw_set_blinkrate,
1357 .get = rtl8366s_sw_get_blinkrate,
1358 .max = 5
1359 },
1360 };
1361
1362 static struct switch_attr rtl8366s_port[] = {
1363 {
1364 .type = SWITCH_TYPE_STRING,
1365 .name = "link",
1366 .description = "Get port link information",
1367 .max = 1,
1368 .set = NULL,
1369 .get = rtl8366s_sw_get_port_link,
1370 }, {
1371 .type = SWITCH_TYPE_INT,
1372 .name = "reset_mib",
1373 .description = "Reset single port MIB counters",
1374 .max = 1,
1375 .set = rtl8366s_sw_reset_port_mibs,
1376 .get = NULL,
1377 }, {
1378 .type = SWITCH_TYPE_STRING,
1379 .name = "mib",
1380 .description = "Get MIB counters for port",
1381 .max = 33,
1382 .set = NULL,
1383 .get = rtl8366s_sw_get_port_mib,
1384 }, {
1385 .type = SWITCH_TYPE_INT,
1386 .name = "led",
1387 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1388 .max = 15,
1389 .set = rtl8366s_sw_set_port_led,
1390 .get = rtl8366s_sw_get_port_led,
1391 },
1392 };
1393
1394 static struct switch_attr rtl8366s_vlan[] = {
1395 {
1396 .type = SWITCH_TYPE_STRING,
1397 .name = "info",
1398 .description = "Get vlan information",
1399 .max = 1,
1400 .set = NULL,
1401 .get = rtl8366s_sw_get_vlan_info,
1402 },
1403 };
1404
1405 /* template */
1406 static struct switch_dev rtl8366_switch_dev = {
1407 .name = "RTL8366S",
1408 .cpu_port = RTL8366_PORT_NUM_CPU,
1409 .ports = RTL8366_NUM_PORTS,
1410 .vlans = RTL8366_NUM_VLANS,
1411 .attr_global = {
1412 .attr = rtl8366s_globals,
1413 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1414 },
1415 .attr_port = {
1416 .attr = rtl8366s_port,
1417 .n_attr = ARRAY_SIZE(rtl8366s_port),
1418 },
1419 .attr_vlan = {
1420 .attr = rtl8366s_vlan,
1421 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1422 },
1423
1424 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1425 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1426 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1427 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1428 .reset_switch = rtl8366s_sw_reset_switch,
1429 };
1430
1431 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1432 {
1433 struct switch_dev *dev = &rtl->dev;
1434 int err;
1435
1436 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1437 dev->priv = rtl;
1438 dev->devname = dev_name(rtl->parent);
1439
1440 err = register_switch(dev, NULL);
1441 if (err)
1442 dev_err(rtl->parent, "switch registration failed\n");
1443
1444 return err;
1445 }
1446
1447 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1448 {
1449 unregister_switch(&rtl->dev);
1450 }
1451
1452 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1453 {
1454 struct rtl8366s *rtl = bus->priv;
1455 u32 val = 0;
1456 int err;
1457
1458 err = rtl8366s_read_phy_reg(rtl, addr, 0, reg, &val);
1459 if (err)
1460 return 0xffff;
1461
1462 return val;
1463 }
1464
1465 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1466 {
1467 struct rtl8366s *rtl = bus->priv;
1468 u32 t;
1469 int err;
1470
1471 err = rtl8366s_write_phy_reg(rtl, addr, 0, reg, val);
1472 /* flush write */
1473 (void) rtl8366s_read_phy_reg(rtl, addr, 0, reg, &t);
1474
1475 return err;
1476 }
1477
1478 static int rtl8366s_mii_init(struct rtl8366s *rtl)
1479 {
1480 int ret;
1481 int i;
1482
1483 rtl->mii_bus = mdiobus_alloc();
1484 if (rtl->mii_bus == NULL) {
1485 ret = -ENOMEM;
1486 goto err;
1487 }
1488
1489 rtl->mii_bus->priv = (void *) rtl;
1490 rtl->mii_bus->name = "rtl8366-rtl";
1491 rtl->mii_bus->read = rtl8366s_mii_read;
1492 rtl->mii_bus->write = rtl8366s_mii_write;
1493 snprintf(rtl->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1494 dev_name(rtl->parent));
1495 rtl->mii_bus->parent = rtl->parent;
1496 rtl->mii_bus->phy_mask = ~(0x1f);
1497 rtl->mii_bus->irq = rtl->mii_irq;
1498 for (i = 0; i < PHY_MAX_ADDR; i++)
1499 rtl->mii_irq[i] = PHY_POLL;
1500
1501 ret = mdiobus_register(rtl->mii_bus);
1502 if (ret)
1503 goto err_free;
1504
1505 return 0;
1506
1507 err_free:
1508 mdiobus_free(rtl->mii_bus);
1509 err:
1510 return ret;
1511 }
1512
1513 static void rtl8366s_mii_cleanup(struct rtl8366s *rtl)
1514 {
1515 mdiobus_unregister(rtl->mii_bus);
1516 mdiobus_free(rtl->mii_bus);
1517 }
1518
1519 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1520 {
1521 return (bus->read == rtl8366s_mii_read &&
1522 bus->write == rtl8366s_mii_write);
1523 }
1524
1525 static int rtl8366s_setup(struct rtl8366s *rtl)
1526 {
1527 struct rtl8366_smi *smi = &rtl->smi;
1528 u32 chip_id = 0;
1529 u32 chip_ver = 0;
1530 int ret;
1531
1532 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1533 if (ret) {
1534 dev_err(rtl->parent, "unable to read chip id\n");
1535 return ret;
1536 }
1537
1538 switch (chip_id) {
1539 case RTL8366S_CHIP_ID_8366:
1540 break;
1541 default:
1542 dev_err(rtl->parent, "unknown chip id (%04x)\n", chip_id);
1543 return -ENODEV;
1544 }
1545
1546 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1547 &chip_ver);
1548 if (ret) {
1549 dev_err(rtl->parent, "unable to read chip version\n");
1550 return ret;
1551 }
1552
1553 dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
1554 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1555
1556 rtl8366s_debugfs_init(rtl);
1557
1558 return 0;
1559 }
1560
1561 static int __init rtl8366s_probe(struct platform_device *pdev)
1562 {
1563 static int rtl8366_smi_version_printed;
1564 struct rtl8366s_platform_data *pdata;
1565 struct rtl8366s *rtl;
1566 struct rtl8366_smi *smi;
1567 int err;
1568
1569 if (!rtl8366_smi_version_printed++)
1570 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1571 " version " RTL8366S_DRIVER_VER"\n");
1572
1573 pdata = pdev->dev.platform_data;
1574 if (!pdata) {
1575 dev_err(&pdev->dev, "no platform data specified\n");
1576 err = -EINVAL;
1577 goto err_out;
1578 }
1579
1580 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1581 if (!rtl) {
1582 dev_err(&pdev->dev, "no memory for private data\n");
1583 err = -ENOMEM;
1584 goto err_out;
1585 }
1586
1587 rtl->parent = &pdev->dev;
1588
1589 smi = &rtl->smi;
1590 smi->parent = &pdev->dev;
1591 smi->gpio_sda = pdata->gpio_sda;
1592 smi->gpio_sck = pdata->gpio_sck;
1593
1594 err = rtl8366_smi_init(smi);
1595 if (err)
1596 goto err_free_rtl;
1597
1598 platform_set_drvdata(pdev, rtl);
1599
1600 err = rtl8366s_setup(rtl);
1601 if (err)
1602 goto err_clear_drvdata;
1603
1604 err = rtl8366s_mii_init(rtl);
1605 if (err)
1606 goto err_clear_drvdata;
1607
1608 err = rtl8366s_switch_init(rtl);
1609 if (err)
1610 goto err_mii_cleanup;
1611
1612 return 0;
1613
1614 err_mii_cleanup:
1615 rtl8366s_mii_cleanup(rtl);
1616 err_clear_drvdata:
1617 platform_set_drvdata(pdev, NULL);
1618 rtl8366_smi_cleanup(smi);
1619 err_free_rtl:
1620 kfree(rtl);
1621 err_out:
1622 return err;
1623 }
1624
1625 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1626 {
1627 if (!rtl8366s_mii_bus_match(phydev->bus))
1628 return -EINVAL;
1629
1630 return 0;
1631 }
1632
1633 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1634 {
1635 return 0;
1636 }
1637
1638 static struct phy_driver rtl8366s_phy_driver = {
1639 .phy_id = 0x001cc960,
1640 .name = "Realtek RTL8366S",
1641 .phy_id_mask = 0x1ffffff0,
1642 .features = PHY_GBIT_FEATURES,
1643 .config_aneg = rtl8366s_phy_config_aneg,
1644 .config_init = rtl8366s_phy_config_init,
1645 .read_status = genphy_read_status,
1646 .driver = {
1647 .owner = THIS_MODULE,
1648 },
1649 };
1650
1651 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1652 {
1653 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1654
1655 if (rtl) {
1656 rtl8366s_switch_cleanup(rtl);
1657 rtl8366s_debugfs_remove(rtl);
1658 rtl8366s_mii_cleanup(rtl);
1659 platform_set_drvdata(pdev, NULL);
1660 rtl8366_smi_cleanup(&rtl->smi);
1661 kfree(rtl);
1662 }
1663
1664 return 0;
1665 }
1666
1667 static struct platform_driver rtl8366s_driver = {
1668 .driver = {
1669 .name = RTL8366S_DRIVER_NAME,
1670 .owner = THIS_MODULE,
1671 },
1672 .probe = rtl8366s_probe,
1673 .remove = __devexit_p(rtl8366s_remove),
1674 };
1675
1676 static int __init rtl8366s_module_init(void)
1677 {
1678 int ret;
1679 ret = platform_driver_register(&rtl8366s_driver);
1680 if (ret)
1681 return ret;
1682
1683 ret = phy_driver_register(&rtl8366s_phy_driver);
1684 if (ret)
1685 goto err_platform_unregister;
1686
1687 return 0;
1688
1689 err_platform_unregister:
1690 platform_driver_unregister(&rtl8366s_driver);
1691 return ret;
1692 }
1693 module_init(rtl8366s_module_init);
1694
1695 static void __exit rtl8366s_module_exit(void)
1696 {
1697 phy_driver_unregister(&rtl8366s_phy_driver);
1698 platform_driver_unregister(&rtl8366s_driver);
1699 }
1700 module_exit(rtl8366s_module_exit);
1701
1702 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1703 MODULE_VERSION(RTL8366S_DRIVER_VER);
1704 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1705 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1706 MODULE_LICENSE("GPL v2");
1707 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
Personal OpenWRT clone
This page took 0.147672 seconds and 3 git commands to generate.