projects / openwrt.git / blob
? search:


8bf0046fcda4e0123d4ce1a703bceea65cc15b2a
[openwrt.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
37
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
41
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0509
45 #define RTL8366S_CHIP_ID_8366 0x5937
46
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
50
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
53
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
59
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0430
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
64
65 #define RTL8366_LED_CTRL_REG 0x0431
66 #define RTL8366_LED_0_1_CTRL_REG 0x0432
67 #define RTL8366_LED_2_3_CTRL_REG 0x0433
68
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x13F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
77
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
81
82
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
88
89
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
97
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
99
100
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
108
109
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
117
118
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
124
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
126
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
128 RTL8366_PORT_2 | \
129 RTL8366_PORT_3 | \
130 RTL8366_PORT_4 | \
131 RTL8366_PORT_5 | \
132 RTL8366_PORT_CPU)
133
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
135 RTL8366_PORT_2 | \
136 RTL8366_PORT_3 | \
137 RTL8366_PORT_4 | \
138 RTL8366_PORT_5)
139
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
141 RTL8366_PORT_2 | \
142 RTL8366_PORT_3 | \
143 RTL8366_PORT_4)
144
145 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
146
147 struct rtl8366rb {
148 struct device *parent;
149 struct rtl8366_smi smi;
150 struct switch_dev dev;
151 char buf[4096];
152 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
153 struct dentry *debugfs_root;
154 #endif
155 };
156
157 struct rtl8366rb_vlan_mc {
158 u16 reserved2:1;
159 u16 priority:3;
160 u16 vid:12;
161 u16 untag:8;
162 u16 member:8;
163 u16 stag_mbr:8;
164 u16 stag_idx:3;
165 u16 reserved1:2;
166 u16 fid:3;
167 };
168
169 struct rtl8366rb_vlan_4k {
170 u16 reserved1:4;
171 u16 vid:12;
172 u16 untag:8;
173 u16 member:8;
174 u16 reserved2:13;
175 u16 fid:3;
176 };
177
178 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
179 u16 gl_dbg_reg;
180 #endif
181
182 struct mib_counter {
183 unsigned offset;
184 unsigned length;
185 const char *name;
186 };
187
188 static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = {
189 { 0, 4, "IfInOctets " },
190 { 4, 4, "EtherStatsOctets " },
191 { 8, 2, "EtherStatsUnderSizePkts " },
192 { 10, 2, "EtherFregament " },
193 { 12, 2, "EtherStatsPkts64Octets " },
194 { 14, 2, "EtherStatsPkts65to127Octets " },
195 { 16, 2, "EtherStatsPkts128to255Octets " },
196 { 18, 2, "EtherStatsPkts256to511Octets " },
197 { 20, 2, "EtherStatsPkts512to1023Octets " },
198 { 22, 2, "EtherStatsPkts1024to1518Octets " },
199 { 24, 2, "EtherOversizeStats " },
200 { 26, 2, "EtherStatsJabbers " },
201 { 28, 2, "IfInUcastPkts " },
202 { 30, 2, "EtherStatsMulticastPkts " },
203 { 32, 2, "EtherStatsBroadcastPkts " },
204 { 34, 2, "EtherStatsDropEvents " },
205 { 36, 2, "Dot3StatsFCSErrors " },
206 { 38, 2, "Dot3StatsSymbolErrors " },
207 { 40, 2, "Dot3InPauseFrames " },
208 { 42, 2, "Dot3ControlInUnknownOpcodes " },
209 { 44, 4, "IfOutOctets " },
210 { 48, 2, "Dot3StatsSingleCollisionFrames " },
211 { 50, 2, "Dot3StatMultipleCollisionFrames " },
212 { 52, 2, "Dot3sDeferredTransmissions " },
213 { 54, 2, "Dot3StatsLateCollisions " },
214 { 56, 2, "EtherStatsCollisions " },
215 { 58, 2, "Dot3StatsExcessiveCollisions " },
216 { 60, 2, "Dot3OutPauseFrames " },
217 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
218 { 64, 2, "Dot1dTpPortInDiscards " },
219 { 66, 2, "IfOutUcastPkts " },
220 { 68, 2, "IfOutMulticastPkts " },
221 { 70, 2, "IfOutBroadcastPkts " },
222 };
223
224 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
225 {
226 return container_of(smi, struct rtl8366rb, smi);
227 }
228
229 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
230 {
231 return container_of(sw, struct rtl8366rb, dev);
232 }
233
234 static int rtl8366rb_reset_chip(struct rtl8366rb *rtl)
235 {
236 struct rtl8366_smi *smi = &rtl->smi;
237 int timeout = 10;
238 u32 data;
239
240 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
241 RTL8366_CHIP_CTRL_RESET_HW);
242 do {
243 msleep(1);
244 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
245 return -EIO;
246
247 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
248 break;
249 } while (--timeout);
250
251 if (!timeout) {
252 printk("Timeout waiting for the switch to reset\n");
253 return -EIO;
254 }
255
256 return 0;
257 }
258
259 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
260 u32 phy_no, u32 page, u32 addr, u32 *data)
261 {
262 u32 reg;
263 int ret;
264
265 if (phy_no > RTL8366S_PHY_NO_MAX)
266 return -EINVAL;
267
268 if (page > RTL8366S_PHY_PAGE_MAX)
269 return -EINVAL;
270
271 if (addr > RTL8366S_PHY_ADDR_MAX)
272 return -EINVAL;
273
274 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
275 RTL8366S_PHY_CTRL_READ);
276 if (ret)
277 return ret;
278
279 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
280 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
281 (addr & RTL8366S_PHY_REG_MASK);
282
283 ret = rtl8366_smi_write_reg(smi, reg, 0);
284 if (ret)
285 return ret;
286
287 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
288 if (ret)
289 return ret;
290
291 return 0;
292 }
293
294 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
295 u32 phy_no, u32 page, u32 addr, u32 data)
296 {
297 u32 reg;
298 int ret;
299
300 if (phy_no > RTL8366S_PHY_NO_MAX)
301 return -EINVAL;
302
303 if (page > RTL8366S_PHY_PAGE_MAX)
304 return -EINVAL;
305
306 if (addr > RTL8366S_PHY_ADDR_MAX)
307 return -EINVAL;
308
309 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
310 RTL8366S_PHY_CTRL_WRITE);
311 if (ret)
312 return ret;
313
314 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
315 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
316 (addr & RTL8366S_PHY_REG_MASK);
317
318 ret = rtl8366_smi_write_reg(smi, reg, data);
319 if (ret)
320 return ret;
321
322 return 0;
323 }
324
325 static int rtl8366_get_mib_counter(struct rtl8366rb *rtl, int counter,
326 int port, unsigned long long *val)
327 {
328 struct rtl8366_smi *smi = &rtl->smi;
329 int i;
330 int err;
331 u32 addr, data;
332 u64 mibvalue;
333
334 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
335 return -EINVAL;
336
337 addr = RTL8366S_MIB_COUNTER_BASE +
338 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
339 rtl8366rb_mib_counters[counter].offset;
340
341 /*
342 * Writing access counter address first
343 * then ASIC will prepare 64bits counter wait for being retrived
344 */
345 data = 0; /* writing data will be discard by ASIC */
346 err = rtl8366_smi_write_reg(smi, addr, data);
347 if (err)
348 return err;
349
350 /* read MIB control register */
351 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
352 if (err)
353 return err;
354
355 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
356 return -EBUSY;
357
358 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
359 return -EIO;
360
361 mibvalue = 0;
362 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
363 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
364 if (err)
365 return err;
366
367 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
368 }
369
370 *val = mibvalue;
371 return 0;
372 }
373
374 static int rtl8366rb_get_vlan_4k(struct rtl8366rb *rtl, u32 vid,
375 struct rtl8366rb_vlan_4k *vlan4k)
376 {
377 struct rtl8366_smi *smi = &rtl->smi;
378 int err;
379 u32 data;
380 u16 *tableaddr;
381
382 memset(vlan4k, '\0', sizeof(struct rtl8366rb_vlan_4k));
383 vlan4k->vid = vid;
384
385 if (vid >= RTL8366_NUM_VIDS)
386 return -EINVAL;
387
388 tableaddr = (u16 *)vlan4k;
389
390 /* write VID */
391 data = *tableaddr;
392 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
393 if (err)
394 return err;
395
396 /* write table access control word */
397 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
398 RTL8366S_TABLE_VLAN_READ_CTRL);
399 if (err)
400 return err;
401
402 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
403 if (err)
404 return err;
405
406 *tableaddr = data;
407 tableaddr++;
408
409 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
410 &data);
411 if (err)
412 return err;
413
414 *tableaddr = data;
415 tableaddr++;
416
417 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2,
418 &data);
419 if (err)
420 return err;
421 *tableaddr = data;
422 vlan4k->vid = vid;
423
424 return 0;
425 }
426
427 static int rtl8366rb_set_vlan_4k(struct rtl8366rb *rtl,
428 const struct rtl8366rb_vlan_4k *vlan4k)
429 {
430 struct rtl8366_smi *smi = &rtl->smi;
431 int err;
432 u32 data;
433 u16 *tableaddr;
434
435 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
436 vlan4k->member > RTL8366_PORT_ALL ||
437 vlan4k->untag > RTL8366_PORT_ALL ||
438 vlan4k->fid > RTL8366S_FIDMAX)
439 return -EINVAL;
440
441 tableaddr = (u16 *)vlan4k;
442
443 data = *tableaddr;
444
445 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
446 if (err)
447 return err;
448
449 tableaddr++;
450
451 data = *tableaddr;
452
453 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
454 data);
455 if (err)
456 return err;
457
458 tableaddr++;
459
460 data = *tableaddr;
461
462 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2,
463 data);
464 if (err)
465 return err;
466
467 /* write table access control word */
468 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
469 RTL8366S_TABLE_VLAN_WRITE_CTRL);
470
471 return err;
472 }
473
474 static int rtl8366rb_get_vlan_mc(struct rtl8366rb *rtl, u32 index,
475 struct rtl8366_vlan_mc *vlanmc)
476 {
477 struct rtl8366_smi *smi = &rtl->smi;
478 struct rtl8366rb_vlan_mc vlanmc_priv;
479 int err;
480 u32 addr;
481 u32 data;
482 u16 *tableaddr;
483
484 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
485
486 if (index >= RTL8366_NUM_VLANS)
487 return -EINVAL;
488
489 tableaddr = (u16 *)&vlanmc_priv;
490
491 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
492 err = rtl8366_smi_read_reg(smi, addr, &data);
493 if (err)
494 return err;
495
496 *tableaddr = data;
497 tableaddr++;
498
499 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
500 err = rtl8366_smi_read_reg(smi, addr, &data);
501 if (err)
502 return err;
503
504 *tableaddr = data;
505 tableaddr++;
506
507 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
508 err = rtl8366_smi_read_reg(smi, addr, &data);
509 if (err)
510 return err;
511
512 *tableaddr = data;
513
514 vlanmc->vid = vlanmc_priv.vid;
515 vlanmc->priority = vlanmc_priv.priority;
516 vlanmc->untag = vlanmc_priv.untag;
517 vlanmc->member = vlanmc_priv.member;
518 vlanmc->fid = vlanmc_priv.fid;
519
520 return 0;
521 }
522
523 static int rtl8366rb_set_vlan_mc(struct rtl8366rb *rtl, u32 index,
524 const struct rtl8366_vlan_mc *vlanmc)
525 {
526 struct rtl8366_smi *smi = &rtl->smi;
527 struct rtl8366rb_vlan_mc vlanmc_priv;
528 int err;
529 u32 addr;
530 u32 data;
531 u16 *tableaddr;
532
533 if (index >= RTL8366_NUM_VLANS ||
534 vlanmc->vid >= RTL8366_NUM_VIDS ||
535 vlanmc->priority > RTL8366S_PRIORITYMAX ||
536 vlanmc->member > RTL8366_PORT_ALL ||
537 vlanmc->untag > RTL8366_PORT_ALL ||
538 vlanmc->fid > RTL8366S_FIDMAX)
539 return -EINVAL;
540
541 vlanmc_priv.vid = vlanmc->vid;
542 vlanmc_priv.priority = vlanmc->priority;
543 vlanmc_priv.untag = vlanmc->untag;
544 vlanmc_priv.member = vlanmc->member;
545 vlanmc_priv.stag_mbr = 0;
546 vlanmc_priv.stag_idx = 0;
547 vlanmc_priv.fid = vlanmc->fid;
548
549 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
550
551 tableaddr = (u16 *)&vlanmc_priv;
552 data = *tableaddr;
553
554 err = rtl8366_smi_write_reg(smi, addr, data);
555 if (err)
556 return err;
557
558 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
559
560 tableaddr++;
561 data = *tableaddr;
562
563 err = rtl8366_smi_write_reg(smi, addr, data);
564 if (err)
565 return err;
566
567 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
568
569 tableaddr++;
570 data = *tableaddr;
571
572 err = rtl8366_smi_write_reg(smi, addr, data);
573 if (err)
574 return err;
575 return 0;
576 }
577
578 static int rtl8366rb_get_port_vlan_index(struct rtl8366rb *rtl, int port,
579 int *val)
580 {
581 struct rtl8366_smi *smi = &rtl->smi;
582 u32 data;
583 int err;
584
585 if (port >= RTL8366_NUM_PORTS)
586 return -EINVAL;
587
588 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
589 &data);
590 if (err)
591 return err;
592
593 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
594 RTL8366S_PORT_VLAN_CTRL_MASK;
595
596 return 0;
597
598 }
599
600 static int rtl8366rb_get_vlan_port_pvid(struct rtl8366rb *rtl, int port,
601 int *val)
602 {
603 struct rtl8366_vlan_mc vlanmc;
604 int err;
605 int index;
606
607 err = rtl8366rb_get_port_vlan_index(rtl, port, &index);
608 if (err)
609 return err;
610
611 err = rtl8366rb_get_vlan_mc(rtl, index, &vlanmc);
612 if (err)
613 return err;
614
615 *val = vlanmc.vid;
616 return 0;
617 }
618
619 static int rtl8366rb_set_port_vlan_index(struct rtl8366rb *rtl, int port,
620 int index)
621 {
622 struct rtl8366_smi *smi = &rtl->smi;
623 u32 data;
624 int err;
625
626 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
627 return -EINVAL;
628
629 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
630 &data);
631 if (err)
632 return err;
633
634 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
635 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
636 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
637 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
638
639 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
640 data);
641 return err;
642 }
643
644 static int rtl8366rb_set_vlan_port_pvid(struct rtl8366rb *rtl, int port, int val)
645 {
646 int i;
647 struct rtl8366_vlan_mc vlanmc;
648 struct rtl8366rb_vlan_4k vlan4k;
649
650 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
651 return -EINVAL;
652
653 /* Updating the 4K entry; lookup it and change the port member set */
654 rtl8366rb_get_vlan_4k(rtl, val, &vlan4k);
655 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
656 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
657 rtl8366rb_set_vlan_4k(rtl, &vlan4k);
658
659 /*
660 * For the 16 entries more work needs to be done. First see if such
661 * VID is already there and change it
662 */
663 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
664 rtl8366rb_get_vlan_mc(rtl, i, &vlanmc);
665
666 /* Try to find an existing vid and update port member set */
667 if (val == vlanmc.vid) {
668 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
669 rtl8366rb_set_vlan_mc(rtl, i, &vlanmc);
670
671 /* Now update PVID register settings */
672 rtl8366rb_set_port_vlan_index(rtl, port, i);
673
674 return 0;
675 }
676 }
677
678 /*
679 * PVID could not be found from vlan table. Replace unused (one that
680 * has no member ports) with new one
681 */
682 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
683 rtl8366rb_get_vlan_mc(rtl, i, &vlanmc);
684
685 /*
686 * See if this vlan member configuration is unused. It is
687 * unused if member set contains no ports or CPU port only
688 */
689 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
690 vlanmc.vid = val;
691 vlanmc.priority = 0;
692 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
693 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
694 vlanmc.fid = 0;
695
696 rtl8366rb_set_vlan_mc(rtl, i, &vlanmc);
697
698 /* Now update PVID register settings */
699 rtl8366rb_set_port_vlan_index(rtl, port, i);
700
701 return 0;
702 }
703 }
704
705 dev_err(rtl->parent,
706 "All 16 vlan member configurations are in use\n");
707
708 return -EINVAL;
709 }
710
711
712 static int rtl8366rb_vlan_set_vlan(struct rtl8366rb *rtl, int enable)
713 {
714 struct rtl8366_smi *smi = &rtl->smi;
715 u32 data = 0;
716
717 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
718
719 if (enable)
720 data |= RTL8366_CHIP_CTRL_VLAN;
721 else
722 data &= ~RTL8366_CHIP_CTRL_VLAN;
723
724 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
725 }
726
727 static int rtl8366rb_vlan_set_4ktable(struct rtl8366rb *rtl, int enable)
728 {
729 struct rtl8366_smi *smi = &rtl->smi;
730 u32 data = 0;
731
732 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
733
734 if (enable)
735 data |= RTL8366_CHIP_CTRL_VLAN_4KTB;
736 else
737 data &= ~RTL8366_CHIP_CTRL_VLAN_4KTB;
738
739 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
740 }
741
742 static int rtl8366rb_reset_vlan(struct rtl8366rb *rtl)
743 {
744 struct rtl8366rb_vlan_4k vlan4k;
745 struct rtl8366_vlan_mc vlanmc;
746 int err;
747 int i;
748
749 /* clear 16 VLAN member configuration */
750 vlanmc.vid = 0;
751 vlanmc.priority = 0;
752 vlanmc.member = 0;
753 vlanmc.untag = 0;
754 vlanmc.fid = 0;
755 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
756 err = rtl8366rb_set_vlan_mc(rtl, i, &vlanmc);
757 if (err)
758 return err;
759 }
760
761 /* Set a default VLAN with vid 1 to 4K table for all ports */
762 vlan4k.vid = 1;
763 vlan4k.member = RTL8366_PORT_ALL;
764 vlan4k.untag = RTL8366_PORT_ALL;
765 vlan4k.fid = 0;
766 err = rtl8366rb_set_vlan_4k(rtl, &vlan4k);
767 if (err)
768 return err;
769
770 /* Set all ports PVID to default VLAN */
771 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
772 err = rtl8366rb_set_vlan_port_pvid(rtl, i, 0);
773 if (err)
774 return err;
775 }
776
777 return 0;
778 }
779
780 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
781 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
782 {
783 file->private_data = inode->i_private;
784 return 0;
785 }
786
787 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
788 char __user *user_buf,
789 size_t count, loff_t *ppos)
790 {
791 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
792 int i, j, len = 0;
793 char *buf = rtl->buf;
794
795 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
796 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
797 " "
798 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
799 "Port 4\n");
800
801 for (i = 0; i < 33; ++i) {
802 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
803 i, rtl8366rb_mib_counters[i].name);
804 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
805 unsigned long long counter = 0;
806
807 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
808 len += snprintf(buf + len,
809 sizeof(rtl->buf) - len,
810 "[%llu]", counter);
811 else
812 len += snprintf(buf + len,
813 sizeof(rtl->buf) - len,
814 "[error]");
815
816 if (j != RTL8366_NUM_PORTS - 1) {
817 if (counter < 100000)
818 len += snprintf(buf + len,
819 sizeof(rtl->buf) - len,
820 "\t");
821
822 len += snprintf(buf + len,
823 sizeof(rtl->buf) - len,
824 "\t");
825 }
826 }
827 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
828 }
829
830 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
831
832 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
833 }
834
835 static ssize_t rtl8366rb_read_debugfs_vlan(struct file *file,
836 char __user *user_buf,
837 size_t count, loff_t *ppos)
838 {
839 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
840 int i, j, len = 0;
841 char *buf = rtl->buf;
842
843 len += snprintf(buf + len, sizeof(rtl->buf) - len,
844 "VLAN Member Config:\n");
845 len += snprintf(buf + len, sizeof(rtl->buf) - len,
846 "\t id \t vid \t prio \t member \t untag \t fid "
847 "\tports\n");
848
849 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
850 struct rtl8366_vlan_mc vlanmc;
851
852 rtl8366rb_get_vlan_mc(rtl, i, &vlanmc);
853
854 len += snprintf(buf + len, sizeof(rtl->buf) - len,
855 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
856 "\t", i, vlanmc.vid, vlanmc.priority,
857 vlanmc.member, vlanmc.untag, vlanmc.fid);
858
859 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
860 int index = 0;
861 if (!rtl8366rb_get_port_vlan_index(rtl, j, &index)) {
862 if (index == i)
863 len += snprintf(buf + len,
864 sizeof(rtl->buf) - len,
865 "%d", j);
866 }
867 }
868 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
869 }
870
871 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
872 }
873
874 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
875 char __user *user_buf,
876 size_t count, loff_t *ppos)
877 {
878 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
879 struct rtl8366_smi *smi = &rtl->smi;
880 u32 t, reg = gl_dbg_reg;
881 int err, len = 0;
882 char *buf = rtl->buf;
883
884 memset(buf, '\0', sizeof(rtl->buf));
885
886 err = rtl8366_smi_read_reg(smi, reg, &t);
887 if (err) {
888 len += snprintf(buf, sizeof(rtl->buf),
889 "Read failed (reg: 0x%04x)\n", reg);
890 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
891 }
892
893 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
894 reg, t);
895
896 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
897 }
898
899 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
900 const char __user *user_buf,
901 size_t count, loff_t *ppos)
902 {
903 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
904 struct rtl8366_smi *smi = &rtl->smi;
905 unsigned long data;
906 u32 reg = gl_dbg_reg;
907 int err;
908 size_t len;
909 char *buf = rtl->buf;
910
911 len = min(count, sizeof(rtl->buf) - 1);
912 if (copy_from_user(buf, user_buf, len)) {
913 dev_err(rtl->parent, "copy from user failed\n");
914 return -EFAULT;
915 }
916
917 buf[len] = '\0';
918 if (len > 0 && buf[len - 1] == '\n')
919 buf[len - 1] = '\0';
920
921
922 if (strict_strtoul(buf, 16, &data)) {
923 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
924 } else {
925 err = rtl8366_smi_write_reg(smi, reg, data);
926 if (err) {
927 dev_err(rtl->parent,
928 "writing reg 0x%04x val 0x%04lx failed\n",
929 reg, data);
930 }
931 }
932
933 return count;
934 }
935
936 static const struct file_operations fops_rtl8366rb_regs = {
937 .read = rtl8366rb_read_debugfs_reg,
938 .write = rtl8366rb_write_debugfs_reg,
939 .open = rtl8366rb_debugfs_open,
940 .owner = THIS_MODULE
941 };
942
943 static const struct file_operations fops_rtl8366rb_vlan = {
944 .read = rtl8366rb_read_debugfs_vlan,
945 .open = rtl8366rb_debugfs_open,
946 .owner = THIS_MODULE
947 };
948
949 static const struct file_operations fops_rtl8366rb_mibs = {
950 .read = rtl8366rb_read_debugfs_mibs,
951 .open = rtl8366rb_debugfs_open,
952 .owner = THIS_MODULE
953 };
954
955 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
956 {
957 struct dentry *node;
958 struct dentry *root;
959
960 if (!rtl->debugfs_root)
961 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
962
963 if (!rtl->debugfs_root) {
964 dev_err(rtl->parent, "Unable to create debugfs dir\n");
965 return;
966 }
967 root = rtl->debugfs_root;
968
969 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
970 if (!node) {
971 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
972 "reg");
973 return;
974 }
975
976 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
977 &fops_rtl8366rb_regs);
978 if (!node) {
979 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
980 "val");
981 return;
982 }
983
984 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
985 &fops_rtl8366rb_vlan);
986 if (!node) {
987 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
988 "vlan");
989 return;
990 }
991
992 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
993 &fops_rtl8366rb_mibs);
994 if (!node) {
995 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
996 "mibs");
997 return;
998 }
999 }
1000
1001 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
1002 {
1003 if (rtl->debugfs_root) {
1004 debugfs_remove_recursive(rtl->debugfs_root);
1005 rtl->debugfs_root = NULL;
1006 }
1007 }
1008
1009 #else
1010 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
1011 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
1012 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1013
1014 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
1015 const struct switch_attr *attr,
1016 struct switch_val *val)
1017 {
1018 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1019 struct rtl8366_smi *smi = &rtl->smi;
1020 u32 data = 0;
1021
1022 if (val->value.i == 1) {
1023 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1024 data |= (1 << 2);
1025 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1026 }
1027
1028 return 0;
1029 }
1030
1031 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
1032 const struct switch_attr *attr,
1033 struct switch_val *val)
1034 {
1035 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1036 struct rtl8366_smi *smi = &rtl->smi;
1037 u32 data;
1038
1039 if (attr->ofs == 1) {
1040 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1041
1042 if (data & RTL8366_CHIP_CTRL_VLAN)
1043 val->value.i = 1;
1044 else
1045 val->value.i = 0;
1046 } else if (attr->ofs == 2) {
1047 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1048
1049 if (data & RTL8366_CHIP_CTRL_VLAN_4KTB)
1050 val->value.i = 1;
1051 else
1052 val->value.i = 0;
1053 }
1054
1055 return 0;
1056 }
1057
1058 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
1059 const struct switch_attr *attr,
1060 struct switch_val *val)
1061 {
1062 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1063 struct rtl8366_smi *smi = &rtl->smi;
1064 u32 data;
1065
1066 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1067
1068 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1069
1070 return 0;
1071 }
1072
1073 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
1074 const struct switch_attr *attr,
1075 struct switch_val *val)
1076 {
1077 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1078 struct rtl8366_smi *smi = &rtl->smi;
1079 u32 data;
1080
1081 if (val->value.i >= 6)
1082 return -EINVAL;
1083
1084 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1085
1086 data &= ~RTL8366_LED_BLINKRATE_MASK;
1087 data |= val->value.i;
1088
1089 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1090
1091 return 0;
1092 }
1093
1094 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
1095 const struct switch_attr *attr,
1096 struct switch_val *val)
1097 {
1098 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1099
1100 if (attr->ofs == 1)
1101 return rtl8366rb_vlan_set_vlan(rtl, val->value.i);
1102 else
1103 return rtl8366rb_vlan_set_4ktable(rtl, val->value.i);
1104 }
1105
1106 static const char *rtl8366rb_speed_str(unsigned speed)
1107 {
1108 switch (speed) {
1109 case 0:
1110 return "10baseT";
1111 case 1:
1112 return "100baseT";
1113 case 2:
1114 return "1000baseT";
1115 }
1116
1117 return "unknown";
1118 }
1119
1120 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
1121 const struct switch_attr *attr,
1122 struct switch_val *val)
1123 {
1124 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1125 struct rtl8366_smi *smi = &rtl->smi;
1126 u32 len = 0, data = 0;
1127
1128 if (val->port_vlan >= RTL8366_NUM_PORTS)
1129 return -EINVAL;
1130
1131 memset(rtl->buf, '\0', sizeof(rtl->buf));
1132 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1133 (val->port_vlan / 2), &data);
1134
1135 if (val->port_vlan % 2)
1136 data = data >> 8;
1137
1138 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1139 len = snprintf(rtl->buf, sizeof(rtl->buf),
1140 "port:%d link:up speed:%s %s-duplex %s%s%s",
1141 val->port_vlan,
1142 rtl8366rb_speed_str(data &
1143 RTL8366S_PORT_STATUS_SPEED_MASK),
1144 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1145 "full" : "half",
1146 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1147 "tx-pause ": "",
1148 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1149 "rx-pause " : "",
1150 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1151 "nway ": "");
1152 } else {
1153 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1154 val->port_vlan);
1155 }
1156
1157 val->value.s = rtl->buf;
1158 val->len = len;
1159
1160 return 0;
1161 }
1162
1163 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1164 const struct switch_attr *attr,
1165 struct switch_val *val)
1166 {
1167 int i;
1168 u32 len = 0;
1169 struct rtl8366_vlan_mc vlanmc;
1170 struct rtl8366rb_vlan_4k vlan4k;
1171 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1172 char *buf = rtl->buf;
1173
1174 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1175 return -EINVAL;
1176
1177 memset(buf, '\0', sizeof(rtl->buf));
1178
1179 rtl8366rb_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1180 rtl8366rb_get_vlan_4k(rtl, vlanmc.vid, &vlan4k);
1181
1182 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1183 val->port_vlan);
1184
1185 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1186 int index = 0;
1187 if (!rtl8366rb_get_port_vlan_index(rtl, i, &index) &&
1188 index == val->port_vlan)
1189 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1190 "%d", i);
1191 }
1192 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1193
1194 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1195 "\t\t vid \t prio \t member \t untag \t fid\n");
1196 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1197 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1198 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1199 vlanmc.vid, vlanmc.priority, vlanmc.member,
1200 vlanmc.untag, vlanmc.fid);
1201 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1202 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1203 "%d \t \t 0x%04x \t 0x%04x \t %d",
1204 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1205
1206 val->value.s = buf;
1207 val->len = len;
1208
1209 return 0;
1210 }
1211
1212 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1213 const struct switch_attr *attr,
1214 struct switch_val *val)
1215 {
1216 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1217 struct rtl8366_smi *smi = &rtl->smi;
1218 u32 data = 0;
1219
1220 if (val->port_vlan >= RTL8366_NUM_PORTS)
1221 return -EINVAL;
1222
1223 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1224 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1225 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1226 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1227 } else {
1228 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1229 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1230 (val->value.i << (val->port_vlan * 4));
1231 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1238 const struct switch_attr *attr,
1239 struct switch_val *val)
1240 {
1241 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1242 struct rtl8366_smi *smi = &rtl->smi;
1243 u32 data = 0;
1244
1245 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1246 return -EINVAL;
1247
1248 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1249 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1250
1251 return 0;
1252 }
1253
1254 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1255 const struct switch_attr *attr,
1256 struct switch_val *val)
1257 {
1258 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1259 struct rtl8366_smi *smi = &rtl->smi;
1260 u32 data = 0;
1261
1262 if (val->port_vlan >= RTL8366_NUM_PORTS)
1263 return -EINVAL;
1264
1265 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1266 data |= (1 << (val->port_vlan + 3));
1267 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1268
1269 return 0;
1270 }
1271
1272 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1273 const struct switch_attr *attr,
1274 struct switch_val *val)
1275 {
1276 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1277 int i, len = 0;
1278 unsigned long long counter = 0;
1279 char *buf = rtl->buf;
1280
1281 if (val->port_vlan >= RTL8366_NUM_PORTS)
1282 return -EINVAL;
1283
1284 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1285 "Port %d MIB counters\n",
1286 val->port_vlan);
1287
1288 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1289 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1290 "%d:%s\t", i, rtl8366rb_mib_counters[i].name);
1291 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1292 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1293 "[%llu]\n", counter);
1294 else
1295 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1296 "[error]\n");
1297 }
1298
1299 val->value.s = buf;
1300 val->len = len;
1301 return 0;
1302 }
1303
1304 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1305 struct switch_val *val)
1306 {
1307 struct rtl8366_vlan_mc vlanmc;
1308 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1309 struct switch_port *port;
1310 int i;
1311
1312 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1313 return -EINVAL;
1314
1315 rtl8366rb_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1316
1317 port = &val->value.ports[0];
1318 val->len = 0;
1319 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1320 if (!(vlanmc.member & BIT(i)))
1321 continue;
1322
1323 port->id = i;
1324 port->flags = (vlanmc.untag & BIT(i)) ?
1325 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1326 val->len++;
1327 port++;
1328 }
1329 return 0;
1330 }
1331
1332 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1333 struct switch_val *val)
1334 {
1335 struct rtl8366_vlan_mc vlanmc;
1336 struct rtl8366rb_vlan_4k vlan4k;
1337 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1338 struct switch_port *port;
1339 int i;
1340
1341 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1342 return -EINVAL;
1343
1344 rtl8366rb_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1345 rtl8366rb_get_vlan_4k(rtl, vlanmc.vid, &vlan4k);
1346
1347 vlanmc.untag = 0;
1348 vlanmc.member = 0;
1349
1350 port = &val->value.ports[0];
1351 for (i = 0; i < val->len; i++, port++) {
1352 vlanmc.member |= BIT(port->id);
1353
1354 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1355 vlanmc.untag |= BIT(port->id);
1356 }
1357
1358 vlan4k.member = vlanmc.member;
1359 vlan4k.untag = vlanmc.untag;
1360
1361 rtl8366rb_set_vlan_mc(rtl, val->port_vlan, &vlanmc);
1362 rtl8366rb_set_vlan_4k(rtl, &vlan4k);
1363 return 0;
1364 }
1365
1366 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1367 {
1368 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1369 return rtl8366rb_get_vlan_port_pvid(rtl, port, val);
1370 }
1371
1372 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1373 {
1374 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1375 return rtl8366rb_set_vlan_port_pvid(rtl, port, val);
1376 }
1377
1378 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1379 {
1380 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1381 int err;
1382
1383 err = rtl8366rb_reset_chip(rtl);
1384 if (err)
1385 return err;
1386
1387 return rtl8366rb_reset_vlan(rtl);
1388 }
1389
1390 static struct switch_attr rtl8366rb_globals[] = {
1391 {
1392 .type = SWITCH_TYPE_INT,
1393 .name = "enable_vlan",
1394 .description = "Enable VLAN mode",
1395 .set = rtl8366rb_sw_set_vlan_enable,
1396 .get = rtl8366rb_sw_get_vlan_enable,
1397 .max = 1,
1398 .ofs = 1
1399 }, {
1400 .type = SWITCH_TYPE_INT,
1401 .name = "enable_vlan4k",
1402 .description = "Enable VLAN 4K mode",
1403 .set = rtl8366rb_sw_set_vlan_enable,
1404 .get = rtl8366rb_sw_get_vlan_enable,
1405 .max = 1,
1406 .ofs = 2
1407 }, {
1408 .type = SWITCH_TYPE_INT,
1409 .name = "reset_mibs",
1410 .description = "Reset all MIB counters",
1411 .set = rtl8366rb_sw_reset_mibs,
1412 .get = NULL,
1413 .max = 1
1414 }, {
1415 .type = SWITCH_TYPE_INT,
1416 .name = "blinkrate",
1417 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1418 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1419 .set = rtl8366rb_sw_set_blinkrate,
1420 .get = rtl8366rb_sw_get_blinkrate,
1421 .max = 5
1422 },
1423 };
1424
1425 static struct switch_attr rtl8366rb_port[] = {
1426 {
1427 .type = SWITCH_TYPE_STRING,
1428 .name = "link",
1429 .description = "Get port link information",
1430 .max = 1,
1431 .set = NULL,
1432 .get = rtl8366rb_sw_get_port_link,
1433 }, {
1434 .type = SWITCH_TYPE_INT,
1435 .name = "reset_mib",
1436 .description = "Reset single port MIB counters",
1437 .max = 1,
1438 .set = rtl8366rb_sw_reset_port_mibs,
1439 .get = NULL,
1440 }, {
1441 .type = SWITCH_TYPE_STRING,
1442 .name = "mib",
1443 .description = "Get MIB counters for port",
1444 .max = 33,
1445 .set = NULL,
1446 .get = rtl8366rb_sw_get_port_mib,
1447 }, {
1448 .type = SWITCH_TYPE_INT,
1449 .name = "led",
1450 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1451 .max = 15,
1452 .set = rtl8366rb_sw_set_port_led,
1453 .get = rtl8366rb_sw_get_port_led,
1454 },
1455 };
1456
1457 static struct switch_attr rtl8366rb_vlan[] = {
1458 {
1459 .type = SWITCH_TYPE_STRING,
1460 .name = "info",
1461 .description = "Get vlan information",
1462 .max = 1,
1463 .set = NULL,
1464 .get = rtl8366rb_sw_get_vlan_info,
1465 },
1466 };
1467
1468 /* template */
1469 static struct switch_dev rtl8366_switch_dev = {
1470 .name = "RTL8366S",
1471 .cpu_port = RTL8366_PORT_NUM_CPU,
1472 .ports = RTL8366_NUM_PORTS,
1473 .vlans = RTL8366_NUM_VLANS,
1474 .attr_global = {
1475 .attr = rtl8366rb_globals,
1476 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1477 },
1478 .attr_port = {
1479 .attr = rtl8366rb_port,
1480 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1481 },
1482 .attr_vlan = {
1483 .attr = rtl8366rb_vlan,
1484 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1485 },
1486
1487 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1488 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1489 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1490 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1491 .reset_switch = rtl8366rb_sw_reset_switch,
1492 };
1493
1494 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1495 {
1496 struct switch_dev *dev = &rtl->dev;
1497 int err;
1498
1499 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1500 dev->priv = rtl;
1501 dev->devname = dev_name(rtl->parent);
1502
1503 err = register_switch(dev, NULL);
1504 if (err)
1505 dev_err(rtl->parent, "switch registration failed\n");
1506
1507 return err;
1508 }
1509
1510 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1511 {
1512 unregister_switch(&rtl->dev);
1513 }
1514
1515 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1516 {
1517 struct rtl8366_smi *smi = bus->priv;
1518 u32 val = 0;
1519 int err;
1520
1521 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1522 if (err)
1523 return 0xffff;
1524
1525 return val;
1526 }
1527
1528 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1529 {
1530 struct rtl8366_smi *smi = bus->priv;
1531 u32 t;
1532 int err;
1533
1534 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1535 /* flush write */
1536 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1537
1538 return err;
1539 }
1540
1541 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1542 {
1543 return (bus->read == rtl8366rb_mii_read &&
1544 bus->write == rtl8366rb_mii_write);
1545 }
1546
1547 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1548 {
1549 int ret;
1550
1551 ret = rtl8366rb_reset_chip(rtl);
1552 if (ret)
1553 return ret;
1554
1555 rtl8366rb_debugfs_init(rtl);
1556 return 0;
1557 }
1558
1559 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1560 {
1561 u32 chip_id = 0;
1562 u32 chip_ver = 0;
1563 int ret;
1564
1565 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1566 if (ret) {
1567 dev_err(smi->parent, "unable to read chip id\n");
1568 return ret;
1569 }
1570
1571 switch (chip_id) {
1572 case RTL8366S_CHIP_ID_8366:
1573 break;
1574 default:
1575 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1576 return -ENODEV;
1577 }
1578
1579 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1580 &chip_ver);
1581 if (ret) {
1582 dev_err(smi->parent, "unable to read chip version\n");
1583 return ret;
1584 }
1585
1586 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1587 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1588
1589 return 0;
1590 }
1591
1592 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1593 .detect = rtl8366rb_detect,
1594 .mii_read = rtl8366rb_mii_read,
1595 .mii_write = rtl8366rb_mii_write,
1596 };
1597
1598 static int __init rtl8366rb_probe(struct platform_device *pdev)
1599 {
1600 static int rtl8366_smi_version_printed;
1601 struct rtl8366rb_platform_data *pdata;
1602 struct rtl8366rb *rtl;
1603 struct rtl8366_smi *smi;
1604 int err;
1605
1606 if (!rtl8366_smi_version_printed++)
1607 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1608 " version " RTL8366S_DRIVER_VER"\n");
1609
1610 pdata = pdev->dev.platform_data;
1611 if (!pdata) {
1612 dev_err(&pdev->dev, "no platform data specified\n");
1613 err = -EINVAL;
1614 goto err_out;
1615 }
1616
1617 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1618 if (!rtl) {
1619 dev_err(&pdev->dev, "no memory for private data\n");
1620 err = -ENOMEM;
1621 goto err_out;
1622 }
1623
1624 rtl->parent = &pdev->dev;
1625
1626 smi = &rtl->smi;
1627 smi->parent = &pdev->dev;
1628 smi->gpio_sda = pdata->gpio_sda;
1629 smi->gpio_sck = pdata->gpio_sck;
1630 smi->ops = &rtl8366rb_smi_ops;
1631
1632 err = rtl8366_smi_init(smi);
1633 if (err)
1634 goto err_free_rtl;
1635
1636 platform_set_drvdata(pdev, rtl);
1637
1638 err = rtl8366rb_setup(rtl);
1639 if (err)
1640 goto err_clear_drvdata;
1641
1642 err = rtl8366rb_switch_init(rtl);
1643 if (err)
1644 goto err_clear_drvdata;
1645
1646 return 0;
1647
1648 err_clear_drvdata:
1649 platform_set_drvdata(pdev, NULL);
1650 rtl8366_smi_cleanup(smi);
1651 err_free_rtl:
1652 kfree(rtl);
1653 err_out:
1654 return err;
1655 }
1656
1657 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1658 {
1659 if (!rtl8366rb_mii_bus_match(phydev->bus))
1660 return -EINVAL;
1661
1662 return 0;
1663 }
1664
1665 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1666 {
1667 return 0;
1668 }
1669
1670 static struct phy_driver rtl8366rb_phy_driver = {
1671 .phy_id = 0x001cc960,
1672 .name = "Realtek RTL8366RB",
1673 .phy_id_mask = 0x1ffffff0,
1674 .features = PHY_GBIT_FEATURES,
1675 .config_aneg = rtl8366rb_phy_config_aneg,
1676 .config_init = rtl8366rb_phy_config_init,
1677 .read_status = genphy_read_status,
1678 .driver = {
1679 .owner = THIS_MODULE,
1680 },
1681 };
1682
1683 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1684 {
1685 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1686
1687 if (rtl) {
1688 rtl8366rb_switch_cleanup(rtl);
1689 rtl8366rb_debugfs_remove(rtl);
1690 platform_set_drvdata(pdev, NULL);
1691 rtl8366_smi_cleanup(&rtl->smi);
1692 kfree(rtl);
1693 }
1694
1695 return 0;
1696 }
1697
1698 static struct platform_driver rtl8366rb_driver = {
1699 .driver = {
1700 .name = RTL8366RB_DRIVER_NAME,
1701 .owner = THIS_MODULE,
1702 },
1703 .probe = rtl8366rb_probe,
1704 .remove = __devexit_p(rtl8366rb_remove),
1705 };
1706
1707 static int __init rtl8366rb_module_init(void)
1708 {
1709 int ret;
1710 ret = platform_driver_register(&rtl8366rb_driver);
1711 if (ret)
1712 return ret;
1713
1714 ret = phy_driver_register(&rtl8366rb_phy_driver);
1715 if (ret)
1716 goto err_platform_unregister;
1717
1718 return 0;
1719
1720 err_platform_unregister:
1721 platform_driver_unregister(&rtl8366rb_driver);
1722 return ret;
1723 }
1724 module_init(rtl8366rb_module_init);
1725
1726 static void __exit rtl8366rb_module_exit(void)
1727 {
1728 phy_driver_unregister(&rtl8366rb_phy_driver);
1729 platform_driver_unregister(&rtl8366rb_driver);
1730 }
1731 module_exit(rtl8366rb_module_exit);
1732
1733 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1734 MODULE_VERSION(RTL8366S_DRIVER_VER);
1735 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1736 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1737 MODULE_LICENSE("GPL v2");
1738 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
Personal OpenWRT clone
This page took 0.123442 seconds and 3 git commands to generate.