target/linux/generic-2.4/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h

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  64
  65
  66 #ifndef __INCmvDramIfh
  67 #define __INCmvDramIfh
  68
  69 /* includes */
  70 #include "ddr1_2/mvDramIfRegs.h"
  71 #include "ddr1_2/mvDramIfConfig.h"
  72 #include "ctrlEnv/mvCtrlEnvLib.h"
  73
  74 /* defines  */
  75 /* DRAM Timing parameters */
  76 #define SDRAM_TWR                    15  /* ns tWr */
  77 #define SDRAM_TRFC_64_512M_AT_200MHZ 70  /* ns tRfc for dens 64-512 @ 200MHz */
  78 #define SDRAM_TRFC_64_512M           75  /* ns tRfc for dens 64-512          */
  79 #define SDRAM_TRFC_1G                120 /* ns tRfc for dens 1GB             */
  80 #define SDRAM_TR2R_CYC               1   /* cycle for tR2r                   */
  81 #define SDRAM_TR2WW2R_CYC            1   /* cycle for tR2wW2r                */
  82
  83 /* typedefs */
  84
  85 /* enumeration for memory types */
  86 typedef enum _mvMemoryType
  87 {
  88     MEM_TYPE_SDRAM,
  89     MEM_TYPE_DDR1,
  90     MEM_TYPE_DDR2
  91 }MV_MEMORY_TYPE;
  92
  93 /* enumeration for DDR1 supported CAS Latencies */
  94 typedef enum _mvDimmDdr1Cas
  95 {
  96     DDR1_CL_1_5  = 0x02,
  97     DDR1_CL_2    = 0x04,
  98     DDR1_CL_2_5  = 0x08,
  99     DDR1_CL_3    = 0x10,
 100     DDR1_CL_4    = 0x40,
 101     DDR1_CL_FAULT
 102 } MV_DIMM_DDR1_CAS;
 103
 104 /* enumeration for DDR2 supported CAS Latencies */
 105 typedef enum _mvDimmDdr2Cas
 106 {
 107     DDR2_CL_3    = 0x08,
 108     DDR2_CL_4    = 0x10,
 109     DDR2_CL_5    = 0x20,
 110     DDR2_CL_FAULT
 111 } MV_DIMM_DDR2_CAS;
 112
 113
 114 typedef struct _mvDramBankInfo
 115 {
 116     MV_MEMORY_TYPE  memoryType;         /* DDR1, DDR2 or SDRAM */
 117
 118     /* DIMM dimensions */
 119     MV_U32  numOfRowAddr;
 120     MV_U32  numOfColAddr;
 121     MV_U32  dataWidth;
 122     MV_U32  errorCheckType;             /* ECC , PARITY..*/
 123     MV_U32  sdramWidth;                 /* 4,8,16 or 32 */
 124     MV_U32  errorCheckDataWidth;        /* 0 - no, 1 - Yes */
 125     MV_U32  burstLengthSupported;
 126     MV_U32  numOfBanksOnEachDevice;
 127     MV_U32  suportedCasLatencies;
 128     MV_U32  refreshInterval;
 129
 130     /* DIMM timing parameters */
 131     MV_U32  minCycleTimeAtMaxCasLatPs;
 132     MV_U32  minCycleTimeAtMaxCasLatMinus1Ps;
 133     MV_U32  minCycleTimeAtMaxCasLatMinus2Ps;
 134         MV_U32  minRowPrechargeTime;
 135         MV_U32  minRowActiveToRowActive;
 136         MV_U32  minRasToCasDelay;
 137         MV_U32  minRasPulseWidth;
 138     MV_U32  minWriteRecoveryTime;   /* DDR2 only */
 139     MV_U32  minWriteToReadCmdDelay; /* DDR2 only */
 140     MV_U32  minReadToPrechCmdDelay; /* DDR2 only */
 141     MV_U32  minRefreshToActiveCmd;  /* DDR2 only */
 142
 143     /* Parameters calculated from the extracted DIMM information */
 144     MV_U32  size;
 145     MV_U32  deviceDensity;              /* 16,64,128,256 or 512 Mbit */
 146     MV_U32  numberOfDevices;
 147
 148     /* DIMM attributes (MV_TRUE for yes) */
 149     MV_BOOL registeredAddrAndControlInputs;
 150
 151 }MV_DRAM_BANK_INFO;
 152
 153 /* This structure describes CPU interface address decode window               */
 154 typedef struct _mvDramIfDecWin
 155 {
 156         MV_ADDR_WIN   addrWin;    /* An address window*/
 157         MV_BOOL       enable;     /* Address decode window is enabled/disabled    */
 158 }MV_DRAM_DEC_WIN;
 159
 160 #include "ddr1_2/mvDram.h"
 161
 162 /* mvDramIf.h API list */
 163 MV_VOID   mvDramIfBasicAsmInit(MV_VOID);
 164 MV_STATUS mvDramIfDetect(MV_U32 forcedCl);
 165 MV_VOID   _mvDramIfConfig(MV_VOID);
 166
 167 MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
 168 MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin);
 169 MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable);
 170 MV_32 mvDramIfBankSizeGet(MV_U32 bankNum);
 171 MV_32 mvDramIfBankBaseGet(MV_U32 bankNum);
 172 MV_32 mvDramIfSizeGet(MV_VOID);
 173
 174 #if 0
 175 MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray);
 176 MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable);
 177 #endif
 178
 179 #endif /* __INCmvDramIfh */