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8e4ac19ab1980da21b1d2f733932a6fa36841ab3
[openwrt.git] / target / linux / generic / patches-2.6.39 / 020-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
4 if (!ccdev)
5 return;
6 bus = ccdev->bus;
7 +
8 + /* We support SLOW only on 6..9 */
9 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
10 + mode = SSB_CLKMODE_DYNAMIC;
11 +
12 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
13 + return; /* PMU controls clockmode, separated function needed */
14 + SSB_WARN_ON(ccdev->id.revision >= 20);
15 +
16 /* chipcommon cores prior to rev6 don't support dynamic clock control */
17 if (ccdev->id.revision < 6)
18 return;
19 - /* chipcommon cores rev10 are a whole new ball game */
20 +
21 + /* ChipCommon cores rev10+ need testing */
22 if (ccdev->id.revision >= 10)
23 return;
24 +
25 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
26 return;
27
28 switch (mode) {
29 - case SSB_CLKMODE_SLOW:
30 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
31 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
32 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
33 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
34 break;
35 case SSB_CLKMODE_FAST:
36 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
37 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
38 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
39 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
40 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
41 + if (ccdev->id.revision < 10) {
42 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
43 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
44 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
45 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
46 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
47 + } else {
48 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
49 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
50 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
51 + /* udelay(150); TODO: not available in early init */
52 + }
53 break;
54 case SSB_CLKMODE_DYNAMIC:
55 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
56 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
57 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
58 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
59 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
60 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
61 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
62 -
63 - /* for dynamic control, we have to release our xtal_pu "force on" */
64 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
65 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
66 + if (ccdev->id.revision < 10) {
67 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
68 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
69 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
70 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
71 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
72 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
73 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
74 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
75 +
76 + /* For dynamic control, we have to release our xtal_pu
77 + * "force on" */
78 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
79 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
80 + } else {
81 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
82 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
83 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
84 + }
85 break;
86 default:
87 SSB_WARN_ON(1);
88 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
89 if (cc->dev->id.revision >= 11)
90 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
91 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
92 +
93 + if (cc->dev->id.revision >= 20) {
94 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
95 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
96 + }
97 +
98 ssb_pmu_init(cc);
99 chipco_powercontrol_init(cc);
100 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
101 --- a/drivers/ssb/driver_chipcommon_pmu.c
102 +++ b/drivers/ssb/driver_chipcommon_pmu.c
103 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
104 u32 min_msk = 0, max_msk = 0;
105 unsigned int i;
106 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
107 - unsigned int updown_tab_size;
108 + unsigned int updown_tab_size = 0;
109 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
110 - unsigned int depend_tab_size;
111 + unsigned int depend_tab_size = 0;
112
113 switch (bus->chip_id) {
114 case 0x4312:
115 + min_msk = 0xCBB;
116 + break;
117 case 0x4322:
118 /* We keep the default settings:
119 * min_msk = 0xCBB
120 --- a/drivers/ssb/driver_gige.c
121 +++ b/drivers/ssb/driver_gige.c
122 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
123 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
124 }
125
126 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
127 - int reg, int size, u32 *val)
128 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
129 + unsigned int devfn, int reg,
130 + int size, u32 *val)
131 {
132 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
133 unsigned long flags;
134 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
135 return PCIBIOS_SUCCESSFUL;
136 }
137
138 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
139 - int reg, int size, u32 val)
140 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
141 + unsigned int devfn, int reg,
142 + int size, u32 val)
143 {
144 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
145 unsigned long flags;
146 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
147 return PCIBIOS_SUCCESSFUL;
148 }
149
150 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
151 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
152 + const struct ssb_device_id *id)
153 {
154 struct ssb_gige *dev;
155 u32 base, tmslow, tmshigh;
156 --- a/drivers/ssb/driver_pcicore.c
157 +++ b/drivers/ssb/driver_pcicore.c
158 @@ -15,6 +15,11 @@
159
160 #include "ssb_private.h"
161
162 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
163 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
164 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
165 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
166 + u8 address, u16 data);
167
168 static inline
169 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
170 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
171 return ssb_mips_irq(extpci_core->dev) + 2;
172 }
173
174 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
175 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
176 {
177 u32 val;
178
179 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
180 register_pci_controller(&ssb_pcicore_controller);
181 }
182
183 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
184 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
185 {
186 struct ssb_bus *bus = pc->dev->bus;
187 u16 chipid_top;
188 @@ -403,28 +408,129 @@ static int pcicore_is_in_hostmode(struct
189 }
190 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
191
192 +/**************************************************
193 + * Workarounds.
194 + **************************************************/
195 +
196 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
197 +{
198 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
199 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
200 + tmp &= ~0xF000;
201 + tmp |= (pc->dev->core_index << 12);
202 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
203 + }
204 +}
205 +
206 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
207 +{
208 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
209 +}
210 +
211 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
212 +{
213 + const u8 serdes_pll_device = 0x1D;
214 + const u8 serdes_rx_device = 0x1F;
215 + u16 tmp;
216 +
217 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
218 + ssb_pcicore_polarity_workaround(pc));
219 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
220 + if (tmp & 0x4000)
221 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
222 +}
223 +
224 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
225 +{
226 + struct ssb_device *pdev = pc->dev;
227 + struct ssb_bus *bus = pdev->bus;
228 + u32 tmp;
229 +
230 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
231 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
232 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
233 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
234 +
235 + if (pdev->id.revision < 5) {
236 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
237 + tmp &= ~SSB_IMCFGLO_SERTO;
238 + tmp |= 2;
239 + tmp &= ~SSB_IMCFGLO_REQTO;
240 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
241 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
242 + ssb_commit_settings(bus);
243 + } else if (pdev->id.revision >= 11) {
244 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
245 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
246 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
247 + }
248 +}
249 +
250 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
251 +{
252 + u32 tmp;
253 + u8 rev = pc->dev->id.revision;
254 +
255 + if (rev == 0 || rev == 1) {
256 + /* TLP Workaround register. */
257 + tmp = ssb_pcie_read(pc, 0x4);
258 + tmp |= 0x8;
259 + ssb_pcie_write(pc, 0x4, tmp);
260 + }
261 + if (rev == 1) {
262 + /* DLLP Link Control register. */
263 + tmp = ssb_pcie_read(pc, 0x100);
264 + tmp |= 0x40;
265 + ssb_pcie_write(pc, 0x100, tmp);
266 + }
267 +
268 + if (rev == 0) {
269 + const u8 serdes_rx_device = 0x1F;
270 +
271 + ssb_pcie_mdio_write(pc, serdes_rx_device,
272 + 2 /* Timer */, 0x8128);
273 + ssb_pcie_mdio_write(pc, serdes_rx_device,
274 + 6 /* CDR */, 0x0100);
275 + ssb_pcie_mdio_write(pc, serdes_rx_device,
276 + 7 /* CDR BW */, 0x1466);
277 + } else if (rev == 3 || rev == 4 || rev == 5) {
278 + /* TODO: DLLP Power Management Threshold */
279 + ssb_pcicore_serdes_workaround(pc);
280 + /* TODO: ASPM */
281 + } else if (rev == 7) {
282 + /* TODO: No PLL down */
283 + }
284 +
285 + if (rev >= 6) {
286 + /* Miscellaneous Configuration Fixup */
287 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
288 + if (!(tmp & 0x8000))
289 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
290 + tmp | 0x8000);
291 + }
292 +}
293
294 /**************************************************
295 * Generic and Clientmode operation code.
296 **************************************************/
297
298 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
299 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
300 {
301 /* Disable PCI interrupts. */
302 ssb_write32(pc->dev, SSB_INTVEC, 0);
303 }
304
305 -void ssb_pcicore_init(struct ssb_pcicore *pc)
306 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
307 {
308 struct ssb_device *dev = pc->dev;
309 - struct ssb_bus *bus;
310
311 if (!dev)
312 return;
313 - bus = dev->bus;
314 if (!ssb_device_is_enabled(dev))
315 ssb_device_enable(dev, 0);
316
317 + ssb_pcicore_fix_sprom_core_index(pc);
318 +
319 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
320 pc->hostmode = pcicore_is_in_hostmode(pc);
321 if (pc->hostmode)
322 @@ -432,6 +538,13 @@ void ssb_pcicore_init(struct ssb_pcicore
323 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
324 if (!pc->hostmode)
325 ssb_pcicore_init_clientmode(pc);
326 +
327 + /* Additional PCIe always once-executed workarounds */
328 + if (dev->id.coreid == SSB_DEV_PCIE) {
329 + ssb_pcicore_serdes_workaround(pc);
330 + /* TODO: ASPM */
331 + /* TODO: Clock Request Update */
332 + }
333 }
334
335 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
336 @@ -446,11 +559,35 @@ static void ssb_pcie_write(struct ssb_pc
337 pcicore_write32(pc, 0x134, data);
338 }
339
340 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
341 - u8 address, u16 data)
342 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
343 +{
344 + const u16 mdio_control = 0x128;
345 + const u16 mdio_data = 0x12C;
346 + u32 v;
347 + int i;
348 +
349 + v = (1 << 30); /* Start of Transaction */
350 + v |= (1 << 28); /* Write Transaction */
351 + v |= (1 << 17); /* Turnaround */
352 + v |= (0x1F << 18);
353 + v |= (phy << 4);
354 + pcicore_write32(pc, mdio_data, v);
355 +
356 + udelay(10);
357 + for (i = 0; i < 200; i++) {
358 + v = pcicore_read32(pc, mdio_control);
359 + if (v & 0x100 /* Trans complete */)
360 + break;
361 + msleep(1);
362 + }
363 +}
364 +
365 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
366 {
367 const u16 mdio_control = 0x128;
368 const u16 mdio_data = 0x12C;
369 + int max_retries = 10;
370 + u16 ret = 0;
371 u32 v;
372 int i;
373
374 @@ -458,46 +595,68 @@ static void ssb_pcie_mdio_write(struct s
375 v |= 0x2; /* MDIO Clock Divisor */
376 pcicore_write32(pc, mdio_control, v);
377
378 + if (pc->dev->id.revision >= 10) {
379 + max_retries = 200;
380 + ssb_pcie_mdio_set_phy(pc, device);
381 + }
382 +
383 v = (1 << 30); /* Start of Transaction */
384 - v |= (1 << 28); /* Write Transaction */
385 + v |= (1 << 29); /* Read Transaction */
386 v |= (1 << 17); /* Turnaround */
387 - v |= (u32)device << 22;
388 + if (pc->dev->id.revision < 10)
389 + v |= (u32)device << 22;
390 v |= (u32)address << 18;
391 - v |= data;
392 pcicore_write32(pc, mdio_data, v);
393 /* Wait for the device to complete the transaction */
394 udelay(10);
395 - for (i = 0; i < 10; i++) {
396 + for (i = 0; i < max_retries; i++) {
397 v = pcicore_read32(pc, mdio_control);
398 - if (v & 0x100 /* Trans complete */)
399 + if (v & 0x100 /* Trans complete */) {
400 + udelay(10);
401 + ret = pcicore_read32(pc, mdio_data);
402 break;
403 + }
404 msleep(1);
405 }
406 pcicore_write32(pc, mdio_control, 0);
407 + return ret;
408 }
409
410 -static void ssb_broadcast_value(struct ssb_device *dev,
411 - u32 address, u32 data)
412 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
413 + u8 address, u16 data)
414 {
415 - /* This is used for both, PCI and ChipCommon core, so be careful. */
416 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
417 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
418 + const u16 mdio_control = 0x128;
419 + const u16 mdio_data = 0x12C;
420 + int max_retries = 10;
421 + u32 v;
422 + int i;
423
424 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
425 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
426 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
427 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
428 -}
429 + v = 0x80; /* Enable Preamble Sequence */
430 + v |= 0x2; /* MDIO Clock Divisor */
431 + pcicore_write32(pc, mdio_control, v);
432
433 -static void ssb_commit_settings(struct ssb_bus *bus)
434 -{
435 - struct ssb_device *dev;
436 + if (pc->dev->id.revision >= 10) {
437 + max_retries = 200;
438 + ssb_pcie_mdio_set_phy(pc, device);
439 + }
440
441 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
442 - if (WARN_ON(!dev))
443 - return;
444 - /* This forces an update of the cached registers. */
445 - ssb_broadcast_value(dev, 0xFD8, 0);
446 + v = (1 << 30); /* Start of Transaction */
447 + v |= (1 << 28); /* Write Transaction */
448 + v |= (1 << 17); /* Turnaround */
449 + if (pc->dev->id.revision < 10)
450 + v |= (u32)device << 22;
451 + v |= (u32)address << 18;
452 + v |= data;
453 + pcicore_write32(pc, mdio_data, v);
454 + /* Wait for the device to complete the transaction */
455 + udelay(10);
456 + for (i = 0; i < max_retries; i++) {
457 + v = pcicore_read32(pc, mdio_control);
458 + if (v & 0x100 /* Trans complete */)
459 + break;
460 + msleep(1);
461 + }
462 + pcicore_write32(pc, mdio_control, 0);
463 }
464
465 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
466 @@ -550,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
467 if (pc->setup_done)
468 goto out;
469 if (pdev->id.coreid == SSB_DEV_PCI) {
470 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
471 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
472 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
473 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
474 -
475 - if (pdev->id.revision < 5) {
476 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
477 - tmp &= ~SSB_IMCFGLO_SERTO;
478 - tmp |= 2;
479 - tmp &= ~SSB_IMCFGLO_REQTO;
480 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
481 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
482 - ssb_commit_settings(bus);
483 - } else if (pdev->id.revision >= 11) {
484 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
485 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
486 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
487 - }
488 + ssb_pcicore_pci_setup_workarounds(pc);
489 } else {
490 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
491 - //TODO: Better make defines for all these magic PCIE values.
492 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
493 - /* TLP Workaround register. */
494 - tmp = ssb_pcie_read(pc, 0x4);
495 - tmp |= 0x8;
496 - ssb_pcie_write(pc, 0x4, tmp);
497 - }
498 - if (pdev->id.revision == 0) {
499 - const u8 serdes_rx_device = 0x1F;
500 -
501 - ssb_pcie_mdio_write(pc, serdes_rx_device,
502 - 2 /* Timer */, 0x8128);
503 - ssb_pcie_mdio_write(pc, serdes_rx_device,
504 - 6 /* CDR */, 0x0100);
505 - ssb_pcie_mdio_write(pc, serdes_rx_device,
506 - 7 /* CDR BW */, 0x1466);
507 - } else if (pdev->id.revision == 1) {
508 - /* DLLP Link Control register. */
509 - tmp = ssb_pcie_read(pc, 0x100);
510 - tmp |= 0x40;
511 - ssb_pcie_write(pc, 0x100, tmp);
512 - }
513 + ssb_pcicore_pcie_setup_workarounds(pc);
514 }
515 pc->setup_done = 1;
516 out:
517 --- a/drivers/ssb/main.c
518 +++ b/drivers/ssb/main.c
519 @@ -557,7 +557,7 @@ error:
520 }
521
522 /* Needs ssb_buses_lock() */
523 -static int ssb_attach_queued_buses(void)
524 +static int __devinit ssb_attach_queued_buses(void)
525 {
526 struct ssb_bus *bus, *n;
527 int err = 0;
528 @@ -768,9 +768,9 @@ out:
529 return err;
530 }
531
532 -static int ssb_bus_register(struct ssb_bus *bus,
533 - ssb_invariants_func_t get_invariants,
534 - unsigned long baseaddr)
535 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
536 + ssb_invariants_func_t get_invariants,
537 + unsigned long baseaddr)
538 {
539 int err;
540
541 @@ -851,8 +851,8 @@ err_disable_xtal:
542 }
543
544 #ifdef CONFIG_SSB_PCIHOST
545 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
546 - struct pci_dev *host_pci)
547 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
548 + struct pci_dev *host_pci)
549 {
550 int err;
551
552 @@ -875,9 +875,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
553 #endif /* CONFIG_SSB_PCIHOST */
554
555 #ifdef CONFIG_SSB_PCMCIAHOST
556 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
557 - struct pcmcia_device *pcmcia_dev,
558 - unsigned long baseaddr)
559 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
560 + struct pcmcia_device *pcmcia_dev,
561 + unsigned long baseaddr)
562 {
563 int err;
564
565 @@ -897,8 +897,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
566 #endif /* CONFIG_SSB_PCMCIAHOST */
567
568 #ifdef CONFIG_SSB_SDIOHOST
569 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
570 - unsigned int quirks)
571 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
572 + struct sdio_func *func,
573 + unsigned int quirks)
574 {
575 int err;
576
577 @@ -918,9 +919,9 @@ int ssb_bus_sdiobus_register(struct ssb_
578 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
579 #endif /* CONFIG_SSB_PCMCIAHOST */
580
581 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
582 - unsigned long baseaddr,
583 - ssb_invariants_func_t get_invariants)
584 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
585 + unsigned long baseaddr,
586 + ssb_invariants_func_t get_invariants)
587 {
588 int err;
589
590 @@ -1001,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
591 switch (plltype) {
592 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
593 if (m & SSB_CHIPCO_CLK_T6_MMASK)
594 - return SSB_CHIPCO_CLK_T6_M0;
595 - return SSB_CHIPCO_CLK_T6_M1;
596 + return SSB_CHIPCO_CLK_T6_M1;
597 + return SSB_CHIPCO_CLK_T6_M0;
598 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
599 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
600 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
601 @@ -1117,23 +1118,22 @@ static u32 ssb_tmslow_reject_bitmask(str
602 {
603 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
604
605 - /* The REJECT bit changed position in TMSLOW between
606 - * Backplane revisions. */
607 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
608 switch (rev) {
609 case SSB_IDLOW_SSBREV_22:
610 - return SSB_TMSLOW_REJECT_22;
611 + case SSB_IDLOW_SSBREV_24:
612 + case SSB_IDLOW_SSBREV_26:
613 + return SSB_TMSLOW_REJECT;
614 case SSB_IDLOW_SSBREV_23:
615 return SSB_TMSLOW_REJECT_23;
616 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
617 - case SSB_IDLOW_SSBREV_25: /* same here */
618 - case SSB_IDLOW_SSBREV_26: /* same here */
619 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
620 case SSB_IDLOW_SSBREV_27: /* same here */
621 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
622 + return SSB_TMSLOW_REJECT; /* this is a guess */
623 default:
624 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
625 WARN_ON(1);
626 }
627 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
628 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
629 }
630
631 int ssb_device_is_enabled(struct ssb_device *dev)
632 @@ -1309,20 +1309,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
633
634 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
635 {
636 - struct ssb_chipcommon *cc;
637 int err;
638 enum ssb_clkmode mode;
639
640 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
641 if (err)
642 goto error;
643 - cc = &bus->chipco;
644 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
645 - ssb_chipco_set_clockmode(cc, mode);
646
647 #ifdef CONFIG_SSB_DEBUG
648 bus->powered_up = 1;
649 #endif
650 +
651 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
652 + ssb_chipco_set_clockmode(&bus->chipco, mode);
653 +
654 return 0;
655 error:
656 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
657 @@ -1330,6 +1330,37 @@ error:
658 }
659 EXPORT_SYMBOL(ssb_bus_powerup);
660
661 +static void ssb_broadcast_value(struct ssb_device *dev,
662 + u32 address, u32 data)
663 +{
664 +#ifdef CONFIG_SSB_DRIVER_PCICORE
665 + /* This is used for both, PCI and ChipCommon core, so be careful. */
666 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
667 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
668 +#endif
669 +
670 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
671 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
672 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
673 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
674 +}
675 +
676 +void ssb_commit_settings(struct ssb_bus *bus)
677 +{
678 + struct ssb_device *dev;
679 +
680 +#ifdef CONFIG_SSB_DRIVER_PCICORE
681 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
682 +#else
683 + dev = bus->chipco.dev;
684 +#endif
685 + if (WARN_ON(!dev))
686 + return;
687 + /* This forces an update of the cached registers. */
688 + ssb_broadcast_value(dev, 0xFD8, 0);
689 +}
690 +EXPORT_SYMBOL(ssb_commit_settings);
691 +
692 u32 ssb_admatch_base(u32 adm)
693 {
694 u32 base = 0;
695 --- a/drivers/ssb/pci.c
696 +++ b/drivers/ssb/pci.c
697 @@ -662,7 +662,6 @@ static int sprom_extract(struct ssb_bus
698 static int ssb_pci_sprom_get(struct ssb_bus *bus,
699 struct ssb_sprom *sprom)
700 {
701 - const struct ssb_sprom *fallback;
702 int err;
703 u16 *buf;
704
705 @@ -707,10 +706,17 @@ static int ssb_pci_sprom_get(struct ssb_
706 if (err) {
707 /* All CRC attempts failed.
708 * Maybe there is no SPROM on the device?
709 - * If we have a fallback, use that. */
710 - fallback = ssb_get_fallback_sprom();
711 - if (fallback) {
712 - memcpy(sprom, fallback, sizeof(*sprom));
713 + * Now we ask the arch code if there is some sprom
714 + * available for this device in some other storage */
715 + err = ssb_fill_sprom_with_fallback(bus, sprom);
716 + if (err) {
717 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
718 + " fallback SPROM failed (err %d)\n",
719 + err);
720 + } else {
721 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
722 + " revision %d provided by"
723 + " platform.\n", sprom->revision);
724 err = 0;
725 goto out_free;
726 }
727 --- a/drivers/ssb/pcihost_wrapper.c
728 +++ b/drivers/ssb/pcihost_wrapper.c
729 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
730 # define ssb_pcihost_resume NULL
731 #endif /* CONFIG_PM */
732
733 -static int ssb_pcihost_probe(struct pci_dev *dev,
734 - const struct pci_device_id *id)
735 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
736 + const struct pci_device_id *id)
737 {
738 struct ssb_bus *ssb;
739 int err = -ENOMEM;
740 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
741 pci_set_drvdata(dev, NULL);
742 }
743
744 -int ssb_pcihost_register(struct pci_driver *driver)
745 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
746 {
747 driver->probe = ssb_pcihost_probe;
748 driver->remove = ssb_pcihost_remove;
749 --- a/drivers/ssb/scan.c
750 +++ b/drivers/ssb/scan.c
751 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
752 #ifdef CONFIG_SSB_PCIHOST
753 if (bus->bustype == SSB_BUSTYPE_PCI) {
754 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
755 - bus->host_pci->device == 0x4324)
756 + ((bus->host_pci->device == 0x4313) ||
757 + (bus->host_pci->device == 0x431A) ||
758 + (bus->host_pci->device == 0x4321) ||
759 + (bus->host_pci->device == 0x4324)))
760 return 1;
761 }
762 #endif /* CONFIG_SSB_PCIHOST */
763 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
764 } else {
765 if (bus->bustype == SSB_BUSTYPE_PCI) {
766 bus->chip_id = pcidev_to_chipid(bus->host_pci);
767 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
768 - &bus->chip_rev);
769 + bus->chip_rev = bus->host_pci->revision;
770 bus->chip_package = 0;
771 } else {
772 bus->chip_id = 0x4710;
773 --- a/drivers/ssb/sprom.c
774 +++ b/drivers/ssb/sprom.c
775 @@ -17,7 +17,7 @@
776 #include <linux/slab.h>
777
778
779 -static const struct ssb_sprom *fallback_sprom;
780 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
781
782
783 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
784 @@ -145,36 +145,43 @@ out:
785 }
786
787 /**
788 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
789 + * ssb_arch_register_fallback_sprom - Registers a method providing a
790 + * fallback SPROM if no SPROM is found.
791 *
792 - * @sprom: The SPROM data structure to register.
793 + * @sprom_callback: The callback function.
794 *
795 - * With this function the architecture implementation may register a fallback
796 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
797 - * where no valid SPROM can be found in the shadow registers.
798 + * With this function the architecture implementation may register a
799 + * callback handler which fills the SPROM data structure. The fallback is
800 + * only used for PCI based SSB devices, where no valid SPROM can be found
801 + * in the shadow registers.
802 *
803 - * This function is useful for weird architectures that have a half-assed SSB device
804 - * hardwired to their PCI bus.
805 + * This function is useful for weird architectures that have a half-assed
806 + * SSB device hardwired to their PCI bus.
807 *
808 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
809 - * don't use this fallback.
810 - * Architectures must provide the SPROM for native SSB devices anyway,
811 - * so the fallback also isn't used for native devices.
812 + * Note that it does only work with PCI attached SSB devices. PCMCIA
813 + * devices currently don't use this fallback.
814 + * Architectures must provide the SPROM for native SSB devices anyway, so
815 + * the fallback also isn't used for native devices.
816 *
817 - * This function is available for architecture code, only. So it is not exported.
818 + * This function is available for architecture code, only. So it is not
819 + * exported.
820 */
821 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
822 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
823 + struct ssb_sprom *out))
824 {
825 - if (fallback_sprom)
826 + if (get_fallback_sprom)
827 return -EEXIST;
828 - fallback_sprom = sprom;
829 + get_fallback_sprom = sprom_callback;
830
831 return 0;
832 }
833
834 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
835 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
836 {
837 - return fallback_sprom;
838 + if (!get_fallback_sprom)
839 + return -ENOENT;
840 +
841 + return get_fallback_sprom(bus, out);
842 }
843
844 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
845 --- a/drivers/ssb/ssb_private.h
846 +++ b/drivers/ssb/ssb_private.h
847 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
848 const char *buf, size_t count,
849 int (*sprom_check_crc)(const u16 *sprom, size_t size),
850 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
851 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
852 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
853 + struct ssb_sprom *out);
854
855
856 /* core.c */
857 --- a/include/linux/ssb/ssb.h
858 +++ b/include/linux/ssb/ssb.h
859 @@ -308,7 +308,7 @@ struct ssb_bus {
860
861 /* ID information about the Chip. */
862 u16 chip_id;
863 - u16 chip_rev;
864 + u8 chip_rev;
865 u16 sprom_offset;
866 u16 sprom_size; /* number of words in sprom */
867 u8 chip_package;
868 @@ -404,7 +404,9 @@ extern bool ssb_is_sprom_available(struc
869
870 /* Set a fallback SPROM.
871 * See kdoc at the function definition for complete documentation. */
872 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
873 +extern int ssb_arch_register_fallback_sprom(
874 + int (*sprom_callback)(struct ssb_bus *bus,
875 + struct ssb_sprom *out));
876
877 /* Suspend a SSB bus.
878 * Call this from the parent bus suspend routine. */
879 @@ -518,6 +520,7 @@ extern int ssb_bus_may_powerdown(struct
880 * Otherwise static always-on powercontrol will be used. */
881 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
882
883 +extern void ssb_commit_settings(struct ssb_bus *bus);
884
885 /* Various helper functions */
886 extern u32 ssb_admatch_base(u32 adm);
887 --- a/include/linux/ssb/ssb_driver_chipcommon.h
888 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
889 @@ -123,6 +123,8 @@
890 #define SSB_CHIPCO_FLASHDATA 0x0048
891 #define SSB_CHIPCO_BCAST_ADDR 0x0050
892 #define SSB_CHIPCO_BCAST_DATA 0x0054
893 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
894 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
895 #define SSB_CHIPCO_GPIOIN 0x0060
896 #define SSB_CHIPCO_GPIOOUT 0x0064
897 #define SSB_CHIPCO_GPIOOUTEN 0x0068
898 @@ -131,6 +133,9 @@
899 #define SSB_CHIPCO_GPIOIRQ 0x0074
900 #define SSB_CHIPCO_WATCHDOG 0x0080
901 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
902 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
903 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
904 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
905 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
906 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
907 #define SSB_CHIPCO_CLOCK_N 0x0090
908 @@ -189,8 +194,10 @@
909 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
910 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
911 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
912 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
913 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
914 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
915 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
916 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
917 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
918 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
919 #define SSB_CHIPCO_UART0_DATA 0x0300
920 #define SSB_CHIPCO_UART0_IMR 0x0304
921 --- a/include/linux/ssb/ssb_regs.h
922 +++ b/include/linux/ssb/ssb_regs.h
923 @@ -97,7 +97,7 @@
924 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
925 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
926 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
927 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
928 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
929 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
930 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
931 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
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