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[openwrt.git] / target / linux / at91-2.6 / patches / 000-at91patches.patch
1 diff -urN -x CVS linux-2.6.21/arch/arm/boot/compressed/head-at91rm9200.S linux-2.6-stable/arch/arm/boot/compressed/head-at91rm9200.S
2 --- linux-2.6.21/arch/arm/boot/compressed/head-at91rm9200.S Thu Apr 26 05:08:32 2007
3 +++ linux-2.6-stable/arch/arm/boot/compressed/head-at91rm9200.S Tue May 8 12:13:30 2007
4 @@ -67,6 +67,12 @@
5 cmp r7, r3
6 beq 99f
7
8 + @ Promwad Chub : 1181
9 + mov r3, #(MACH_TYPE_CHUB & 0xff)
10 + orr r3, r3, #(MACH_TYPE_CHUB & 0xff00)
11 + cmp r7, r3
12 + beq 99f
13 +
14 @ Unknown board, use the AT91RM9200DK board
15 @ mov r7, #MACH_TYPE_AT91RM9200
16 mov r7, #(MACH_TYPE_AT91RM9200DK & 0xff)
17 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/Kconfig linux-2.6-stable/arch/arm/mach-at91/Kconfig
18 --- linux-2.6.21/arch/arm/mach-at91/Kconfig Thu Apr 26 05:08:32 2007
19 +++ linux-2.6-stable/arch/arm/mach-at91/Kconfig Wed May 9 10:20:54 2007
20 @@ -17,6 +17,9 @@
21 config ARCH_AT91SAM9263
22 bool "AT91SAM9263"
23
24 +config ARCH_AT91SAM9RL
25 + bool "AT91SAM9RL"
26 +
27 endchoice
28
29 # ----------------------------------------------------------
30 @@ -87,6 +90,12 @@
31 help
32 Select this if you are using Sperry-Sun's KAFA board.
33
34 +config MACH_CHUB
35 + bool "Promwad Chub board"
36 + depends on ARCH_AT91RM9200
37 + help
38 + Select this if you are using Promwad's Chub board.
39 +
40 endif
41
42 # ----------------------------------------------------------
43 @@ -111,6 +120,13 @@
44 Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
45 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
46
47 +config MACH_CAM60
48 + bool "KwikByte CAM60 board"
49 + depends on ARCH_AT91SAM9260
50 + help
51 + Select this if you are using KwikByte's CAM60 board based on the Atmel AT91SAM9260.
52 + <http://www.kwikbyte.com>
53 +
54 endif
55
56 # ----------------------------------------------------------
57 @@ -145,6 +161,20 @@
58
59 # ----------------------------------------------------------
60
61 +if ARCH_AT91SAM9RL
62 +
63 +comment "AT91SAM9RL Board Type"
64 +
65 +config MACH_AT91SAM9RLEK
66 + bool "Atmel AT91SAM9RL-EK Evaluation Kit"
67 + depends on ARCH_AT91SAM9RL
68 + help
69 + Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
70 +
71 +endif
72 +
73 +# ----------------------------------------------------------
74 +
75 comment "AT91 Board Options"
76
77 config MTD_AT91_DATAFLASH_CARD
78 @@ -160,6 +190,20 @@
79 On AT91SAM926x boards both types of NAND flash can be present
80 (8 and 16 bit data bus width).
81
82 +config CSB300_WAKE_SW0
83 + bool "CSB300 SW0 irq0 wakeup"
84 + depends on MACH_CSB337 && PM
85 + help
86 + If you have a CSB300 connected to your CSB337, this lets
87 + SW0 serve as a wakeup button. It uses IRQ0.
88 +
89 +config CSB300_WAKE_SW1
90 + bool "CSB300 SW1 gpio wakeup"
91 + depends on MACH_CSB337 && PM
92 + help
93 + If you have a CSB300 connected to your CSB337, this lets
94 + SW1 serve as a wakeup button. It uses GPIO.
95 +
96 # ----------------------------------------------------------
97
98 comment "AT91 Feature Selections"
99 @@ -170,6 +214,20 @@
100 Select this if you need to program one or more of the PCK0..PCK3
101 programmable clock outputs.
102
103 +config ATMEL_TCLIB
104 + bool "Timer/Counter Library"
105 + help
106 + Select this if you want a library to allocate the Timer/Counter
107 + blocks found on many Atmel processors. This facilitates using
108 + these modules despite processor differences.
109 +
110 +config AT91_SLOW_CLOCK
111 + bool "Suspend-to-RAM uses slow clock mode (EXPERIMENTAL)"
112 + depends on PM && EXPERIMENTAL
113 + help
114 + Select this if you wish to put the CPU into slow clock mode
115 + while in the "Suspend to RAM" state, to save more power.
116 +
117 endmenu
118
119 endif
120 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/Makefile linux-2.6-stable/arch/arm/mach-at91/Makefile
121 --- linux-2.6.21/arch/arm/mach-at91/Makefile Thu Apr 26 05:08:32 2007
122 +++ linux-2.6-stable/arch/arm/mach-at91/Makefile Wed May 9 12:37:19 2007
123 @@ -8,12 +8,15 @@
124 obj- :=
125
126 obj-$(CONFIG_PM) += pm.o
127 +obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
128 +obj-$(CONFIG_ATMEL_TCLIB) += tclib.o
129
130 # CPU-specific support
131 obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
132 obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
133 obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
134 obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
135 +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
136
137 # AT91RM9200 board-specific support
138 obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
139 @@ -25,9 +28,11 @@
140 obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
141 obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
142 obj-$(CONFIG_MACH_KAFA) += board-kafa.o
143 +obj-$(CONFIG_MACH_CHUB) += board-chub.o
144
145 # AT91SAM9260 board-specific support
146 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
147 +obj-$(CONFIG_MACH_CAM60) += board-cam60.o
148
149 # AT91SAM9261 board-specific support
150 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
151 @@ -35,9 +40,13 @@
152 # AT91SAM9263 board-specific support
153 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
154
155 +# AT91SAM9RL board-specific support
156 +obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
157 +
158 # LEDs support
159 led-$(CONFIG_ARCH_AT91RM9200DK) += leds.o
160 led-$(CONFIG_MACH_AT91RM9200EK) += leds.o
161 +led-$(CONFIG_MACH_AT91SAM9261EK)+= leds.o
162 led-$(CONFIG_MACH_CSB337) += leds.o
163 led-$(CONFIG_MACH_CSB637) += leds.o
164 led-$(CONFIG_MACH_KB9200) += leds.o
165 @@ -45,7 +54,7 @@
166 obj-$(CONFIG_LEDS) += $(led-y)
167
168 # VGA support
169 -#obj-$(CONFIG_FB_S1D13XXX) += ics1523.o
170 +obj-$(CONFIG_FB_S1D13XXX) += ics1523.o
171
172
173 ifeq ($(CONFIG_PM_DEBUG),y)
174 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91rm9200.c linux-2.6-stable/arch/arm/mach-at91/at91rm9200.c
175 --- linux-2.6.21/arch/arm/mach-at91/at91rm9200.c Thu Apr 26 05:08:32 2007
176 +++ linux-2.6-stable/arch/arm/mach-at91/at91rm9200.c Tue May 8 12:13:30 2007
177 @@ -117,6 +117,21 @@
178 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
179 .type = CLK_TYPE_PERIPHERAL,
180 };
181 +static struct clk ssc0_clk = {
182 + .name = "ssc0_clk",
183 + .pmc_mask = 1 << AT91RM9200_ID_SSC0,
184 + .type = CLK_TYPE_PERIPHERAL,
185 +};
186 +static struct clk ssc1_clk = {
187 + .name = "ssc1_clk",
188 + .pmc_mask = 1 << AT91RM9200_ID_SSC1,
189 + .type = CLK_TYPE_PERIPHERAL,
190 +};
191 +static struct clk ssc2_clk = {
192 + .name = "ssc2_clk",
193 + .pmc_mask = 1 << AT91RM9200_ID_SSC2,
194 + .type = CLK_TYPE_PERIPHERAL,
195 +};
196 static struct clk tc0_clk = {
197 .name = "tc0_clk",
198 .pmc_mask = 1 << AT91RM9200_ID_TC0,
199 @@ -161,7 +176,9 @@
200 &udc_clk,
201 &twi_clk,
202 &spi_clk,
203 - // ssc 0 .. ssc2
204 + &ssc0_clk,
205 + &ssc1_clk,
206 + &ssc2_clk,
207 &tc0_clk,
208 &tc1_clk,
209 &tc2_clk,
210 @@ -250,6 +267,33 @@
211
212
213 /* --------------------------------------------------------------------
214 + * Timer/Counter library initialization
215 + * -------------------------------------------------------------------- */
216 +#ifdef CONFIG_ATMEL_TCLIB
217 +
218 +#include "tclib.h"
219 +
220 +static struct atmel_tcblock at91rm9200_tcblocks[] = {
221 + [0] = {
222 + .physaddr = AT91RM9200_BASE_TCB0,
223 + .irq = { AT91RM9200_ID_TC0, AT91RM9200_ID_TC1, AT91RM9200_ID_TC2 },
224 + .clk = { &tc0_clk, &tc1_clk, &tc2_clk },
225 + },
226 + [1] = {
227 + .physaddr = AT91RM9200_BASE_TCB1,
228 + .irq = { AT91RM9200_ID_TC3, AT91RM9200_ID_TC4, AT91RM9200_ID_TC5 },
229 + .clk = { &tc3_clk, &tc4_clk, &tc5_clk },
230 + },
231 +};
232 +
233 +#define at91rm9200_tc_init() atmel_tc_init(at91rm9200_tcblocks, ARRAY_SIZE(at91rm9200_tcblocks))
234 +
235 +#else
236 +#define at91rm9200_tc_init() do {} while(0)
237 +#endif
238 +
239 +
240 +/* --------------------------------------------------------------------
241 * AT91RM9200 processor initialization
242 * -------------------------------------------------------------------- */
243 void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks)
244 @@ -271,6 +315,9 @@
245
246 /* Initialize GPIO subsystem */
247 at91_gpio_init(at91rm9200_gpio, banks);
248 +
249 + /* Initialize the Timer/Counter blocks */
250 + at91rm9200_tc_init();
251 }
252
253
254 @@ -284,28 +331,28 @@
255 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
256 7, /* Advanced Interrupt Controller (FIQ) */
257 7, /* System Peripherals */
258 - 0, /* Parallel IO Controller A */
259 - 0, /* Parallel IO Controller B */
260 - 0, /* Parallel IO Controller C */
261 - 0, /* Parallel IO Controller D */
262 - 6, /* USART 0 */
263 - 6, /* USART 1 */
264 - 6, /* USART 2 */
265 - 6, /* USART 3 */
266 + 1, /* Parallel IO Controller A */
267 + 1, /* Parallel IO Controller B */
268 + 1, /* Parallel IO Controller C */
269 + 1, /* Parallel IO Controller D */
270 + 5, /* USART 0 */
271 + 5, /* USART 1 */
272 + 5, /* USART 2 */
273 + 5, /* USART 3 */
274 0, /* Multimedia Card Interface */
275 - 4, /* USB Device Port */
276 - 0, /* Two-Wire Interface */
277 - 6, /* Serial Peripheral Interface */
278 - 5, /* Serial Synchronous Controller 0 */
279 - 5, /* Serial Synchronous Controller 1 */
280 - 5, /* Serial Synchronous Controller 2 */
281 + 2, /* USB Device Port */
282 + 6, /* Two-Wire Interface */
283 + 5, /* Serial Peripheral Interface */
284 + 4, /* Serial Synchronous Controller 0 */
285 + 4, /* Serial Synchronous Controller 1 */
286 + 4, /* Serial Synchronous Controller 2 */
287 0, /* Timer Counter 0 */
288 0, /* Timer Counter 1 */
289 0, /* Timer Counter 2 */
290 0, /* Timer Counter 3 */
291 0, /* Timer Counter 4 */
292 0, /* Timer Counter 5 */
293 - 3, /* USB Host port */
294 + 2, /* USB Host port */
295 3, /* Ethernet MAC */
296 0, /* Advanced Interrupt Controller (IRQ0) */
297 0, /* Advanced Interrupt Controller (IRQ1) */
298 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91rm9200_devices.c linux-2.6-stable/arch/arm/mach-at91/at91rm9200_devices.c
299 --- linux-2.6.21/arch/arm/mach-at91/at91rm9200_devices.c Thu Apr 26 05:08:32 2007
300 +++ linux-2.6-stable/arch/arm/mach-at91/at91rm9200_devices.c Tue May 8 12:13:30 2007
301 @@ -480,7 +480,18 @@
302 * SPI
303 * -------------------------------------------------------------------- */
304
305 -#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
306 +#if defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE) /* legacy SPI driver */
307 +#define SPI_DEVNAME "at91_spi"
308 +
309 +#elif defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) /* SPI bitbanging driver */
310 +#define SPI_DEVNAME "at91_spi"
311 +
312 +#elif defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) /* new SPI driver */
313 +#define SPI_DEVNAME "atmel_spi"
314 +
315 +#endif
316 +
317 +#ifdef SPI_DEVNAME
318 static u64 spi_dmamask = 0xffffffffUL;
319
320 static struct resource spi_resources[] = {
321 @@ -497,7 +508,7 @@
322 };
323
324 static struct platform_device at91rm9200_spi_device = {
325 - .name = "at91_spi",
326 + .name = SPI_DEVNAME,
327 .id = 0,
328 .dev = {
329 .dma_mask = &spi_dmamask,
330 @@ -606,6 +617,32 @@
331 #endif
332
333
334 +#if defined(CONFIG_NEW_LEDS)
335 +
336 +static struct platform_device at91_leds = {
337 + .name = "at91_leds",
338 + .id = -1,
339 +};
340 +
341 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
342 +{
343 + if (!nr)
344 + return;
345 +
346 + at91_leds.dev.platform_data = leds;
347 +
348 + for ( ; nr; nr--, leds++) {
349 + leds->index = nr; /* first record stores number of leds */
350 + at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
351 + }
352 +
353 + platform_device_register(&at91_leds);
354 +}
355 +#else
356 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
357 +#endif
358 +
359 +
360 /* --------------------------------------------------------------------
361 * UART
362 * -------------------------------------------------------------------- */
363 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9260.c linux-2.6-stable/arch/arm/mach-at91/at91sam9260.c
364 --- linux-2.6.21/arch/arm/mach-at91/at91sam9260.c Thu Apr 26 05:08:32 2007
365 +++ linux-2.6-stable/arch/arm/mach-at91/at91sam9260.c Tue May 8 12:13:30 2007
366 @@ -119,6 +119,11 @@
367 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
368 .type = CLK_TYPE_PERIPHERAL,
369 };
370 +static struct clk ssc_clk = {
371 + .name = "ssc_clk",
372 + .pmc_mask = 1 << AT91SAM9260_ID_SSC,
373 + .type = CLK_TYPE_PERIPHERAL,
374 +};
375 static struct clk tc0_clk = {
376 .name = "tc0_clk",
377 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
378 @@ -193,7 +198,7 @@
379 &twi_clk,
380 &spi0_clk,
381 &spi1_clk,
382 - // ssc
383 + &ssc_clk,
384 &tc0_clk,
385 &tc1_clk,
386 &tc2_clk,
387 @@ -264,6 +269,33 @@
388
389
390 /* --------------------------------------------------------------------
391 + * Timer/Counter library initialization
392 + * -------------------------------------------------------------------- */
393 +#ifdef CONFIG_ATMEL_TCLIB
394 +
395 +#include "tclib.h"
396 +
397 +static struct atmel_tcblock at91sam9260_tcblocks[] = {
398 + [0] = {
399 + .physaddr = AT91SAM9260_BASE_TCB0,
400 + .irq = { AT91SAM9260_ID_TC0, AT91SAM9260_ID_TC1, AT91SAM9260_ID_TC2 },
401 + .clk = { &tc0_clk, &tc1_clk, &tc2_clk },
402 + },
403 + [1] = {
404 + .physaddr = AT91SAM9260_BASE_TCB1,
405 + .irq = { AT91SAM9260_ID_TC3, AT91SAM9260_ID_TC4, AT91SAM9260_ID_TC5 },
406 + .clk = { &tc3_clk, &tc4_clk, &tc5_clk },
407 + },
408 +};
409 +
410 +#define at91sam9260_tc_init() atmel_tc_init(at91sam9260_tcblocks, ARRAY_SIZE(at91sam9260_tcblocks))
411 +
412 +#else
413 +#define at91sam9260_tc_init() do {} while(0)
414 +#endif
415 +
416 +
417 +/* --------------------------------------------------------------------
418 * AT91SAM9260 processor initialization
419 * -------------------------------------------------------------------- */
420
421 @@ -310,6 +342,9 @@
422
423 /* Register GPIO subsystem */
424 at91_gpio_init(at91sam9260_gpio, 3);
425 +
426 + /* Initialize the Timer/Counter blocks */
427 + at91sam9260_tc_init();
428 }
429
430 /* --------------------------------------------------------------------
431 @@ -322,30 +357,30 @@
432 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
433 7, /* Advanced Interrupt Controller */
434 7, /* System Peripherals */
435 - 0, /* Parallel IO Controller A */
436 - 0, /* Parallel IO Controller B */
437 - 0, /* Parallel IO Controller C */
438 + 1, /* Parallel IO Controller A */
439 + 1, /* Parallel IO Controller B */
440 + 1, /* Parallel IO Controller C */
441 0, /* Analog-to-Digital Converter */
442 - 6, /* USART 0 */
443 - 6, /* USART 1 */
444 - 6, /* USART 2 */
445 + 5, /* USART 0 */
446 + 5, /* USART 1 */
447 + 5, /* USART 2 */
448 0, /* Multimedia Card Interface */
449 - 4, /* USB Device Port */
450 - 0, /* Two-Wire Interface */
451 - 6, /* Serial Peripheral Interface 0 */
452 - 6, /* Serial Peripheral Interface 1 */
453 + 2, /* USB Device Port */
454 + 6, /* Two-Wire Interface */
455 + 5, /* Serial Peripheral Interface 0 */
456 + 5, /* Serial Peripheral Interface 1 */
457 5, /* Serial Synchronous Controller */
458 0,
459 0,
460 0, /* Timer Counter 0 */
461 0, /* Timer Counter 1 */
462 0, /* Timer Counter 2 */
463 - 3, /* USB Host port */
464 + 2, /* USB Host port */
465 3, /* Ethernet */
466 0, /* Image Sensor Interface */
467 - 6, /* USART 3 */
468 - 6, /* USART 4 */
469 - 6, /* USART 5 */
470 + 5, /* USART 3 */
471 + 5, /* USART 4 */
472 + 5, /* USART 5 */
473 0, /* Timer Counter 3 */
474 0, /* Timer Counter 4 */
475 0, /* Timer Counter 5 */
476 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9260_devices.c linux-2.6-stable/arch/arm/mach-at91/at91sam9260_devices.c
477 --- linux-2.6.21/arch/arm/mach-at91/at91sam9260_devices.c Thu Apr 26 05:08:32 2007
478 +++ linux-2.6-stable/arch/arm/mach-at91/at91sam9260_devices.c Tue May 8 12:13:30 2007
479 @@ -527,6 +527,32 @@
480 #endif
481
482
483 +#if defined(CONFIG_NEW_LEDS)
484 +
485 +static struct platform_device at91_leds = {
486 + .name = "at91_leds",
487 + .id = -1,
488 +};
489 +
490 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
491 +{
492 + if (!nr)
493 + return;
494 +
495 + at91_leds.dev.platform_data = leds;
496 +
497 + for ( ; nr; nr--, leds++) {
498 + leds->index = nr; /* first record stores number of leds */
499 + at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
500 + }
501 +
502 + platform_device_register(&at91_leds);
503 +}
504 +#else
505 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
506 +#endif
507 +
508 +
509 /* --------------------------------------------------------------------
510 * UART
511 * -------------------------------------------------------------------- */
512 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9261.c linux-2.6-stable/arch/arm/mach-at91/at91sam9261.c
513 --- linux-2.6.21/arch/arm/mach-at91/at91sam9261.c Thu Apr 26 05:08:32 2007
514 +++ linux-2.6-stable/arch/arm/mach-at91/at91sam9261.c Tue May 8 12:13:30 2007
515 @@ -97,6 +97,21 @@
516 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
517 .type = CLK_TYPE_PERIPHERAL,
518 };
519 +static struct clk ssc0_clk = {
520 + .name = "ssc0_clk",
521 + .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
522 + .type = CLK_TYPE_PERIPHERAL,
523 +};
524 +static struct clk ssc1_clk = {
525 + .name = "ssc1_clk",
526 + .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
527 + .type = CLK_TYPE_PERIPHERAL,
528 +};
529 +static struct clk ssc2_clk = {
530 + .name = "ssc2_clk",
531 + .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
532 + .type = CLK_TYPE_PERIPHERAL,
533 +};
534 static struct clk tc0_clk = {
535 .name = "tc0_clk",
536 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
537 @@ -135,7 +150,9 @@
538 &twi_clk,
539 &spi0_clk,
540 &spi1_clk,
541 - // ssc 0 .. ssc2
542 + &ssc0_clk,
543 + &ssc1_clk,
544 + &ssc2_clk,
545 &tc0_clk,
546 &tc1_clk,
547 &tc2_clk,
548 @@ -230,6 +247,28 @@
549
550
551 /* --------------------------------------------------------------------
552 + * Timer/Counter library initialization
553 + * -------------------------------------------------------------------- */
554 +#ifdef CONFIG_ATMEL_TCLIB
555 +
556 +#include "tclib.h"
557 +
558 +static struct atmel_tcblock at91sam9261_tcblocks[] = {
559 + [0] = {
560 + .physaddr = AT91SAM9261_BASE_TCB0,
561 + .irq = { AT91SAM9261_ID_TC0, AT91SAM9261_ID_TC1, AT91SAM9261_ID_TC2 },
562 + .clk = { &tc0_clk, &tc1_clk, &tc2_clk },
563 + }
564 +};
565 +
566 +#define at91sam9261_tc_init() atmel_tc_init(at91sam9261_tcblocks, ARRAY_SIZE(at91sam9261_tcblocks))
567 +
568 +#else
569 +#define at91sam9261_tc_init() do {} while(0)
570 +#endif
571 +
572 +
573 +/* --------------------------------------------------------------------
574 * AT91SAM9261 processor initialization
575 * -------------------------------------------------------------------- */
576
577 @@ -250,6 +289,9 @@
578
579 /* Register GPIO subsystem */
580 at91_gpio_init(at91sam9261_gpio, 3);
581 +
582 + /* Initialize the Timer/Counter blocks */
583 + at91sam9261_tc_init();
584 }
585
586 /* --------------------------------------------------------------------
587 @@ -262,25 +304,25 @@
588 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
589 7, /* Advanced Interrupt Controller */
590 7, /* System Peripherals */
591 - 0, /* Parallel IO Controller A */
592 - 0, /* Parallel IO Controller B */
593 - 0, /* Parallel IO Controller C */
594 + 1, /* Parallel IO Controller A */
595 + 1, /* Parallel IO Controller B */
596 + 1, /* Parallel IO Controller C */
597 0,
598 - 6, /* USART 0 */
599 - 6, /* USART 1 */
600 - 6, /* USART 2 */
601 + 5, /* USART 0 */
602 + 5, /* USART 1 */
603 + 5, /* USART 2 */
604 0, /* Multimedia Card Interface */
605 - 4, /* USB Device Port */
606 - 0, /* Two-Wire Interface */
607 - 6, /* Serial Peripheral Interface 0 */
608 - 6, /* Serial Peripheral Interface 1 */
609 - 5, /* Serial Synchronous Controller 0 */
610 - 5, /* Serial Synchronous Controller 1 */
611 - 5, /* Serial Synchronous Controller 2 */
612 + 2, /* USB Device Port */
613 + 6, /* Two-Wire Interface */
614 + 5, /* Serial Peripheral Interface 0 */
615 + 5, /* Serial Peripheral Interface 1 */
616 + 4, /* Serial Synchronous Controller 0 */
617 + 4, /* Serial Synchronous Controller 1 */
618 + 4, /* Serial Synchronous Controller 2 */
619 0, /* Timer Counter 0 */
620 0, /* Timer Counter 1 */
621 0, /* Timer Counter 2 */
622 - 3, /* USB Host port */
623 + 2, /* USB Host port */
624 3, /* LCD Controller */
625 0,
626 0,
627 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9261_devices.c linux-2.6-stable/arch/arm/mach-at91/at91sam9261_devices.c
628 --- linux-2.6.21/arch/arm/mach-at91/at91sam9261_devices.c Thu Apr 26 05:08:32 2007
629 +++ linux-2.6-stable/arch/arm/mach-at91/at91sam9261_devices.c Tue May 8 12:56:33 2007
630 @@ -14,6 +14,9 @@
631 #include <asm/mach/map.h>
632
633 #include <linux/platform_device.h>
634 +#include <linux/fb.h>
635 +
636 +#include <video/atmel_lcdc.h>
637
638 #include <asm/arch/board.h>
639 #include <asm/arch/gpio.h>
640 @@ -430,9 +433,9 @@
641 * LCD Controller
642 * -------------------------------------------------------------------- */
643
644 -#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE)
645 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
646 static u64 lcdc_dmamask = 0xffffffffUL;
647 -static struct at91fb_info lcdc_data;
648 +static struct atmel_lcdfb_info lcdc_data;
649
650 static struct resource lcdc_resources[] = {
651 [0] = {
652 @@ -455,7 +458,7 @@
653 };
654
655 static struct platform_device at91_lcdc_device = {
656 - .name = "at91-fb",
657 + .name = "atmel_lcdfb",
658 .id = 0,
659 .dev = {
660 .dma_mask = &lcdc_dmamask,
661 @@ -466,7 +469,7 @@
662 .num_resources = ARRAY_SIZE(lcdc_resources),
663 };
664
665 -void __init at91_add_device_lcdc(struct at91fb_info *data)
666 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
667 {
668 if (!data) {
669 return;
670 @@ -499,7 +502,7 @@
671 platform_device_register(&at91_lcdc_device);
672 }
673 #else
674 -void __init at91_add_device_lcdc(struct at91fb_info *data) {}
675 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
676 #endif
677
678
679 @@ -525,6 +528,32 @@
680 #endif
681
682
683 +#if defined(CONFIG_NEW_LEDS)
684 +
685 +static struct platform_device at91_leds = {
686 + .name = "at91_leds",
687 + .id = -1,
688 +};
689 +
690 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
691 +{
692 + if (!nr)
693 + return;
694 +
695 + at91_leds.dev.platform_data = leds;
696 +
697 + for ( ; nr; nr--, leds++) {
698 + leds->index = nr; /* first record stores number of leds */
699 + at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
700 + }
701 +
702 + platform_device_register(&at91_leds);
703 +}
704 +#else
705 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
706 +#endif
707 +
708 +
709 /* --------------------------------------------------------------------
710 * UART
711 * -------------------------------------------------------------------- */
712 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9263.c linux-2.6-stable/arch/arm/mach-at91/at91sam9263.c
713 --- linux-2.6.21/arch/arm/mach-at91/at91sam9263.c Thu Apr 26 05:08:32 2007
714 +++ linux-2.6-stable/arch/arm/mach-at91/at91sam9263.c Tue May 8 12:13:30 2007
715 @@ -87,6 +87,11 @@
716 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
717 .type = CLK_TYPE_PERIPHERAL,
718 };
719 +static struct clk can_clk = {
720 + .name = "can_clk",
721 + .pmc_mask = 1 << AT91SAM9263_ID_CAN,
722 + .type = CLK_TYPE_PERIPHERAL,
723 +};
724 static struct clk twi_clk = {
725 .name = "twi_clk",
726 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
727 @@ -102,16 +107,46 @@
728 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
729 .type = CLK_TYPE_PERIPHERAL,
730 };
731 +static struct clk ssc0_clk = {
732 + .name = "ssc0_clk",
733 + .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
734 + .type = CLK_TYPE_PERIPHERAL,
735 +};
736 +static struct clk ssc1_clk = {
737 + .name = "ssc1_clk",
738 + .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
739 + .type = CLK_TYPE_PERIPHERAL,
740 +};
741 +static struct clk ac97_clk = {
742 + .name = "ac97_clk",
743 + .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
744 + .type = CLK_TYPE_PERIPHERAL,
745 +};
746 static struct clk tcb_clk = {
747 .name = "tcb_clk",
748 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
749 .type = CLK_TYPE_PERIPHERAL,
750 };
751 +static struct clk pwmc_clk = {
752 + .name = "pwmc_clk",
753 + .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
754 + .type = CLK_TYPE_PERIPHERAL,
755 +};
756 static struct clk macb_clk = {
757 .name = "macb_clk",
758 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
759 .type = CLK_TYPE_PERIPHERAL,
760 };
761 +static struct clk dma_clk = {
762 + .name = "dma_clk",
763 + .pmc_mask = 1 << AT91SAM9263_ID_DMA,
764 + .type = CLK_TYPE_PERIPHERAL,
765 +};
766 +static struct clk twodge_clk = {
767 + .name = "2dge_clk",
768 + .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
769 + .type = CLK_TYPE_PERIPHERAL,
770 +};
771 static struct clk udc_clk = {
772 .name = "udc_clk",
773 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
774 @@ -142,20 +177,21 @@
775 &usart2_clk,
776 &mmc0_clk,
777 &mmc1_clk,
778 - // can
779 + &can_clk,
780 &twi_clk,
781 &spi0_clk,
782 &spi1_clk,
783 - // ssc0 .. ssc1
784 - // ac97
785 + &ssc0_clk,
786 + &ssc1_clk,
787 + &ac97_clk,
788 &tcb_clk,
789 - // pwmc
790 + &pwmc_clk,
791 &macb_clk,
792 - // 2dge
793 + &twodge_clk,
794 &udc_clk,
795 &isi_clk,
796 &lcdc_clk,
797 - // dma
798 + &dma_clk,
799 &ohci_clk,
800 // irq0 .. irq1
801 };
802 @@ -237,6 +273,28 @@
803
804
805 /* --------------------------------------------------------------------
806 + * Timer/Counter library initialization
807 + * -------------------------------------------------------------------- */
808 +#ifdef CONFIG_ATMEL_TCLIB
809 +
810 +#include "tclib.h"
811 +
812 +static struct atmel_tcblock at91sam9263_tcblocks[] = {
813 + [0] = {
814 + .physaddr = AT91SAM9263_BASE_TCB0,
815 + .irq = { AT91SAM9263_ID_TCB, AT91SAM9263_ID_TCB, AT91SAM9263_ID_TCB },
816 + .clk = { &tcb_clk, &tcb_clk, &tcb_clk },
817 + }
818 +};
819 +
820 +#define at91sam9263_tc_init() atmel_tc_init(at91sam9263_tcblocks, ARRAY_SIZE(at91sam9263_tcblocks))
821 +
822 +#else
823 +#define at91sam9263_tc_init() do {} while(0)
824 +#endif
825 +
826 +
827 +/* --------------------------------------------------------------------
828 * AT91SAM9263 processor initialization
829 * -------------------------------------------------------------------- */
830
831 @@ -256,6 +314,9 @@
832
833 /* Register GPIO subsystem */
834 at91_gpio_init(at91sam9263_gpio, 5);
835 +
836 + /* Initialize the Timer/Counter blocks */
837 + at91sam9263_tc_init();
838 }
839
840 /* --------------------------------------------------------------------
841 @@ -268,34 +329,34 @@
842 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
843 7, /* Advanced Interrupt Controller (FIQ) */
844 7, /* System Peripherals */
845 - 0, /* Parallel IO Controller A */
846 - 0, /* Parallel IO Controller B */
847 - 0, /* Parallel IO Controller C, D and E */
848 + 1, /* Parallel IO Controller A */
849 + 1, /* Parallel IO Controller B */
850 + 1, /* Parallel IO Controller C, D and E */
851 0,
852 0,
853 - 6, /* USART 0 */
854 - 6, /* USART 1 */
855 - 6, /* USART 2 */
856 + 5, /* USART 0 */
857 + 5, /* USART 1 */
858 + 5, /* USART 2 */
859 0, /* Multimedia Card Interface 0 */
860 0, /* Multimedia Card Interface 1 */
861 - 4, /* CAN */
862 - 0, /* Two-Wire Interface */
863 - 6, /* Serial Peripheral Interface 0 */
864 - 6, /* Serial Peripheral Interface 1 */
865 - 5, /* Serial Synchronous Controller 0 */
866 - 5, /* Serial Synchronous Controller 1 */
867 - 6, /* AC97 Controller */
868 + 3, /* CAN */
869 + 6, /* Two-Wire Interface */
870 + 5, /* Serial Peripheral Interface 0 */
871 + 5, /* Serial Peripheral Interface 1 */
872 + 4, /* Serial Synchronous Controller 0 */
873 + 4, /* Serial Synchronous Controller 1 */
874 + 5, /* AC97 Controller */
875 0, /* Timer Counter 0, 1 and 2 */
876 0, /* Pulse Width Modulation Controller */
877 3, /* Ethernet */
878 0,
879 0, /* 2D Graphic Engine */
880 - 3, /* USB Device Port */
881 + 2, /* USB Device Port */
882 0, /* Image Sensor Interface */
883 3, /* LDC Controller */
884 0, /* DMA Controller */
885 0,
886 - 3, /* USB Host port */
887 + 2, /* USB Host port */
888 0, /* Advanced Interrupt Controller (IRQ0) */
889 0, /* Advanced Interrupt Controller (IRQ1) */
890 };
891 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9263_devices.c linux-2.6-stable/arch/arm/mach-at91/at91sam9263_devices.c
892 --- linux-2.6.21/arch/arm/mach-at91/at91sam9263_devices.c Thu Apr 26 05:08:32 2007
893 +++ linux-2.6-stable/arch/arm/mach-at91/at91sam9263_devices.c Thu May 10 12:23:46 2007
894 @@ -13,6 +13,9 @@
895 #include <asm/mach/map.h>
896
897 #include <linux/platform_device.h>
898 +#include <linux/fb.h>
899 +
900 +#include <video/atmel_lcdc.h>
901
902 #include <asm/arch/board.h>
903 #include <asm/arch/gpio.h>
904 @@ -573,6 +576,180 @@
905
906
907 /* --------------------------------------------------------------------
908 + * AC97
909 + * -------------------------------------------------------------------- */
910 +
911 +#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
912 +static u64 ac97_dmamask = 0xffffffffUL;
913 +static struct atmel_ac97_data ac97_data;
914 +
915 +static struct resource ac97_resources[] = {
916 + [0] = {
917 + .start = AT91SAM9263_BASE_AC97C,
918 + .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
919 + .flags = IORESOURCE_MEM,
920 + },
921 + [1] = {
922 + .start = AT91SAM9263_ID_AC97C,
923 + .end = AT91SAM9263_ID_AC97C,
924 + .flags = IORESOURCE_IRQ,
925 + },
926 +};
927 +
928 +static struct platform_device at91sam9263_ac97_device = {
929 + .name = "ac97c",
930 + .id = 1,
931 + .dev = {
932 + .dma_mask = &ac97_dmamask,
933 + .coherent_dma_mask = 0xffffffff,
934 + .platform_data = &ac97_data,
935 + },
936 + .resource = ac97_resources,
937 + .num_resources = ARRAY_SIZE(ac97_resources),
938 +};
939 +
940 +void __init at91_add_device_ac97(struct atmel_ac97_data *data)
941 +{
942 + if (!data)
943 + return;
944 +
945 + at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
946 + at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
947 + at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
948 + at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
949 +
950 + /* reset */
951 + if (data->reset_pin)
952 + at91_set_gpio_output(data->reset_pin, 0);
953 +
954 + ac97_data = *ek_data;
955 + platform_device_register(&at91sam9263_ac97_device);
956 +}
957 +#else
958 +void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
959 +#endif
960 +
961 +
962 +/* --------------------------------------------------------------------
963 + * Image Sensor Interface
964 + * -------------------------------------------------------------------- */
965 +
966 +#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
967 +
968 +struct resource isi_resources[] = {
969 + [0] = {
970 + .start = AT91SAM9263_BASE_ISI,
971 + .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
972 + .flags = IORESOURCE_MEM,
973 + },
974 + [1] = {
975 + .start = AT91SAM9263_ID_ISI,
976 + .end = AT91SAM9263_ID_ISI,
977 + .flags = IORESOURCE_IRQ,
978 + },
979 +};
980 +
981 +static struct platform_device at91sam9263_isi_device = {
982 + .name = "at91_isi",
983 + .id = -1,
984 + .resource = isi_resources,
985 + .num_resources = ARRAY_SIZE(isi_resources),
986 +};
987 +
988 +void __init at91_add_device_isi(void)
989 +{
990 + at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
991 + at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
992 + at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
993 + at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
994 + at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
995 + at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
996 + at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
997 + at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
998 + at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
999 + at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
1000 + at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
1001 + at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
1002 + at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
1003 + at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
1004 + at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
1005 + at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
1006 +}
1007 +#else
1008 +void __init at91_add_device_isi(void) {}
1009 +#endif
1010 +
1011 +
1012 +/* --------------------------------------------------------------------
1013 + * LCD Controller
1014 + * -------------------------------------------------------------------- */
1015 +
1016 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
1017 +static u64 lcdc_dmamask = 0xffffffffUL;
1018 +static struct atmel_lcdfb_info lcdc_data;
1019 +
1020 +static struct resource lcdc_resources[] = {
1021 + [0] = {
1022 + .start = AT91SAM9263_LCDC_BASE,
1023 + .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
1024 + .flags = IORESOURCE_MEM,
1025 + },
1026 + [1] = {
1027 + .start = AT91SAM9263_ID_LCDC,
1028 + .end = AT91SAM9263_ID_LCDC,
1029 + .flags = IORESOURCE_IRQ,
1030 + },
1031 +};
1032 +
1033 +static struct platform_device at91_lcdc_device = {
1034 + .name = "atmel_lcdfb",
1035 + .id = 0,
1036 + .dev = {
1037 + .dma_mask = &lcdc_dmamask,
1038 + .coherent_dma_mask = 0xffffffff,
1039 + .platform_data = &lcdc_data,
1040 + },
1041 + .resource = lcdc_resources,
1042 + .num_resources = ARRAY_SIZE(lcdc_resources),
1043 +};
1044 +
1045 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
1046 +{
1047 + if (!data)
1048 + return;
1049 +
1050 + at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
1051 + at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
1052 + at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
1053 + at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
1054 + at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
1055 + at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
1056 + at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
1057 + at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
1058 + at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
1059 + at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
1060 + at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
1061 + at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
1062 + at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
1063 + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
1064 + at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
1065 + at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
1066 + at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
1067 + at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
1068 + at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
1069 + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
1070 + at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
1071 + at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
1072 +
1073 + lcdc_data = *data;
1074 + platform_device_register(&at91_lcdc_device);
1075 +}
1076 +#else
1077 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1078 +#endif
1079 +
1080 +
1081 +/* --------------------------------------------------------------------
1082 * LEDs
1083 * -------------------------------------------------------------------- */
1084
1085 @@ -594,6 +771,32 @@
1086 #endif
1087
1088
1089 +#if defined(CONFIG_NEW_LEDS)
1090 +
1091 +static struct platform_device at91_leds = {
1092 + .name = "at91_leds",
1093 + .id = -1,
1094 +};
1095 +
1096 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
1097 +{
1098 + if (!nr)
1099 + return;
1100 +
1101 + at91_leds.dev.platform_data = leds;
1102 +
1103 + for ( ; nr; nr--, leds++) {
1104 + leds->index = nr; /* first record stores number of leds */
1105 + at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
1106 + }
1107 +
1108 + platform_device_register(&at91_leds);
1109 +}
1110 +#else
1111 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
1112 +#endif
1113 +
1114 +
1115 /* --------------------------------------------------------------------
1116 * UART
1117 * -------------------------------------------------------------------- */
1118 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9rl.c linux-2.6-stable/arch/arm/mach-at91/at91sam9rl.c
1119 --- linux-2.6.21/arch/arm/mach-at91/at91sam9rl.c Thu Jan 1 02:00:00 1970
1120 +++ linux-2.6-stable/arch/arm/mach-at91/at91sam9rl.c Fri May 11 15:48:14 2007
1121 @@ -0,0 +1,366 @@
1122 +/*
1123 + * arch/arm/mach-at91/at91sam9rl.c
1124 + *
1125 + * Copyright (C) 2005 SAN People
1126 + * Copyright (C) 2007 Atmel Corporation
1127 + *
1128 + * This file is subject to the terms and conditions of the GNU General Public
1129 + * License. See the file COPYING in the main directory of this archive for
1130 + * more details.
1131 + */
1132 +
1133 +#include <linux/module.h>
1134 +
1135 +#include <asm/mach/arch.h>
1136 +#include <asm/mach/map.h>
1137 +#include <asm/arch/cpu.h>
1138 +#include <asm/arch/at91sam9rl.h>
1139 +#include <asm/arch/at91_pmc.h>
1140 +#include <asm/arch/at91_rstc.h>
1141 +
1142 +#include "generic.h"
1143 +#include "clock.h"
1144 +
1145 +static struct map_desc at91sam9rl_io_desc[] __initdata = {
1146 + {
1147 + .virtual = AT91_VA_BASE_SYS,
1148 + .pfn = __phys_to_pfn(AT91_BASE_SYS),
1149 + .length = SZ_16K,
1150 + .type = MT_DEVICE,
1151 + },
1152 +};
1153 +
1154 +static struct map_desc at91sam9rl_sram_desc[] __initdata = {
1155 + {
1156 + .pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
1157 + .type = MT_DEVICE,
1158 + }
1159 +};
1160 +
1161 +/* --------------------------------------------------------------------
1162 + * Clocks
1163 + * -------------------------------------------------------------------- */
1164 +
1165 +/*
1166 + * The peripheral clocks.
1167 + */
1168 +static struct clk pioA_clk = {
1169 + .name = "pioA_clk",
1170 + .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
1171 + .type = CLK_TYPE_PERIPHERAL,
1172 +};
1173 +static struct clk pioB_clk = {
1174 + .name = "pioB_clk",
1175 + .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
1176 + .type = CLK_TYPE_PERIPHERAL,
1177 +};
1178 +static struct clk pioC_clk = {
1179 + .name = "pioC_clk",
1180 + .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
1181 + .type = CLK_TYPE_PERIPHERAL,
1182 +};
1183 +static struct clk pioD_clk = {
1184 + .name = "pioD_clk",
1185 + .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
1186 + .type = CLK_TYPE_PERIPHERAL,
1187 +};
1188 +static struct clk usart0_clk = {
1189 + .name = "usart0_clk",
1190 + .pmc_mask = 1 << AT91SAM9RL_ID_US0,
1191 + .type = CLK_TYPE_PERIPHERAL,
1192 +};
1193 +static struct clk usart1_clk = {
1194 + .name = "usart1_clk",
1195 + .pmc_mask = 1 << AT91SAM9RL_ID_US1,
1196 + .type = CLK_TYPE_PERIPHERAL,
1197 +};
1198 +static struct clk usart2_clk = {
1199 + .name = "usart2_clk",
1200 + .pmc_mask = 1 << AT91SAM9RL_ID_US2,
1201 + .type = CLK_TYPE_PERIPHERAL,
1202 +};
1203 +static struct clk usart3_clk = {
1204 + .name = "usart3_clk",
1205 + .pmc_mask = 1 << AT91SAM9RL_ID_US3,
1206 + .type = CLK_TYPE_PERIPHERAL,
1207 +};
1208 +static struct clk mmc_clk = {
1209 + .name = "mci_clk",
1210 + .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
1211 + .type = CLK_TYPE_PERIPHERAL,
1212 +};
1213 +static struct clk twi0_clk = {
1214 + .name = "twi0_clk",
1215 + .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
1216 + .type = CLK_TYPE_PERIPHERAL,
1217 +};
1218 +static struct clk twi1_clk = {
1219 + .name = "twi1_clk",
1220 + .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
1221 + .type = CLK_TYPE_PERIPHERAL,
1222 +};
1223 +static struct clk spi_clk = {
1224 + .name = "spi_clk",
1225 + .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
1226 + .type = CLK_TYPE_PERIPHERAL,
1227 +};
1228 +static struct clk ssc0_clk = {
1229 + .name = "ssc0_clk",
1230 + .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
1231 + .type = CLK_TYPE_PERIPHERAL,
1232 +};
1233 +static struct clk ssc1_clk = {
1234 + .name = "ssc1_clk",
1235 + .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
1236 + .type = CLK_TYPE_PERIPHERAL,
1237 +};
1238 +static struct clk tc0_clk = {
1239 + .name = "tc0_clk",
1240 + .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
1241 + .type = CLK_TYPE_PERIPHERAL,
1242 +};
1243 +static struct clk tc1_clk = {
1244 + .name = "tc1_clk",
1245 + .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
1246 + .type = CLK_TYPE_PERIPHERAL,
1247 +};
1248 +static struct clk tc2_clk = {
1249 + .name = "tc2_clk",
1250 + .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
1251 + .type = CLK_TYPE_PERIPHERAL,
1252 +};
1253 +static struct clk pwmc_clk = {
1254 + .name = "pwmc_clk",
1255 + .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
1256 + .type = CLK_TYPE_PERIPHERAL,
1257 +};
1258 +static struct clk tsc_clk = {
1259 + .name = "tsc_clk",
1260 + .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
1261 + .type = CLK_TYPE_PERIPHERAL,
1262 +};
1263 +static struct clk dma_clk = {
1264 + .name = "dma_clk",
1265 + .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
1266 + .type = CLK_TYPE_PERIPHERAL,
1267 +};
1268 +static struct clk udphs_clk = {
1269 + .name = "udphs_clk",
1270 + .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
1271 + .type = CLK_TYPE_PERIPHERAL,
1272 +};
1273 +static struct clk lcdc_clk = {
1274 + .name = "lcdc_clk",
1275 + .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
1276 + .type = CLK_TYPE_PERIPHERAL,
1277 +};
1278 +static struct clk ac97_clk = {
1279 + .name = "ac97_clk",
1280 + .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
1281 + .type = CLK_TYPE_PERIPHERAL,
1282 +};
1283 +
1284 +static struct clk *periph_clocks[] __initdata = {
1285 + &pioA_clk,
1286 + &pioB_clk,
1287 + &pioC_clk,
1288 + &pioD_clk,
1289 + &usart0_clk,
1290 + &usart1_clk,
1291 + &usart2_clk,
1292 + &usart3_clk,
1293 + &mmc_clk,
1294 + &twi0_clk,
1295 + &twi1_clk,
1296 + &spi_clk,
1297 + &ssc0_clk,
1298 + &ssc1_clk,
1299 + &tc0_clk,
1300 + &tc1_clk,
1301 + &tc2_clk,
1302 + &pwmc_clk,
1303 + &tsc_clk,
1304 + &dma_clk,
1305 + &udphs_clk,
1306 + &lcdc_clk,
1307 + &ac97_clk,
1308 + // irq0
1309 +};
1310 +
1311 +/*
1312 + * The two programmable clocks.
1313 + * You must configure pin multiplexing to bring these signals out.
1314 + */
1315 +static struct clk pck0 = {
1316 + .name = "pck0",
1317 + .pmc_mask = AT91_PMC_PCK0,
1318 + .type = CLK_TYPE_PROGRAMMABLE,
1319 + .id = 0,
1320 +};
1321 +static struct clk pck1 = {
1322 + .name = "pck1",
1323 + .pmc_mask = AT91_PMC_PCK1,
1324 + .type = CLK_TYPE_PROGRAMMABLE,
1325 + .id = 1,
1326 +};
1327 +
1328 +static void __init at91sam9rl_register_clocks(void)
1329 +{
1330 + int i;
1331 +
1332 + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
1333 + clk_register(periph_clocks[i]);
1334 +
1335 + clk_register(&pck0);
1336 + clk_register(&pck1);
1337 +}
1338 +
1339 +/* --------------------------------------------------------------------
1340 + * GPIO
1341 + * -------------------------------------------------------------------- */
1342 +
1343 +static struct at91_gpio_bank at91sam9rl_gpio[] = {
1344 + {
1345 + .id = AT91SAM9RL_ID_PIOA,
1346 + .offset = AT91_PIOA,
1347 + .clock = &pioA_clk,
1348 + }, {
1349 + .id = AT91SAM9RL_ID_PIOB,
1350 + .offset = AT91_PIOB,
1351 + .clock = &pioB_clk,
1352 + }, {
1353 + .id = AT91SAM9RL_ID_PIOC,
1354 + .offset = AT91_PIOC,
1355 + .clock = &pioC_clk,
1356 + }, {
1357 + .id = AT91SAM9RL_ID_PIOD,
1358 + .offset = AT91_PIOD,
1359 + .clock = &pioD_clk,
1360 + }
1361 +};
1362 +
1363 +static void at91sam9rl_reset(void)
1364 +{
1365 + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
1366 +}
1367 +
1368 +
1369 +/* --------------------------------------------------------------------
1370 + * Timer/Counter library initialization
1371 + * -------------------------------------------------------------------- */
1372 +#ifdef CONFIG_ATMEL_TCLIB
1373 +
1374 +#include "tclib.h"
1375 +
1376 +static struct atmel_tcblock at91sam9rl_tcblocks[] = {
1377 + [0] = {
1378 + .physaddr = AT91SAM9RL_BASE_TCB0,
1379 + .irq = { AT91SAM9RL_ID_TC0, AT91SAM9RL_ID_TC1, AT91SAM9RL_ID_TC2 },
1380 + .clk = { &tc0_clk, &tc1_clk, &tc2_clk },
1381 + }
1382 +};
1383 +
1384 +#define at91sam9rl_tc_init() atmel_tc_init(at91sam9rl_tcblocks, ARRAY_SIZE(at91sam9rl_tcblocks))
1385 +
1386 +#else
1387 +#define at91sam9rl_tc_init() do {} while(0)
1388 +#endif
1389 +
1390 +
1391 +/* --------------------------------------------------------------------
1392 + * AT91SAM9RL processor initialization
1393 + * -------------------------------------------------------------------- */
1394 +
1395 +void __init at91sam9rl_initialize(unsigned long main_clock)
1396 +{
1397 + unsigned long cidr, sram_size;
1398 +
1399 + /* Map peripherals */
1400 + iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
1401 +
1402 + cidr = at91_sys_read(AT91_DBGU_CIDR);
1403 +
1404 + switch (cidr & AT91_CIDR_SRAMSIZ) {
1405 + case AT91_CIDR_SRAMSIZ_32K:
1406 + sram_size = 2 * SZ_16K;
1407 + break;
1408 + case AT91_CIDR_SRAMSIZ_16K:
1409 + default:
1410 + sram_size = SZ_16K;
1411 + }
1412 +
1413 + at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
1414 + at91sam9rl_sram_desc->length = sram_size;
1415 +
1416 + /* Map SRAM */
1417 + iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
1418 +
1419 + at91_arch_reset = at91sam9rl_reset;
1420 + at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
1421 +
1422 + /* Init clock subsystem */
1423 + at91_clock_init(main_clock);
1424 +
1425 + /* Register the processor-specific clocks */
1426 + at91sam9rl_register_clocks();
1427 +
1428 + /* Register GPIO subsystem */
1429 + at91_gpio_init(at91sam9rl_gpio, 4);
1430 +
1431 + /* Initialize the Timer/Counter blocks */
1432 + at91sam9rl_tc_init();
1433 +}
1434 +
1435 +/* --------------------------------------------------------------------
1436 + * Interrupt initialization
1437 + * -------------------------------------------------------------------- */
1438 +
1439 +/*
1440 + * The default interrupt priority levels (0 = lowest, 7 = highest).
1441 + */
1442 +static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
1443 + 7, /* Advanced Interrupt Controller */
1444 + 7, /* System Peripherals */
1445 + 1, /* Parallel IO Controller A */
1446 + 1, /* Parallel IO Controller B */
1447 + 1, /* Parallel IO Controller C */
1448 + 1, /* Parallel IO Controller D */
1449 + 5, /* USART 0 */
1450 + 5, /* USART 1 */
1451 + 5, /* USART 2 */
1452 + 5, /* USART 3 */
1453 + 0, /* Multimedia Card Interface */
1454 + 6, /* Two-Wire Interface 0 */
1455 + 6, /* Two-Wire Interface 1 */
1456 + 5, /* Serial Peripheral Interface */
1457 + 4, /* Serial Synchronous Controller 0 */
1458 + 4, /* Serial Synchronous Controller 1 */
1459 + 0, /* Timer Counter 0 */
1460 + 0, /* Timer Counter 1 */
1461 + 0, /* Timer Counter 2 */
1462 + 0,
1463 + 0, /* Touch Screen Controller */
1464 + 0, /* DMA Controller */
1465 + 2, /* USB Device High speed port */
1466 + 2, /* LCD Controller */
1467 + 6, /* AC97 Controller */
1468 + 0,
1469 + 0,
1470 + 0,
1471 + 0,
1472 + 0,
1473 + 0,
1474 + 0, /* Advanced Interrupt Controller */
1475 +};
1476 +
1477 +void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
1478 +{
1479 + if (!priority)
1480 + priority = at91sam9rl_default_irq_priority;
1481 +
1482 + /* Initialize the AIC interrupt controller */
1483 + at91_aic_init(priority);
1484 +
1485 + /* Enable GPIO interrupts */
1486 + at91_gpio_irq_setup();
1487 +}
1488 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/at91sam9rl_devices.c linux-2.6-stable/arch/arm/mach-at91/at91sam9rl_devices.c
1489 --- linux-2.6.21/arch/arm/mach-at91/at91sam9rl_devices.c Thu Jan 1 02:00:00 1970
1490 +++ linux-2.6-stable/arch/arm/mach-at91/at91sam9rl_devices.c Fri May 11 16:03:25 2007
1491 @@ -0,0 +1,660 @@
1492 +/*
1493 + * Copyright (C) 2007 Atmel Corporation
1494 + *
1495 + * This file is subject to the terms and conditions of the GNU General Public
1496 + * License. See the file COPYING in the main directory of this archive for
1497 + * more details.
1498 + */
1499 +
1500 +#include <asm/mach/arch.h>
1501 +#include <asm/mach/map.h>
1502 +
1503 +#include <linux/platform_device.h>
1504 +#include <linux/fb.h>
1505 +
1506 +#include <video/atmel_lcdc.h>
1507 +
1508 +#include <asm/arch/board.h>
1509 +#include <asm/arch/gpio.h>
1510 +#include <asm/arch/at91sam9rl.h>
1511 +#include <asm/arch/at91sam9rl_matrix.h>
1512 +#include <asm/arch/at91sam926x_mc.h>
1513 +
1514 +#include "generic.h"
1515 +
1516 +#define SZ_512 0x00000200
1517 +#define SZ_256 0x00000100
1518 +#define SZ_16 0x00000010
1519 +
1520 +
1521 +/* --------------------------------------------------------------------
1522 + * MMC / SD
1523 + * -------------------------------------------------------------------- */
1524 +
1525 +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
1526 +static u64 mmc_dmamask = 0xffffffffUL;
1527 +static struct at91_mmc_data mmc_data;
1528 +
1529 +static struct resource mmc_resources[] = {
1530 + [0] = {
1531 + .start = AT91SAM9RL_BASE_MCI,
1532 + .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
1533 + .flags = IORESOURCE_MEM,
1534 + },
1535 + [1] = {
1536 + .start = AT91SAM9RL_ID_MCI,
1537 + .end = AT91SAM9RL_ID_MCI,
1538 + .flags = IORESOURCE_IRQ,
1539 + },
1540 +};
1541 +
1542 +static struct platform_device at91sam9rl_mmc_device = {
1543 + .name = "at91_mci",
1544 + .id = -1,
1545 + .dev = {
1546 + .dma_mask = &mmc_dmamask,
1547 + .coherent_dma_mask = 0xffffffff,
1548 + .platform_data = &mmc_data,
1549 + },
1550 + .resource = mmc_resources,
1551 + .num_resources = ARRAY_SIZE(mmc_resources),
1552 +};
1553 +
1554 +void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
1555 +{
1556 + if (!data)
1557 + return;
1558 +
1559 + /* input/irq */
1560 + if (data->det_pin) {
1561 + at91_set_gpio_input(data->det_pin, 1);
1562 + at91_set_deglitch(data->det_pin, 1);
1563 + }
1564 + if (data->wp_pin)
1565 + at91_set_gpio_input(data->wp_pin, 1);
1566 + if (data->vcc_pin)
1567 + at91_set_gpio_output(data->vcc_pin, 0);
1568 +
1569 + /* CLK */
1570 + at91_set_A_periph(AT91_PIN_PA2, 0);
1571 +
1572 + /* CMD */
1573 + at91_set_A_periph(AT91_PIN_PA1, 1);
1574 +
1575 + /* DAT0, maybe DAT1..DAT3 */
1576 + at91_set_A_periph(AT91_PIN_PA0, 1);
1577 + if (data->wire4) {
1578 + at91_set_A_periph(AT91_PIN_PA3, 1);
1579 + at91_set_A_periph(AT91_PIN_PA4, 1);
1580 + at91_set_A_periph(AT91_PIN_PA5, 1);
1581 + }
1582 +
1583 + mmc_data = *data;
1584 + platform_device_register(&at91sam9rl_mmc_device);
1585 +}
1586 +#else
1587 +void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
1588 +#endif
1589 +
1590 +
1591 +/* --------------------------------------------------------------------
1592 + * NAND / SmartMedia
1593 + * -------------------------------------------------------------------- */
1594 +
1595 +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
1596 +static struct at91_nand_data nand_data;
1597 +
1598 +#define NAND_BASE AT91_CHIPSELECT_3
1599 +
1600 +static struct resource nand_resources[] = {
1601 + {
1602 + .start = NAND_BASE,
1603 + .end = NAND_BASE + SZ_256M - 1,
1604 + .flags = IORESOURCE_MEM,
1605 + }
1606 +};
1607 +
1608 +static struct platform_device at91_nand_device = {
1609 + .name = "at91_nand",
1610 + .id = -1,
1611 + .dev = {
1612 + .platform_data = &nand_data,
1613 + },
1614 + .resource = nand_resources,
1615 + .num_resources = ARRAY_SIZE(nand_resources),
1616 +};
1617 +
1618 +void __init at91_add_device_nand(struct at91_nand_data *data)
1619 +{
1620 + unsigned long csa;
1621 +
1622 + if (!data)
1623 + return;
1624 +
1625 + csa = at91_sys_read(AT91_MATRIX_EBICSA);
1626 + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
1627 +
1628 + /* set the bus interface characteristics */
1629 + at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
1630 + | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
1631 +
1632 + at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
1633 + | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
1634 +
1635 + at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
1636 +
1637 + at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
1638 +
1639 + /* enable pin */
1640 + if (data->enable_pin)
1641 + at91_set_gpio_output(data->enable_pin, 1);
1642 +
1643 + /* ready/busy pin */
1644 + if (data->rdy_pin)
1645 + at91_set_gpio_input(data->rdy_pin, 1);
1646 +
1647 + /* card detect pin */
1648 + if (data->det_pin)
1649 + at91_set_gpio_input(data->det_pin, 1);
1650 +
1651 + at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
1652 + at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
1653 +
1654 + nand_data = *data;
1655 + platform_device_register(&at91_nand_device);
1656 +}
1657 +
1658 +#else
1659 +void __init at91_add_device_nand(struct at91_nand_data *data) {}
1660 +#endif
1661 +
1662 +
1663 +/* --------------------------------------------------------------------
1664 + * TWI (i2c)
1665 + * -------------------------------------------------------------------- */
1666 +
1667 +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
1668 +
1669 +static struct resource twi_resources[] = {
1670 + [0] = {
1671 + .start = AT91SAM9RL_BASE_TWI0,
1672 + .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
1673 + .flags = IORESOURCE_MEM,
1674 + },
1675 + [1] = {
1676 + .start = AT91SAM9RL_ID_TWI0,
1677 + .end = AT91SAM9RL_ID_TWI0,
1678 + .flags = IORESOURCE_IRQ,
1679 + },
1680 +};
1681 +
1682 +static struct platform_device at91sam9rl_twi_device = {
1683 + .name = "at91_i2c",
1684 + .id = -1,
1685 + .resource = twi_resources,
1686 + .num_resources = ARRAY_SIZE(twi_resources),
1687 +};
1688 +
1689 +void __init at91_add_device_i2c(void)
1690 +{
1691 + /* pins used for TWI interface */
1692 + at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
1693 + at91_set_multi_drive(AT91_PIN_PA23, 1);
1694 +
1695 + at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
1696 + at91_set_multi_drive(AT91_PIN_PA24, 1);
1697 +
1698 + platform_device_register(&at91sam9rl_twi_device);
1699 +}
1700 +#else
1701 +void __init at91_add_device_i2c(void) {}
1702 +#endif
1703 +
1704 +
1705 +/* --------------------------------------------------------------------
1706 + * SPI
1707 + * -------------------------------------------------------------------- */
1708 +
1709 +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
1710 +static u64 spi_dmamask = 0xffffffffUL;
1711 +
1712 +static struct resource spi_resources[] = {
1713 + [0] = {
1714 + .start = AT91SAM9RL_BASE_SPI,
1715 + .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
1716 + .flags = IORESOURCE_MEM,
1717 + },
1718 + [1] = {
1719 + .start = AT91SAM9RL_ID_SPI,
1720 + .end = AT91SAM9RL_ID_SPI,
1721 + .flags = IORESOURCE_IRQ,
1722 + },
1723 +};
1724 +
1725 +static struct platform_device at91sam9rl_spi_device = {
1726 + .name = "atmel_spi",
1727 + .id = 0,
1728 + .dev = {
1729 + .dma_mask = &spi_dmamask,
1730 + .coherent_dma_mask = 0xffffffff,
1731 + },
1732 + .resource = spi_resources,
1733 + .num_resources = ARRAY_SIZE(spi_resources),
1734 +};
1735 +
1736 +static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
1737 +
1738 +
1739 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
1740 +{
1741 + int i;
1742 + unsigned long cs_pin;
1743 +
1744 + at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
1745 + at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
1746 + at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
1747 +
1748 + /* Enable SPI chip-selects */
1749 + for (i = 0; i < nr_devices; i++) {
1750 + if (devices[i].controller_data)
1751 + cs_pin = (unsigned long) devices[i].controller_data;
1752 + else
1753 + cs_pin = spi_standard_cs[devices[i].chip_select];
1754 +
1755 + /* enable chip-select pin */
1756 + at91_set_gpio_output(cs_pin, 1);
1757 +
1758 + /* pass chip-select pin to driver */
1759 + devices[i].controller_data = (void *) cs_pin;
1760 + }
1761 +
1762 + spi_register_board_info(devices, nr_devices);
1763 + platform_device_register(&at91sam9rl_spi_device);
1764 +}
1765 +#else
1766 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
1767 +#endif
1768 +
1769 +
1770 +/* --------------------------------------------------------------------
1771 + * LCD Controller
1772 + * -------------------------------------------------------------------- */
1773 +
1774 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
1775 +static u64 lcdc_dmamask = 0xffffffffUL;
1776 +static struct atmel_lcdfb_info lcdc_data;
1777 +
1778 +static struct resource lcdc_resources[] = {
1779 + [0] = {
1780 + .start = AT91SAM9RL_LCDC_BASE,
1781 + .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
1782 + .flags = IORESOURCE_MEM,
1783 + },
1784 + [1] = {
1785 + .start = AT91SAM9RL_ID_LCDC,
1786 + .end = AT91SAM9RL_ID_LCDC,
1787 + .flags = IORESOURCE_IRQ,
1788 + },
1789 +#if defined(CONFIG_FB_INTSRAM)
1790 + [2] = {
1791 + .start = AT91SAM9RL_SRAM_BASE,
1792 + .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
1793 + .flags = IORESOURCE_MEM,
1794 + },
1795 +#endif
1796 +};
1797 +
1798 +static struct platform_device at91_lcdc_device = {
1799 + .name = "atmel_lcdfb",
1800 + .id = 0,
1801 + .dev = {
1802 + .dma_mask = &lcdc_dmamask,
1803 + .coherent_dma_mask = 0xffffffff,
1804 + .platform_data = &lcdc_data,
1805 + },
1806 + .resource = lcdc_resources,
1807 + .num_resources = ARRAY_SIZE(lcdc_resources),
1808 +};
1809 +
1810 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
1811 +{
1812 + if (!data) {
1813 + return;
1814 + }
1815 +
1816 +#warning "Check this"
1817 + at91_set_B_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
1818 + at91_set_B_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
1819 + at91_set_B_periph(AT91_PIN_PC7, 0); /* LCDDEN */
1820 + at91_set_B_periph(AT91_PIN_PC3, 0); /* LCDCC */
1821 + at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
1822 + at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
1823 + at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
1824 + at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
1825 + at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
1826 + at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
1827 + at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
1828 + at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
1829 + at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
1830 + at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
1831 + at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
1832 + at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
1833 + at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
1834 + at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
1835 + at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
1836 + at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
1837 +
1838 + lcdc_data = *data;
1839 + platform_device_register(&at91_lcdc_device);
1840 +}
1841 +#else
1842 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1843 +#endif
1844 +
1845 +
1846 +/* --------------------------------------------------------------------
1847 + * LEDs
1848 + * -------------------------------------------------------------------- */
1849 +
1850 +#if defined(CONFIG_LEDS)
1851 +u8 at91_leds_cpu;
1852 +u8 at91_leds_timer;
1853 +
1854 +void __init at91_init_leds(u8 cpu_led, u8 timer_led)
1855 +{
1856 + /* Enable GPIO to access the LEDs */
1857 + at91_set_gpio_output(cpu_led, 1);
1858 + at91_set_gpio_output(timer_led, 1);
1859 +
1860 + at91_leds_cpu = cpu_led;
1861 + at91_leds_timer = timer_led;
1862 +}
1863 +#else
1864 +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
1865 +#endif
1866 +
1867 +
1868 +#if defined(CONFIG_NEW_LEDS)
1869 +
1870 +static struct platform_device at91_leds = {
1871 + .name = "at91_leds",
1872 + .id = -1,
1873 +};
1874 +
1875 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
1876 +{
1877 + if (!nr)
1878 + return;
1879 +
1880 + at91_leds.dev.platform_data = leds;
1881 +
1882 + for ( ; nr; nr--, leds++) {
1883 + leds->index = nr; /* first record stores number of leds */
1884 + at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
1885 + }
1886 +
1887 + platform_device_register(&at91_leds);
1888 +}
1889 +#else
1890 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
1891 +#endif
1892 +
1893 +
1894 +/* --------------------------------------------------------------------
1895 + * UART
1896 + * -------------------------------------------------------------------- */
1897 +
1898 +#if defined(CONFIG_SERIAL_ATMEL)
1899 +static struct resource dbgu_resources[] = {
1900 + [0] = {
1901 + .start = AT91_VA_BASE_SYS + AT91_DBGU,
1902 + .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1903 + .flags = IORESOURCE_MEM,
1904 + },
1905 + [1] = {
1906 + .start = AT91_ID_SYS,
1907 + .end = AT91_ID_SYS,
1908 + .flags = IORESOURCE_IRQ,
1909 + },
1910 +};
1911 +
1912 +static struct atmel_uart_data dbgu_data = {
1913 + .use_dma_tx = 0,
1914 + .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1915 + .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1916 +};
1917 +
1918 +static struct platform_device at91sam9rl_dbgu_device = {
1919 + .name = "atmel_usart",
1920 + .id = 0,
1921 + .dev = {
1922 + .platform_data = &dbgu_data,
1923 + .coherent_dma_mask = 0xffffffff,
1924 + },
1925 + .resource = dbgu_resources,
1926 + .num_resources = ARRAY_SIZE(dbgu_resources),
1927 +};
1928 +
1929 +static inline void configure_dbgu_pins(void)
1930 +{
1931 + at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
1932 + at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
1933 +}
1934 +
1935 +static struct resource uart0_resources[] = {
1936 + [0] = {
1937 + .start = AT91SAM9RL_BASE_US0,
1938 + .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
1939 + .flags = IORESOURCE_MEM,
1940 + },
1941 + [1] = {
1942 + .start = AT91SAM9RL_ID_US0,
1943 + .end = AT91SAM9RL_ID_US0,
1944 + .flags = IORESOURCE_IRQ,
1945 + },
1946 +};
1947 +
1948 +static struct atmel_uart_data uart0_data = {
1949 + .use_dma_tx = 1,
1950 + .use_dma_rx = 1,
1951 +};
1952 +
1953 +static struct platform_device at91sam9rl_uart0_device = {
1954 + .name = "atmel_usart",
1955 + .id = 1,
1956 + .dev = {
1957 + .platform_data = &uart0_data,
1958 + .coherent_dma_mask = 0xffffffff,
1959 + },
1960 + .resource = uart0_resources,
1961 + .num_resources = ARRAY_SIZE(uart0_resources),
1962 +};
1963 +
1964 +static inline void configure_usart0_pins(void)
1965 +{
1966 + at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
1967 + at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
1968 + at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
1969 + at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
1970 +}
1971 +
1972 +static struct resource uart1_resources[] = {
1973 + [0] = {
1974 + .start = AT91SAM9RL_BASE_US1,
1975 + .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1976 + .flags = IORESOURCE_MEM,
1977 + },
1978 + [1] = {
1979 + .start = AT91SAM9RL_ID_US1,
1980 + .end = AT91SAM9RL_ID_US1,
1981 + .flags = IORESOURCE_IRQ,
1982 + },
1983 +};
1984 +
1985 +static struct atmel_uart_data uart1_data = {
1986 + .use_dma_tx = 1,
1987 + .use_dma_rx = 1,
1988 +};
1989 +
1990 +static struct platform_device at91sam9rl_uart1_device = {
1991 + .name = "atmel_usart",
1992 + .id = 2,
1993 + .dev = {
1994 + .platform_data = &uart1_data,
1995 + .coherent_dma_mask = 0xffffffff,
1996 + },
1997 + .resource = uart1_resources,
1998 + .num_resources = ARRAY_SIZE(uart1_resources),
1999 +};
2000 +
2001 +static inline void configure_usart1_pins(void)
2002 +{
2003 + at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
2004 + at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
2005 +}
2006 +
2007 +static struct resource uart2_resources[] = {
2008 + [0] = {
2009 + .start = AT91SAM9RL_BASE_US2,
2010 + .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
2011 + .flags = IORESOURCE_MEM,
2012 + },
2013 + [1] = {
2014 + .start = AT91SAM9RL_ID_US2,
2015 + .end = AT91SAM9RL_ID_US2,
2016 + .flags = IORESOURCE_IRQ,
2017 + },
2018 +};
2019 +
2020 +static struct atmel_uart_data uart2_data = {
2021 + .use_dma_tx = 1,
2022 + .use_dma_rx = 1,
2023 +};
2024 +
2025 +static struct platform_device at91sam9rl_uart2_device = {
2026 + .name = "atmel_usart",
2027 + .id = 3,
2028 + .dev = {
2029 + .platform_data = &uart2_data,
2030 + .coherent_dma_mask = 0xffffffff,
2031 + },
2032 + .resource = uart2_resources,
2033 + .num_resources = ARRAY_SIZE(uart2_resources),
2034 +};
2035 +
2036 +static inline void configure_usart2_pins(void)
2037 +{
2038 + at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
2039 + at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
2040 +}
2041 +
2042 +static struct resource uart3_resources[] = {
2043 + [0] = {
2044 + .start = AT91SAM9RL_BASE_US3,
2045 + .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
2046 + .flags = IORESOURCE_MEM,
2047 + },
2048 + [1] = {
2049 + .start = AT91SAM9RL_ID_US3,
2050 + .end = AT91SAM9RL_ID_US3,
2051 + .flags = IORESOURCE_IRQ,
2052 + },
2053 +};
2054 +
2055 +static struct atmel_uart_data uart3_data = {
2056 + .use_dma_tx = 1,
2057 + .use_dma_rx = 1,
2058 +};
2059 +
2060 +static struct platform_device at91sam9rl_uart3_device = {
2061 + .name = "atmel_usart",
2062 + .id = 4,
2063 + .dev = {
2064 + .platform_data = &uart3_data,
2065 + .coherent_dma_mask = 0xffffffff,
2066 + },
2067 + .resource = uart3_resources,
2068 + .num_resources = ARRAY_SIZE(uart3_resources),
2069 +};
2070 +
2071 +static inline void configure_usart3_pins(void)
2072 +{
2073 + at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
2074 + at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
2075 +}
2076 +
2077 +struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
2078 +struct platform_device *atmel_default_console_device; /* the serial console device */
2079 +
2080 +void __init at91_init_serial(struct at91_uart_config *config)
2081 +{
2082 + int i;
2083 +
2084 + /* Fill in list of supported UARTs */
2085 + for (i = 0; i < config->nr_tty; i++) {
2086 + switch (config->tty_map[i]) {
2087 + case 0:
2088 + configure_usart0_pins();
2089 + at91_uarts[i] = &at91sam9rl_uart0_device;
2090 + at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
2091 + break;
2092 + case 1:
2093 + configure_usart1_pins();
2094 + at91_uarts[i] = &at91sam9rl_uart1_device;
2095 + at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
2096 + break;
2097 + case 2:
2098 + configure_usart2_pins();
2099 + at91_uarts[i] = &at91sam9rl_uart2_device;
2100 + at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
2101 + break;
2102 + case 3:
2103 + configure_usart3_pins();
2104 + at91_uarts[i] = &at91sam9rl_uart3_device;
2105 + at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
2106 + break;
2107 + case 4:
2108 + configure_dbgu_pins();
2109 + at91_uarts[i] = &at91sam9rl_dbgu_device;
2110 + at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
2111 + break;
2112 + default:
2113 + continue;
2114 + }
2115 + at91_uarts[i]->id = i; /* update ID number to mapped ID */
2116 + }
2117 +
2118 + /* Set serial console device */
2119 + if (config->console_tty < ATMEL_MAX_UART)
2120 + atmel_default_console_device = at91_uarts[config->console_tty];
2121 + if (!atmel_default_console_device)
2122 + printk(KERN_INFO "AT91: No default serial console defined.\n");
2123 +}
2124 +
2125 +void __init at91_add_device_serial(void)
2126 +{
2127 + int i;
2128 +
2129 + for (i = 0; i < ATMEL_MAX_UART; i++) {
2130 + if (at91_uarts[i])
2131 + platform_device_register(at91_uarts[i]);
2132 + }
2133 +}
2134 +#else
2135 +void __init at91_init_serial(struct at91_uart_config *config) {}
2136 +void __init at91_add_device_serial(void) {}
2137 +#endif
2138 +
2139 +
2140 +/* -------------------------------------------------------------------- */
2141 +
2142 +/*
2143 + * These devices are always present and don't need any board-specific
2144 + * setup.
2145 + */
2146 +static int __init at91_add_standard_devices(void)
2147 +{
2148 + return 0;
2149 +}
2150 +
2151 +arch_initcall(at91_add_standard_devices);
2152 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-cam60.c linux-2.6-stable/arch/arm/mach-at91/board-cam60.c
2153 --- linux-2.6.21/arch/arm/mach-at91/board-cam60.c Thu Jan 1 02:00:00 1970
2154 +++ linux-2.6-stable/arch/arm/mach-at91/board-cam60.c Tue May 8 12:13:30 2007
2155 @@ -0,0 +1,148 @@
2156 +/*
2157 + * KwikByte CAM60
2158 + *
2159 + * based on board-sam9260ek.c
2160 + * Copyright (C) 2005 SAN People
2161 + * Copyright (C) 2006 Atmel
2162 + *
2163 + * This program is free software; you can redistribute it and/or modify
2164 + * it under the terms of the GNU General Public License as published by
2165 + * the Free Software Foundation; either version 2 of the License, or
2166 + * (at your option) any later version.
2167 + *
2168 + * This program is distributed in the hope that it will be useful,
2169 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2170 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2171 + * GNU General Public License for more details.
2172 + *
2173 + * You should have received a copy of the GNU General Public License
2174 + * along with this program; if not, write to the Free Software
2175 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2176 + */
2177 +
2178 +#include <linux/types.h>
2179 +#include <linux/init.h>
2180 +#include <linux/mm.h>
2181 +#include <linux/module.h>
2182 +#include <linux/platform_device.h>
2183 +#include <linux/spi/spi.h>
2184 +#include <linux/spi/flash.h>
2185 +
2186 +#include <asm/hardware.h>
2187 +#include <asm/setup.h>
2188 +#include <asm/mach-types.h>
2189 +#include <asm/irq.h>
2190 +
2191 +#include <asm/mach/arch.h>
2192 +#include <asm/mach/map.h>
2193 +#include <asm/mach/irq.h>
2194 +
2195 +#include <asm/arch/board.h>
2196 +#include <asm/arch/gpio.h>
2197 +#include <asm/arch/at91sam926x_mc.h>
2198 +
2199 +#include "generic.h"
2200 +
2201 +
2202 +/*
2203 + * Serial port configuration.
2204 + * 0 .. 5 = USART0 .. USART5
2205 + * 6 = DBGU
2206 + */
2207 +static struct at91_uart_config __initdata cam60_uart_config = {
2208 + .console_tty = 0, /* ttyS0 */
2209 + .nr_tty = 1,
2210 + .tty_map = { 6, -1, -1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */
2211 +};
2212 +
2213 +static void __init cam60_map_io(void)
2214 +{
2215 + /* Initialize processor: 10 MHz crystal */
2216 + at91sam9260_initialize(10000000);
2217 +
2218 + /* Setup the serial ports and console */
2219 + at91_init_serial(&cam60_uart_config);
2220 +}
2221 +
2222 +static void __init cam60_init_irq(void)
2223 +{
2224 + at91sam9260_init_interrupts(NULL);
2225 +}
2226 +
2227 +
2228 +/*
2229 + * SPI devices.
2230 + */
2231 +#if defined(CONFIG_MTD_DATAFLASH)
2232 +static struct mtd_partition __initdata cam60_spi_partitions[] = {
2233 + {
2234 + .name = "BOOT1",
2235 + .offset = 0,
2236 + .size = 4 * 1056,
2237 + },
2238 + {
2239 + .name = "BOOT2",
2240 + .offset = MTDPART_OFS_NXTBLK,
2241 + .size = 256 * 1056,
2242 + },
2243 + {
2244 + .name = "kernel",
2245 + .offset = MTDPART_OFS_NXTBLK,
2246 + .size = 2222 * 1056,
2247 + },
2248 + {
2249 + .name = "file system",
2250 + .offset = MTDPART_OFS_NXTBLK,
2251 + .size = MTDPART_SIZ_FULL,
2252 + },
2253 +};
2254 +
2255 +static struct flash_platform_data __initdata cam60_spi_flash_platform_data = {
2256 + .name = "spi_flash",
2257 + .parts = cam60_spi_partitions,
2258 + .nr_parts = ARRAY_SIZE(cam60_spi_partitions)
2259 +};
2260 +#endif
2261 +
2262 +static struct spi_board_info cam60_spi_devices[] = {
2263 +#if defined(CONFIG_MTD_DATAFLASH)
2264 + { /* DataFlash chip */
2265 + .modalias = "mtd_dataflash",
2266 + .chip_select = 0,
2267 + .max_speed_hz = 15 * 1000 * 1000,
2268 + .bus_num = 0,
2269 + .platform_data = &cam60_spi_flash_platform_data
2270 + },
2271 +#endif
2272 +};
2273 +
2274 +
2275 +/*
2276 + * MACB Ethernet device
2277 + */
2278 +static struct __initdata at91_eth_data cam60_macb_data = {
2279 + .phy_irq_pin = AT91_PIN_PB5,
2280 + .is_rmii = 0,
2281 +};
2282 +
2283 +
2284 +static void __init cam60_board_init(void)
2285 +{
2286 + /* Serial */
2287 + at91_add_device_serial();
2288 + /* SPI */
2289 + at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
2290 + /* Ethernet */
2291 + at91_add_device_eth(&cam60_macb_data);
2292 +}
2293 +
2294 +MACHINE_START(CAM60, "KwikByte CAM60")
2295 + /* Maintainer: KwikByte */
2296 + .phys_io = AT91_BASE_SYS,
2297 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
2298 + .boot_params = AT91_SDRAM_BASE + 0x100,
2299 + .timer = &at91sam926x_timer,
2300 + .map_io = cam60_map_io,
2301 + .init_irq = cam60_init_irq,
2302 + .init_machine = cam60_board_init,
2303 +MACHINE_END
2304 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-chub.c linux-2.6-stable/arch/arm/mach-at91/board-chub.c
2305 --- linux-2.6.21/arch/arm/mach-at91/board-chub.c Thu Jan 1 02:00:00 1970
2306 +++ linux-2.6-stable/arch/arm/mach-at91/board-chub.c Tue May 8 12:13:30 2007
2307 @@ -0,0 +1,132 @@
2308 +/*
2309 + * linux/arch/arm/mach-at91/board-chub.c
2310 + *
2311 + * Copyright (C) 2005 SAN People, adapted for Promwad Chub board
2312 + * by Kuten Ivan
2313 + *
2314 + * This program is free software; you can redistribute it and/or modify
2315 + * it under the terms of the GNU General Public License as published by
2316 + * the Free Software Foundation; either version 2 of the License, or
2317 + * (at your option) any later version.
2318 + *
2319 + * This program is distributed in the hope that it will be useful,
2320 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2321 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2322 + * GNU General Public License for more details.
2323 + *
2324 + * You should have received a copy of the GNU General Public License
2325 + * along with this program; if not, write to the Free Software
2326 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2327 + */
2328 +
2329 +#include <linux/types.h>
2330 +#include <linux/init.h>
2331 +#include <linux/mm.h>
2332 +#include <linux/module.h>
2333 +#include <linux/platform_device.h>
2334 +
2335 +#include <asm/hardware.h>
2336 +#include <asm/setup.h>
2337 +#include <asm/mach-types.h>
2338 +#include <asm/irq.h>
2339 +
2340 +#include <asm/mach/arch.h>
2341 +#include <asm/mach/map.h>
2342 +#include <asm/mach/irq.h>
2343 +
2344 +#include <asm/arch/board.h>
2345 +#include <asm/arch/gpio.h>
2346 +
2347 +#include "generic.h"
2348 +
2349 +/*
2350 + * Serial port configuration.
2351 + * 0 .. 3 = USART0 .. USART3
2352 + * 4 = DBGU
2353 + */
2354 +static struct at91_uart_config __initdata chub_uart_config = {
2355 + .console_tty = 0, /* ttyS0 */
2356 + .nr_tty = 5,
2357 + .tty_map = { 4, 0, 1, 2, 3 } /* ttyS0, ..., ttyS4 */
2358 +};
2359 +
2360 +static void __init chub_init_irq(void)
2361 +{
2362 + at91rm9200_init_interrupts(NULL);
2363 +}
2364 +
2365 +static void __init chub_map_io(void)
2366 +{
2367 + /* Initialize clocks: 18.432 MHz crystal */
2368 + at91rm9200_initialize(18432000, AT91RM9200_PQFP);
2369 +
2370 + /* Setup the serial ports and console */
2371 + at91_init_serial(&chub_uart_config);
2372 +}
2373 +
2374 +static struct at91_eth_data __initdata chub_eth_data = {
2375 + .phy_irq_pin = AT91_PIN_PB29,
2376 + .is_rmii = 0,
2377 +};
2378 +
2379 +static struct mtd_partition __initdata chub_nand_partition[] = {
2380 + {
2381 + .name = "NAND Partition 1",
2382 + .offset = 0,
2383 + .size = MTDPART_SIZ_FULL,
2384 + },
2385 +};
2386 +
2387 +static struct mtd_partition *nand_partitions(int size, int *num_partitions)
2388 +{
2389 + *num_partitions = ARRAY_SIZE(chub_nand_partition);
2390 + return chub_nand_partition;
2391 +}
2392 +
2393 +static struct at91_nand_data __initdata chub_nand_data = {
2394 + .ale = 22,
2395 + .cle = 21,
2396 + .enable_pin = AT91_PIN_PA27,
2397 + .partition_info = nand_partitions,
2398 +};
2399 +
2400 +static struct spi_board_info chub_spi_devices[] = {
2401 + { /* DataFlash chip */
2402 + .modalias = "mtd_dataflash",
2403 + .chip_select = 0,
2404 + .max_speed_hz = 15 * 1000 * 1000,
2405 + },
2406 +};
2407 +
2408 +static void __init chub_board_init(void)
2409 +{
2410 + /* Serial */
2411 + at91_add_device_serial();
2412 + /* I2C */
2413 + at91_add_device_i2c();
2414 + /* Ethernet */
2415 + at91_add_device_eth(&chub_eth_data);
2416 + /* SPI */
2417 + at91_add_device_spi(chub_spi_devices, ARRAY_SIZE(chub_spi_devices));
2418 + /* NAND Flash */
2419 + at91_add_device_nand(&chub_nand_data);
2420 + /* Disable write protect for NAND */
2421 + at91_set_gpio_output(AT91_PIN_PB7, 1);
2422 + /* Power enable for 3x RS-232 and 1x RS-485 */
2423 + at91_set_gpio_output(AT91_PIN_PB9, 1);
2424 + /* Disable write protect for FRAM */
2425 + at91_set_gpio_output(AT91_PIN_PA21, 1);
2426 + /* Disable write protect for Dataflash */
2427 + at91_set_gpio_output(AT91_PIN_PA19, 1);
2428 +}
2429 +
2430 +MACHINE_START(CHUB, "Promwad Chub")
2431 + /* Maintainer: Ivan Kuten AT Promwad DOT com */
2432 + .phys_io = AT91_BASE_SYS,
2433 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
2434 + .boot_params = AT91_SDRAM_BASE + 0x100,
2435 + .timer = &at91rm9200_timer,
2436 + .map_io = chub_map_io,
2437 + .init_irq = chub_init_irq,
2438 + .init_machine = chub_board_init,
2439 +MACHINE_END
2440 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-csb337.c linux-2.6-stable/arch/arm/mach-at91/board-csb337.c
2441 --- linux-2.6.21/arch/arm/mach-at91/board-csb337.c Thu Apr 26 05:08:32 2007
2442 +++ linux-2.6-stable/arch/arm/mach-at91/board-csb337.c Tue May 8 12:13:30 2007
2443 @@ -24,6 +24,7 @@
2444 #include <linux/module.h>
2445 #include <linux/platform_device.h>
2446 #include <linux/spi/spi.h>
2447 +#include <linux/interrupt.h>
2448 #include <linux/mtd/physmap.h>
2449
2450 #include <asm/hardware.h>
2451 @@ -59,6 +60,7 @@
2452
2453 /* Setup the LEDs */
2454 at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
2455 + at91_set_gpio_output(AT91_PIN_PB2, 1); /* third (unused) LED */
2456
2457 /* Setup the serial ports and console */
2458 at91_init_serial(&csb337_uart_config);
2459 @@ -149,6 +151,55 @@
2460 .num_resources = ARRAY_SIZE(csb_flash_resources),
2461 };
2462
2463 +static struct at91_gpio_led csb337_leds[] = {
2464 + {
2465 + .name = "led0",
2466 + .gpio = AT91_PIN_PB0,
2467 + .trigger = "heartbeat",
2468 + },
2469 + {
2470 + .name = "led1",
2471 + .gpio = AT91_PIN_PB1,
2472 + .trigger = "timer",
2473 + },
2474 + {
2475 + .name = "led2",
2476 + .gpio = AT91_PIN_PB2,
2477 + }
2478 +};
2479 +
2480 +#if defined(CONFIG_CSB300_WAKE_SW0) || defined(CONFIG_CSB300_WAKE_SW1)
2481 +static irqreturn_t switch_irq_handler(int irq, void *context)
2482 +{
2483 + return IRQ_HANDLED;
2484 +}
2485 +
2486 +static inline void __init switch_irq_setup(int irq, char *name, unsigned long mode)
2487 +{
2488 + int res;
2489 +
2490 + res = request_irq(irq, switch_irq_handler, IRQF_SAMPLE_RANDOM | mode, name, NULL);
2491 + if (res == 0)
2492 + enable_irq_wake(irq);
2493 +}
2494 +
2495 +static void __init csb300_switches(void)
2496 +{
2497 +#ifdef CONFIG_CSB300_WAKE_SW0
2498 + at91_set_A_periph(AT91_PIN_PB29, 1); /* IRQ0 */
2499 + switch_irq_setup(AT91RM9200_ID_IRQ0, "csb300_sw0", IRQF_TRIGGER_FALLING);
2500 +#endif
2501 +#ifdef CONFIG_CSB300_WAKE_SW1
2502 + at91_set_gpio_input(AT91_PIN_PB28, 1);
2503 + at91_set_deglitch(AT91_PIN_PB28, 1);
2504 + switch_irq_setup(AT91_PIN_PB28, "csb300_sw1", IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING);
2505 +#endif
2506 + /* there's also SW2 at PA21, GPIO or TIOA2 */
2507 +}
2508 +#else
2509 +static void __init csb300_switches(void) {}
2510 +#endif
2511 +
2512 static void __init csb337_board_init(void)
2513 {
2514 /* Serial */
2515 @@ -168,8 +219,12 @@
2516 at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
2517 /* MMC */
2518 at91_add_device_mmc(0, &csb337_mmc_data);
2519 + /* LEDS */
2520 + at91_gpio_leds(csb337_leds, ARRAY_SIZE(csb337_leds));
2521 /* NOR flash */
2522 platform_device_register(&csb_flash);
2523 + /* Switches on CSB300 */
2524 + csb300_switches();
2525 }
2526
2527 MACHINE_START(CSB337, "Cogent CSB337")
2528 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-dk.c linux-2.6-stable/arch/arm/mach-at91/board-dk.c
2529 --- linux-2.6.21/arch/arm/mach-at91/board-dk.c Thu Apr 26 05:08:32 2007
2530 +++ linux-2.6-stable/arch/arm/mach-at91/board-dk.c Tue May 8 14:29:12 2007
2531 @@ -73,6 +73,185 @@
2532 at91rm9200_init_interrupts(NULL);
2533 }
2534
2535 +#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
2536 +#include <video/s1d13xxxfb.h>
2537 +#include <asm/arch/ics1523.h>
2538 +
2539 +/* EPSON S1D13806 FB */
2540 +#define AT91_FB_REG_BASE 0x30000000L
2541 +#define AT91_FB_REG_SIZE 0x200
2542 +#define AT91_FB_VMEM_BASE 0x30200000L
2543 +#define AT91_FB_VMEM_SIZE 0x140000L
2544 +
2545 +static void __init dk_init_video(void)
2546 +{
2547 + /* NWAIT Signal */
2548 + at91_set_A_periph(AT91_PIN_PC6, 0);
2549 +
2550 + /* Initialization of the Static Memory Controller for Chip Select 2 */
2551 + at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
2552 + | AT91_SMC_WSEN | AT91_SMC_NWS_(4) /* wait states */
2553 + | AT91_SMC_TDF_(1) /* float time */
2554 + );
2555 +
2556 + at91_ics1523_init();
2557 +}
2558 +
2559 +/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz)
2560 + Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
2561 +static const struct s1d13xxxfb_regval dk_s1dfb_initregs[] = {
2562 + {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */
2563 + {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */
2564 + {S1DREG_GPIO_CNF0, 0x00},
2565 + {S1DREG_GPIO_CNF1, 0x00},
2566 + {S1DREG_GPIO_CTL0, 0x08},
2567 + {S1DREG_GPIO_CTL1, 0x00},
2568 + {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/
2569 + {S1DREG_LCD_CLK_CNF, 0x00},
2570 + {S1DREG_CRT_CLK_CNF, 0x00},
2571 + {S1DREG_MPLUG_CLK_CNF, 0x00},
2572 + {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */
2573 + {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */
2574 + {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */
2575 + {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */
2576 + {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */
2577 + {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
2578 + {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */
2579 + {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */
2580 + {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */
2581 + {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */
2582 + {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */
2583 + {S1DREG_LCD_DISP_VHEIGHT0, 0xDF},
2584 + {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */
2585 + {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */
2586 + {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */
2587 + {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */
2588 + {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */
2589 + {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */
2590 + {S1DREG_LCD_DISP_START0, 0x00},
2591 + {S1DREG_LCD_DISP_START1, 0xC8},
2592 + {S1DREG_LCD_DISP_START2, 0x00},
2593 + {S1DREG_LCD_MEM_OFF0, 0x80},
2594 + {S1DREG_LCD_MEM_OFF1, 0x02},
2595 + {S1DREG_LCD_PIX_PAN, 0x00},
2596 + {S1DREG_LCD_DISP_FIFO_HTC, 0x3B},
2597 + {S1DREG_LCD_DISP_FIFO_LTC, 0x3C},
2598 + {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */
2599 + {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */
2600 + {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */
2601 + {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */
2602 + {S1DREG_CRT_DISP_VHEIGHT0, 0xDF},
2603 + {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */
2604 + {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */
2605 + {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */
2606 + {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */
2607 + {S1DREG_TV_OUT_CTL, 0x10},
2608 + {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */
2609 + {S1DREG_CRT_DISP_START0, 0x00},
2610 + {S1DREG_CRT_DISP_START1, 0x00},
2611 + {S1DREG_CRT_DISP_START2, 0x00},
2612 + {S1DREG_CRT_MEM_OFF0, 0x80},
2613 + {S1DREG_CRT_MEM_OFF1, 0x02},
2614 + {S1DREG_CRT_PIX_PAN, 0x00},
2615 + {S1DREG_CRT_DISP_FIFO_HTC, 0x3B},
2616 + {S1DREG_CRT_DISP_FIFO_LTC, 0x3C},
2617 + {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */
2618 + {S1DREG_LCD_CUR_START, 0x01},
2619 + {S1DREG_LCD_CUR_XPOS0, 0x00},
2620 + {S1DREG_LCD_CUR_XPOS1, 0x00},
2621 + {S1DREG_LCD_CUR_YPOS0, 0x00},
2622 + {S1DREG_LCD_CUR_YPOS1, 0x00},
2623 + {S1DREG_LCD_CUR_BCTL0, 0x00},
2624 + {S1DREG_LCD_CUR_GCTL0, 0x00},
2625 + {S1DREG_LCD_CUR_RCTL0, 0x00},
2626 + {S1DREG_LCD_CUR_BCTL1, 0x1F},
2627 + {S1DREG_LCD_CUR_GCTL1, 0x3F},
2628 + {S1DREG_LCD_CUR_RCTL1, 0x1F},
2629 + {S1DREG_LCD_CUR_FIFO_HTC, 0x00},
2630 + {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */
2631 + {S1DREG_CRT_CUR_START, 0x01},
2632 + {S1DREG_CRT_CUR_XPOS0, 0x00},
2633 + {S1DREG_CRT_CUR_XPOS1, 0x00},
2634 + {S1DREG_CRT_CUR_YPOS0, 0x00},
2635 + {S1DREG_CRT_CUR_YPOS1, 0x00},
2636 + {S1DREG_CRT_CUR_BCTL0, 0x00},
2637 + {S1DREG_CRT_CUR_GCTL0, 0x00},
2638 + {S1DREG_CRT_CUR_RCTL0, 0x00},
2639 + {S1DREG_CRT_CUR_BCTL1, 0x1F},
2640 + {S1DREG_CRT_CUR_GCTL1, 0x3F},
2641 + {S1DREG_CRT_CUR_RCTL1, 0x1F},
2642 + {S1DREG_CRT_CUR_FIFO_HTC, 0x00},
2643 + {S1DREG_BBLT_CTL0, 0x00},
2644 + {S1DREG_BBLT_CTL0, 0x00},
2645 + {S1DREG_BBLT_CC_EXP, 0x00},
2646 + {S1DREG_BBLT_OP, 0x00},
2647 + {S1DREG_BBLT_SRC_START0, 0x00},
2648 + {S1DREG_BBLT_SRC_START1, 0x00},
2649 + {S1DREG_BBLT_SRC_START2, 0x00},
2650 + {S1DREG_BBLT_DST_START0, 0x00},
2651 + {S1DREG_BBLT_DST_START1, 0x00},
2652 + {S1DREG_BBLT_DST_START2, 0x00},
2653 + {S1DREG_BBLT_MEM_OFF0, 0x00},
2654 + {S1DREG_BBLT_MEM_OFF1, 0x00},
2655 + {S1DREG_BBLT_WIDTH0, 0x00},
2656 + {S1DREG_BBLT_WIDTH1, 0x00},
2657 + {S1DREG_BBLT_HEIGHT0, 0x00},
2658 + {S1DREG_BBLT_HEIGHT1, 0x00},
2659 + {S1DREG_BBLT_BGC0, 0x00},
2660 + {S1DREG_BBLT_BGC1, 0x00},
2661 + {S1DREG_BBLT_FGC0, 0x00},
2662 + {S1DREG_BBLT_FGC1, 0x00},
2663 + {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */
2664 + {S1DREG_LKUP_ADDR, 0x00},
2665 + {S1DREG_PS_CNF, 0x00}, /* Power Save disable */
2666 + {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */
2667 + {S1DREG_CPU2MEM_WDOGT, 0x00},
2668 + {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */
2669 +};
2670 +
2671 +static struct s1d13xxxfb_pdata dk_s1dfb_pdata = {
2672 + .initregs = dk_s1dfb_initregs,
2673 + .initregssize = ARRAY_SIZE(dk_s1dfb_initregs),
2674 + .platform_init_video = dk_init_video,
2675 +};
2676 +
2677 +static u64 s1dfb_dmamask = 0xffffffffUL;
2678 +
2679 +static struct resource dk_s1dfb_resource[] = {
2680 + [0] = { /* video mem */
2681 + .name = "s1d13806 memory",
2682 + .start = AT91_FB_VMEM_BASE,
2683 + .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
2684 + .flags = IORESOURCE_MEM,
2685 + },
2686 + [1] = { /* video registers */
2687 + .name = "s1d13806 registers",
2688 + .start = AT91_FB_REG_BASE,
2689 + .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
2690 + .flags = IORESOURCE_MEM,
2691 + },
2692 +};
2693 +
2694 +static struct platform_device dk_s1dfb_device = {
2695 + .name = "s1d13806fb",
2696 + .id = -1,
2697 + .dev = {
2698 + .dma_mask = &s1dfb_dmamask,
2699 + .coherent_dma_mask = 0xffffffff,
2700 + .platform_data = &dk_s1dfb_pdata,
2701 + },
2702 + .resource = dk_s1dfb_resource,
2703 + .num_resources = ARRAY_SIZE(dk_s1dfb_resource),
2704 +};
2705 +
2706 +static void __init dk_add_device_video(void)
2707 +{
2708 + platform_device_register(&dk_s1dfb_device);
2709 +}
2710 +#else
2711 +static void __init dk_add_device_video(void) {}
2712 +#endif
2713 +
2714 static struct at91_eth_data __initdata dk_eth_data = {
2715 .phy_irq_pin = AT91_PIN_PC4,
2716 .is_rmii = 1,
2717 @@ -151,7 +330,7 @@
2718 #define DK_FLASH_SIZE 0x200000
2719
2720 static struct physmap_flash_data dk_flash_data = {
2721 - .width = 2,
2722 + .width = 2,
2723 };
2724
2725 static struct resource dk_flash_resource = {
2726 @@ -170,6 +349,13 @@
2727 .num_resources = 1,
2728 };
2729
2730 +static struct at91_gpio_led dk_leds[] = {
2731 + {
2732 + .name = "led0",
2733 + .gpio = AT91_PIN_PB2,
2734 + .trigger = "timer",
2735 + }
2736 +};
2737
2738 static void __init dk_board_init(void)
2739 {
2740 @@ -200,8 +386,10 @@
2741 at91_add_device_nand(&dk_nand_data);
2742 /* NOR Flash */
2743 platform_device_register(&dk_flash);
2744 + /* LEDs */
2745 + at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds));
2746 /* VGA */
2747 -// dk_add_device_video();
2748 + dk_add_device_video();
2749 }
2750
2751 MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
2752 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-ek.c linux-2.6-stable/arch/arm/mach-at91/board-ek.c
2753 --- linux-2.6.21/arch/arm/mach-at91/board-ek.c Thu Apr 26 05:08:32 2007
2754 +++ linux-2.6-stable/arch/arm/mach-at91/board-ek.c Tue May 8 14:29:22 2007
2755 @@ -73,6 +73,187 @@
2756 at91rm9200_init_interrupts(NULL);
2757 }
2758
2759 +#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
2760 +#include <video/s1d13xxxfb.h>
2761 +#include <asm/arch/ics1523.h>
2762 +
2763 +/* EPSON S1D13806 FB */
2764 +#define AT91_FB_REG_BASE 0x40000000L
2765 +#define AT91_FB_REG_SIZE 0x200
2766 +#define AT91_FB_VMEM_BASE 0x40200000L
2767 +#define AT91_FB_VMEM_SIZE 0x140000L
2768 +
2769 +static void __init ek_init_video(void)
2770 +{
2771 + /* NWAIT Signal */
2772 + at91_set_A_periph(AT91_PIN_PC6, 0);
2773 +
2774 + /* Initialization of the Static Memory Controller for Chip Select 3 */
2775 + at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16 /* 16 bit */
2776 + | AT91_SMC_WSEN | AT91_SMC_NWS_(5) /* wait states */
2777 + | AT91_SMC_TDF_(1) /* float time */
2778 + );
2779 +
2780 + at91_ics1523_init();
2781 +}
2782 +
2783 +/* CRT: (active) 640x480 60Hz (PCLK=CLKI=25.175MHz)
2784 + Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
2785 +static const struct s1d13xxxfb_regval ek_s1dfb_initregs[] = {
2786 + {S1DREG_MISC, 0x00}, /* Enable Memory/Register select bit */
2787 + {S1DREG_COM_DISP_MODE, 0x00}, /* disable display output */
2788 + {S1DREG_GPIO_CNF0, 0xFF}, // 0x00
2789 + {S1DREG_GPIO_CNF1, 0x1F}, // 0x08
2790 + {S1DREG_GPIO_CTL0, 0x00},
2791 + {S1DREG_GPIO_CTL1, 0x00},
2792 + {S1DREG_CLK_CNF, 0x01}, /* no divide, MCLK source is CLKI3 0x02*/
2793 + {S1DREG_LCD_CLK_CNF, 0x00},
2794 + {S1DREG_CRT_CLK_CNF, 0x00},
2795 + {S1DREG_MPLUG_CLK_CNF, 0x00},
2796 + {S1DREG_CPU2MEM_WST_SEL, 0x01}, /* 2*period(MCLK) - 4ns > period(BCLK) */
2797 + {S1DREG_SDRAM_REF_RATE, 0x03}, /* 32768 <= MCLK <= 50000 (MHz) */
2798 + {S1DREG_SDRAM_TC0, 0x00}, /* MCLK source freq (MHz): */
2799 + {S1DREG_SDRAM_TC1, 0x01}, /* 42 <= MCLK <= 50 */
2800 + {S1DREG_MEM_CNF, 0x80}, /* SDRAM Initialization - needed before mem access */
2801 + {S1DREG_PANEL_TYPE, 0x25}, /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
2802 + {S1DREG_MOD_RATE, 0x00}, /* toggle every FPFRAME */
2803 + {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* 680 pix */
2804 + {S1DREG_LCD_NDISP_HPER, 0x12}, /* 152 pix */
2805 + {S1DREG_TFT_FPLINE_START, 0x01}, /* 13 pix */
2806 + {S1DREG_TFT_FPLINE_PWIDTH, 0x0B}, /* 96 pix */
2807 + {S1DREG_LCD_DISP_VHEIGHT0, 0xDF},
2808 + {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* 480 lines */
2809 + {S1DREG_LCD_NDISP_VPER, 0x2C}, /* 44 lines */
2810 + {S1DREG_TFT_FPFRAME_START, 0x0A}, /* 10 lines */
2811 + {S1DREG_TFT_FPFRAME_PWIDTH, 0x01}, /* 2 lines */
2812 + {S1DREG_LCD_DISP_MODE, 0x05}, /* 16 bpp */
2813 + {S1DREG_LCD_MISC, 0x00}, /* dithering enabled, dual panel buffer enabled */
2814 + {S1DREG_LCD_DISP_START0, 0x00},
2815 + {S1DREG_LCD_DISP_START1, 0xC8},
2816 + {S1DREG_LCD_DISP_START2, 0x00},
2817 + {S1DREG_LCD_MEM_OFF0, 0x80},
2818 + {S1DREG_LCD_MEM_OFF1, 0x02},
2819 + {S1DREG_LCD_PIX_PAN, 0x00},
2820 + {S1DREG_LCD_DISP_FIFO_HTC, 0x3B},
2821 + {S1DREG_LCD_DISP_FIFO_LTC, 0x3C},
2822 + {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* 680 pix */
2823 + {S1DREG_CRT_NDISP_HPER, 0x13}, /* 160 pix */
2824 + {S1DREG_CRT_HRTC_START, 0x01}, /* 13 pix */
2825 + {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* 96 pix */
2826 + {S1DREG_CRT_DISP_VHEIGHT0, 0xDF},
2827 + {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* 480 lines */
2828 + {S1DREG_CRT_NDISP_VPER, 0x2B}, /* 44 lines */
2829 + {S1DREG_CRT_VRTC_START, 0x09}, /* 10 lines */
2830 + {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* 2 lines */
2831 + {S1DREG_TV_OUT_CTL, 0x10},
2832 + {0x005E, 0x9F},
2833 + {0x005F, 0x00},
2834 + {S1DREG_CRT_DISP_MODE, 0x05}, /* 16 bpp */
2835 + {S1DREG_CRT_DISP_START0, 0x00},
2836 + {S1DREG_CRT_DISP_START1, 0x00},
2837 + {S1DREG_CRT_DISP_START2, 0x00},
2838 + {S1DREG_CRT_MEM_OFF0, 0x80},
2839 + {S1DREG_CRT_MEM_OFF1, 0x02},
2840 + {S1DREG_CRT_PIX_PAN, 0x00},
2841 + {S1DREG_CRT_DISP_FIFO_HTC, 0x3B},
2842 + {S1DREG_CRT_DISP_FIFO_LTC, 0x3C},
2843 + {S1DREG_LCD_CUR_CTL, 0x00}, /* inactive */
2844 + {S1DREG_LCD_CUR_START, 0x01},
2845 + {S1DREG_LCD_CUR_XPOS0, 0x00},
2846 + {S1DREG_LCD_CUR_XPOS1, 0x00},
2847 + {S1DREG_LCD_CUR_YPOS0, 0x00},
2848 + {S1DREG_LCD_CUR_YPOS1, 0x00},
2849 + {S1DREG_LCD_CUR_BCTL0, 0x00},
2850 + {S1DREG_LCD_CUR_GCTL0, 0x00},
2851 + {S1DREG_LCD_CUR_RCTL0, 0x00},
2852 + {S1DREG_LCD_CUR_BCTL1, 0x1F},
2853 + {S1DREG_LCD_CUR_GCTL1, 0x3F},
2854 + {S1DREG_LCD_CUR_RCTL1, 0x1F},
2855 + {S1DREG_LCD_CUR_FIFO_HTC, 0x00},
2856 + {S1DREG_CRT_CUR_CTL, 0x00}, /* inactive */
2857 + {S1DREG_CRT_CUR_START, 0x01},
2858 + {S1DREG_CRT_CUR_XPOS0, 0x00},
2859 + {S1DREG_CRT_CUR_XPOS1, 0x00},
2860 + {S1DREG_CRT_CUR_YPOS0, 0x00},
2861 + {S1DREG_CRT_CUR_YPOS1, 0x00},
2862 + {S1DREG_CRT_CUR_BCTL0, 0x00},
2863 + {S1DREG_CRT_CUR_GCTL0, 0x00},
2864 + {S1DREG_CRT_CUR_RCTL0, 0x00},
2865 + {S1DREG_CRT_CUR_BCTL1, 0x1F},
2866 + {S1DREG_CRT_CUR_GCTL1, 0x3F},
2867 + {S1DREG_CRT_CUR_RCTL1, 0x1F},
2868 + {S1DREG_CRT_CUR_FIFO_HTC, 0x00},
2869 + {S1DREG_BBLT_CTL0, 0x00},
2870 + {S1DREG_BBLT_CTL0, 0x00},
2871 + {S1DREG_BBLT_CC_EXP, 0x00},
2872 + {S1DREG_BBLT_OP, 0x00},
2873 + {S1DREG_BBLT_SRC_START0, 0x00},
2874 + {S1DREG_BBLT_SRC_START1, 0x00},
2875 + {S1DREG_BBLT_SRC_START2, 0x00},
2876 + {S1DREG_BBLT_DST_START0, 0x00},
2877 + {S1DREG_BBLT_DST_START1, 0x00},
2878 + {S1DREG_BBLT_DST_START2, 0x00},
2879 + {S1DREG_BBLT_MEM_OFF0, 0x00},
2880 + {S1DREG_BBLT_MEM_OFF1, 0x00},
2881 + {S1DREG_BBLT_WIDTH0, 0x00},
2882 + {S1DREG_BBLT_WIDTH1, 0x00},
2883 + {S1DREG_BBLT_HEIGHT0, 0x00},
2884 + {S1DREG_BBLT_HEIGHT1, 0x00},
2885 + {S1DREG_BBLT_BGC0, 0x00},
2886 + {S1DREG_BBLT_BGC1, 0x00},
2887 + {S1DREG_BBLT_FGC0, 0x00},
2888 + {S1DREG_BBLT_FGC1, 0x00},
2889 + {S1DREG_LKUP_MODE, 0x00}, /* LCD LUT r | LCD and CRT/TV LUT w */
2890 + {S1DREG_LKUP_ADDR, 0x00},
2891 + {S1DREG_PS_CNF, 0x10}, /* Power Save disable */
2892 + {S1DREG_PS_STATUS, 0x02}, /* LCD Panel down, mem up */
2893 + {S1DREG_CPU2MEM_WDOGT, 0x00},
2894 + {S1DREG_COM_DISP_MODE, 0x02}, /* enable CRT display output */
2895 +};
2896 +
2897 +static struct s1d13xxxfb_pdata ek_s1dfb_pdata = {
2898 + .initregs = ek_s1dfb_initregs,
2899 + .initregssize = ARRAY_SIZE(ek_s1dfb_initregs),
2900 + .platform_init_video = ek_init_video,
2901 +};
2902 +
2903 +static u64 s1dfb_dmamask = 0xffffffffUL;
2904 +
2905 +static struct resource ek_s1dfb_resource[] = {
2906 + [0] = { /* video mem */
2907 + .name = "s1d13806 memory",
2908 + .start = AT91_FB_VMEM_BASE,
2909 + .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
2910 + .flags = IORESOURCE_MEM,
2911 + },
2912 + [1] = { /* video registers */
2913 + .name = "s1d13806 registers",
2914 + .start = AT91_FB_REG_BASE,
2915 + .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
2916 + .flags = IORESOURCE_MEM,
2917 + },
2918 +};
2919 +
2920 +static struct platform_device ek_s1dfb_device = {
2921 + .name = "s1d13806fb",
2922 + .id = -1,
2923 + .dev = {
2924 + .dma_mask = &s1dfb_dmamask,
2925 + .coherent_dma_mask = 0xffffffff,
2926 + .platform_data = &ek_s1dfb_pdata,
2927 + },
2928 + .resource = ek_s1dfb_resource,
2929 + .num_resources = ARRAY_SIZE(ek_s1dfb_resource),
2930 +};
2931 +
2932 +static void __init ek_add_device_video(void)
2933 +{
2934 + platform_device_register(&ek_s1dfb_device);
2935 +}
2936 +#else
2937 +static void __init ek_add_device_video(void) {}
2938 +#endif
2939 +
2940 static struct at91_eth_data __initdata ek_eth_data = {
2941 .phy_irq_pin = AT91_PIN_PC4,
2942 .is_rmii = 1,
2943 @@ -113,7 +294,7 @@
2944 #define EK_FLASH_SIZE 0x200000
2945
2946 static struct physmap_flash_data ek_flash_data = {
2947 - .width = 2,
2948 + .width = 2,
2949 };
2950
2951 static struct resource ek_flash_resource = {
2952 @@ -132,6 +313,18 @@
2953 .num_resources = 1,
2954 };
2955
2956 +static struct at91_gpio_led ek_leds[] = {
2957 + {
2958 + .name = "led0",
2959 + .gpio = AT91_PIN_PB1,
2960 + .trigger = "heartbeat",
2961 + },
2962 + {
2963 + .name = "led1",
2964 + .gpio = AT91_PIN_PB2,
2965 + .trigger = "timer",
2966 + }
2967 +};
2968
2969 static void __init ek_board_init(void)
2970 {
2971 @@ -158,8 +351,10 @@
2972 #endif
2973 /* NOR Flash */
2974 platform_device_register(&ek_flash);
2975 + /* LEDs */
2976 + at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
2977 /* VGA */
2978 -// ek_add_device_video();
2979 + ek_add_device_video();
2980 }
2981
2982 MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
2983 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-kb9202.c linux-2.6-stable/arch/arm/mach-at91/board-kb9202.c
2984 --- linux-2.6.21/arch/arm/mach-at91/board-kb9202.c Thu Apr 26 05:08:32 2007
2985 +++ linux-2.6-stable/arch/arm/mach-at91/board-kb9202.c Tue May 8 12:21:31 2007
2986 @@ -37,6 +37,8 @@
2987 #include <asm/arch/board.h>
2988 #include <asm/arch/gpio.h>
2989
2990 +#include <asm/arch/at91rm9200_mc.h>
2991 +
2992 #include "generic.h"
2993
2994
2995 @@ -111,6 +113,48 @@
2996 .partition_info = nand_partitions,
2997 };
2998
2999 +
3000 +#if defined(CONFIG_FB_S1D15605)
3001 +#warning "Rather pass reset pin via platform_data"
3002 +static struct resource kb9202_lcd_resources[] = {
3003 + [0] = {
3004 + .start = AT91_CHIPSELECT_2,
3005 + .end = AT91_CHIPSELECT_2 + 0x200FF,
3006 + .flags = IORESOURCE_MEM
3007 + },
3008 + [1] = { /* reset pin */
3009 + .start = AT91_PIN_PC22,
3010 + .end = AT91_PIN_PC22,
3011 + .flags = IORESOURCE_MEM
3012 + },
3013 +};
3014 +
3015 +static struct platform_device kb9202_lcd_device = {
3016 + .name = "s1d15605fb",
3017 + .id = 0,
3018 + .num_resources = ARRAY_SIZE(kb9202_lcd_resources),
3019 + .resource = kb9202_lcd_resources,
3020 +};
3021 +
3022 +static void __init kb9202_add_device_lcd(void)
3023 +{
3024 + /* In case the boot loader did not set the chip select mode and timing */
3025 + at91_sys_write(AT91_SMC_CSR(2),
3026 + AT91_SMC_WSEN | AT91_SMC_NWS_(18) | AT91_SMC_TDF_(1) | AT91_SMC_DBW_8 |
3027 + AT91_SMC_RWSETUP_(1) | AT91_SMC_RWHOLD_(1));
3028 +
3029 + /* Backlight pin = output, off */
3030 + at91_set_gpio_output(AT91_PIN_PC23, 0);
3031 +
3032 + /* Reset pin = output, in reset */
3033 + at91_set_gpio_output(AT91_PIN_PC22, 0);
3034 +
3035 + platform_device_register(&kb9202_lcd_device);
3036 +}
3037 +#else
3038 +static void __init kb9202_add_device_lcd(void) {}
3039 +#endif
3040 +
3041 static void __init kb9202_board_init(void)
3042 {
3043 /* Serial */
3044 @@ -129,6 +173,8 @@
3045 at91_add_device_spi(NULL, 0);
3046 /* NAND */
3047 at91_add_device_nand(&kb9202_nand_data);
3048 + /* LCD */
3049 + kb9202_add_device_lcd();
3050 }
3051
3052 MACHINE_START(KB9200, "KB920x")
3053 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-sam9260ek.c linux-2.6-stable/arch/arm/mach-at91/board-sam9260ek.c
3054 --- linux-2.6.21/arch/arm/mach-at91/board-sam9260ek.c Thu Apr 26 05:08:32 2007
3055 +++ linux-2.6-stable/arch/arm/mach-at91/board-sam9260ek.c Tue May 8 12:13:30 2007
3056 @@ -104,9 +104,9 @@
3057 },
3058 #endif
3059 #endif
3060 -#if defined(CONFIG_SND_AT73C213)
3061 +#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
3062 { /* AT73C213 DAC */
3063 - .modalias = "snd_at73c213",
3064 + .modalias = "at73c213",
3065 .chip_select = 0,
3066 .max_speed_hz = 10 * 1000 * 1000,
3067 .bus_num = 1,
3068 @@ -118,7 +118,7 @@
3069 /*
3070 * MACB Ethernet device
3071 */
3072 -static struct __initdata at91_eth_data ek_macb_data = {
3073 +static struct at91_eth_data __initdata ek_macb_data = {
3074 .phy_irq_pin = AT91_PIN_PA7,
3075 .is_rmii = 1,
3076 };
3077 @@ -188,6 +188,8 @@
3078 at91_add_device_eth(&ek_macb_data);
3079 /* MMC */
3080 at91_add_device_mmc(0, &ek_mmc_data);
3081 + /* I2C */
3082 + at91_add_device_i2c();
3083 }
3084
3085 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
3086 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-sam9261ek.c linux-2.6-stable/arch/arm/mach-at91/board-sam9261ek.c
3087 --- linux-2.6.21/arch/arm/mach-at91/board-sam9261ek.c Thu Apr 26 05:08:32 2007
3088 +++ linux-2.6-stable/arch/arm/mach-at91/board-sam9261ek.c Wed May 9 12:37:19 2007
3089 @@ -25,7 +25,11 @@
3090 #include <linux/module.h>
3091 #include <linux/platform_device.h>
3092 #include <linux/spi/spi.h>
3093 +#include <linux/spi/ads7846.h>
3094 #include <linux/dm9000.h>
3095 +#include <linux/fb.h>
3096 +
3097 +#include <video/atmel_lcdc.h>
3098
3099 #include <asm/hardware.h>
3100 #include <asm/setup.h>
3101 @@ -59,6 +63,9 @@
3102 /* Initialize processor: 18.432 MHz crystal */
3103 at91sam9261_initialize(18432000);
3104
3105 + /* Setup the LEDs */
3106 + at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
3107 +
3108 /* Setup the serial ports and console */
3109 at91_init_serial(&ek_uart_config);
3110 }
3111 @@ -195,6 +202,41 @@
3112 };
3113
3114 /*
3115 + * ADS7846 Touchscreen
3116 + */
3117 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
3118 +
3119 +static int ads7843_pendown_state(void)
3120 +{
3121 + return !at91_get_gpio_value(AT91_PIN_PC2); /* Touchscreen PENIRQ */
3122 +}
3123 +
3124 +static struct ads7846_platform_data ads_info = {
3125 + .model = 7843,
3126 + .x_min = 150,
3127 + .x_max = 3830,
3128 + .y_min = 190,
3129 + .y_max = 3830,
3130 + .vref_delay_usecs = 100,
3131 + .x_plate_ohms = 450,
3132 + .y_plate_ohms = 250,
3133 + .pressure_max = 15000,
3134 + .debounce_max = 1,
3135 + .debounce_rep = 0,
3136 + .debounce_tol = (~0),
3137 + .get_pendown_state = ads7843_pendown_state,
3138 +};
3139 +
3140 +static void __init ek_add_device_ts(void)
3141 +{
3142 + at91_set_B_periph(AT91_PIN_PC2, 1); /* External IRQ0, with pullup */
3143 + at91_set_gpio_input(AT91_PIN_PA11, 1); /* Touchscreen BUSY signal */
3144 +}
3145 +#else
3146 +static void __init ek_add_device_ts(void) {}
3147 +#endif
3148 +
3149 +/*
3150 * SPI devices
3151 */
3152 static struct spi_board_info ek_spi_devices[] = {
3153 @@ -204,6 +246,17 @@
3154 .max_speed_hz = 15 * 1000 * 1000,
3155 .bus_num = 0,
3156 },
3157 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
3158 + {
3159 + .modalias = "ads7846",
3160 + .chip_select = 2,
3161 + .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
3162 + .bus_num = 0,
3163 + .platform_data = &ads_info,
3164 + .irq = AT91SAM9261_ID_IRQ0,
3165 + .controller_data = AT91_PIN_PA28, /* CS pin */
3166 + },
3167 +#endif
3168 #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
3169 { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
3170 .modalias = "mtd_dataflash",
3171 @@ -211,9 +264,9 @@
3172 .max_speed_hz = 15 * 1000 * 1000,
3173 .bus_num = 0,
3174 },
3175 -#elif defined(CONFIG_SND_AT73C213)
3176 +#elif defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
3177 { /* AT73C213 DAC */
3178 - .modalias = "snd_at73c213",
3179 + .modalias = "at73c213",
3180 .chip_select = 3,
3181 .max_speed_hz = 10 * 1000 * 1000,
3182 .bus_num = 0,
3183 @@ -222,6 +275,65 @@
3184 };
3185
3186
3187 +/*
3188 + * LCD Controller
3189 + */
3190 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
3191 +static struct fb_videomode at91_tft_vga_modes[] = {
3192 + {
3193 + .name = "TX09D50VM1CCA @ 60",
3194 + .refresh = 60,
3195 + .xres = 240, .yres = 320,
3196 + .pixclock = KHZ2PICOS(4965),
3197 +
3198 + .left_margin = 1, .right_margin = 33,
3199 + .upper_margin = 1, .lower_margin = 0,
3200 + .hsync_len = 5, .vsync_len = 1,
3201 +
3202 + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
3203 + .vmode = FB_VMODE_NONINTERLACED,
3204 + },
3205 +};
3206 +
3207 +static struct fb_monspecs at91fb_default_monspecs = {
3208 + .manufacturer = "HIT",
3209 + .monitor = "TX09D50VM1CCA",
3210 +
3211 + .modedb = at91_tft_vga_modes,
3212 + .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
3213 + .hfmin = 15000,
3214 + .hfmax = 64000,
3215 + .vfmin = 50,
3216 + .vfmax = 150,
3217 +};
3218 +
3219 +#define AT91SAM9261_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
3220 + | ATMEL_LCDC_DISTYPE_TFT \
3221 + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
3222 +
3223 +static void at91_lcdc_power_control(int on)
3224 +{
3225 + if (on)
3226 + at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
3227 + else
3228 + at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
3229 +}
3230 +
3231 +/* Driver datas */
3232 +static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
3233 + .default_bpp = 16,
3234 + .default_dmacon = ATMEL_LCDC_DMAEN,
3235 + .default_lcdcon2 = AT91SAM9261_DEFAULT_LCDCON2,
3236 + .default_monspecs = &at91fb_default_monspecs,
3237 + .atmel_lcdfb_power_control = at91_lcdc_power_control,
3238 + .guard_time = 1,
3239 +};
3240 +
3241 +#else
3242 +static struct atmel_lcdfb_info __initdata ek_lcdc_data;
3243 +#endif
3244 +
3245 +
3246 static void __init ek_board_init(void)
3247 {
3248 /* Serial */
3249 @@ -241,10 +353,14 @@
3250 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
3251 /* SPI */
3252 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
3253 + /* Touchscreen */
3254 + ek_add_device_ts();
3255 #else
3256 /* MMC */
3257 at91_add_device_mmc(0, &ek_mmc_data);
3258 #endif
3259 + /* LCD Controller */
3260 + at91_add_device_lcdc(&ek_lcdc_data);
3261 }
3262
3263 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
3264 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-sam9263ek.c linux-2.6-stable/arch/arm/mach-at91/board-sam9263ek.c
3265 --- linux-2.6.21/arch/arm/mach-at91/board-sam9263ek.c Thu Apr 26 05:08:32 2007
3266 +++ linux-2.6-stable/arch/arm/mach-at91/board-sam9263ek.c Tue May 8 12:56:33 2007
3267 @@ -25,6 +25,10 @@
3268 #include <linux/module.h>
3269 #include <linux/platform_device.h>
3270 #include <linux/spi/spi.h>
3271 +#include <linux/spi/ads7846.h>
3272 +#include <linux/fb.h>
3273 +
3274 +#include <video/atmel_lcdc.h>
3275
3276 #include <asm/hardware.h>
3277 #include <asm/setup.h>
3278 @@ -86,6 +90,40 @@
3279
3280
3281 /*
3282 + * ADS7846 Touchscreen
3283 + */
3284 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
3285 +static int ads7843_pendown_state(void)
3286 +{
3287 + return !at91_get_gpio_value(AT91_PIN_PA15); /* Touchscreen PENIRQ */
3288 +}
3289 +
3290 +static struct ads7846_platform_data ads_info = {
3291 + .model = 7843,
3292 + .x_min = 150,
3293 + .x_max = 3830,
3294 + .y_min = 190,
3295 + .y_max = 3830,
3296 + .vref_delay_usecs = 100,
3297 + .x_plate_ohms = 450,
3298 + .y_plate_ohms = 250,
3299 + .pressure_max = 15000,
3300 + .debounce_max = 1,
3301 + .debounce_rep = 0,
3302 + .debounce_tol = (~0),
3303 + .get_pendown_state = ads7843_pendown_state,
3304 +};
3305 +
3306 +static void __init ek_add_device_ts(void)
3307 +{
3308 + at91_set_B_periph(AT91_PIN_PA15, 1); /* External IRQ1, with pullup */
3309 + at91_set_gpio_input(AT91_PIN_PA31, 1); /* Touchscreen BUSY signal */
3310 +}
3311 +#else
3312 +static void __init ek_add_device_ts(void) {}
3313 +#endif
3314 +
3315 +/*
3316 * SPI devices.
3317 */
3318 static struct spi_board_info ek_spi_devices[] = {
3319 @@ -97,6 +135,16 @@
3320 .bus_num = 0,
3321 },
3322 #endif
3323 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
3324 + {
3325 + .modalias = "ads7846",
3326 + .chip_select = 3,
3327 + .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
3328 + .bus_num = 0,
3329 + .platform_data = &ads_info,
3330 + .irq = AT91SAM9263_ID_IRQ1,
3331 + },
3332 +#endif
3333 };
3334
3335
3336 @@ -112,6 +160,14 @@
3337
3338
3339 /*
3340 + * MACB Ethernet device
3341 + */
3342 +static struct at91_eth_data __initdata ek_macb_data = {
3343 + .is_rmii = 1,
3344 +};
3345 +
3346 +
3347 +/*
3348 * NAND flash
3349 */
3350 static struct mtd_partition __initdata ek_nand_partition[] = {
3351 @@ -148,6 +204,73 @@
3352 };
3353
3354
3355 +/*
3356 + * LCD Controller
3357 + */
3358 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
3359 +static struct fb_videomode at91_tft_vga_modes[] = {
3360 + {
3361 + .name = "TX09D50VM1CCA @ 60",
3362 + .refresh = 60,
3363 + .xres = 240, .yres = 320,
3364 + .pixclock = KHZ2PICOS(4965),
3365 +
3366 + .left_margin = 1, .right_margin = 33,
3367 + .upper_margin = 1, .lower_margin = 0,
3368 + .hsync_len = 5, .vsync_len = 1,
3369 +
3370 + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
3371 + .vmode = FB_VMODE_NONINTERLACED,
3372 + },
3373 +};
3374 +
3375 +static struct fb_monspecs at91fb_default_monspecs = {
3376 + .manufacturer = "HIT",
3377 + .monitor = "TX09D70VM1CCA",
3378 +
3379 + .modedb = at91_tft_vga_modes,
3380 + .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
3381 + .hfmin = 15000,
3382 + .hfmax = 64000,
3383 + .vfmin = 50,
3384 + .vfmax = 150,
3385 +};
3386 +
3387 +#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
3388 + | ATMEL_LCDC_DISTYPE_TFT \
3389 + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
3390 +
3391 +static void at91_lcdc_power_control(int on)
3392 +{
3393 + if (on)
3394 + at91_set_gpio_value(AT91_PIN_PD12, 0); /* power up */
3395 + else
3396 + at91_set_gpio_value(AT91_PIN_PD12, 1); /* power down */
3397 +}
3398 +
3399 +/* Driver datas */
3400 +static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
3401 + .default_bpp = 16,
3402 + .default_dmacon = ATMEL_LCDC_DMAEN,
3403 + .default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2,
3404 + .default_monspecs = &at91fb_default_monspecs,
3405 + .atmel_lcdfb_power_control = at91_lcdc_power_control,
3406 + .guard_time = 1,
3407 +};
3408 +
3409 +#else
3410 +static struct atmel_lcdfb_info __initdata ek_lcdc_data;
3411 +#endif
3412 +
3413 +
3414 +/*
3415 + * AC97
3416 + */
3417 +static struct atmel_ac97_data ek_ac97_data = {
3418 + .reset_pin = AT91_PIN_PA13,
3419 +};
3420 +
3421 +
3422 static void __init ek_board_init(void)
3423 {
3424 /* Serial */
3425 @@ -157,11 +280,22 @@
3426 /* USB Device */
3427 at91_add_device_udc(&ek_udc_data);
3428 /* SPI */
3429 + at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */
3430 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
3431 + /* Touchscreen */
3432 + ek_add_device_ts();
3433 /* MMC */
3434 at91_add_device_mmc(1, &ek_mmc_data);
3435 + /* Ethernet */
3436 + at91_add_device_eth(&ek_macb_data);
3437 /* NAND */
3438 at91_add_device_nand(&ek_nand_data);
3439 + /* I2C */
3440 + at91_add_device_i2c();
3441 + /* LCD Controller */
3442 + at91_add_device_lcdc(&ek_lcdc_data);
3443 + /* AC97 */
3444 + at91_add_device_ac97(&ek_ac97_data);
3445 }
3446
3447 MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
3448 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/board-sam9rlek.c linux-2.6-stable/arch/arm/mach-at91/board-sam9rlek.c
3449 --- linux-2.6.21/arch/arm/mach-at91/board-sam9rlek.c Thu Jan 1 02:00:00 1970
3450 +++ linux-2.6-stable/arch/arm/mach-at91/board-sam9rlek.c Wed May 9 10:58:34 2007
3451 @@ -0,0 +1,204 @@
3452 +/*
3453 + * Copyright (C) 2005 SAN People
3454 + * Copyright (C) 2007 Atmel Corporation
3455 + *
3456 + * This file is subject to the terms and conditions of the GNU General Public
3457 + * License. See the file COPYING in the main directory of this archive for
3458 + * more details.
3459 + */
3460 +
3461 +#include <linux/types.h>
3462 +#include <linux/init.h>
3463 +#include <linux/mm.h>
3464 +#include <linux/module.h>
3465 +#include <linux/platform_device.h>
3466 +#include <linux/spi/spi.h>
3467 +#include <linux/fb.h>
3468 +#include <linux/clk.h>
3469 +
3470 +#include <video/atmel_lcdc.h>
3471 +
3472 +#include <asm/hardware.h>
3473 +#include <asm/setup.h>
3474 +#include <asm/mach-types.h>
3475 +#include <asm/irq.h>
3476 +
3477 +#include <asm/mach/arch.h>
3478 +#include <asm/mach/map.h>
3479 +#include <asm/mach/irq.h>
3480 +
3481 +#include <asm/arch/board.h>
3482 +#include <asm/arch/gpio.h>
3483 +#include <asm/arch/at91sam926x_mc.h>
3484 +
3485 +#include "generic.h"
3486 +
3487 +
3488 +/*
3489 + * Serial port configuration.
3490 + * 0 .. 3 = USART0 .. USART3
3491 + * 4 = DBGU
3492 + */
3493 +static struct at91_uart_config __initdata ek_uart_config = {
3494 + .console_tty = 0, /* ttyS0 */
3495 + .nr_tty = 2,
3496 + .tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
3497 +};
3498 +
3499 +static void __init ek_map_io(void)
3500 +{
3501 + /* Initialize processor: 12.000 MHz crystal */
3502 + at91sam9rl_initialize(12000000);
3503 +
3504 + /* Setup the serial ports and console */
3505 + at91_init_serial(&ek_uart_config);
3506 +}
3507 +
3508 +static void __init ek_init_irq(void)
3509 +{
3510 + at91sam9rl_init_interrupts(NULL);
3511 +}
3512 +
3513 +
3514 +/*
3515 + * MCI (SD/MMC)
3516 + */
3517 +static struct at91_mmc_data __initdata ek_mmc_data = {
3518 + .wire4 = 1,
3519 + .det_pin = AT91_PIN_PA15,
3520 +// .wp_pin = ... not connected
3521 +// .vcc_pin = ... not connected
3522 +};
3523 +
3524 +
3525 +/*
3526 + * NAND flash
3527 + */
3528 +static struct mtd_partition __initdata ek_nand_partition[] = {
3529 + {
3530 + .name = "Partition 1",
3531 + .offset = 0,
3532 + .size = 256 * 1024,
3533 + },
3534 + {
3535 + .name = "Partition 2",
3536 + .offset = 256 * 1024 ,
3537 + .size = MTDPART_SIZ_FULL,
3538 + },
3539 +};
3540 +
3541 +static struct mtd_partition *nand_partitions(int size, int *num_partitions)
3542 +{
3543 + *num_partitions = ARRAY_SIZE(ek_nand_partition);
3544 + return ek_nand_partition;
3545 +}
3546 +
3547 +static struct at91_nand_data __initdata ek_nand_data = {
3548 + .ale = 21,
3549 + .cle = 22,
3550 +// .det_pin = ... not connected
3551 + .rdy_pin = AT91_PIN_PD17,
3552 + .enable_pin = AT91_PIN_PB6,
3553 + .partition_info = nand_partitions,
3554 + .bus_width_16 = 0,
3555 +};
3556 +
3557 +
3558 +/*
3559 + * SPI devices
3560 + */
3561 +static struct spi_board_info ek_spi_devices[] = {
3562 + { /* DataFlash chip */
3563 + .modalias = "mtd_dataflash",
3564 + .chip_select = 0,
3565 + .max_speed_hz = 15 * 1000 * 1000,
3566 + .bus_num = 0,
3567 + },
3568 +};
3569 +
3570 +
3571 +/*
3572 + * LCD Controller
3573 + */
3574 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
3575 +static struct fb_videomode at91_tft_vga_modes[] = {
3576 + {
3577 + .name = "TX09D50VM1CCA @ 60",
3578 + .refresh = 60,
3579 + .xres = 240, .yres = 320,
3580 + .pixclock = KHZ2PICOS(4965),
3581 +
3582 + .left_margin = 1, .right_margin = 33,
3583 + .upper_margin = 1, .lower_margin = 0,
3584 + .hsync_len = 5, .vsync_len = 1,
3585 +
3586 + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
3587 + .vmode = FB_VMODE_NONINTERLACED,
3588 + },
3589 +};
3590 +
3591 +static struct fb_monspecs at91fb_default_monspecs = {
3592 + .manufacturer = "HIT",
3593 + .monitor = "TX09D50VM1CCA",
3594 +
3595 + .modedb = at91_tft_vga_modes,
3596 + .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
3597 + .hfmin = 15000,
3598 + .hfmax = 64000,
3599 + .vfmin = 50,
3600 + .vfmax = 150,
3601 +};
3602 +
3603 +#define AT91SAM9RL_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
3604 + | ATMEL_LCDC_DISTYPE_TFT \
3605 + | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
3606 +
3607 +static void at91_lcdc_power_control(int on)
3608 +{
3609 + if (on)
3610 + at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
3611 + else
3612 + at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
3613 +}
3614 +
3615 +/* Driver datas */
3616 +static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
3617 + .default_bpp = 16,
3618 + .default_dmacon = ATMEL_LCDC_DMAEN,
3619 + .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2,
3620 + .default_monspecs = &at91fb_default_monspecs,
3621 + .atmel_lcdfb_power_control = at91_lcdc_power_control,
3622 + .guard_time = 1,
3623 +};
3624 +
3625 +#else
3626 +static struct atmel_lcdfb_info __initdata ek_lcdc_data;
3627 +#endif
3628 +
3629 +
3630 +static void __init ek_board_init(void)
3631 +{
3632 + /* Serial */
3633 + at91_add_device_serial();
3634 + /* I2C */
3635 + at91_add_device_i2c();
3636 + /* NAND */
3637 + at91_add_device_nand(&ek_nand_data);
3638 + /* SPI */
3639 + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
3640 + /* MMC */
3641 + at91_add_device_mmc(0, &ek_mmc_data);
3642 + /* LCD Controller */
3643 + at91_add_device_lcdc(&ek_lcdc_data);
3644 +}
3645 +
3646 +MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
3647 + /* Maintainer: Atmel */
3648 + .phys_io = AT91_BASE_SYS,
3649 + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
3650 + .boot_params = AT91_SDRAM_BASE + 0x100,
3651 + .timer = &at91sam926x_timer,
3652 + .map_io = ek_map_io,
3653 + .init_irq = ek_init_irq,
3654 + .init_machine = ek_board_init,
3655 +MACHINE_END
3656 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/clock.c linux-2.6-stable/arch/arm/mach-at91/clock.c
3657 --- linux-2.6.21/arch/arm/mach-at91/clock.c Thu Apr 26 05:08:32 2007
3658 +++ linux-2.6-stable/arch/arm/mach-at91/clock.c Tue May 8 12:13:30 2007
3659 @@ -32,6 +32,7 @@
3660 #include <asm/arch/cpu.h>
3661
3662 #include "clock.h"
3663 +#include "generic.h"
3664
3665
3666 /*
3667 @@ -254,6 +255,23 @@
3668
3669 /*------------------------------------------------------------------------*/
3670
3671 +#ifdef CONFIG_PM
3672 +
3673 +int clk_must_disable(struct clk *clk)
3674 +{
3675 + if (!at91_suspend_entering_slow_clock())
3676 + return 0;
3677 +
3678 + while (clk->parent)
3679 + clk = clk->parent;
3680 + return clk != &clk32k;
3681 +}
3682 +EXPORT_SYMBOL(clk_must_disable);
3683 +
3684 +#endif
3685 +
3686 +/*------------------------------------------------------------------------*/
3687 +
3688 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
3689
3690 /*
3691 @@ -375,6 +393,7 @@
3692 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
3693
3694 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
3695 +#warning "Hard-coded PCK"
3696 for (i = 0; i < 4; i++)
3697 seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
3698 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
3699 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/generic.h linux-2.6-stable/arch/arm/mach-at91/generic.h
3700 --- linux-2.6.21/arch/arm/mach-at91/generic.h Thu Apr 26 05:08:32 2007
3701 +++ linux-2.6-stable/arch/arm/mach-at91/generic.h Wed May 9 10:20:54 2007
3702 @@ -13,12 +13,14 @@
3703 extern void __init at91sam9260_initialize(unsigned long main_clock);
3704 extern void __init at91sam9261_initialize(unsigned long main_clock);
3705 extern void __init at91sam9263_initialize(unsigned long main_clock);
3706 +extern void __init at91sam9rl_initialize(unsigned long main_clock);
3707
3708 /* Interrupts */
3709 extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
3710 extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
3711 extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
3712 extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
3713 +extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
3714 extern void __init at91_aic_init(unsigned int priority[]);
3715
3716 /* Timer */
3717 @@ -34,6 +36,7 @@
3718 /* Power Management */
3719 extern void at91_irq_suspend(void);
3720 extern void at91_irq_resume(void);
3721 +extern int at91_suspend_entering_slow_clock(void);
3722
3723 /* GPIO */
3724 #define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
3725 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/ics1523.c linux-2.6-stable/arch/arm/mach-at91/ics1523.c
3726 --- linux-2.6.21/arch/arm/mach-at91/ics1523.c Thu Jan 1 02:00:00 1970
3727 +++ linux-2.6-stable/arch/arm/mach-at91/ics1523.c Tue May 8 12:13:30 2007
3728 @@ -0,0 +1,207 @@
3729 +/*
3730 + * arch/arm/mach-at91rm9200/ics1523.c
3731 + *
3732 + * Copyright (C) 2003 ATMEL Rousset
3733 + *
3734 + * This program is free software; you can redistribute it and/or modify
3735 + * it under the terms of the GNU General Public License as published by
3736 + * the Free Software Foundation; either version 2 of the License, or
3737 + * (at your option) any later version.
3738 + *
3739 + * This program is distributed in the hope that it will be useful,
3740 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3741 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3742 + * GNU General Public License for more details.
3743 + *
3744 + * You should have received a copy of the GNU General Public License
3745 + * along with this program; if not, write to the Free Software
3746 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3747 + */
3748 +
3749 +#include <asm/hardware.h>
3750 +#include <asm/io.h>
3751 +
3752 +#include <linux/clk.h>
3753 +#include <linux/delay.h>
3754 +#include <linux/err.h>
3755 +#include <linux/init.h>
3756 +
3757 +#include <asm/arch/ics1523.h>
3758 +#include <asm/arch/at91_twi.h>
3759 +#include <asm/arch/gpio.h>
3760 +
3761 +/* TWI Errors */
3762 +#define AT91_TWI_ERROR (AT91_TWI_NACK | AT91_TWI_UNRE | AT91_TWI_OVRE)
3763 +
3764 +
3765 +static void __iomem *twi_base;
3766 +
3767 +#define at91_twi_read(reg) __raw_readl(twi_base + (reg))
3768 +#define at91_twi_write(reg, val) __raw_writel((val), twi_base + (reg))
3769 +
3770 +
3771 +/* -----------------------------------------------------------------------------
3772 + * Initialization of TWI CLOCK
3773 + * ----------------------------------------------------------------------------- */
3774 +
3775 +static void at91_ics1523_SetTwiClock(unsigned int mck_khz)
3776 +{
3777 + int sclock;
3778 +
3779 + /* Here, CKDIV = 1 and CHDIV = CLDIV ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
3780 + sclock = (10*mck_khz / ICS_TRANSFER_RATE);
3781 + if (sclock % 10 >= 5)
3782 + sclock = (sclock /10) - 5;
3783 + else
3784 + sclock = (sclock /10)- 6;
3785 + sclock = (sclock + (4 - sclock %4)) >> 2; /* div 4 */
3786 +
3787 + at91_twi_write(AT91_TWI_CWGR, 0x00010000 | sclock | (sclock << 8));
3788 +}
3789 +
3790 +/* -----------------------------------------------------------------------------
3791 + * Read a byte with TWI Interface from the Clock Generator ICS1523
3792 + * ----------------------------------------------------------------------------- */
3793 +
3794 +static int at91_ics1523_ReadByte(unsigned char reg_address, unsigned char *data_in)
3795 +{
3796 + int Status, nb_trial;
3797 +
3798 + at91_twi_write(AT91_TWI_MMR, AT91_TWI_MREAD | AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR));
3799 + at91_twi_write(AT91_TWI_IADR, reg_address);
3800 + at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
3801 +
3802 + /* Program temporizing period (300us) */
3803 + udelay(300);
3804 +
3805 + /* Wait TXcomplete ... */
3806 + nb_trial = 0;
3807 + Status = at91_twi_read(AT91_TWI_SR);
3808 + while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
3809 + nb_trial++;
3810 + Status = at91_twi_read(AT91_TWI_SR);
3811 + }
3812 +
3813 + if (Status & AT91_TWI_TXCOMP) {
3814 + *data_in = (unsigned char) at91_twi_read(AT91_TWI_RHR);
3815 + return ICS1523_ACCESS_OK;
3816 + }
3817 + else
3818 + return ICS1523_ACCESS_ERROR;
3819 +}
3820 +
3821 +/* -----------------------------------------------------------------------------
3822 + * Write a byte with TWI Interface to the Clock Generator ICS1523
3823 + * ----------------------------------------------------------------------------- */
3824 +
3825 +static int at91_ics1523_WriteByte(unsigned char reg_address, unsigned char data_out)
3826 +{
3827 + int Status, nb_trial;
3828 +
3829 + at91_twi_write(AT91_TWI_MMR, AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR));
3830 + at91_twi_write(AT91_TWI_IADR, reg_address);
3831 + at91_twi_write(AT91_TWI_THR, data_out);
3832 + at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
3833 +
3834 + /* Program temporizing period (300us) */
3835 + udelay(300);
3836 +
3837 + nb_trial = 0;
3838 + Status = at91_twi_read(AT91_TWI_SR);
3839 + while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
3840 + nb_trial++;
3841 + if (Status & AT91_TWI_ERROR) {
3842 + /* If Underrun OR NACK - Start again */
3843 + at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
3844 +
3845 + /* Program temporizing period (300us) */
3846 + udelay(300);
3847 + }
3848 + Status = at91_twi_read(AT91_TWI_SR);
3849 + };
3850 +
3851 + if (Status & AT91_TWI_TXCOMP)
3852 + return ICS1523_ACCESS_OK;
3853 + else
3854 + return ICS1523_ACCESS_ERROR;
3855 +}
3856 +
3857 +/* -----------------------------------------------------------------------------
3858 + * Initialization of the Clock Generator ICS1523
3859 + * ----------------------------------------------------------------------------- */
3860 +
3861 +int at91_ics1523_init(void)
3862 +{
3863 + int nb_trial;
3864 + int ack = ICS1523_ACCESS_OK;
3865 + unsigned int status = 0xffffffff;
3866 + struct clk *twi_clk;
3867 +
3868 + /* Map in TWI peripheral */
3869 + twi_base = ioremap(AT91RM9200_BASE_TWI, SZ_16K);
3870 + if (!twi_base)
3871 + return -ENOMEM;
3872 +
3873 + /* pins used for TWI interface */
3874 + at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
3875 + at91_set_multi_drive(AT91_PIN_PA25, 1);
3876 + at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
3877 + at91_set_multi_drive(AT91_PIN_PA26, 1);
3878 +
3879 + /* Enable the TWI clock */
3880 + twi_clk = clk_get(NULL, "twi_clk");
3881 + if (IS_ERR(twi_clk))
3882 + return ICS1523_ACCESS_ERROR;
3883 + clk_enable(twi_clk);
3884 +
3885 + /* Disable interrupts */
3886 + at91_twi_write(AT91_TWI_IDR, -1);
3887 +
3888 + /* Reset peripheral */
3889 + at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST);
3890 +
3891 + /* Set Master mode */
3892 + at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN);
3893 +
3894 + /* Set TWI Clock Waveform Generator Register */
3895 + at91_ics1523_SetTwiClock(60000); /* MCK in KHz = 60000 KHz */
3896 +
3897 + /* ICS1523 Initialisation */
3898 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) 0);
3899 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OE, (unsigned char) (ICS_OEF | ICS_OET2 | ICS_OETCK));
3900 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OD, (unsigned char) (ICS_INSEL | 0x7F));
3901 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0);
3902 +
3903 + nb_trial = 0;
3904 + do {
3905 + nb_trial++;
3906 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) (ICS_ENDLS | ICS_ENPLS | ICS_PDEN /*| ICS_FUNCSEL*/));
3907 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_LCR, (unsigned char) (ICS_PSD | ICS_PFD));
3908 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD0, (unsigned char) 0x39) ; /* 0x7A */
3909 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD1, (unsigned char) 0x00);
3910 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_PLLR));
3911 +
3912 + /* Program 1ms temporizing period */
3913 + mdelay(1);
3914 +
3915 + at91_ics1523_ReadByte ((unsigned char) ICS_SR, (char *)&status);
3916 + } while (!((unsigned int) status & (unsigned int) ICS_PLLLOCK) && (nb_trial < 10));
3917 +
3918 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAC, (unsigned char) 0x03) ; /* 0x01 */
3919 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_DPAR));
3920 +
3921 + /* Program 1ms temporizing period */
3922 + mdelay(1);
3923 +
3924 + ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0x00);
3925 +
3926 + /* Program 1ms temporizing period */
3927 + mdelay(1);
3928 +
3929 + /* All done - cleanup */
3930 + iounmap(twi_base);
3931 + clk_disable(twi_clk);
3932 + clk_put(twi_clk);
3933 +
3934 + return ack;
3935 +}
3936 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/pm.c linux-2.6-stable/arch/arm/mach-at91/pm.c
3937 --- linux-2.6.21/arch/arm/mach-at91/pm.c Thu Apr 26 05:08:32 2007
3938 +++ linux-2.6-stable/arch/arm/mach-at91/pm.c Tue May 8 12:13:31 2007
3939 @@ -63,6 +63,7 @@
3940 * Verify that all the clocks are correct before entering
3941 * slow-clock mode.
3942 */
3943 +#warning "SAM9260 only has 3 programmable clocks."
3944 static int at91_pm_verify_clocks(void)
3945 {
3946 unsigned long scsr;
3947 @@ -104,20 +105,15 @@
3948 }
3949
3950 /*
3951 - * Call this from platform driver suspend() to see how deeply to suspend.
3952 + * This is called from clk_must_disable(), to see how deeply to suspend.
3953 * For example, some controllers (like OHCI) need one of the PLL clocks
3954 * in order to act as a wakeup source, and those are not available when
3955 * going into slow clock mode.
3956 - *
3957 - * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
3958 - * the very same problem (but not using at91 main_clk), and it'd be better
3959 - * to add one generic API rather than lots of platform-specific ones.
3960 */
3961 int at91_suspend_entering_slow_clock(void)
3962 {
3963 return (target_state == PM_SUSPEND_MEM);
3964 }
3965 -EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
3966
3967
3968 static void (*slow_clock)(void);
3969 @@ -207,16 +203,23 @@
3970 .enter = at91_pm_enter,
3971 };
3972
3973 +#ifdef CONFIG_AT91_SLOW_CLOCK
3974 +extern void at91rm9200_slow_clock(void);
3975 +extern u32 at91rm9200_slow_clock_sz;
3976 +#endif
3977 +
3978 static int __init at91_pm_init(void)
3979 {
3980 - printk("AT91: Power Management\n");
3981 -
3982 -#ifdef CONFIG_AT91_PM_SLOW_CLOCK
3983 - /* REVISIT allocations of SRAM should be dynamically managed.
3984 +#ifdef CONFIG_AT91_SLOW_CLOCK
3985 + /*
3986 + * REVISIT allocations of SRAM should be dynamically managed.
3987 * FIQ handlers and other components will want SRAM/TCM too...
3988 */
3989 - slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
3990 + slow_clock = (void *) (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE + (3 * SZ_4K));
3991 memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
3992 + printk("AT91: Power Management (with slow clock mode)\n");
3993 +#else
3994 + printk("AT91: Power Management\n");
3995 #endif
3996
3997 /* Disable SDRAM low-power mode. Cannot be used with self-refresh. */
3998 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/pm_slowclock.S linux-2.6-stable/arch/arm/mach-at91/pm_slowclock.S
3999 --- linux-2.6.21/arch/arm/mach-at91/pm_slowclock.S Thu Jan 1 02:00:00 1970
4000 +++ linux-2.6-stable/arch/arm/mach-at91/pm_slowclock.S Tue May 8 12:13:31 2007
4001 @@ -0,0 +1,172 @@
4002 +/*
4003 + * arch/arm/mach-at91/pm_slow_clock.S
4004 + *
4005 + * Copyright (C) 2006 Savin Zlobec
4006 + *
4007 + * This program is free software; you can redistribute it and/or modify
4008 + * it under the terms of the GNU General Public License version 2 as
4009 + * published by the Free Software Foundation.
4010 + *
4011 + */
4012 +
4013 +#include <linux/linkage.h>
4014 +#include <asm/hardware.h>
4015 +#include <asm/arch/at91_pmc.h>
4016 +#include <asm/arch/at91rm9200_mc.h>
4017 +
4018 +#define MCKRDY_TIMEOUT 1000
4019 +#define MOSCRDY_TIMEOUT 1000
4020 +#define PLLALOCK_TIMEOUT 1000
4021 +
4022 + .macro wait_mckrdy
4023 + mov r2, #MCKRDY_TIMEOUT
4024 +1: sub r2, r2, #1
4025 + cmp r2, #0
4026 + beq 2f
4027 + ldr r3, [r1, #AT91_PMC_SR]
4028 + tst r3, #AT91_PMC_MCKRDY
4029 + beq 1b
4030 +2:
4031 + .endm
4032 +
4033 + .macro wait_moscrdy
4034 + mov r2, #MOSCRDY_TIMEOUT
4035 +1: sub r2, r2, #1
4036 + cmp r2, #0
4037 + beq 2f
4038 + ldr r3, [r1, #AT91_PMC_SR]
4039 + tst r3, #AT91_PMC_MOSCS
4040 + beq 1b
4041 +2:
4042 + .endm
4043 +
4044 + .macro wait_pllalock
4045 + mov r2, #PLLALOCK_TIMEOUT
4046 +1: sub r2, r2, #1
4047 + cmp r2, #0
4048 + beq 2f
4049 + ldr r3, [r1, #AT91_PMC_SR]
4050 + tst r3, #AT91_PMC_LOCKA
4051 + beq 1b
4052 +2:
4053 + .endm
4054 +
4055 + .macro wait_plladis
4056 + mov r2, #PLLALOCK_TIMEOUT
4057 +1: sub r2, r2, #1
4058 + cmp r2, #0
4059 + beq 2f
4060 + ldr r3, [r1, #AT91_PMC_SR]
4061 + tst r3, #AT91_PMC_LOCKA
4062 + bne 1b
4063 +2:
4064 + .endm
4065 +
4066 + .text
4067 +
4068 +ENTRY(at91rm9200_slow_clock)
4069 +
4070 + ldr r1, .at91_va_base_sys
4071 +
4072 + /* Put SDRAM in self refresh mode */
4073 +
4074 + b 1f
4075 + .align 5
4076 +1: mcr p15, 0, r0, c7, c10, 4
4077 + mov r2, #1
4078 + str r2, [r1, #AT91_SDRAMC_SRR]
4079 +
4080 + /* Save Master clock setting */
4081 +
4082 + ldr r2, [r1, #AT91_PMC_MCKR]
4083 + str r2, .saved_mckr
4084 +
4085 + /*
4086 + * Set the Master clock source to slow clock
4087 + *
4088 + * First set the CSS field, wait for MCKRDY
4089 + * and than set the PRES and MDIV fields.
4090 + *
4091 + * See eratta #2[78] for details.
4092 + */
4093 +
4094 + bic r2, r2, #3
4095 + str r2, [r1, #AT91_PMC_MCKR]
4096 +
4097 + wait_mckrdy
4098 +
4099 + mov r2, #0
4100 + str r2, [r1, #AT91_PMC_MCKR]
4101 +
4102 + /* Save PLLA setting and disable it */
4103 +
4104 + ldr r2, [r1, #AT91_CKGR_PLLAR]
4105 + str r2, .saved_pllar
4106 +
4107 + mov r2, #0
4108 + str r2, [r1, #AT91_CKGR_PLLAR]
4109 +
4110 + wait_plladis
4111 +
4112 + /* Turn off the main oscillator */
4113 +
4114 + ldr r2, [r1, #AT91_CKGR_MOR]
4115 + bic r2, r2, #AT91_PMC_MOSCEN
4116 + str r2, [r1, #AT91_CKGR_MOR]
4117 +
4118 + /* Wait for interrupt */
4119 +
4120 + mcr p15, 0, r0, c7, c0, 4
4121 +
4122 + /* Turn on the main oscillator */
4123 +
4124 + ldr r2, [r1, #AT91_CKGR_MOR]
4125 + orr r2, r2, #AT91_PMC_MOSCEN
4126 + str r2, [r1, #AT91_CKGR_MOR]
4127 +
4128 + wait_moscrdy
4129 +
4130 + /* Restore PLLA setting */
4131 +
4132 + ldr r2, .saved_pllar
4133 + str r2, [r1, #AT91_CKGR_PLLAR]
4134 +
4135 + wait_pllalock
4136 +
4137 + /*
4138 + * Restore master clock setting
4139 + *
4140 + * First set PRES if it was not 0,
4141 + * than set CSS and MDIV fields.
4142 + * After every change wait for
4143 + * MCKRDY.
4144 + *
4145 + * See eratta #2[78] for details.
4146 + */
4147 +
4148 + ldr r2, .saved_mckr
4149 + tst r2, #0x1C
4150 + beq 2f
4151 + and r2, r2, #0x1C
4152 + str r2, [r1, #AT91_PMC_MCKR]
4153 +
4154 + wait_mckrdy
4155 +
4156 +2: ldr r2, .saved_mckr
4157 + str r2, [r1, #AT91_PMC_MCKR]
4158 +
4159 + wait_mckrdy
4160 +
4161 + mov pc, lr
4162 +
4163 +.saved_mckr:
4164 + .word 0
4165 +
4166 +.saved_pllar:
4167 + .word 0
4168 +
4169 +.at91_va_base_sys:
4170 + .word AT91_VA_BASE_SYS
4171 +
4172 +ENTRY(at91rm9200_slow_clock_sz)
4173 + .word .-at91rm9200_slow_clock
4174 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/tclib.c linux-2.6-stable/arch/arm/mach-at91/tclib.c
4175 --- linux-2.6.21/arch/arm/mach-at91/tclib.c Thu Jan 1 02:00:00 1970
4176 +++ linux-2.6-stable/arch/arm/mach-at91/tclib.c Tue May 8 12:13:31 2007
4177 @@ -0,0 +1,17 @@
4178 +#include <linux/clk.h>
4179 +#include <linux/kernel.h>
4180 +#include <linux/module.h>
4181 +
4182 +#include "tclib.h"
4183 +
4184 +static struct atmel_tcblock *blocks;
4185 +static int nblocks;
4186 +
4187 +/*
4188 + * Called from the processor-specific init to register the TC Blocks.
4189 + */
4190 +void __init atmel_tc_init(struct atmel_tcblock *tcblocks, int n)
4191 +{
4192 + blocks = tcblocks;
4193 + nblocks = n;
4194 +}
4195 diff -urN -x CVS linux-2.6.21/arch/arm/mach-at91/tclib.h linux-2.6-stable/arch/arm/mach-at91/tclib.h
4196 --- linux-2.6.21/arch/arm/mach-at91/tclib.h Thu Jan 1 02:00:00 1970
4197 +++ linux-2.6-stable/arch/arm/mach-at91/tclib.h Tue May 8 12:13:31 2007
4198 @@ -0,0 +1,11 @@
4199 +
4200 +#define TC_PER_TCB 3
4201 +
4202 +struct atmel_tcblock {
4203 + u32 physaddr;
4204 + void __iomem *ioaddr;
4205 + struct clk *clk[TC_PER_TCB];
4206 + int irq[TC_PER_TCB];
4207 +};
4208 +
4209 +extern void __init atmel_tc_init(struct atmel_tcblock *tcblocks, int n);
4210 diff -urN -x CVS linux-2.6.21/arch/arm/mm/Kconfig linux-2.6-stable/arch/arm/mm/Kconfig
4211 --- linux-2.6.21/arch/arm/mm/Kconfig Thu Apr 26 05:08:32 2007
4212 +++ linux-2.6-stable/arch/arm/mm/Kconfig Wed May 9 10:20:54 2007
4213 @@ -171,8 +171,8 @@
4214 # ARM926T
4215 config CPU_ARM926T
4216 bool "Support ARM926T processor"
4217 - depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX
4218 - default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX
4219 + depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX
4220 + default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX
4221 select CPU_32v5
4222 select CPU_ABRT_EV5TJ
4223 select CPU_CACHE_VIVT
4224 diff -urN -x CVS linux-2.6.21/arch/arm/tools/mach-types linux-2.6-stable/arch/arm/tools/mach-types
4225 --- linux-2.6.21/arch/arm/tools/mach-types Thu Apr 26 05:08:32 2007
4226 +++ linux-2.6-stable/arch/arm/tools/mach-types Tue May 8 12:13:31 2007
4227 @@ -1335,3 +1335,32 @@
4228 comtech_router MACH_COMTECH_ROUTER COMTECH_ROUTER 1327
4229 sbc2410x MACH_SBC2410X SBC2410X 1328
4230 at4x0bd MACH_AT4X0BD AT4X0BD 1329
4231 +cbifr MACH_CBIFR CBIFR 1330
4232 +arcom_quantum MACH_ARCOM_QUANTUM ARCOM_QUANTUM 1331
4233 +matrix520 MACH_MATRIX520 MATRIX520 1332
4234 +matrix510 MACH_MATRIX510 MATRIX510 1333
4235 +matrix500 MACH_MATRIX500 MATRIX500 1334
4236 +m501 MACH_M501 M501 1335
4237 +aaeon1270 MACH_AAEON1270 AAEON1270 1336
4238 +matrix500ev MACH_MATRIX500EV MATRIX500EV 1337
4239 +pac500 MACH_PAC500 PAC500 1338
4240 +pnx8181 MACH_PNX8181 PNX8181 1339
4241 +colibri320 MACH_COLIBRI320 COLIBRI320 1340
4242 +aztoolbb MACH_AZTOOLBB AZTOOLBB 1341
4243 +aztoolg2 MACH_AZTOOLG2 AZTOOLG2 1342
4244 +dvlhost MACH_DVLHOST DVLHOST 1343
4245 +zir9200 MACH_ZIR9200 ZIR9200 1344
4246 +zir9260 MACH_ZIR9260 ZIR9260 1345
4247 +cocopah MACH_COCOPAH COCOPAH 1346
4248 +nds MACH_NDS NDS 1347
4249 +rosencrantz MACH_ROSENCRANTZ ROSENCRANTZ 1348
4250 +fttx_odsc MACH_FTTX_ODSC FTTX_ODSC 1349
4251 +classe_r6904 MACH_CLASSE_R6904 CLASSE_R6904 1350
4252 +cam60 MACH_CAM60 CAM60 1351
4253 +mxc30031ads MACH_MXC30031ADS MXC30031ADS 1352
4254 +datacall MACH_DATACALL DATACALL 1353
4255 +at91eb01 MACH_AT91EB01 AT91EB01 1354
4256 +rty MACH_RTY RTY 1355
4257 +dwl2100 MACH_DWL2100 DWL2100 1356
4258 +vinsi MACH_VINSI VINSI 1357
4259 +db88f5281 MACH_DB88F5281 DB88F5281 1358
4260 diff -urN -x CVS linux-2.6.21/drivers/char/Kconfig linux-2.6-stable/drivers/char/Kconfig
4261 --- linux-2.6.21/drivers/char/Kconfig Thu Apr 26 05:08:32 2007
4262 +++ linux-2.6-stable/drivers/char/Kconfig Tue May 8 14:31:24 2007
4263 @@ -1071,5 +1071,21 @@
4264 /sys/devices/platform/telco_clock, with a number of files for
4265 controlling the behavior of this hardware.
4266
4267 +config AT91_SPI
4268 + bool "SPI driver (legacy) for AT91RM9200 processors"
4269 + depends on ARCH_AT91RM9200
4270 + default y
4271 + help
4272 + The SPI driver gives access to this serial bus on the AT91RM9200
4273 + processor.
4274 +
4275 +config AT91_SPIDEV
4276 + bool "SPI device interface (legacy) for AT91RM9200 processors"
4277 + depends on ARCH_AT91RM9200 && AT91_SPI
4278 + default n
4279 + help
4280 + The SPI driver gives user mode access to this serial
4281 + bus on the AT91RM9200 processor.
4282 +
4283 endmenu
4284
4285 diff -urN -x CVS linux-2.6.21/drivers/char/Makefile linux-2.6-stable/drivers/char/Makefile
4286 --- linux-2.6.21/drivers/char/Makefile Thu Apr 26 05:08:32 2007
4287 +++ linux-2.6-stable/drivers/char/Makefile Tue May 8 14:31:24 2007
4288 @@ -93,6 +93,8 @@
4289 obj-$(CONFIG_GPIO_VR41XX) += vr41xx_giu.o
4290 obj-$(CONFIG_TANBAC_TB0219) += tb0219.o
4291 obj-$(CONFIG_TELCLOCK) += tlclk.o
4292 +obj-$(CONFIG_AT91_SPI) += at91_spi.o
4293 +obj-$(CONFIG_AT91_SPIDEV) += at91_spidev.o
4294
4295 obj-$(CONFIG_WATCHDOG) += watchdog/
4296 obj-$(CONFIG_MWAVE) += mwave/
4297 diff -urN -x CVS linux-2.6.21/drivers/char/at91_spi.c linux-2.6-stable/drivers/char/at91_spi.c
4298 --- linux-2.6.21/drivers/char/at91_spi.c Thu Jan 1 02:00:00 1970
4299 +++ linux-2.6-stable/drivers/char/at91_spi.c Tue May 8 14:31:24 2007
4300 @@ -0,0 +1,336 @@
4301 +/*
4302 + * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder)
4303 + *
4304 + * Copyright (C) SAN People (Pty) Ltd
4305 + *
4306 + * This program is free software; you can redistribute it and/or
4307 + * modify it under the terms of the GNU General Public License
4308 + * as published by the Free Software Foundation; either version
4309 + * 2 of the License, or (at your option) any later version.
4310 + */
4311 +
4312 +#include <linux/init.h>
4313 +#include <linux/dma-mapping.h>
4314 +#include <linux/module.h>
4315 +#include <linux/sched.h>
4316 +#include <linux/completion.h>
4317 +#include <linux/interrupt.h>
4318 +#include <linux/clk.h>
4319 +#include <linux/platform_device.h>
4320 +#include <linux/atmel_pdc.h>
4321 +#include <asm/io.h>
4322 +#include <asm/semaphore.h>
4323 +
4324 +#include <asm/arch/at91_spi.h>
4325 +#include <asm/arch/board.h>
4326 +#include <asm/arch/spi.h>
4327 +
4328 +#undef DEBUG_SPI
4329 +
4330 +static struct spi_local spi_dev[NR_SPI_DEVICES]; /* state of the SPI devices */
4331 +static int spi_enabled = 0;
4332 +static struct semaphore spi_lock; /* protect access to SPI bus */
4333 +static int current_device = -1; /* currently selected SPI device */
4334 +static struct clk *spi_clk; /* SPI clock */
4335 +static void __iomem *spi_base; /* SPI peripheral base-address */
4336 +
4337 +DECLARE_COMPLETION(transfer_complete);
4338 +
4339 +
4340 +#define at91_spi_read(reg) __raw_readl(spi_base + (reg))
4341 +#define at91_spi_write(reg, val) __raw_writel((val), spi_base + (reg))
4342 +
4343 +
4344 +/* ......................................................................... */
4345 +
4346 +/*
4347 + * Access and enable the SPI bus.
4348 + * This MUST be called before any transfers are performed.
4349 + */
4350 +void spi_access_bus(short device)
4351 +{
4352 + /* Ensure that requested device is valid */
4353 + if ((device < 0) || (device >= NR_SPI_DEVICES))
4354 + panic("at91_spi: spi_access_bus called with invalid device");
4355 +
4356 + if (spi_enabled == 0) {
4357 + clk_enable(spi_clk); /* Enable Peripheral clock */
4358 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */
4359 +#ifdef DEBUG_SPI
4360 + printk("SPI on\n");
4361 +#endif
4362 + }
4363 + spi_enabled++;
4364 +
4365 + /* Lock the SPI bus */
4366 + down(&spi_lock);
4367 + current_device = device;
4368 +
4369 + /* Configure SPI bus for device */
4370 + at91_spi_write(AT91_SPI_MR, AT91_SPI_MSTR | AT91_SPI_MODFDIS | (spi_dev[device].pcs << 16));
4371 +}
4372 +
4373 +/*
4374 + * Relinquish control of the SPI bus.
4375 + */
4376 +void spi_release_bus(short device)
4377 +{
4378 + if (device != current_device)
4379 + panic("at91_spi: spi_release called with invalid device");
4380 +
4381 + /* Release the SPI bus */
4382 + current_device = -1;
4383 + up(&spi_lock);
4384 +
4385 + spi_enabled--;
4386 + if (spi_enabled == 0) {
4387 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */
4388 + clk_disable(spi_clk); /* Disable Peripheral clock */
4389 +#ifdef DEBUG_SPI
4390 + printk("SPI off\n");
4391 +#endif
4392 + }
4393 +}
4394 +
4395 +/*
4396 + * Perform a data transfer over the SPI bus
4397 + */
4398 +int spi_transfer(struct spi_transfer_list* list)
4399 +{
4400 + struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
4401 + int tx_size;
4402 +
4403 + if (!list)
4404 + panic("at91_spi: spi_transfer called with NULL transfer list");
4405 + if (current_device == -1)
4406 + panic("at91_spi: spi_transfer called without acquiring bus");
4407 +
4408 +#ifdef DEBUG_SPI
4409 + printk("SPI transfer start [%i]\n", list->nr_transfers);
4410 +#endif
4411 +
4412 + /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
4413 + tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
4414 +
4415 + /* Store transfer list */
4416 + device->xfers = list;
4417 + list->curr = 0;
4418 +
4419 + /* Assume there must be at least one transfer */
4420 + device->tx = dma_map_single(NULL, list->tx[0], list->txlen[0], DMA_TO_DEVICE);
4421 + device->rx = dma_map_single(NULL, list->rx[0], list->rxlen[0], DMA_FROM_DEVICE);
4422 +
4423 + /* Program PDC registers */
4424 + at91_spi_write(ATMEL_PDC_TPR, device->tx);
4425 + at91_spi_write(ATMEL_PDC_RPR, device->rx);
4426 + at91_spi_write(ATMEL_PDC_TCR, list->txlen[0] / tx_size);
4427 + at91_spi_write(ATMEL_PDC_RCR, list->rxlen[0] / tx_size);
4428 +
4429 + /* Is there a second transfer? */
4430 + if (list->nr_transfers > 1) {
4431 + device->txnext = dma_map_single(NULL, list->tx[1], list->txlen[1], DMA_TO_DEVICE);
4432 + device->rxnext = dma_map_single(NULL, list->rx[1], list->rxlen[1], DMA_FROM_DEVICE);
4433 +
4434 + /* Program Next PDC registers */
4435 + at91_spi_write(ATMEL_PDC_TNPR, device->txnext);
4436 + at91_spi_write(ATMEL_PDC_RNPR, device->rxnext);
4437 + at91_spi_write(ATMEL_PDC_TNCR, list->txlen[1] / tx_size);
4438 + at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[1] / tx_size);
4439 + }
4440 + else {
4441 + device->txnext = 0;
4442 + device->rxnext = 0;
4443 + at91_spi_write(ATMEL_PDC_TNCR, 0);
4444 + at91_spi_write(ATMEL_PDC_RNCR, 0);
4445 + }
4446 +
4447 + // TODO: If we are doing consecutive transfers (at high speed, or
4448 + // small buffers), then it might be worth modifying the 'Delay between
4449 + // Consecutive Transfers' in the CSR registers.
4450 + // This is an issue if we cannot chain the next buffer fast enough
4451 + // in the interrupt handler.
4452 +
4453 + /* Enable transmitter and receiver */
4454 + at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN | ATMEL_PDC_TXTEN);
4455 +
4456 + at91_spi_write(AT91_SPI_IER, AT91_SPI_ENDRX); /* enable buffer complete interrupt */
4457 + wait_for_completion(&transfer_complete);
4458 +
4459 +#ifdef DEBUG_SPI
4460 + printk("SPI transfer end\n");
4461 +#endif
4462 +
4463 + return 0;
4464 +}
4465 +
4466 +/* ......................................................................... */
4467 +
4468 +/*
4469 + * Handle interrupts from the SPI controller.
4470 + */
4471 +static irqreturn_t at91spi_interrupt(int irq, void *dev_id)
4472 +{
4473 + unsigned int status;
4474 + struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
4475 + struct spi_transfer_list *list = device->xfers;
4476 +
4477 +#ifdef DEBUG_SPI
4478 + printk("SPI interrupt %i\n", current_device);
4479 +#endif
4480 +
4481 + if (!list)
4482 + panic("at91_spi: spi_interrupt with a NULL transfer list");
4483 +
4484 + status = at91_spi_read(AT91_SPI_SR) & at91_spi_read(AT91_SPI_IMR); /* read status */
4485 +
4486 + dma_unmap_single(NULL, device->tx, list->txlen[list->curr], DMA_TO_DEVICE);
4487 + dma_unmap_single(NULL, device->rx, list->rxlen[list->curr], DMA_FROM_DEVICE);
4488 +
4489 + device->tx = device->txnext; /* move next transfer to current transfer */
4490 + device->rx = device->rxnext;
4491 +
4492 + list->curr = list->curr + 1;
4493 + if (list->curr == list->nr_transfers) { /* all transfers complete */
4494 + at91_spi_write(AT91_SPI_IDR, AT91_SPI_ENDRX); /* disable interrupt */
4495 +
4496 + /* Disable transmitter and receiver */
4497 + at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
4498 +
4499 + device->xfers = NULL;
4500 + complete(&transfer_complete);
4501 + }
4502 + else if (list->curr+1 == list->nr_transfers) { /* no more next transfers */
4503 + device->txnext = 0;
4504 + device->rxnext = 0;
4505 + at91_spi_write(ATMEL_PDC_TNCR, 0);
4506 + at91_spi_write(ATMEL_PDC_RNCR, 0);
4507 + }
4508 + else {
4509 + int i = (list->curr)+1;
4510 +
4511 + /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
4512 + int tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
4513 +
4514 + device->txnext = dma_map_single(NULL, list->tx[i], list->txlen[i], DMA_TO_DEVICE);
4515 + device->rxnext = dma_map_single(NULL, list->rx[i], list->rxlen[i], DMA_FROM_DEVICE);
4516 + at91_spi_write(ATMEL_PDC_TNPR, device->txnext);
4517 + at91_spi_write(ATMEL_PDC_RNPR, device->rxnext);
4518 + at91_spi_write(ATMEL_PDC_TNCR, list->txlen[i] / tx_size);
4519 + at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[i] / tx_size);
4520 + }
4521 + return IRQ_HANDLED;
4522 +}
4523 +
4524 +/* ......................................................................... */
4525 +
4526 +/*
4527 + * Initialize the SPI controller
4528 + */
4529 +static int __init at91spi_probe(struct platform_device *pdev)
4530 +{
4531 + int i;
4532 + unsigned long scbr;
4533 + struct resource *res;
4534 +
4535 + init_MUTEX(&spi_lock);
4536 +
4537 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4538 + if (!res)
4539 + return -ENXIO;
4540 +
4541 + if (!request_mem_region(res->start, res->end - res->start + 1, "at91_spi"))
4542 + return -EBUSY;
4543 +
4544 + spi_base = ioremap(res->start, res->end - res->start + 1);
4545 + if (!spi_base) {
4546 + release_mem_region(res->start, res->end - res->start + 1);
4547 + return -ENOMEM;
4548 + }
4549 +
4550 + spi_clk = clk_get(NULL, "spi_clk");
4551 + if (IS_ERR(spi_clk)) {
4552 + printk(KERN_ERR "at91_spi: no clock defined\n");
4553 + iounmap(spi_base);
4554 + release_mem_region(res->start, res->end - res->start + 1);
4555 + return -ENODEV;
4556 + }
4557 +
4558 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SWRST); /* software reset of SPI controller */
4559 +
4560 + /*
4561 + * Calculate the correct SPI baud-rate divisor.
4562 + */
4563 + scbr = clk_get_rate(spi_clk) / (2 * DEFAULT_SPI_CLK);
4564 + scbr = scbr + 1; /* round up */
4565 +
4566 + printk(KERN_INFO "at91_spi: Baud rate set to %ld\n", clk_get_rate(spi_clk) / (2 * scbr));
4567 +
4568 + /* Set Chip Select registers to good defaults */
4569 + for (i = 0; i < 4; i++) {
4570 + at91_spi_write(AT91_SPI_CSR(i), AT91_SPI_CPOL | AT91_SPI_BITS_8 | (16 << 16) | (scbr << 8));
4571 + }
4572 +
4573 + at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
4574 +
4575 + memset(&spi_dev, 0, sizeof(spi_dev));
4576 + spi_dev[0].pcs = 0xE;
4577 + spi_dev[1].pcs = 0xD;
4578 + spi_dev[2].pcs = 0xB;
4579 + spi_dev[3].pcs = 0x7;
4580 +
4581 + if (request_irq(AT91RM9200_ID_SPI, at91spi_interrupt, 0, "spi", NULL)) {
4582 + clk_put(spi_clk);
4583 + iounmap(spi_base);
4584 + release_mem_region(res->start, res->end - res->start + 1);
4585 + return -EBUSY;
4586 + }
4587 +
4588 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN); /* Enable SPI */
4589 +
4590 + return 0;
4591 +}
4592 +
4593 +static int __devexit at91spi_remove(struct platform_device *pdev)
4594 +{
4595 + struct resource *res;
4596 +
4597 + at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS); /* Disable SPI */
4598 + clk_put(spi_clk);
4599 +
4600 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4601 + iounmap(spi_base);
4602 + release_mem_region(res->start, res->end - res->start + 1);
4603 +
4604 + free_irq(AT91RM9200_ID_SPI, 0);
4605 + return 0;
4606 +}
4607 +
4608 +static struct platform_driver at91spi_driver = {
4609 + .probe = at91spi_probe,
4610 + .remove = __devexit_p(at91spi_remove),
4611 + .driver = {
4612 + .name = "at91_spi",
4613 + .owner = THIS_MODULE,
4614 + },
4615 +};
4616 +
4617 +static int __init at91spi_init(void)
4618 +{
4619 + return platform_driver_register(&at91spi_driver);
4620 +}
4621 +
4622 +static void __exit at91spi_exit(void)
4623 +{
4624 + platform_driver_unregister(&at91spi_driver);
4625 +}
4626 +
4627 +EXPORT_SYMBOL(spi_access_bus);
4628 +EXPORT_SYMBOL(spi_release_bus);
4629 +EXPORT_SYMBOL(spi_transfer);
4630 +
4631 +module_init(at91spi_init);
4632 +module_exit(at91spi_exit);
4633 +
4634 +MODULE_LICENSE("GPL")
4635 +MODULE_AUTHOR("Andrew Victor")
4636 +MODULE_DESCRIPTION("SPI driver for Atmel AT91RM9200")
4637 diff -urN -x CVS linux-2.6.21/drivers/char/at91_spidev.c linux-2.6-stable/drivers/char/at91_spidev.c
4638 --- linux-2.6.21/drivers/char/at91_spidev.c Thu Jan 1 02:00:00 1970
4639 +++ linux-2.6-stable/drivers/char/at91_spidev.c Tue May 8 14:31:24 2007
4640 @@ -0,0 +1,236 @@
4641 +/*
4642 + * User-space interface to the SPI bus on Atmel AT91RM9200
4643 + *
4644 + * Copyright (C) 2003 SAN People (Pty) Ltd
4645 + *
4646 + * Based on SPI driver by Rick Bronson
4647 + *
4648 + * This program is free software; you can redistribute it and/or
4649 + * modify it under the terms of the GNU General Public License
4650 + * as published by the Free Software Foundation; either version
4651 + * 2 of the License, or (at your option) any later version.
4652 + */
4653 +
4654 +#include <linux/module.h>
4655 +#include <linux/init.h>
4656 +#include <linux/slab.h>
4657 +#include <linux/highmem.h>
4658 +#include <linux/pagemap.h>
4659 +#include <asm/arch/spi.h>
4660 +
4661 +#ifdef CONFIG_DEVFS_FS
4662 +#include <linux/devfs_fs_kernel.h>
4663 +#endif
4664 +
4665 +
4666 +#undef DEBUG_SPIDEV
4667 +
4668 +/* ......................................................................... */
4669 +
4670 +/*
4671 + * Read or Write to SPI bus.
4672 + */
4673 +static ssize_t spidev_rd_wr(struct file *file, char *buf, size_t count, loff_t *offset)
4674 +{
4675 + unsigned int spi_device = (unsigned int) file->private_data;
4676 +
4677 + struct mm_struct * mm;
4678 + struct page ** maplist;
4679 + struct spi_transfer_list* list;
4680 + int pgcount;
4681 +
4682 + unsigned int ofs, pagelen;
4683 + int res, i, err;
4684 +
4685 + if (!count) {
4686 + return 0;
4687 + }
4688 +
4689 + list = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
4690 + if (!list) {
4691 + return -ENOMEM;
4692 + }
4693 +
4694 + mm = current->mm;
4695 +
4696 + pgcount = ((unsigned long)buf+count+PAGE_SIZE-1)/PAGE_SIZE - (unsigned long)buf/PAGE_SIZE;
4697 +
4698 + if (pgcount >= MAX_SPI_TRANSFERS) {
4699 + kfree(list);
4700 + return -EFBIG;
4701 + }
4702 +
4703 + maplist = kmalloc (pgcount * sizeof (struct page *), GFP_KERNEL);
4704 +
4705 + if (!maplist) {
4706 + kfree(list);
4707 + return -ENOMEM;
4708 + }
4709 + flush_cache_all();
4710 + down_read(&mm->mmap_sem);
4711 + err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL);
4712 + up_read(&mm->mmap_sem);
4713 +
4714 + if (err < 0) {
4715 + kfree(list);
4716 + kfree(maplist);
4717 + return err;
4718 + }
4719 + pgcount = err;
4720 +
4721 +#ifdef DEBUG_SPIDEV
4722 + printk("spidev_rd_rw: %i %i\n", count, pgcount);
4723 +#endif
4724 +
4725 + /* Set default return value = transfer length */
4726 + res = count;
4727 +
4728 + /*
4729 + * At this point, the virtual area buf[0] .. buf[count-1] will have
4730 + * corresponding pages mapped in the physical memory and locked until
4731 + * we unmap the kiobuf. The pages cannot be swapped out or moved
4732 + * around.
4733 + */
4734 + ofs = (unsigned long) buf & (PAGE_SIZE -1);
4735 + pagelen = PAGE_SIZE - ofs;
4736 + if (count < pagelen)
4737 + pagelen = count;
4738 +
4739 + for (i = 0; i < pgcount; i++) {
4740 + flush_dcache_page(maplist[i]);
4741 +
4742 + list->tx[i] = list->rx[i] = page_address(maplist[i]) + ofs;
4743 + list->txlen[i] = list->rxlen[i] = pagelen;
4744 +
4745 +#ifdef DEBUG_SPIDEV
4746 + printk(" %i: %x (%i)\n", i, list->tx[i], list->txlen[i]);
4747 +#endif
4748 +
4749 + ofs = 0; /* all subsequent transfers start at beginning of a page */
4750 + count = count - pagelen;
4751 + pagelen = (count < PAGE_SIZE) ? count : PAGE_SIZE;
4752 + }
4753 + list->nr_transfers = pgcount;
4754 +
4755 + /* Perform transfer on SPI bus */
4756 + spi_access_bus(spi_device);
4757 + spi_transfer(list);
4758 + spi_release_bus(spi_device);
4759 +
4760 + while (pgcount--) {
4761 + page_cache_release (maplist[pgcount]);
4762 + }
4763 + flush_cache_all();
4764 +
4765 + kfree(maplist);
4766 + kfree(list);
4767 +
4768 + return res;
4769 +}
4770 +
4771 +static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
4772 +{
4773 + int spi_device = MINOR(inode->i_rdev);
4774 +
4775 + if (spi_device >= NR_SPI_DEVICES)
4776 + return -ENODEV;
4777 +
4778 + // TODO: This interface can be used to configure the SPI bus.
4779 + // Configurable options could include: Speed, Clock Polarity, Clock Phase
4780 +
4781 + switch(cmd) {
4782 + default:
4783 + return -ENOIOCTLCMD;
4784 + }
4785 +}
4786 +
4787 +/*
4788 + * Open the SPI device
4789 + */
4790 +static int spidev_open(struct inode *inode, struct file *file)
4791 +{
4792 + unsigned int spi_device = MINOR(inode->i_rdev);
4793 +
4794 + if (spi_device >= NR_SPI_DEVICES)
4795 + return -ENODEV;
4796 +
4797 + /*
4798 + * 'private_data' is actually a pointer, but we overload it with the
4799 + * value we want to store.
4800 + */
4801 + file->private_data = (void *)spi_device;
4802 +
4803 + return 0;
4804 +}
4805 +
4806 +/*
4807 + * Close the SPI device
4808 + */
4809 +static int spidev_close(struct inode *inode, struct file *file)
4810 +{
4811 + return 0;
4812 +}
4813 +
4814 +/* ......................................................................... */
4815 +
4816 +static struct file_operations spidev_fops = {
4817 + .owner = THIS_MODULE,
4818 + .llseek = no_llseek,
4819 + .read = spidev_rd_wr,
4820 + .write = (int (*) (struct file *file, const char *buf, size_t count, loff_t *offset))spidev_rd_wr,
4821 + .ioctl = spidev_ioctl,
4822 + .open = spidev_open,
4823 + .release = spidev_close,
4824 +};
4825 +
4826 +/*
4827 + * Install the SPI /dev interface driver
4828 + */
4829 +static int __init at91_spidev_init(void)
4830 +{
4831 +#ifdef CONFIG_DEVFS_FS
4832 + int i;
4833 +#endif
4834 +
4835 + if (register_chrdev(SPI_MAJOR, "spi", &spidev_fops)) {
4836 + printk(KERN_ERR "at91_spidev: Unable to get major %d for SPI bus\n", SPI_MAJOR);
4837 + return -EIO;
4838 + }
4839 +
4840 +#ifdef CONFIG_DEVFS_FS
4841 + devfs_mk_dir("spi");
4842 + for (i = 0; i < NR_SPI_DEVICES; i++) {
4843 + devfs_mk_cdev(MKDEV(SPI_MAJOR, i), S_IFCHR | S_IRUSR | S_IWUSR, "spi/%d",i);
4844 + }
4845 +#endif
4846 + printk(KERN_INFO "AT91 SPI driver loaded\n");
4847 +
4848 + return 0;
4849 +}
4850 +
4851 +/*
4852 + * Remove the SPI /dev interface driver
4853 + */
4854 +static void __exit at91_spidev_exit(void)
4855 +{
4856 +#ifdef CONFIG_DEVFS_FS
4857 + int i;
4858 + for (i = 0; i < NR_SPI_DEVICES; i++) {
4859 + devfs_remove("spi/%d", i);
4860 + }
4861 +
4862 + devfs_remove("spi");
4863 +#endif
4864 +
4865 + if (unregister_chrdev(SPI_MAJOR, "spi")) {
4866 + printk(KERN_ERR "at91_spidev: Unable to release major %d for SPI bus\n", SPI_MAJOR);
4867 + return;
4868 + }
4869 +}
4870 +
4871 +module_init(at91_spidev_init);
4872 +module_exit(at91_spidev_exit);
4873 +
4874 +MODULE_LICENSE("GPL")
4875 +MODULE_AUTHOR("Andrew Victor")
4876 +MODULE_DESCRIPTION("SPI /dev interface for Atmel AT91RM9200")
4877 diff -urN -x CVS linux-2.6.21/drivers/i2c/busses/Kconfig linux-2.6-stable/drivers/i2c/busses/Kconfig
4878 --- linux-2.6.21/drivers/i2c/busses/Kconfig Thu Apr 26 05:08:32 2007
4879 +++ linux-2.6-stable/drivers/i2c/busses/Kconfig Tue May 8 12:13:31 2007
4880 @@ -81,6 +81,14 @@
4881 This supports the use of the I2C interface on Atmel AT91
4882 processors.
4883
4884 +config I2C_AT91_CLOCKRATE
4885 + prompt "Atmel AT91 I2C/TWI clock-rate"
4886 + depends on I2C_AT91
4887 + int
4888 + default 100000
4889 + help
4890 + Set the AT91 I2C/TWI clock-rate.
4891 +
4892 config I2C_AU1550
4893 tristate "Au1550/Au1200 SMBus interface"
4894 depends on I2C && (SOC_AU1550 || SOC_AU1200)
4895 @@ -545,6 +553,14 @@
4896 This driver can also be built as a module. If so, the module
4897 will be called i2c-voodoo3.
4898
4899 +config I2C_PCA
4900 + tristate "PCA9564"
4901 + depends on I2C
4902 + select I2C_ALGOPCA
4903 + help
4904 + This driver support the Philips PCA 9564 Parallel bus to I2C
4905 + bus controller.
4906 +
4907 config I2C_PCA_ISA
4908 tristate "PCA9564 on an ISA bus"
4909 depends on I2C
4910 diff -urN -x CVS linux-2.6.21/drivers/i2c/busses/Makefile linux-2.6-stable/drivers/i2c/busses/Makefile
4911 --- linux-2.6.21/drivers/i2c/busses/Makefile Thu Apr 26 05:08:32 2007
4912 +++ linux-2.6-stable/drivers/i2c/busses/Makefile Tue May 8 12:13:31 2007
4913 @@ -28,6 +28,7 @@
4914 obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
4915 obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o
4916 obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
4917 +obj-$(CONFIG_I2C_PCA) += i2c-pca.o
4918 obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
4919 obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
4920 obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
4921 diff -urN -x CVS linux-2.6.21/drivers/i2c/busses/i2c-at91.c linux-2.6-stable/drivers/i2c/busses/i2c-at91.c
4922 --- linux-2.6.21/drivers/i2c/busses/i2c-at91.c Thu Apr 26 05:08:32 2007
4923 +++ linux-2.6-stable/drivers/i2c/busses/i2c-at91.c Tue May 8 12:13:31 2007
4924 @@ -31,8 +31,11 @@
4925 #include <asm/arch/board.h>
4926 #include <asm/arch/cpu.h>
4927
4928 -#define TWI_CLOCK 100000 /* Hz. max 400 Kbits/sec */
4929
4930 +/* Clockrate is configurable - max 400 Kbits/sec */
4931 +static unsigned int clockrate = CONFIG_I2C_AT91_CLOCKRATE;
4932 +module_param(clockrate, uint, 0);
4933 +MODULE_PARM_DESC(clockrate, "The TWI clockrate");
4934
4935 static struct clk *twi_clk;
4936 static void __iomem *twi_base;
4937 @@ -53,7 +56,7 @@
4938 at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); /* Set Master mode */
4939
4940 /* Calcuate clock dividers */
4941 - cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3;
4942 + cdiv = (clk_get_rate(twi_clk) / (2 * clockrate)) - 3;
4943 cdiv = cdiv + 1; /* round up */
4944 ckdiv = 0;
4945 while (cdiv > 255) {
4946 @@ -61,11 +64,12 @@
4947 cdiv = cdiv >> 1;
4948 }
4949
4950 - if (cpu_is_at91rm9200()) { /* AT91RM9200 Errata #22 */
4951 - if (ckdiv > 5) {
4952 - printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n");
4953 - ckdiv = 5;
4954 - }
4955 + if (cpu_is_at91rm9200() && (ckdiv > 5)) { /* AT91RM9200 Errata #22 */
4956 + printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n");
4957 + ckdiv = 5;
4958 + } else if (ckdiv > 7) {
4959 + printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n");
4960 + ckdiv = 7;
4961 }
4962
4963 at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv);
4964 diff -urN -x CVS linux-2.6.21/drivers/i2c/busses/i2c-pca.c linux-2.6-stable/drivers/i2c/busses/i2c-pca.c
4965 --- linux-2.6.21/drivers/i2c/busses/i2c-pca.c Thu Jan 1 02:00:00 1970
4966 +++ linux-2.6-stable/drivers/i2c/busses/i2c-pca.c Tue May 8 12:13:31 2007
4967 @@ -0,0 +1,213 @@
4968 +/*
4969 + * Platform driver for PCA9564 I2C bus controller.
4970 + *
4971 + * (C) 2006 Andrew Victor
4972 + *
4973 + * Based on i2c-pca-isa.c driver for PCA9564 on ISA boards
4974 + * Copyright (C) 2004 Arcom Control Systems
4975 + *
4976 + * This program is free software; you can redistribute it and/or modify
4977 + * it under the terms of the GNU General Public License as published by
4978 + * the Free Software Foundation; either version 2 of the License, or
4979 + * (at your option) any later version.
4980 + *
4981 + * This program is distributed in the hope that it will be useful,
4982 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4983 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4984 + * GNU General Public License for more details.
4985 + *
4986 + * You should have received a copy of the GNU General Public License
4987 + * along with this program; if not, write to the Free Software
4988 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
4989 + */
4990 +
4991 +#include <linux/kernel.h>
4992 +#include <linux/module.h>
4993 +#include <linux/moduleparam.h>
4994 +#include <linux/delay.h>
4995 +#include <linux/init.h>
4996 +#include <linux/interrupt.h>
4997 +#include <linux/wait.h>
4998 +#include <linux/platform_device.h>
4999 +
5000 +#include <linux/i2c.h>
5001 +#include <linux/i2c-algo-pca.h>
5002 +
5003 +#include <asm/io.h>
5004 +
5005 +#include "../algos/i2c-algo-pca.h"
5006 +
5007 +#define PCA_OWN_ADDRESS 0x55 /* our address for slave mode */
5008 +#define PCA_CLOCK I2C_PCA_CON_59kHz
5009 +
5010 +//#define REG_SHIFT 2
5011 +#define REG_SHIFT 0
5012 +
5013 +//#define DEBUG_IO
5014 +
5015 +#define PCA_IO_SIZE 4
5016 +
5017 +static void __iomem *base_addr;
5018 +static int irq;
5019 +static wait_queue_head_t pca_wait;
5020 +
5021 +static int pca_getown(struct i2c_algo_pca_data *adap)
5022 +{
5023 + return PCA_OWN_ADDRESS;
5024 +}
5025 +
5026 +static int pca_getclock(struct i2c_algo_pca_data *adap)
5027 +{
5028 + return PCA_CLOCK;
5029 +}
5030 +
5031 +static void pca_writebyte(struct i2c_algo_pca_data *adap, int reg, int val)
5032 +{
5033 +#ifdef DEBUG_IO
5034 + static char *names[] = { "T/O", "DAT", "ADR", "CON" };
5035 + printk("*** write %s at %#lx <= %#04x\n", names[reg], (unsigned long) base_addr+reg, val);
5036 +#endif
5037 + udelay(1);
5038 + outb(val, base_addr + (reg << REG_SHIFT));
5039 +}
5040 +
5041 +static int pca_readbyte(struct i2c_algo_pca_data *adap, int reg)
5042 +{
5043 + int res;
5044 +
5045 + udelay(1);
5046 + res = inb(base_addr + (reg << REG_SHIFT));
5047 +#ifdef DEBUG_IO
5048 + {
5049 + static char *names[] = { "STA", "DAT", "ADR", "CON" };
5050 + printk("*** read %s => %#04x\n", names[reg], res);
5051 + }
5052 +#endif
5053 + return res;
5054 +}
5055 +
5056 +static int pca_waitforinterrupt(struct i2c_algo_pca_data *adap)
5057 +{
5058 + int ret = 0;
5059 +
5060 + if (irq > -1) {
5061 + ret = wait_event_interruptible(pca_wait,
5062 + pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI);
5063 + } else {
5064 + while ((pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
5065 + udelay(100);
5066 + }
5067 + return ret;
5068 +}
5069 +
5070 +static irqreturn_t pca_handler(int this_irq, void *dev_id)
5071 +{
5072 + wake_up_interruptible(&pca_wait);
5073 + return IRQ_HANDLED;
5074 +}
5075 +
5076 +static struct i2c_algo_pca_data pca_i2c_data = {
5077 + .get_own = pca_getown,
5078 + .get_clock = pca_getclock,
5079 + .write_byte = pca_writebyte,
5080 + .read_byte = pca_readbyte,
5081 + .wait_for_interrupt = pca_waitforinterrupt,
5082 +};
5083 +
5084 +static struct i2c_adapter pca_i2c_ops = {
5085 + .owner = THIS_MODULE,
5086 + .id = I2C_HW_A_PLAT,
5087 + .algo_data = &pca_i2c_data,
5088 + .name = "PCA9564",
5089 + .class = I2C_CLASS_HWMON,
5090 +};
5091 +
5092 +static int __devinit pca_i2c_probe(struct platform_device *pdev)
5093 +{
5094 + struct resource *res;
5095 +
5096 + init_waitqueue_head(&pca_wait);
5097 +
5098 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5099 + if (!res)
5100 + return -ENODEV;
5101 +
5102 + if (!request_mem_region(res->start, PCA_IO_SIZE, "PCA9564"))
5103 + return -ENXIO;
5104 +
5105 + base_addr = ioremap(res->start, PCA_IO_SIZE);
5106 + if (base_addr == NULL)
5107 + goto out_region;
5108 +
5109 + irq = platform_get_irq(pdev, 0);
5110 + if (irq > -1) {
5111 + if (request_irq(irq, pca_handler, 0, "pca9564", NULL) < 0) {
5112 + printk(KERN_ERR "i2c-pca: Request irq%d failed\n", irq);
5113 + goto out_remap;
5114 + }
5115 + }
5116 +
5117 + /* set up the driverfs linkage to our parent device */
5118 + pca_i2c_ops.dev.parent = &pdev->dev;
5119 +
5120 + if (i2c_pca_add_bus(&pca_i2c_ops) < 0) {
5121 + printk(KERN_ERR "i2c-pca: Failed to add i2c bus\n");
5122 + goto out_irq;
5123 + }
5124 +
5125 + return 0;
5126 +
5127 + out_irq:
5128 + if (irq > -1)
5129 + free_irq(irq, &pca_i2c_ops);
5130 +
5131 + out_remap:
5132 + iounmap(base_addr);
5133 +
5134 + out_region:
5135 + release_mem_region(res->start, PCA_IO_SIZE);
5136 + return -ENODEV;
5137 +}
5138 +
5139 +static int __devexit pca_i2c_remove(struct platform_device *pdev)
5140 +{
5141 + struct resource *res;
5142 +
5143 + i2c_del_adapter(&pca_i2c_ops);
5144 +
5145 + if (irq > 0)
5146 + free_irq(irq, NULL);
5147 +
5148 + iounmap(base_addr);
5149 +
5150 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5151 + release_mem_region(res->start, PCA_IO_SIZE);
5152 +
5153 + return 0;
5154 +}
5155 +
5156 +static struct platform_driver pca_i2c_driver = {
5157 + .probe = pca_i2c_probe,
5158 + .remove = __devexit_p(pca_i2c_remove),
5159 + .driver = {
5160 + .name = "pca9564",
5161 + .owner = THIS_MODULE,
5162 + },
5163 +};
5164 +
5165 +static int __init pca_i2c_init(void)
5166 +{
5167 + return platform_driver_register(&pca_i2c_driver);
5168 +}
5169 +
5170 +static void __exit pca_i2c_exit(void)
5171 +{
5172 + platform_driver_unregister(&pca_i2c_driver);
5173 +}
5174 +
5175 +module_init(pca_i2c_init);
5176 +module_exit(pca_i2c_exit);
5177 +
5178 +MODULE_AUTHOR("Andrew Victor");
5179 +MODULE_DESCRIPTION("PCA9564 platform driver");
5180 +MODULE_LICENSE("GPL");
5181 diff -urN -x CVS linux-2.6.21/drivers/input/touchscreen/ads7846.c linux-2.6-stable/drivers/input/touchscreen/ads7846.c
5182 --- linux-2.6.21/drivers/input/touchscreen/ads7846.c Thu Apr 26 05:08:32 2007
5183 +++ linux-2.6-stable/drivers/input/touchscreen/ads7846.c Tue May 8 12:56:33 2007
5184 @@ -39,7 +39,8 @@
5185 /*
5186 * This code has been heavily tested on a Nokia 770, and lightly
5187 * tested on other ads7846 devices (OSK/Mistral, Lubbock).
5188 - * Support for ads7843 and ads7845 has only been stubbed in.
5189 + * Support for ads7843 tested on Atmel at91sam926x-EK.
5190 + * Support for ads7845 has only been stubbed in.
5191 *
5192 * IRQ handling needs a workaround because of a shortcoming in handling
5193 * edge triggered IRQs on some platforms like the OMAP1/2. These
5194 @@ -246,18 +247,16 @@
5195
5196 /* REVISIT: take a few more samples, and compare ... */
5197
5198 - /* maybe off internal vREF */
5199 - if (use_internal) {
5200 - req->ref_off = REF_OFF;
5201 - req->xfer[4].tx_buf = &req->ref_off;
5202 - req->xfer[4].len = 1;
5203 - spi_message_add_tail(&req->xfer[4], &req->msg);
5204 -
5205 - req->xfer[5].rx_buf = &req->scratch;
5206 - req->xfer[5].len = 2;
5207 - CS_CHANGE(req->xfer[5]);
5208 - spi_message_add_tail(&req->xfer[5], &req->msg);
5209 - }
5210 + /* converter in low power mode & enable PENIRQ */
5211 + req->ref_off = PWRDOWN;
5212 + req->xfer[4].tx_buf = &req->ref_off;
5213 + req->xfer[4].len = 1;
5214 + spi_message_add_tail(&req->xfer[4], &req->msg);
5215 +
5216 + req->xfer[5].rx_buf = &req->scratch;
5217 + req->xfer[5].len = 2;
5218 + CS_CHANGE(req->xfer[5]);
5219 + spi_message_add_tail(&req->xfer[5], &req->msg);
5220
5221 ts->irq_disabled = 1;
5222 disable_irq(spi->irq);
5223 @@ -536,6 +535,9 @@
5224 } else
5225 Rt = 0;
5226
5227 + if (ts->model == 7843)
5228 + Rt = ts->pressure_max / 2;
5229 +
5230 /* Sample found inconsistent by debouncing or pressure is beyond
5231 * the maximum. Don't report it to user space, repeat at least
5232 * once more the measurement
5233 diff -urN -x CVS linux-2.6.21/drivers/leds/Kconfig linux-2.6-stable/drivers/leds/Kconfig
5234 --- linux-2.6.21/drivers/leds/Kconfig Thu Apr 26 05:08:32 2007
5235 +++ linux-2.6-stable/drivers/leds/Kconfig Tue May 8 12:13:31 2007
5236 @@ -76,6 +76,13 @@
5237 This option enables support for the Soekris net4801 and net4826 error
5238 LED.
5239
5240 +config LEDS_AT91
5241 + tristate "LED support using AT91 GPIOs"
5242 + depends on LEDS_CLASS && ARCH_AT91 && !LEDS
5243 + help
5244 + This option enables support for LEDs connected to GPIO lines
5245 + on AT91-based boards.
5246 +
5247 config LEDS_WRAP
5248 tristate "LED Support for the WRAP series LEDs"
5249 depends on LEDS_CLASS && SCx200_GPIO
5250 diff -urN -x CVS linux-2.6.21/drivers/leds/Makefile linux-2.6-stable/drivers/leds/Makefile
5251 --- linux-2.6.21/drivers/leds/Makefile Thu Apr 26 05:08:32 2007
5252 +++ linux-2.6-stable/drivers/leds/Makefile Tue May 8 12:13:31 2007
5253 @@ -16,6 +16,7 @@
5254 obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o
5255 obj-$(CONFIG_LEDS_H1940) += leds-h1940.o
5256 obj-$(CONFIG_LEDS_COBALT) += leds-cobalt.o
5257 +obj-$(CONFIG_LEDS_AT91) += leds-at91.o
5258
5259 # LED Triggers
5260 obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
5261 diff -urN -x CVS linux-2.6.21/drivers/leds/leds-at91.c linux-2.6-stable/drivers/leds/leds-at91.c
5262 --- linux-2.6.21/drivers/leds/leds-at91.c Thu Jan 1 02:00:00 1970
5263 +++ linux-2.6-stable/drivers/leds/leds-at91.c Tue May 8 12:13:31 2007
5264 @@ -0,0 +1,140 @@
5265 +/*
5266 + * AT91 GPIO based LED driver
5267 + *
5268 + * Copyright (C) 2006 David Brownell
5269 + *
5270 + * This program is free software; you can redistribute it and/or modify
5271 + * it under the terms of the GNU General Public License version 2 as
5272 + * published by the Free Software Foundation.
5273 + */
5274 +
5275 +#include <linux/kernel.h>
5276 +#include <linux/init.h>
5277 +#include <linux/platform_device.h>
5278 +#include <linux/leds.h>
5279 +
5280 +#include <asm/arch/board.h>
5281 +#include <asm/arch/gpio.h>
5282 +
5283 +static LIST_HEAD(at91_led_list); /* list of AT91 LEDs */
5284 +
5285 +struct at91_led {
5286 + struct led_classdev cdev;
5287 + struct list_head list;
5288 + struct at91_gpio_led *led_data;
5289 +};
5290 +
5291 +/*
5292 + * Change the state of the LED.
5293 + */
5294 +static void at91_led_set(struct led_classdev *cdev, enum led_brightness value)
5295 +{
5296 + struct at91_led *led = container_of(cdev, struct at91_led, cdev);
5297 + short active = (value == LED_OFF);
5298 +
5299 + if (led->led_data->flags & 1) /* active high/low? */
5300 + active = !active;
5301 + at91_set_gpio_value(led->led_data->gpio, active);
5302 +}
5303 +
5304 +static int __devexit at91_led_remove(struct platform_device *pdev)
5305 +{
5306 + struct at91_led *led;
5307 +
5308 + list_for_each_entry (led, &at91_led_list, list)
5309 + led_classdev_unregister(&led->cdev);
5310 +
5311 +#warning "Free allocated memory"
5312 + // TODO: Free memory. kfree(led);
5313 +
5314 + return 0;
5315 +}
5316 +
5317 +static int __init at91_led_probe(struct platform_device *pdev)
5318 +{
5319 + int status = 0;
5320 + struct at91_gpio_led *pdata = pdev->dev.platform_data;
5321 + unsigned nr_leds;
5322 + struct at91_led *led;
5323 +
5324 + if (!pdata)
5325 + return -ENODEV;
5326 +
5327 + nr_leds = pdata->index; /* first index stores number of LEDs */
5328 +
5329 + while (nr_leds--) {
5330 + led = kzalloc(sizeof(struct at91_led), GFP_KERNEL);
5331 + if (!led) {
5332 + dev_err(&pdev->dev, "No memory for device\n");
5333 + status = -ENOMEM;
5334 + goto cleanup;
5335 + }
5336 + led->led_data = pdata;
5337 + led->cdev.name = pdata->name;
5338 + led->cdev.brightness_set = at91_led_set,
5339 + led->cdev.default_trigger = pdata->trigger;
5340 +
5341 + status = led_classdev_register(&pdev->dev, &led->cdev);
5342 + if (status < 0) {
5343 + dev_err(&pdev->dev, "led_classdev_register failed - %d\n", status);
5344 +cleanup:
5345 + at91_led_remove(pdev);
5346 + break;
5347 + }
5348 + list_add(&led->list, &at91_led_list);
5349 + pdata++;
5350 + }
5351 + return status;
5352 +}
5353 +
5354 +#ifdef CONFIG_PM
5355 +static int at91_led_suspend(struct platform_device *dev, pm_message_t state)
5356 +{
5357 + struct at91_led *led;
5358 +
5359 + list_for_each_entry (led, &at91_led_list, list)
5360 + led_classdev_suspend(&led->cdev);
5361 +
5362 + return 0;
5363 +}
5364 +
5365 +static int at91_led_resume(struct platform_device *dev)
5366 +{
5367 + struct at91_led *led;
5368 +
5369 + list_for_each_entry (led, &at91_led_list, list)
5370 + led_classdev_resume(&led->cdev);
5371 +
5372 + return 0;
5373 +}
5374 +#else
5375 +#define at91_led_suspend NULL
5376 +#define at91_led_resume NULL
5377 +#endif
5378 +
5379 +static struct platform_driver at91_led_driver = {
5380 + .probe = at91_led_probe,
5381 + .remove = __devexit_p(at91_led_remove),
5382 + .suspend = at91_led_suspend,
5383 + .resume = at91_led_resume,
5384 + .driver = {
5385 + .name = "at91_leds",
5386 + .owner = THIS_MODULE,
5387 + },
5388 +};
5389 +
5390 +static int __init at91_led_init(void)
5391 +{
5392 + return platform_driver_register(&at91_led_driver);
5393 +}
5394 +module_init(at91_led_init);
5395 +
5396 +static void __exit at91_led_exit(void)
5397 +{
5398 + platform_driver_unregister(&at91_led_driver);
5399 +}
5400 +module_exit(at91_led_exit);
5401 +
5402 +MODULE_DESCRIPTION("AT91 GPIO LED driver");
5403 +MODULE_AUTHOR("David Brownell");
5404 +MODULE_LICENSE("GPL");
5405 diff -urN -x CVS linux-2.6.21/drivers/mmc/at91_mci.c linux-2.6-stable/drivers/mmc/at91_mci.c
5406 --- linux-2.6.21/drivers/mmc/at91_mci.c Thu Apr 26 05:08:32 2007
5407 +++ linux-2.6-stable/drivers/mmc/at91_mci.c Fri May 11 17:13:13 2007
5408 @@ -86,7 +86,7 @@
5409
5410 #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
5411 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
5412 - | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
5413 + | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
5414
5415 #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
5416 #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
5417 @@ -561,9 +561,7 @@
5418 pr_debug("Status = %08X [%08X %08X %08X %08X]\n",
5419 status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
5420
5421 - if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
5422 - AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
5423 - AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
5424 + if (status & AT91_MCI_ERRORS) {
5425 if ((status & AT91_MCI_RCRCE) &&
5426 ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
5427 cmd->error = MMC_ERR_NONE;
5428 @@ -665,15 +663,15 @@
5429
5430 int_status = at91_mci_read(host, AT91_MCI_SR);
5431 int_mask = at91_mci_read(host, AT91_MCI_IMR);
5432 -
5433 +
5434 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
5435 int_status & int_mask);
5436 -
5437 +
5438 int_status = int_status & int_mask;
5439
5440 if (int_status & AT91_MCI_ERRORS) {
5441 completed = 1;
5442 -
5443 +
5444 if (int_status & AT91_MCI_UNRE)
5445 pr_debug("MMC: Underrun error\n");
5446 if (int_status & AT91_MCI_OVRE)
5447 @@ -821,7 +819,7 @@
5448 mmc->f_min = 375000;
5449 mmc->f_max = 25000000;
5450 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
5451 - mmc->caps = MMC_CAP_BYTEBLOCK;
5452 + mmc->caps = MMC_CAP_BYTEBLOCK | MMC_CAP_MULTIWRITE;
5453
5454 mmc->max_blk_size = 4095;
5455 mmc->max_blk_count = mmc->max_req_size;
5456 @@ -895,6 +893,8 @@
5457
5458 mmc_add_host(mmc);
5459
5460 + device_init_wakeup(&pdev->dev, 1);
5461 +
5462 /*
5463 * monitor card insertion/removal if we can
5464 */
5465 @@ -924,6 +924,8 @@
5466
5467 host = mmc_priv(mmc);
5468
5469 + device_init_wakeup(&pdev->dev, 0);
5470 +
5471 if (host->present != -1) {
5472 free_irq(host->board->det_pin, host);
5473 cancel_delayed_work(&host->mmc->detect);
5474 @@ -951,8 +953,12 @@
5475 static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
5476 {
5477 struct mmc_host *mmc = platform_get_drvdata(pdev);
5478 + struct at91mci_host *host = mmc_priv(mmc);
5479 int ret = 0;
5480
5481 + if (device_may_wakeup(&pdev->dev))
5482 + enable_irq_wake(host->board->det_pin);
5483 +
5484 if (mmc)
5485 ret = mmc_suspend_host(mmc, state);
5486
5487 @@ -962,8 +968,12 @@
5488 static int at91_mci_resume(struct platform_device *pdev)
5489 {
5490 struct mmc_host *mmc = platform_get_drvdata(pdev);
5491 + struct at91mci_host *host = mmc_priv(mmc);
5492 int ret = 0;
5493
5494 + if (device_may_wakeup(&pdev->dev))
5495 + disable_irq_wake(host->board->det_pin);
5496 +
5497 if (mmc)
5498 ret = mmc_resume_host(mmc);
5499
5500 diff -urN -x CVS linux-2.6.21/drivers/mtd/devices/Kconfig linux-2.6-stable/drivers/mtd/devices/Kconfig
5501 --- linux-2.6.21/drivers/mtd/devices/Kconfig Thu Apr 26 05:08:32 2007
5502 +++ linux-2.6-stable/drivers/mtd/devices/Kconfig Tue May 8 14:31:24 2007
5503 @@ -267,5 +267,11 @@
5504 LinuxBIOS or if you need to recover a DiskOnChip Millennium on which
5505 you have managed to wipe the first block.
5506
5507 -endmenu
5508 +config MTD_AT91_DATAFLASH
5509 + tristate "AT91RM9200 DataFlash AT45DBxxx (legacy driver)"
5510 + depends on MTD && ARCH_AT91RM9200 && AT91_SPI
5511 + help
5512 + This enables access to the DataFlash (AT45DBxxx) on the AT91RM9200.
5513 + If you have such a board, say 'Y'.
5514
5515 +endmenu
5516 diff -urN -x CVS linux-2.6.21/drivers/mtd/devices/Makefile linux-2.6-stable/drivers/mtd/devices/Makefile
5517 --- linux-2.6.21/drivers/mtd/devices/Makefile Thu Apr 26 05:08:32 2007
5518 +++ linux-2.6-stable/drivers/mtd/devices/Makefile Tue May 8 14:31:24 2007
5519 @@ -17,3 +17,4 @@
5520 obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
5521 obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
5522 obj-$(CONFIG_MTD_M25P80) += m25p80.o
5523 +obj-$(CONFIG_MTD_AT91_DATAFLASH)+= at91_dataflash.o
5524 diff -urN -x CVS linux-2.6.21/drivers/mtd/devices/at91_dataflash.c linux-2.6-stable/drivers/mtd/devices/at91_dataflash.c
5525 --- linux-2.6.21/drivers/mtd/devices/at91_dataflash.c Thu Jan 1 02:00:00 1970
5526 +++ linux-2.6-stable/drivers/mtd/devices/at91_dataflash.c Tue May 8 14:31:24 2007
5527 @@ -0,0 +1,667 @@
5528 +/*
5529 + * Atmel DataFlash driver for Atmel AT91RM9200 (Thunder)
5530 + *
5531 + * Copyright (C) SAN People (Pty) Ltd
5532 + *
5533 + * This program is free software; you can redistribute it and/or
5534 + * modify it under the terms of the GNU General Public License
5535 + * as published by the Free Software Foundation; either version
5536 + * 2 of the License, or (at your option) any later version.
5537 +*/
5538 +
5539 +#include <linux/module.h>
5540 +#include <linux/init.h>
5541 +#include <linux/slab.h>
5542 +#include <linux/pci.h>
5543 +#include <linux/mtd/mtd.h>
5544 +#include <linux/mtd/partitions.h>
5545 +
5546 +#include <asm/arch/spi.h>
5547 +
5548 +#undef DEBUG_DATAFLASH
5549 +
5550 +#define DATAFLASH_MAX_DEVICES 4 /* max number of dataflash devices */
5551 +#undef DATAFLASH_ALWAYS_ADD_DEVICE /* always add whole device when using partitions? */
5552 +
5553 +#define OP_READ_CONTINUOUS 0xE8
5554 +#define OP_READ_PAGE 0xD2
5555 +#define OP_READ_BUFFER1 0xD4
5556 +#define OP_READ_BUFFER2 0xD6
5557 +#define OP_READ_STATUS 0xD7
5558 +
5559 +#define OP_ERASE_PAGE 0x81
5560 +#define OP_ERASE_BLOCK 0x50
5561 +
5562 +#define OP_TRANSFER_BUF1 0x53
5563 +#define OP_TRANSFER_BUF2 0x55
5564 +#define OP_COMPARE_BUF1 0x60
5565 +#define OP_COMPARE_BUF2 0x61
5566 +
5567 +#define OP_PROGRAM_VIA_BUF1 0x82
5568 +#define OP_PROGRAM_VIA_BUF2 0x85
5569 +
5570 +struct dataflash_local
5571 +{
5572 + int spi; /* SPI chip-select number */
5573 +
5574 + unsigned int page_size; /* number of bytes per page */
5575 + unsigned short page_offset; /* page offset in flash address */
5576 +};
5577 +
5578 +
5579 +/* Detected DataFlash devices */
5580 +static struct mtd_info* mtd_devices[DATAFLASH_MAX_DEVICES];
5581 +static int nr_devices = 0;
5582 +
5583 +/* ......................................................................... */
5584 +
5585 +#ifdef CONFIG_MTD_PARTITIONS
5586 +
5587 +static struct mtd_partition static_partitions_2M[] =
5588 +{
5589 + {
5590 + .name = "bootloader",
5591 + .offset = 0,
5592 + .size = 1 * 32 * 8 * 528, /* 1st sector = 32 blocks * 8 pages * 528 bytes */
5593 + .mask_flags = MTD_WRITEABLE, /* read-only */
5594 + },
5595 + {
5596 + .name = "kernel",
5597 + .offset = MTDPART_OFS_NXTBLK,
5598 + .size = 6 * 32 * 8 * 528, /* 6 sectors */
5599 + },
5600 + {
5601 + .name = "filesystem",
5602 + .offset = MTDPART_OFS_NXTBLK,
5603 + .size = MTDPART_SIZ_FULL, /* rest = 9 sectors */
5604 + }
5605 +};
5606 +
5607 +static struct mtd_partition static_partitions_4M[] =
5608 +{
5609 + {
5610 + .name = "bootloader",
5611 + .offset = 0,
5612 + .size = 1 * 64 * 8 * 528, /* 1st sector = 64 blocks * 8 pages * 528 bytes */
5613 + .mask_flags = MTD_WRITEABLE, /* read-only */
5614 + },
5615 + {
5616 + .name = "kernel",
5617 + .offset = MTDPART_OFS_NXTBLK,
5618 + .size = 4 * 64 * 8 * 528, /* 4 sectors */
5619 + },
5620 + {
5621 + .name = "filesystem",
5622 + .offset = MTDPART_OFS_NXTBLK,
5623 + .size = MTDPART_SIZ_FULL, /* rest = 11 sectors */
5624 + }
5625 +};
5626 +
5627 +#if defined(CONFIG_MACH_KAFA)
5628 +static struct mtd_partition static_partitions_8M[] =
5629 +{
5630 + {
5631 + name: "romboot",
5632 + offset: 0,
5633 + size: 16 * 1056, /* 160 Kb */
5634 + mask_flags: MTD_WRITEABLE, /* read-only */
5635 + },
5636 + {
5637 + name: "uboot",
5638 + offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
5639 + size: 128 * 1056, /* 1 MB */
5640 + },
5641 + {
5642 + name: "kernel",
5643 + offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
5644 + size: 1024 * 1056, /* 1 MB */
5645 + },
5646 + {
5647 + name: "filesystem",
5648 + offset: MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
5649 + size: MTDPART_SIZ_FULL,
5650 + }
5651 +};
5652 +
5653 +#elif defined(CONFIG_MACH_MULTMDP)
5654 +
5655 +static struct mtd_partition static_partitions_8M[] =
5656 +{
5657 + {
5658 + .name = "bootloader",
5659 + .offset = 0,
5660 + .size = 12 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */
5661 + .mask_flags = MTD_WRITEABLE, /* read-only */
5662 + },
5663 + {
5664 + .name = "configuration",
5665 + .offset = MTDPART_OFS_NXTBLK,
5666 + .size = 20 * 1056,
5667 + },
5668 + {
5669 + .name = "kernel",
5670 + .offset = MTDPART_OFS_NXTBLK,
5671 + .size = 1520 * 1056,
5672 + },
5673 + {
5674 + .name = "filesystem",
5675 + .offset = MTDPART_OFS_NXTBLK,
5676 + .size = MTDPART_SIZ_FULL,
5677 + }
5678 +};
5679 +
5680 +#else
5681 +
5682 +static struct mtd_partition static_partitions_8M[] =
5683 +{
5684 + {
5685 + .name = "bootloader",
5686 + .offset = 0,
5687 + .size = 1 * 32 * 8 * 1056, /* 1st sector = 32 blocks * 8 pages * 1056 bytes */
5688 + .mask_flags = MTD_WRITEABLE, /* read-only */
5689 + },
5690 + {
5691 + .name = "kernel",
5692 + .offset = MTDPART_OFS_NXTBLK,
5693 + .size = 5 * 32 * 8 * 1056, /* 5 sectors */
5694 + },
5695 + {
5696 + .name = "filesystem",
5697 + .offset = MTDPART_OFS_NXTBLK,
5698 + .size = MTDPART_SIZ_FULL, /* rest = 26 sectors */
5699 + }
5700 +};
5701 +#endif
5702 +
5703 +static const char *part_probes[] = { "cmdlinepart", NULL, };
5704 +
5705 +#endif
5706 +
5707 +/* ......................................................................... */
5708 +
5709 +/* Allocate a single SPI transfer descriptor. We're assuming that if multiple
5710 + SPI transfers occur at the same time, spi_access_bus() will serialize them.
5711 + If this is not valid, then either (i) each dataflash 'priv' structure
5712 + needs it's own transfer descriptor, (ii) we lock this one, or (iii) use
5713 + another mechanism. */
5714 +static struct spi_transfer_list* spi_transfer_desc;
5715 +
5716 +/*
5717 + * Perform a SPI transfer to access the DataFlash device.
5718 + */
5719 +static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len,
5720 + char* txnext, int txnext_len, char* rxnext, int rxnext_len)
5721 +{
5722 + struct spi_transfer_list* list = spi_transfer_desc;
5723 +
5724 + list->tx[0] = tx; list->txlen[0] = tx_len;
5725 + list->rx[0] = rx; list->rxlen[0] = rx_len;
5726 +
5727 + list->tx[1] = txnext; list->txlen[1] = txnext_len;
5728 + list->rx[1] = rxnext; list->rxlen[1] = rxnext_len;
5729 +
5730 + list->nr_transfers = nr;
5731 +
5732 + return spi_transfer(list);
5733 +}
5734 +
5735 +/* ......................................................................... */
5736 +
5737 +/*
5738 + * Poll the DataFlash device until it is READY.
5739 + */
5740 +static void at91_dataflash_waitready(void)
5741 +{
5742 + char* command = kmalloc(2, GFP_KERNEL);
5743 +
5744 + if (!command)
5745 + return;
5746 +
5747 + do {
5748 + command[0] = OP_READ_STATUS;
5749 + command[1] = 0;
5750 +
5751 + do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
5752 + } while ((command[1] & 0x80) == 0);
5753 +
5754 + kfree(command);
5755 +}
5756 +
5757 +/*
5758 + * Return the status of the DataFlash device.
5759 + */
5760 +static unsigned short at91_dataflash_status(void)
5761 +{
5762 + unsigned short status;
5763 + char* command = kmalloc(2, GFP_KERNEL);
5764 +
5765 + if (!command)
5766 + return 0;
5767 +
5768 + command[0] = OP_READ_STATUS;
5769 + command[1] = 0;
5770 +
5771 + do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
5772 + status = command[1];
5773 +
5774 + kfree(command);
5775 + return status;
5776 +}
5777 +
5778 +/* ......................................................................... */
5779 +
5780 +/*
5781 + * Erase blocks of flash.
5782 + */
5783 +static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
5784 +{
5785 + struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
5786 + unsigned int pageaddr;
5787 + char* command;
5788 +
5789 +#ifdef DEBUG_DATAFLASH
5790 + printk("dataflash_erase: addr=%i len=%i\n", instr->addr, instr->len);
5791 +#endif
5792 +
5793 + /* Sanity checks */
5794 + if (instr->addr + instr->len > mtd->size)
5795 + return -EINVAL;
5796 + if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0))
5797 + return -EINVAL;
5798 + if ((instr->addr % priv->page_size) != 0)
5799 + return -EINVAL;
5800 +
5801 + command = kmalloc(4, GFP_KERNEL);
5802 + if (!command)
5803 + return -ENOMEM;
5804 +
5805 + while (instr->len > 0) {
5806 + /* Calculate flash page address */
5807 + pageaddr = (instr->addr / priv->page_size) << priv->page_offset;
5808 +
5809 + command[0] = OP_ERASE_PAGE;
5810 + command[1] = (pageaddr & 0x00FF0000) >> 16;
5811 + command[2] = (pageaddr & 0x0000FF00) >> 8;
5812 + command[3] = 0;
5813 +#ifdef DEBUG_DATAFLASH
5814 + printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr);
5815 +#endif
5816 +
5817 + /* Send command to SPI device */
5818 + spi_access_bus(priv->spi);
5819 + do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
5820 +
5821 + at91_dataflash_waitready(); /* poll status until ready */
5822 + spi_release_bus(priv->spi);
5823 +
5824 + instr->addr += priv->page_size; /* next page */
5825 + instr->len -= priv->page_size;
5826 + }
5827 +
5828 + kfree(command);
5829 +
5830 + /* Inform MTD subsystem that erase is complete */
5831 + instr->state = MTD_ERASE_DONE;
5832 + if (instr->callback)
5833 + instr->callback(instr);
5834 +
5835 + return 0;
5836 +}
5837 +
5838 +/*
5839 + * Read from the DataFlash device.
5840 + * from : Start offset in flash device
5841 + * len : Amount to read
5842 + * retlen : About of data actually read
5843 + * buf : Buffer containing the data
5844 + */
5845 +static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
5846 +{
5847 + struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
5848 + unsigned int addr;
5849 + char* command;
5850 +
5851 +#ifdef DEBUG_DATAFLASH
5852 + printk("dataflash_read: %lli .. %lli\n", from, from+len);
5853 +#endif
5854 +
5855 + *retlen = 0;
5856 +
5857 + /* Sanity checks */
5858 + if (!len)
5859 + return 0;
5860 + if (from + len > mtd->size)
5861 + return -EINVAL;
5862 +
5863 + /* Calculate flash page/byte address */
5864 + addr = (((unsigned)from / priv->page_size) << priv->page_offset) + ((unsigned)from % priv->page_size);
5865 +
5866 + command = kmalloc(8, GFP_KERNEL);
5867 + if (!command)
5868 + return -ENOMEM;
5869 +
5870 + command[0] = OP_READ_CONTINUOUS;
5871 + command[1] = (addr & 0x00FF0000) >> 16;
5872 + command[2] = (addr & 0x0000FF00) >> 8;
5873 + command[3] = (addr & 0x000000FF);
5874 +#ifdef DEBUG_DATAFLASH
5875 + printk("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
5876 +#endif
5877 +
5878 + /* Send command to SPI device */
5879 + spi_access_bus(priv->spi);
5880 + do_spi_transfer(2, command, 8, command, 8, buf, len, buf, len);
5881 + spi_release_bus(priv->spi);
5882 +
5883 + *retlen = len;
5884 + kfree(command);
5885 + return 0;
5886 +}
5887 +
5888 +/*
5889 + * Write to the DataFlash device.
5890 + * to : Start offset in flash device
5891 + * len : Amount to write
5892 + * retlen : Amount of data actually written
5893 + * buf : Buffer containing the data
5894 + */
5895 +static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
5896 +{
5897 + struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
5898 + unsigned int pageaddr, addr, offset, writelen;
5899 + size_t remaining;
5900 + u_char *writebuf;
5901 + unsigned short status;
5902 + int res = 0;
5903 + char* command;
5904 + char* tmpbuf = NULL;
5905 +
5906 +#ifdef DEBUG_DATAFLASH
5907 + printk("dataflash_write: %lli .. %lli\n", to, to+len);
5908 +#endif
5909 +
5910 + *retlen = 0;
5911 +
5912 + /* Sanity checks */
5913 + if (!len)
5914 + return 0;
5915 + if (to + len > mtd->size)
5916 + return -EINVAL;
5917 +
5918 + command = kmalloc(4, GFP_KERNEL);
5919 + if (!command)
5920 + return -ENOMEM;
5921 +
5922 + pageaddr = ((unsigned)to / priv->page_size);
5923 + offset = ((unsigned)to % priv->page_size);
5924 + if (offset + len > priv->page_size)
5925 + writelen = priv->page_size - offset;
5926 + else
5927 + writelen = len;
5928 + writebuf = (u_char *)buf;
5929 + remaining = len;
5930 +
5931 + /* Allocate temporary buffer */
5932 + tmpbuf = kmalloc(priv->page_size, GFP_KERNEL);
5933 + if (!tmpbuf) {
5934 + kfree(command);
5935 + return -ENOMEM;
5936 + }
5937 +
5938 + /* Gain access to the SPI bus */
5939 + spi_access_bus(priv->spi);
5940 +
5941 + while (remaining > 0) {
5942 +#ifdef DEBUG_DATAFLASH
5943 + printk("write @ %i:%i len=%i\n", pageaddr, offset, writelen);
5944 +#endif
5945 +
5946 + /* (1) Transfer to Buffer1 */
5947 + if (writelen != priv->page_size) {
5948 + addr = pageaddr << priv->page_offset;
5949 + command[0] = OP_TRANSFER_BUF1;
5950 + command[1] = (addr & 0x00FF0000) >> 16;
5951 + command[2] = (addr & 0x0000FF00) >> 8;
5952 + command[3] = 0;
5953 +#ifdef DEBUG_DATAFLASH
5954 + printk("TRANSFER: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
5955 +#endif
5956 + do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
5957 + at91_dataflash_waitready();
5958 + }
5959 +
5960 + /* (2) Program via Buffer1 */
5961 + addr = (pageaddr << priv->page_offset) + offset;
5962 + command[0] = OP_PROGRAM_VIA_BUF1;
5963 + command[1] = (addr & 0x00FF0000) >> 16;
5964 + command[2] = (addr & 0x0000FF00) >> 8;
5965 + command[3] = (addr & 0x000000FF);
5966 +#ifdef DEBUG_DATAFLASH
5967 + printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
5968 +#endif
5969 + do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen);
5970 + at91_dataflash_waitready();
5971 +
5972 + /* (3) Compare to Buffer1 */
5973 + addr = pageaddr << priv->page_offset;
5974 + command[0] = OP_COMPARE_BUF1;
5975 + command[1] = (addr & 0x00FF0000) >> 16;
5976 + command[2] = (addr & 0x0000FF00) >> 8;
5977 + command[3] = 0;
5978 +#ifdef DEBUG_DATAFLASH
5979 + printk("COMPARE: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
5980 +#endif
5981 + do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
5982 + at91_dataflash_waitready();
5983 +
5984 + /* Get result of the compare operation */
5985 + status = at91_dataflash_status();
5986 + if ((status & 0x40) == 1) {
5987 + printk("at91_dataflash: Write error on page %i\n", pageaddr);
5988 + remaining = 0;
5989 + res = -EIO;
5990 + }
5991 +
5992 + remaining = remaining - writelen;
5993 + pageaddr++;
5994 + offset = 0;
5995 + writebuf += writelen;
5996 + *retlen += writelen;
5997 +
5998 + if (remaining > priv->page_size)
5999 + writelen = priv->page_size;
6000 + else
6001 + writelen = remaining;
6002 + }
6003 +
6004 + /* Release SPI bus */
6005 + spi_release_bus(priv->spi);
6006 +
6007 + kfree(tmpbuf);
6008 + kfree(command);
6009 + return res;
6010 +}
6011 +
6012 +/* ......................................................................... */
6013 +
6014 +/*
6015 + * Initialize and register DataFlash device with MTD subsystem.
6016 + */
6017 +static int __init add_dataflash(int channel, char *name, int IDsize,
6018 + int nr_pages, int pagesize, int pageoffset)
6019 +{
6020 + struct mtd_info *device;
6021 + struct dataflash_local *priv;
6022 +#ifdef CONFIG_MTD_PARTITIONS
6023 + struct mtd_partition *mtd_parts = 0;
6024 + int mtd_parts_nr = 0;
6025 +#endif
6026 +
6027 + if (nr_devices >= DATAFLASH_MAX_DEVICES) {
6028 + printk(KERN_ERR "at91_dataflash: Too many devices detected\n");
6029 + return 0;
6030 + }
6031 +
6032 + device = kmalloc(sizeof(struct mtd_info) + strlen(name) + 8, GFP_KERNEL);
6033 + if (!device)
6034 + return -ENOMEM;
6035 + memset(device, 0, sizeof(struct mtd_info));
6036 +
6037 + device->name = (char *)&device[1];
6038 + sprintf(device->name, "%s.spi%d", name, channel);
6039 + device->size = nr_pages * pagesize;
6040 + device->erasesize = pagesize;
6041 + device->writesize = pagesize;
6042 + device->owner = THIS_MODULE;
6043 + device->type = MTD_DATAFLASH;
6044 + device->flags = MTD_WRITEABLE;
6045 + device->erase = at91_dataflash_erase;
6046 + device->read = at91_dataflash_read;
6047 + device->write = at91_dataflash_write;
6048 +
6049 + priv = (struct dataflash_local *) kmalloc(sizeof(struct dataflash_local), GFP_KERNEL);
6050 + if (!priv) {
6051 + kfree(device);
6052 + return -ENOMEM;
6053 + }
6054 + memset(priv, 0, sizeof(struct dataflash_local));
6055 +
6056 + priv->spi = channel;
6057 + priv->page_size = pagesize;
6058 + priv->page_offset = pageoffset;
6059 + device->priv = priv;
6060 +
6061 + mtd_devices[nr_devices] = device;
6062 + nr_devices++;
6063 + printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size);
6064 +
6065 +#ifdef CONFIG_MTD_PARTITIONS
6066 +#ifdef CONFIG_MTD_CMDLINE_PARTS
6067 + mtd_parts_nr = parse_mtd_partitions(device, part_probes, &mtd_parts, 0);
6068 +#endif
6069 + if (mtd_parts_nr <= 0) {
6070 + switch (IDsize) {
6071 + case SZ_2M:
6072 + mtd_parts = static_partitions_2M;
6073 + mtd_parts_nr = ARRAY_SIZE(static_partitions_2M);
6074 + break;
6075 + case SZ_4M:
6076 + mtd_parts = static_partitions_4M;
6077 + mtd_parts_nr = ARRAY_SIZE(static_partitions_4M);
6078 + break;
6079 + case SZ_8M:
6080 + mtd_parts = static_partitions_8M;
6081 + mtd_parts_nr = ARRAY_SIZE(static_partitions_8M);
6082 + break;
6083 + }
6084 + }
6085 +
6086 + if (mtd_parts_nr > 0) {
6087 +#ifdef DATAFLASH_ALWAYS_ADD_DEVICE
6088 + add_mtd_device(device);
6089 +#endif
6090 + return add_mtd_partitions(device, mtd_parts, mtd_parts_nr);
6091 + }
6092 +#endif
6093 + return add_mtd_device(device); /* add whole device */
6094 +}
6095 +
6096 +/*
6097 + * Detect and initialize DataFlash device connected to specified SPI channel.
6098 + *
6099 + * Device Density ID code Nr Pages Page Size Page offset
6100 + * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
6101 + * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1025 264 9
6102 + * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
6103 + * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
6104 + * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
6105 + * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
6106 + * AT45DB0642 64Mbit (8M) xx1111xx (0x3c) 8192 1056 11
6107 + * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
6108 + */
6109 +static int __init at91_dataflash_detect(int channel)
6110 +{
6111 + int res = 0;
6112 + unsigned short status;
6113 +
6114 + spi_access_bus(channel);
6115 + status = at91_dataflash_status();
6116 + spi_release_bus(channel);
6117 + if (status != 0xff) { /* no dataflash device there */
6118 + switch (status & 0x3c) {
6119 + case 0x0c: /* 0 0 1 1 */
6120 + res = add_dataflash(channel, "AT45DB011B", SZ_128K, 512, 264, 9);
6121 + break;
6122 + case 0x14: /* 0 1 0 1 */
6123 + res = add_dataflash(channel, "AT45DB021B", SZ_256K, 1025, 264, 9);
6124 + break;
6125 + case 0x1c: /* 0 1 1 1 */
6126 + res = add_dataflash(channel, "AT45DB041B", SZ_512K, 2048, 264, 9);
6127 + break;
6128 + case 0x24: /* 1 0 0 1 */
6129 + res = add_dataflash(channel, "AT45DB081B", SZ_1M, 4096, 264, 9);
6130 + break;
6131 + case 0x2c: /* 1 0 1 1 */
6132 + res = add_dataflash(channel, "AT45DB161B", SZ_2M, 4096, 528, 10);
6133 + break;
6134 + case 0x34: /* 1 1 0 1 */
6135 + res = add_dataflash(channel, "AT45DB321B", SZ_4M, 8192, 528, 10);
6136 + break;
6137 + case 0x3c: /* 1 1 1 1 */
6138 + res = add_dataflash(channel, "AT45DB642", SZ_8M, 8192, 1056, 11);
6139 + break;
6140 +// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands.
6141 +// case 0x10: /* 0 1 0 0 */
6142 +// res = add_dataflash(channel, "AT45DB1282", SZ_16M, 16384, 1056, 11);
6143 +// break;
6144 + default:
6145 + printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c);
6146 + }
6147 + }
6148 +
6149 + return res;
6150 +}
6151 +
6152 +static int __init at91_dataflash_init(void)
6153 +{
6154 + spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
6155 + if (!spi_transfer_desc)
6156 + return -ENOMEM;
6157 +
6158 + /* DataFlash (SPI chip select 0) */
6159 + at91_dataflash_detect(0);
6160 +
6161 +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
6162 + /* DataFlash card (SPI chip select 3) */
6163 + at91_dataflash_detect(3);
6164 +#endif
6165 +
6166 + return 0;
6167 +}
6168 +
6169 +static void __exit at91_dataflash_exit(void)
6170 +{
6171 + int i;
6172 +
6173 + for (i = 0; i < DATAFLASH_MAX_DEVICES; i++) {
6174 + if (mtd_devices[i]) {
6175 +#ifdef CONFIG_MTD_PARTITIONS
6176 + del_mtd_partitions(mtd_devices[i]);
6177 +#else
6178 + del_mtd_device(mtd_devices[i]);
6179 +#endif
6180 + kfree(mtd_devices[i]->priv);
6181 + kfree(mtd_devices[i]);
6182 + }
6183 + }
6184 + nr_devices = 0;
6185 + kfree(spi_transfer_desc);
6186 +}
6187 +
6188 +
6189 +module_init(at91_dataflash_init);
6190 +module_exit(at91_dataflash_exit);
6191 +
6192 +MODULE_LICENSE("GPL");
6193 +MODULE_AUTHOR("Andrew Victor");
6194 +MODULE_DESCRIPTION("DataFlash driver for Atmel AT91RM9200");
6195 diff -urN -x CVS linux-2.6.21/drivers/mtd/nand/at91_nand.c linux-2.6-stable/drivers/mtd/nand/at91_nand.c
6196 --- linux-2.6.21/drivers/mtd/nand/at91_nand.c Thu Apr 26 05:08:32 2007
6197 +++ linux-2.6-stable/drivers/mtd/nand/at91_nand.c Tue May 8 12:13:31 2007
6198 @@ -82,6 +82,10 @@
6199 at91_set_gpio_value(host->board->enable_pin, 1);
6200 }
6201
6202 +#ifdef CONFIG_MTD_PARTITIONS
6203 +const char *part_probes[] = { "cmdlinepart", NULL };
6204 +#endif
6205 +
6206 /*
6207 * Probe for the NAND device.
6208 */
6209 @@ -151,6 +155,12 @@
6210 #ifdef CONFIG_MTD_PARTITIONS
6211 if (host->board->partition_info)
6212 partitions = host->board->partition_info(mtd->size, &num_partitions);
6213 +#ifdef CONFIG_MTD_CMDLINE_PARTS
6214 + else {
6215 + mtd->name = "at91_nand";
6216 + num_partitions = parse_mtd_partitions(mtd, part_probes, &partitions, 0);
6217 + }
6218 +#endif
6219
6220 if ((!partitions) || (num_partitions == 0)) {
6221 printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n");
6222 diff -urN -x CVS linux-2.6.21/drivers/net/arm/at91_ether.c linux-2.6-stable/drivers/net/arm/at91_ether.c
6223 --- linux-2.6.21/drivers/net/arm/at91_ether.c Thu Apr 26 05:08:32 2007
6224 +++ linux-2.6-stable/drivers/net/arm/at91_ether.c Tue May 8 12:13:31 2007
6225 @@ -225,6 +225,16 @@
6226 if (!(phy & ((1 << 2) | 1)))
6227 goto done;
6228 }
6229 + else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
6230 + read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
6231 + if (!(phy & ((1 << 2) | 1)))
6232 + goto done;
6233 + }
6234 + else if (lp->phy_type == MII_DP83848_ID) {
6235 + read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
6236 + if (!(phy & (1 << 7)))
6237 + goto done;
6238 + }
6239
6240 update_linkspeed(dev, 0);
6241
6242 @@ -280,6 +290,19 @@
6243 dsintr = (1 << 10) | ( 1 << 8);
6244 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
6245 }
6246 + else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
6247 + read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
6248 + dsintr = dsintr | 0x500; /* set bits 8, 10 */
6249 + write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
6250 + }
6251 + else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
6252 + read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
6253 + dsintr = dsintr | 0x3c; /* set bits 2..5 */
6254 + write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
6255 + read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
6256 + dsintr = dsintr | 0x3; /* set bits 0,1 */
6257 + write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
6258 + }
6259
6260 disable_mdi();
6261 spin_unlock_irq(&lp->lock);
6262 @@ -323,6 +346,19 @@
6263 dsintr = ~((1 << 10) | (1 << 8));
6264 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
6265 }
6266 + else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
6267 + read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
6268 + dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
6269 + write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
6270 + }
6271 + else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
6272 + read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
6273 + dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
6274 + write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
6275 + read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
6276 + dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
6277 + write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
6278 + }
6279
6280 disable_mdi();
6281 spin_unlock_irq(&lp->lock);
6282 @@ -535,8 +571,8 @@
6283 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
6284 }
6285
6286 - at91_emac_write(AT91_EMAC_HSH, mc_filter[0]);
6287 - at91_emac_write(AT91_EMAC_HSL, mc_filter[1]);
6288 + at91_emac_write(AT91_EMAC_HSL, mc_filter[0]);
6289 + at91_emac_write(AT91_EMAC_HSH, mc_filter[1]);
6290 }
6291
6292 /*
6293 @@ -943,14 +979,22 @@
6294 struct net_device *dev;
6295 struct at91_private *lp;
6296 unsigned int val;
6297 - int res;
6298 + struct resource *res;
6299 + int ret;
6300
6301 dev = alloc_etherdev(sizeof(struct at91_private));
6302 if (!dev)
6303 return -ENOMEM;
6304
6305 - dev->base_addr = AT91_VA_BASE_EMAC;
6306 - dev->irq = AT91RM9200_ID_EMAC;
6307 + /* Get I/O base address and IRQ */
6308 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6309 + if (!res) {
6310 + free_netdev(dev);
6311 + return -ENODEV;
6312 + }
6313 + dev->base_addr = res->start;
6314 + dev->irq = platform_get_irq(pdev, 0);
6315 +
6316 SET_MODULE_OWNER(dev);
6317
6318 /* Install the interrupt handler */
6319 @@ -1023,12 +1067,12 @@
6320 lp->phy_address = phy_address; /* MDI address of PHY */
6321
6322 /* Register the network interface */
6323 - res = register_netdev(dev);
6324 - if (res) {
6325 + ret = register_netdev(dev);
6326 + if (ret) {
6327 free_irq(dev->irq, dev);
6328 free_netdev(dev);
6329 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
6330 - return res;
6331 + return ret;
6332 }
6333
6334 /* Determine current link speed */
6335 @@ -1063,10 +1107,16 @@
6336 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
6337 else if (phy_type == MII_DP83847_ID)
6338 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
6339 + else if (phy_type == MII_DP83848_ID)
6340 + printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
6341 else if (phy_type == MII_AC101L_ID)
6342 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
6343 else if (phy_type == MII_KS8721_ID)
6344 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
6345 + else if (phy_type == MII_T78Q21x3_ID)
6346 + printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
6347 + else if (phy_type == MII_LAN83C185_ID)
6348 + printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
6349
6350 return 0;
6351 }
6352 @@ -1104,8 +1154,11 @@
6353 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
6354 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
6355 case MII_DP83847_ID: /* National Semiconductor DP83847: */
6356 + case MII_DP83848_ID: /* National Semiconductor DP83848: */
6357 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
6358 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
6359 + case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
6360 + case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
6361 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
6362 break;
6363 }
6364 diff -urN -x CVS linux-2.6.21/drivers/net/arm/at91_ether.h linux-2.6-stable/drivers/net/arm/at91_ether.h
6365 --- linux-2.6.21/drivers/net/arm/at91_ether.h Thu Apr 26 05:08:32 2007
6366 +++ linux-2.6-stable/drivers/net/arm/at91_ether.h Tue May 8 12:13:31 2007
6367 @@ -17,39 +17,46 @@
6368
6369
6370 /* Davicom 9161 PHY */
6371 -#define MII_DM9161_ID 0x0181b880
6372 -#define MII_DM9161A_ID 0x0181b8a0
6373 -
6374 -/* Davicom specific registers */
6375 -#define MII_DSCR_REG 16
6376 -#define MII_DSCSR_REG 17
6377 -#define MII_DSINTR_REG 21
6378 +#define MII_DM9161_ID 0x0181b880
6379 +#define MII_DM9161A_ID 0x0181b8a0
6380 +#define MII_DSCR_REG 16
6381 +#define MII_DSCSR_REG 17
6382 +#define MII_DSINTR_REG 21
6383
6384 /* Intel LXT971A PHY */
6385 -#define MII_LXT971A_ID 0x001378E0
6386 -
6387 -/* Intel specific registers */
6388 -#define MII_ISINTE_REG 18
6389 -#define MII_ISINTS_REG 19
6390 -#define MII_LEDCTRL_REG 20
6391 +#define MII_LXT971A_ID 0x001378E0
6392 +#define MII_ISINTE_REG 18
6393 +#define MII_ISINTS_REG 19
6394 +#define MII_LEDCTRL_REG 20
6395
6396 /* Realtek RTL8201 PHY */
6397 -#define MII_RTL8201_ID 0x00008200
6398 +#define MII_RTL8201_ID 0x00008200
6399
6400 /* Broadcom BCM5221 PHY */
6401 -#define MII_BCM5221_ID 0x004061e0
6402 -
6403 -/* Broadcom specific registers */
6404 -#define MII_BCMINTR_REG 26
6405 +#define MII_BCM5221_ID 0x004061e0
6406 +#define MII_BCMINTR_REG 26
6407
6408 /* National Semiconductor DP83847 */
6409 -#define MII_DP83847_ID 0x20005c30
6410 +#define MII_DP83847_ID 0x20005c30
6411 +
6412 +/* National Semiconductor DP83848 */
6413 +#define MII_DP83848_ID 0x20005c90
6414 +#define MII_DPPHYSTS_REG 16
6415 +#define MII_DPMICR_REG 17
6416 +#define MII_DPMISR_REG 18
6417
6418 /* Altima AC101L PHY */
6419 -#define MII_AC101L_ID 0x00225520
6420 +#define MII_AC101L_ID 0x00225520
6421
6422 /* Micrel KS8721 PHY */
6423 -#define MII_KS8721_ID 0x00221610
6424 +#define MII_KS8721_ID 0x00221610
6425 +
6426 +/* Teridian 78Q2123/78Q2133 */
6427 +#define MII_T78Q21x3_ID 0x000e7230
6428 +#define MII_T78Q21INT_REG 17
6429 +
6430 +/* SMSC LAN83C185 */
6431 +#define MII_LAN83C185_ID 0x0007C0A0
6432
6433 /* ........................................................................ */
6434
6435 diff -urN -x CVS linux-2.6.21/drivers/pcmcia/at91_cf.c linux-2.6-stable/drivers/pcmcia/at91_cf.c
6436 --- linux-2.6.21/drivers/pcmcia/at91_cf.c Thu Apr 26 05:08:32 2007
6437 +++ linux-2.6-stable/drivers/pcmcia/at91_cf.c Tue May 8 12:13:31 2007
6438 @@ -332,20 +332,27 @@
6439 struct at91_cf_data *board = cf->board;
6440
6441 pcmcia_socket_dev_suspend(&pdev->dev, mesg);
6442 +
6443 if (device_may_wakeup(&pdev->dev)) {
6444 enable_irq_wake(board->det_pin);
6445 if (board->irq_pin)
6446 enable_irq_wake(board->irq_pin);
6447 - } else {
6448 - disable_irq_wake(board->det_pin);
6449 - if (board->irq_pin)
6450 - disable_irq_wake(board->irq_pin);
6451 }
6452 +
6453 return 0;
6454 }
6455
6456 static int at91_cf_resume(struct platform_device *pdev)
6457 {
6458 + struct at91_cf_socket *cf = platform_get_drvdata(pdev);
6459 + struct at91_cf_data *board = cf->board;
6460 +
6461 + if (device_may_wakeup(&pdev->dev)) {
6462 + disable_irq_wake(board->det_pin);
6463 + if (board->irq_pin)
6464 + disable_irq_wake(board->irq_pin);
6465 + }
6466 +
6467 pcmcia_socket_dev_resume(&pdev->dev);
6468 return 0;
6469 }
6470 @@ -360,7 +367,6 @@
6471 .name = (char *) driver_name,
6472 .owner = THIS_MODULE,
6473 },
6474 - .probe = at91_cf_probe,
6475 .remove = __exit_p(at91_cf_remove),
6476 .suspend = at91_cf_suspend,
6477 .resume = at91_cf_resume,
6478 @@ -370,7 +376,7 @@
6479
6480 static int __init at91_cf_init(void)
6481 {
6482 - return platform_driver_register(&at91_cf_driver);
6483 + return platform_driver_probe(&at91_cf_driver, at91_cf_probe);
6484 }
6485 module_init(at91_cf_init);
6486
6487 diff -urN -x CVS linux-2.6.21/drivers/serial/atmel_serial.c linux-2.6-stable/drivers/serial/atmel_serial.c
6488 --- linux-2.6.21/drivers/serial/atmel_serial.c Thu Apr 26 05:08:32 2007
6489 +++ linux-2.6-stable/drivers/serial/atmel_serial.c Tue May 8 12:13:31 2007
6490 @@ -7,6 +7,8 @@
6491 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6492 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6493 *
6494 + * DMA support added by Chip Coldwell.
6495 + *
6496 * This program is free software; you can redistribute it and/or modify
6497 * it under the terms of the GNU General Public License as published by
6498 * the Free Software Foundation; either version 2 of the License, or
6499 @@ -33,6 +35,7 @@
6500 #include <linux/sysrq.h>
6501 #include <linux/tty_flip.h>
6502 #include <linux/platform_device.h>
6503 +#include <linux/dma-mapping.h>
6504 #include <linux/atmel_pdc.h>
6505
6506 #include <asm/io.h>
6507 @@ -47,6 +50,11 @@
6508
6509 #include "atmel_serial.h"
6510
6511 +#define SUPPORT_PDC
6512 +#define PDC_BUFFER_SIZE (L1_CACHE_BYTES << 3)
6513 +#warning "Revisit"
6514 +#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
6515 +
6516 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6517 #define SUPPORT_SYSRQ
6518 #endif
6519 @@ -107,6 +115,13 @@
6520 static int (*atmel_open_hook)(struct uart_port *);
6521 static void (*atmel_close_hook)(struct uart_port *);
6522
6523 +struct atmel_dma_buffer {
6524 + unsigned char *buf;
6525 + dma_addr_t dma_addr;
6526 + size_t dma_size;
6527 + unsigned int ofs;
6528 +};
6529 +
6530 /*
6531 * We wrap our port structure around the generic uart_port.
6532 */
6533 @@ -114,10 +129,20 @@
6534 struct uart_port uart; /* uart */
6535 struct clk *clk; /* uart clock */
6536 unsigned short suspended; /* is port suspended? */
6537 +
6538 + short use_dma_rx; /* enable PDC receiver */
6539 + short pdc_rx_idx; /* current PDC RX buffer */
6540 + struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
6541 +
6542 + short use_dma_tx; /* enable PDC transmitter */
6543 + struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
6544 };
6545
6546 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
6547
6548 +#define PDC_RX_BUF(port) &(port)->pdc_rx[(port)->pdc_rx_idx]
6549 +#define PDC_RX_SWITCH(port) (port)->pdc_rx_idx = !(port)->pdc_rx_idx
6550 +
6551 #ifdef SUPPORT_SYSRQ
6552 static struct console atmel_console;
6553 #endif
6554 @@ -205,7 +230,12 @@
6555 {
6556 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6557
6558 - UART_PUT_IDR(port, ATMEL_US_TXRDY);
6559 + if (atmel_port->use_dma_tx) {
6560 + UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */
6561 + UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
6562 + }
6563 + else
6564 + UART_PUT_IDR(port, ATMEL_US_TXRDY);
6565 }
6566
6567 /*
6568 @@ -215,7 +245,17 @@
6569 {
6570 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6571
6572 - UART_PUT_IER(port, ATMEL_US_TXRDY);
6573 + if (atmel_port->use_dma_tx) {
6574 + if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
6575 + /* The transmitter is already running. Yes, we
6576 + really need this.*/
6577 + return;
6578 +
6579 + UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
6580 + UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); /* re-enable PDC transmit */
6581 + }
6582 + else
6583 + UART_PUT_IER(port, ATMEL_US_TXRDY);
6584 }
6585
6586 /*
6587 @@ -225,7 +265,12 @@
6588 {
6589 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6590
6591 - UART_PUT_IDR(port, ATMEL_US_RXRDY);
6592 + if (atmel_port->use_dma_rx) {
6593 + UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS); /* disable PDC receive */
6594 + UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
6595 + }
6596 + else
6597 + UART_PUT_IDR(port, ATMEL_US_RXRDY);
6598 }
6599
6600 /*
6601 @@ -248,6 +293,134 @@
6602 }
6603
6604 /*
6605 + * Receive data via the PDC. A buffer has been fulled.
6606 + */
6607 +static void atmel_pdc_endrx(struct uart_port *port)
6608 +{
6609 + struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6610 + struct tty_struct *tty = port->info->tty;
6611 + struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port);
6612 + unsigned int count;
6613 +
6614 + count = pdc->dma_size - pdc->ofs;
6615 + if (likely(count > 0)) {
6616 + dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
6617 + tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
6618 + tty_flip_buffer_push(tty);
6619 +
6620 + port->icount.rx += count;
6621 + }
6622 +
6623 + /* Set this buffer as the next receive buffer */
6624 + pdc->ofs = 0;
6625 + UART_PUT_RNPR(port, pdc->dma_addr);
6626 + UART_PUT_RNCR(port, pdc->dma_size);
6627 +
6628 + /* Switch to next buffer */
6629 + PDC_RX_SWITCH(atmel_port); /* next PDC buffer */
6630 +}
6631 +
6632 +/*
6633 + * Receive data via the PDC. At least one byte was received, but the
6634 + * buffer was not full when the inter-character timeout expired.
6635 + */
6636 +static void atmel_pdc_timeout(struct uart_port *port)
6637 +{
6638 + struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6639 + struct tty_struct *tty = port->info->tty;
6640 + struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port);
6641 + /* unsigned */ int ofs, count;
6642 +
6643 + ofs = UART_GET_RPR(port) - pdc->dma_addr; /* current DMA adress */
6644 + count = ofs - pdc->ofs;
6645 +
6646 + if (likely(count > 0)) {
6647 + dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
6648 + tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
6649 + tty_flip_buffer_push(tty);
6650 +
6651 + pdc->ofs = ofs;
6652 + port->icount.rx += count;
6653 + }
6654 +
6655 + /* reset the UART timeout */
6656 + UART_PUT_CR(port, ATMEL_US_STTTO);
6657 +}
6658 +
6659 +/*
6660 + * Deal with parity, framing and overrun errors.
6661 + */
6662 +static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
6663 +{
6664 + /* clear error */
6665 + UART_PUT_CR(port, ATMEL_US_RSTSTA);
6666 +
6667 + if (status & ATMEL_US_RXBRK) {
6668 + status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
6669 + port->icount.brk++;
6670 + }
6671 + if (status & ATMEL_US_PARE)
6672 + port->icount.parity++;
6673 + if (status & ATMEL_US_FRAME)
6674 + port->icount.frame++;
6675 + if (status & ATMEL_US_OVRE)
6676 + port->icount.overrun++;
6677 +}
6678 +
6679 +/*
6680 + * A transmission via the PDC is complete.
6681 + */
6682 +static void atmel_pdc_endtx(struct uart_port *port)
6683 +{
6684 + struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6685 + struct circ_buf *xmit = &port->info->xmit;
6686 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
6687 +
6688 + xmit->tail += pdc->ofs;
6689 + if (xmit->tail >= SERIAL_XMIT_SIZE)
6690 + xmit->tail -= SERIAL_XMIT_SIZE;
6691 +
6692 + port->icount.tx += pdc->ofs;
6693 + pdc->ofs = 0;
6694 +
6695 + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
6696 + uart_write_wakeup(port);
6697 +}
6698 +
6699 +/*
6700 + * The PDC transmitter is idle, so either start the next transfer or
6701 + * disable the transmitter.
6702 + */
6703 +static void atmel_pdc_txbufe(struct uart_port *port)
6704 +{
6705 + struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6706 + struct circ_buf *xmit = &port->info->xmit;
6707 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
6708 + int count;
6709 +
6710 + if (!uart_circ_empty(xmit)) {
6711 + /* more to transmit - setup next transfer */
6712 + UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */
6713 + dma_sync_single_for_device(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE);
6714 +
6715 + if (xmit->tail < xmit->head)
6716 + count = xmit->head - xmit->tail;
6717 + else
6718 + count = SERIAL_XMIT_SIZE - xmit->tail;
6719 + pdc->ofs = count;
6720 +
6721 + UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
6722 + UART_PUT_TCR(port, count);
6723 + UART_PUT_PTCR(port, ATMEL_PDC_TXTEN); /* re-enable PDC transmit */
6724 + }
6725 + else {
6726 + /* nothing left to transmit - disable the transmitter */
6727 + UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS); /* disable PDC transmit */
6728 + UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
6729 + }
6730 +}
6731 +
6732 +/*
6733 * Characters received (called from interrupt handler)
6734 */
6735 static void atmel_rx_chars(struct uart_port *port)
6736 @@ -349,6 +522,14 @@
6737 status = UART_GET_CSR(port);
6738 pending = status & UART_GET_IMR(port);
6739 while (pending) {
6740 + /* PDC receive */
6741 + if (pending & ATMEL_US_ENDRX)
6742 + atmel_pdc_endrx(port);
6743 + if (pending & ATMEL_US_TIMEOUT)
6744 + atmel_pdc_timeout(port);
6745 + if (atmel_port->use_dma_rx && pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | ATMEL_US_FRAME | ATMEL_US_PARE))
6746 + atmel_pdc_rxerr(port, pending);
6747 +
6748 /* Interrupt receive */
6749 if (pending & ATMEL_US_RXRDY)
6750 atmel_rx_chars(port);
6751 @@ -363,6 +544,12 @@
6752 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
6753 wake_up_interruptible(&port->info->delta_msr_wait);
6754
6755 + /* PDC transmit */
6756 + if (pending & ATMEL_US_ENDTX)
6757 + atmel_pdc_endtx(port);
6758 + if (pending & ATMEL_US_TXBUFE)
6759 + atmel_pdc_txbufe(port);
6760 +
6761 /* Interrupt transmit */
6762 if (pending & ATMEL_US_TXRDY)
6763 atmel_tx_chars(port);
6764 @@ -401,6 +588,47 @@
6765 }
6766
6767 /*
6768 + * Initialize DMA (if necessary)
6769 + */
6770 + if (atmel_port->use_dma_rx) {
6771 + int i;
6772 +
6773 + for (i = 0; i < 2; i++) {
6774 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
6775 +
6776 + pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
6777 + if (pdc->buf == NULL) {
6778 + if (i != 0) {
6779 + dma_unmap_single(port->dev, atmel_port->pdc_rx[0].dma_addr, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
6780 + kfree(atmel_port->pdc_rx[0].buf);
6781 + }
6782 + free_irq(port->irq, port);
6783 + return -ENOMEM;
6784 + }
6785 + pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
6786 + pdc->dma_size = PDC_BUFFER_SIZE;
6787 + pdc->ofs = 0;
6788 + }
6789 +
6790 + atmel_port->pdc_rx_idx = 0;
6791 +
6792 + UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
6793 + UART_PUT_RCR(port, PDC_BUFFER_SIZE);
6794 +
6795 + UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
6796 + UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
6797 + }
6798 + if (atmel_port->use_dma_tx) {
6799 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
6800 + struct circ_buf *xmit = &port->info->xmit;
6801 +
6802 + pdc->buf = xmit->buf;
6803 + pdc->dma_addr = dma_map_single(port->dev, pdc->buf, SERIAL_XMIT_SIZE, DMA_TO_DEVICE);
6804 + pdc->dma_size = SERIAL_XMIT_SIZE;
6805 + pdc->ofs = 0;
6806 + }
6807 +
6808 + /*
6809 * If there is a specific "open" function (to register
6810 * control line interrupts)
6811 */
6812 @@ -418,7 +646,15 @@
6813 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
6814 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */
6815
6816 - UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
6817 + if (atmel_port->use_dma_rx) {
6818 + UART_PUT_RTOR(port, PDC_RX_TIMEOUT); /* set UART timeout */
6819 + UART_PUT_CR(port, ATMEL_US_STTTO);
6820 +
6821 + UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
6822 + UART_PUT_PTCR(port, ATMEL_PDC_RXTEN); /* enable PDC controller */
6823 + }
6824 + else
6825 + UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
6826
6827 return 0;
6828 }
6829 @@ -431,6 +667,31 @@
6830 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6831
6832 /*
6833 + * Ensure everything is stopped.
6834 + */
6835 + atmel_stop_rx(port);
6836 + atmel_stop_tx(port);
6837 +
6838 + /*
6839 + * Shut-down the DMA.
6840 + */
6841 + if (atmel_port->use_dma_rx) {
6842 + int i;
6843 +
6844 + for (i = 0; i < 2; i++) {
6845 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
6846 +
6847 + dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
6848 + kfree(pdc->buf);
6849 + }
6850 + }
6851 + if (atmel_port->use_dma_tx) {
6852 + struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
6853 +
6854 + dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE);
6855 + }
6856 +
6857 + /*
6858 * Disable all interrupts, port and break condition.
6859 */
6860 UART_PUT_CR(port, ATMEL_US_RSTSTA);
6861 @@ -481,14 +742,20 @@
6862 */
6863 static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old)
6864 {
6865 + struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6866 unsigned long flags;
6867 unsigned int mode, imr, quot, baud;
6868
6869 + /* Get current mode register */
6870 + mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
6871 +
6872 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
6873 quot = uart_get_divisor(port, baud);
6874
6875 - /* Get current mode register */
6876 - mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
6877 + if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
6878 + quot /= 8;
6879 + mode |= ATMEL_US_USCLKS_MCK_DIV8;
6880 + }
6881
6882 /* byte size */
6883 switch (termios->c_cflag & CSIZE) {
6884 @@ -534,6 +801,9 @@
6885 if (termios->c_iflag & (BRKINT | PARMRK))
6886 port->read_status_mask |= ATMEL_US_RXBRK;
6887
6888 + if (atmel_port->use_dma_rx) /* need to enable error interrupts */
6889 + UART_PUT_IER(port, port->read_status_mask);
6890 +
6891 /*
6892 * Characters to ignore
6893 */
6894 @@ -712,6 +982,13 @@
6895 clk_enable(atmel_port->clk);
6896 port->uartclk = clk_get_rate(atmel_port->clk);
6897 }
6898 +
6899 +#ifdef SUPPORT_PDC
6900 + atmel_port->use_dma_rx = data->use_dma_rx;
6901 + atmel_port->use_dma_tx = data->use_dma_tx;
6902 + if (atmel_port->use_dma_tx)
6903 + port->fifosize = PDC_BUFFER_SIZE;
6904 +#endif
6905 }
6906
6907 /*
6908 @@ -888,7 +1165,8 @@
6909 struct uart_port *port = platform_get_drvdata(pdev);
6910 struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6911
6912 - if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
6913 + if (device_may_wakeup(&pdev->dev)
6914 + && !clk_must_disable(atmel_port->clk))
6915 enable_irq_wake(port->irq);
6916 else {
6917 uart_suspend_port(&atmel_uart, port);
6918 diff -urN -x CVS linux-2.6.21/drivers/serial/atmel_serial.h linux-2.6-stable/drivers/serial/atmel_serial.h
6919 --- linux-2.6.21/drivers/serial/atmel_serial.h Thu Apr 26 05:08:32 2007
6920 +++ linux-2.6-stable/drivers/serial/atmel_serial.h Tue May 8 12:13:31 2007
6921 @@ -46,6 +46,9 @@
6922 #define ATMEL_US_USMODE_ISO7816_T1 6
6923 #define ATMEL_US_USMODE_IRDA 8
6924 #define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
6925 +#define ATMEL_US_USCLKS_MCK (0 << 4)
6926 +#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
6927 +#define ATMEL_US_USCLKS_SCK (3 << 4)
6928 #define ATMEL_US_CHRL (3 << 6) /* Character Length */
6929 #define ATMEL_US_CHRL_5 (0 << 6)
6930 #define ATMEL_US_CHRL_6 (1 << 6)
6931 diff -urN -x CVS linux-2.6.21/drivers/spi/Kconfig linux-2.6-stable/drivers/spi/Kconfig
6932 --- linux-2.6.21/drivers/spi/Kconfig Thu Apr 26 05:08:32 2007
6933 +++ linux-2.6-stable/drivers/spi/Kconfig Tue May 8 14:31:24 2007
6934 @@ -54,6 +54,7 @@
6935 config SPI_ATMEL
6936 tristate "Atmel SPI Controller"
6937 depends on (ARCH_AT91 || AVR32) && SPI_MASTER
6938 + select SPI_AT91_MANUAL_CS if ARCH_AT91RM9200
6939 help
6940 This selects a driver for the Atmel SPI Controller, present on
6941 many AT32 (AVR32) and AT91 (ARM) chips.
6942 @@ -82,6 +83,24 @@
6943 inexpensive battery powered microcontroller evaluation board.
6944 This same cable can be used to flash new firmware.
6945
6946 +config SPI_AT91
6947 + tristate "AT91RM9200 Bitbang SPI Master"
6948 + depends on SPI_MASTER && ARCH_AT91RM9200 && !SPI_ATMEL && EXPERIMENTAL
6949 + select SPI_BITBANG
6950 + select SPI_AT91_MANUAL_CS
6951 + help
6952 + This is dumb PIO bitbanging driver for the Atmel AT91RM9200.
6953 + The SPI_ATMEL driver will be its replacement, using the native
6954 + SPI hardware and its DMA controller.
6955 +
6956 +config SPI_AT91_MANUAL_CS
6957 + bool
6958 + depends on ARCH_AT91RM9200
6959 + help
6960 + Works around an AT91RM9200 problem whereby the SPI chip-select
6961 + will be wrongly disabled. The workaround uses those pins as
6962 + GPIOs instead of letting the SPI controller manage them.
6963 +
6964 config SPI_IMX
6965 tristate "Freescale iMX SPI controller"
6966 depends on SPI_MASTER && ARCH_IMX && EXPERIMENTAL
6967 diff -urN -x CVS linux-2.6.21/drivers/spi/Makefile linux-2.6-stable/drivers/spi/Makefile
6968 --- linux-2.6.21/drivers/spi/Makefile Thu Apr 26 05:08:32 2007
6969 +++ linux-2.6-stable/drivers/spi/Makefile Tue May 8 14:31:24 2007
6970 @@ -20,6 +20,7 @@
6971 obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o
6972 obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
6973 obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
6974 +obj-$(CONFIG_SPI_AT91) += spi_at91_bitbang.o
6975 # ... add above this line ...
6976
6977 # SPI protocol drivers (device/link on bus)
6978 diff -urN -x CVS linux-2.6.21/drivers/spi/spi_at91_bitbang.c linux-2.6-stable/drivers/spi/spi_at91_bitbang.c
6979 --- linux-2.6.21/drivers/spi/spi_at91_bitbang.c Thu Jan 1 02:00:00 1970
6980 +++ linux-2.6-stable/drivers/spi/spi_at91_bitbang.c Tue May 8 14:31:24 2007
6981 @@ -0,0 +1,207 @@
6982 +/*
6983 + * at91_spi.c - at91 SPI driver (BOOTSTRAP/BITBANG VERSION)
6984 + *
6985 + * Copyright (C) 2006 David Brownell
6986 + *
6987 + * This program is free software; you can redistribute it and/or modify
6988 + * it under the terms of the GNU General Public License as published by
6989 + * the Free Software Foundation; either version 2 of the License, or
6990 + * (at your option) any later version.
6991 + *
6992 + * This program is distributed in the hope that it will be useful,
6993 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6994 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6995 + * GNU General Public License for more details.
6996 + *
6997 + * You should have received a copy of the GNU General Public License
6998 + * along with this program; if not, write to the Free Software
6999 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
7000 + */
7001 +#include <linux/kernel.h>
7002 +#include <linux/init.h>
7003 +#include <linux/platform_device.h>
7004 +
7005 +#include <linux/spi/spi.h>
7006 +#include <linux/spi/spi_bitbang.h>
7007 +
7008 +#include <asm/arch/gpio.h>
7009 +
7010 +
7011 +/*
7012 + * FIXME this bitbanging version is just to help bootstrap systems until
7013 + * there's a native SPI+IRQ+DMA controller driver ... such a driver should
7014 + * be a drop-in replacement for this one, and much faster.
7015 + *
7016 + * remember:
7017 + *
7018 + * - other at91 parts (like at91sam9) have multiple controllers
7019 + * and different pin muxing; this version is at91rm9200 specfic.
7020 + *
7021 + * - at91sam9261 SPI0 pins are directly muxed with MMC/SD pins.
7022 + *
7023 + * - rm9200 spi chipselects drop wrongly, so the native driver
7024 + * will need to use gpios much like this does.
7025 + *
7026 + * - real hardware only allows 8..16 bits per word, while this
7027 + * bitbanger allows 1..32 (incompatible superset).
7028 + *
7029 + * - this disregards clock parameters. with inlined gpio calls,
7030 + * gcc 3.4.4 produces about 1.5 mbit/sec, more than 2x faster
7031 + * than using the subroutined veresion from txrx_word().
7032 + *
7033 + * - suspend/resume and <linux/clk.h> support is missing ...
7034 + */
7035 +
7036 +#define spi_miso_bit AT91_PIN_PA0
7037 +#define spi_mosi_bit AT91_PIN_PA1
7038 +#define spi_sck_bit AT91_PIN_PA2
7039 +
7040 +struct at91_spi {
7041 + struct spi_bitbang bitbang;
7042 + struct platform_device *pdev;
7043 +};
7044 +
7045 +/*----------------------------------------------------------------------*/
7046 +
7047 +static inline void setsck(struct spi_device *spi, int is_on)
7048 +{
7049 + at91_set_gpio_value(spi_sck_bit, is_on);
7050 +}
7051 +
7052 +static inline void setmosi(struct spi_device *spi, int is_on)
7053 +{
7054 + at91_set_gpio_value(spi_mosi_bit, is_on);
7055 +}
7056 +
7057 +static inline int getmiso(struct spi_device *spi)
7058 +{
7059 + return at91_get_gpio_value(spi_miso_bit);
7060 +}
7061 +
7062 +static void at91_spi_chipselect(struct spi_device *spi, int is_active)
7063 +{
7064 + unsigned long cs = (unsigned long) spi->controller_data;
7065 +
7066 + /* set default clock polarity */
7067 + if (is_active)
7068 + setsck(spi, spi->mode & SPI_CPOL);
7069 +
7070 + /* only support active-low (default) */
7071 + at91_set_gpio_value(cs, !is_active);
7072 +}
7073 +
7074 +/*
7075 + * NOTE: this is "as fast as we can"; it should be a function of
7076 + * the device clock ...
7077 + */
7078 +#define spidelay(X) do{} while(0)
7079 +
7080 +#define EXPAND_BITBANG_TXRX
7081 +#include <linux/spi/spi_bitbang.h>
7082 +
7083 +static u32 at91_spi_txrx_word_mode0(struct spi_device *spi,
7084 + unsigned nsecs, u32 word, u8 bits)
7085 +{
7086 + return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, 8);
7087 +}
7088 +
7089 +static u32 at91_spi_txrx_word_mode1(struct spi_device *spi,
7090 + unsigned nsecs, u32 word, u8 bits)
7091 +{
7092 + return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, 8);
7093 +}
7094 +
7095 +static u32 at91_spi_txrx_word_mode2(struct spi_device *spi,
7096 + unsigned nsecs, u32 word, u8 bits)
7097 +{
7098 + return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, 8);
7099 +}
7100 +
7101 +static u32 at91_spi_txrx_word_mode3(struct spi_device *spi,
7102 + unsigned nsecs, u32 word, u8 bits)
7103 +{
7104 + return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, 8);
7105 +}
7106 +
7107 +/*----------------------------------------------------------------------*/
7108 +
7109 +static int __init at91_spi_probe(struct platform_device *pdev)
7110 +{
7111 + int status;
7112 + struct spi_master *master;
7113 + struct at91_spi *at91_spi;
7114 +
7115 + if (pdev->id != 0) /* SPI0 bus */
7116 + return -EINVAL;
7117 +
7118 + master = spi_alloc_master(&pdev->dev, sizeof *at91_spi);
7119 + if (!master)
7120 + return -ENOMEM;
7121 +
7122 + at91_spi = spi_master_get_devdata(master);
7123 + at91_spi->pdev = pdev;
7124 + platform_set_drvdata(pdev, at91_spi);
7125 +
7126 + /* SPI and bitbang hookup */
7127 + master->bus_num = 0;
7128 + master->num_chipselect = 4;
7129 +
7130 + at91_spi->bitbang.master = spi_master_get(master);
7131 + at91_spi->bitbang.chipselect = at91_spi_chipselect;
7132 + at91_spi->bitbang.txrx_word[SPI_MODE_0] = at91_spi_txrx_word_mode0;
7133 + at91_spi->bitbang.txrx_word[SPI_MODE_1] = at91_spi_txrx_word_mode1;
7134 + at91_spi->bitbang.txrx_word[SPI_MODE_2] = at91_spi_txrx_word_mode2;
7135 + at91_spi->bitbang.txrx_word[SPI_MODE_3] = at91_spi_txrx_word_mode3;
7136 +
7137 + status = spi_bitbang_start(&at91_spi->bitbang);
7138 + if (status < 0)
7139 + (void) spi_master_put(at91_spi->bitbang.master);
7140 +
7141 + return status;
7142 +}
7143 +
7144 +static int __exit at91_spi_remove(struct platform_device *pdev)
7145 +{
7146 + struct at91_spi *at91_spi = platform_get_drvdata(pdev);
7147 + int status;
7148 +
7149 + /* stop() unregisters child devices too */
7150 + status = spi_bitbang_stop(&at91_spi->bitbang);
7151 + (void) spi_master_put(at91_spi->bitbang.master);
7152 +
7153 + platform_set_drvdata(pdev, NULL);
7154 + return status;
7155 +}
7156 +
7157 +static struct platform_driver at91_spi_driver = {
7158 + .probe = at91_spi_probe,
7159 + .remove = __exit_p(at91_spi_remove),
7160 + .driver = {
7161 + .name = "at91_spi",
7162 + .owner = THIS_MODULE,
7163 + },
7164 +};
7165 +
7166 +static int __init at91_spi_init(void)
7167 +{
7168 + at91_set_gpio_output(spi_sck_bit, 0);
7169 + at91_set_gpio_output(spi_mosi_bit, 0);
7170 + at91_set_gpio_input(spi_miso_bit, 1 /* pullup */);
7171 +
7172 + /* register driver */
7173 + return platform_driver_register(&at91_spi_driver);
7174 +}
7175 +
7176 +static void __exit at91_spi_exit(void)
7177 +{
7178 + platform_driver_unregister(&at91_spi_driver);
7179 +}
7180 +
7181 +device_initcall(at91_spi_init);
7182 +module_exit(at91_spi_exit);
7183 +
7184 +MODULE_ALIAS("at91_spi.0");
7185 +
7186 +MODULE_DESCRIPTION("AT91 SPI support (BOOTSTRAP/BITBANG VERSION)");
7187 +MODULE_AUTHOR("David Brownell");
7188 +MODULE_LICENSE("GPL");
7189 diff -urN -x CVS linux-2.6.21/drivers/usb/gadget/Kconfig linux-2.6-stable/drivers/usb/gadget/Kconfig
7190 --- linux-2.6.21/drivers/usb/gadget/Kconfig Thu Apr 26 05:08:32 2007
7191 +++ linux-2.6-stable/drivers/usb/gadget/Kconfig Wed May 9 10:20:54 2007
7192 @@ -189,7 +189,7 @@
7193
7194 config USB_GADGET_AT91
7195 boolean "AT91 USB Device Port"
7196 - depends on ARCH_AT91
7197 + depends on ARCH_AT91 && !ARCH_AT91SAM9RL
7198 select USB_GADGET_SELECTED
7199 help
7200 Many Atmel AT91 processors (such as the AT91RM2000) have a
7201 diff -urN -x CVS linux-2.6.21/drivers/usb/gadget/at91_udc.c linux-2.6-stable/drivers/usb/gadget/at91_udc.c
7202 --- linux-2.6.21/drivers/usb/gadget/at91_udc.c Thu Apr 26 05:08:32 2007
7203 +++ linux-2.6-stable/drivers/usb/gadget/at91_udc.c Tue May 8 12:13:31 2007
7204 @@ -1804,7 +1804,7 @@
7205 */
7206 if ((!udc->suspended && udc->addr)
7207 || !wake
7208 - || at91_suspend_entering_slow_clock()) {
7209 + || clk_must_disable(udc->fclk)) {
7210 pullup(udc, 0);
7211 wake = 0;
7212 } else
7213 diff -urN -x CVS linux-2.6.21/drivers/usb/host/ohci-at91.c linux-2.6-stable/drivers/usb/host/ohci-at91.c
7214 --- linux-2.6.21/drivers/usb/host/ohci-at91.c Thu Apr 26 05:08:32 2007
7215 +++ linux-2.6-stable/drivers/usb/host/ohci-at91.c Tue May 8 12:13:31 2007
7216 @@ -299,7 +299,7 @@
7217 *
7218 * REVISIT: some boards will be able to turn VBUS off...
7219 */
7220 - if (at91_suspend_entering_slow_clock()) {
7221 + if (clk_must_disable(fclk)) {
7222 ohci_usb_reset (ohci);
7223 at91_stop_clock();
7224 }
7225 diff -urN -x CVS linux-2.6.21/drivers/video/Kconfig linux-2.6-stable/drivers/video/Kconfig
7226 --- linux-2.6.21/drivers/video/Kconfig Thu Apr 26 05:08:32 2007
7227 +++ linux-2.6-stable/drivers/video/Kconfig Thu May 10 12:34:41 2007
7228 @@ -663,6 +663,17 @@
7229 framebuffer. Product specs at
7230 <http://www.erd.epson.com/vdc/html/products.htm>.
7231
7232 +config FB_S1D15605
7233 + tristate "Epson S1D15605 framebuffer support"
7234 + depends on FB
7235 + default m if MACH_KB9200
7236 + select FB_CFB_FILLRECT
7237 + select FB_CFB_COPYAREA
7238 + select FB_CFB_IMAGEBLIT
7239 + help
7240 + Build in support for the S1D15605 Epson Research 128x64
7241 + LCD controller as a framebuffer.
7242 +
7243 config FB_S1D13XXX
7244 tristate "Epson S1D13XXX framebuffer support"
7245 depends on FB
7246 @@ -674,6 +685,22 @@
7247 working with S1D13806). Product specs at
7248 <http://www.erd.epson.com/vdc/html/legacy_13xxx.htm>
7249
7250 +config FB_ATMEL
7251 + tristate "AT91/AT32 LCD Controller support"
7252 + depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || AVR32)
7253 + select FB_CFB_FILLRECT
7254 + select FB_CFB_COPYAREA
7255 + select FB_CFB_IMAGEBLIT
7256 + help
7257 + This enables support for the AT91/AT32 LCD Controller.
7258 +
7259 +config FB_INTSRAM
7260 + bool "Frame Buffer in internal SRAM"
7261 + depends on FB_ATMEL && ARCH_AT91SAM9261
7262 + help
7263 + Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want
7264 + to let frame buffer in external SDRAM.
7265 +
7266 config FB_NVIDIA
7267 tristate "nVidia Framebuffer Support"
7268 depends on FB && PCI
7269 diff -urN -x CVS linux-2.6.21/drivers/video/Makefile linux-2.6-stable/drivers/video/Makefile
7270 --- linux-2.6.21/drivers/video/Makefile Thu Apr 26 05:08:32 2007
7271 +++ linux-2.6-stable/drivers/video/Makefile Thu May 10 12:34:01 2007
7272 @@ -75,6 +75,8 @@
7273 obj-$(CONFIG_FB_SA1100) += sa1100fb.o
7274 obj-$(CONFIG_FB_HIT) += hitfb.o
7275 obj-$(CONFIG_FB_EPSON1355) += epson1355fb.o
7276 +obj-$(CONFIG_FB_S1D15605) += s1d15605fb.o
7277 +obj-$(CONFIG_FB_ATMEL) += atmel_lcdfb.o
7278 obj-$(CONFIG_FB_PVR2) += pvr2fb.o
7279 obj-$(CONFIG_FB_VOODOO1) += sstfb.o
7280 obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o
7281 diff -urN -x CVS linux-2.6.21/drivers/video/atmel_lcdfb.c linux-2.6-stable/drivers/video/atmel_lcdfb.c
7282 --- linux-2.6.21/drivers/video/atmel_lcdfb.c Thu Jan 1 02:00:00 1970
7283 +++ linux-2.6-stable/drivers/video/atmel_lcdfb.c Thu May 10 12:34:01 2007
7284 @@ -0,0 +1,752 @@
7285 +/*
7286 + * Driver for AT91/AT32 LCD Controller
7287 + *
7288 + * Copyright (C) 2007 Atmel Corporation
7289 + *
7290 + * This file is subject to the terms and conditions of the GNU General Public
7291 + * License. See the file COPYING in the main directory of this archive for
7292 + * more details.
7293 + */
7294 +
7295 +#include <linux/kernel.h>
7296 +#include <linux/platform_device.h>
7297 +#include <linux/dma-mapping.h>
7298 +#include <linux/interrupt.h>
7299 +#include <linux/clk.h>
7300 +#include <linux/fb.h>
7301 +#include <linux/init.h>
7302 +#include <linux/delay.h>
7303 +
7304 +#include <asm/arch/board.h>
7305 +#include <asm/arch/cpu.h>
7306 +#include <asm/arch/gpio.h>
7307 +
7308 +#include <video/atmel_lcdc.h>
7309 +
7310 +#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
7311 +#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
7312 +
7313 +/* configurable parameters */
7314 +#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
7315 +#define ATMEL_LCDC_DMA_BURST_LEN 8
7316 +
7317 +#if defined(CONFIG_ARCH_AT91SAM9263)
7318 +#define ATMEL_LCDC_FIFO_SIZE 2048
7319 +#else
7320 +#define ATMEL_LCDC_FIFO_SIZE 512
7321 +#endif
7322 +
7323 +#if defined(CONFIG_ARCH_AT91)
7324 +#define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT
7325 +
7326 +static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
7327 + struct fb_var_screeninfo *var)
7328 +{
7329 +
7330 +}
7331 +#elif defined(CONFIG_AVR32)
7332 +#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
7333 + | FBINFO_PARTIAL_PAN_OK \
7334 + | FBINFO_HWACCEL_XPAN \
7335 + | FBINFO_HWACCEL_YPAN)
7336 +
7337 +static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
7338 + struct fb_var_screeninfo *var)
7339 +{
7340 + u32 dma2dcfg;
7341 + u32 pixeloff;
7342 +
7343 + pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
7344 +
7345 + dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
7346 + dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
7347 + lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
7348 +
7349 + /* Update configuration */
7350 + lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
7351 + lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
7352 + | ATMEL_LCDC_DMAUPDT);
7353 +}
7354 +#endif
7355 +
7356 +
7357 +static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
7358 + .type = FB_TYPE_PACKED_PIXELS,
7359 + .visual = FB_VISUAL_TRUECOLOR,
7360 + .xpanstep = 0,
7361 + .ypanstep = 0,
7362 + .ywrapstep = 0,
7363 + .accel = FB_ACCEL_NONE,
7364 +};
7365 +
7366 +
7367 +static void atmel_lcdfb_update_dma(struct fb_info *info,
7368 + struct fb_var_screeninfo *var)
7369 +{
7370 + struct atmel_lcdfb_info *sinfo = info->par;
7371 + struct fb_fix_screeninfo *fix = &info->fix;
7372 + unsigned long dma_addr;
7373 +
7374 + dma_addr = (fix->smem_start + var->yoffset * fix->line_length
7375 + + var->xoffset * var->bits_per_pixel / 8);
7376 +
7377 + dma_addr &= ~3UL;
7378 +
7379 + /* Set framebuffer DMA base address and pixel offset */
7380 + lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
7381 +
7382 + atmel_lcdfb_update_dma2d(sinfo, var);
7383 +}
7384 +
7385 +static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
7386 +{
7387 + struct fb_info *info = sinfo->info;
7388 +
7389 + dma_free_writecombine(info->device, info->fix.smem_len,
7390 + info->screen_base, info->fix.smem_start);
7391 +}
7392 +
7393 +/**
7394 + * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
7395 + * @sinfo: the frame buffer to allocate memory for
7396 + */
7397 +static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
7398 +{
7399 + struct fb_info *info = sinfo->info;
7400 + struct fb_var_screeninfo *var = &info->var;
7401 +
7402 + info->fix.smem_len = (var->xres_virtual * var->yres_virtual
7403 + * ((var->bits_per_pixel + 7) / 8));
7404 +
7405 + info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
7406 + (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
7407 +
7408 + if (!info->screen_base) {
7409 + return -ENOMEM;
7410 + }
7411 +
7412 + return 0;
7413 +}
7414 +
7415 +/**
7416 + * atmel_lcdfb_check_var - Validates a var passed in.
7417 + * @var: frame buffer variable screen structure
7418 + * @info: frame buffer structure that represents a single frame buffer
7419 + *
7420 + * Checks to see if the hardware supports the state requested by
7421 + * var passed in. This function does not alter the hardware
7422 + * state!!! This means the data stored in struct fb_info and
7423 + * struct atmel_lcdfb_info do not change. This includes the var
7424 + * inside of struct fb_info. Do NOT change these. This function
7425 + * can be called on its own if we intent to only test a mode and
7426 + * not actually set it. The stuff in modedb.c is a example of
7427 + * this. If the var passed in is slightly off by what the
7428 + * hardware can support then we alter the var PASSED in to what
7429 + * we can do. If the hardware doesn't support mode change a
7430 + * -EINVAL will be returned by the upper layers. You don't need
7431 + * to implement this function then. If you hardware doesn't
7432 + * support changing the resolution then this function is not
7433 + * needed. In this case the driver would just provide a var that
7434 + * represents the static state the screen is in.
7435 + *
7436 + * Returns negative errno on error, or zero on success.
7437 + */
7438 +static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
7439 + struct fb_info *info)
7440 +{
7441 + struct device *dev = info->device;
7442 + struct atmel_lcdfb_info *sinfo = info->par;
7443 + unsigned long clk_value_khz;
7444 +
7445 + clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
7446 +
7447 + dev_dbg(dev, "%s:\n", __func__);
7448 + dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
7449 + dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
7450 + dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
7451 + dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
7452 +
7453 + if ((PICOS2KHZ(var->pixclock) * var->bits_per_pixel / 8) > clk_value_khz) {
7454 + dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
7455 + return -EINVAL;
7456 + }
7457 +
7458 + /* Force same alignment for each line */
7459 + var->xres = (var->xres + 3) & ~3UL;
7460 + var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
7461 +
7462 + var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
7463 + var->transp.msb_right = 0;
7464 + var->transp.offset = var->transp.length = 0;
7465 + var->xoffset = var->yoffset = 0;
7466 +
7467 + switch (var->bits_per_pixel) {
7468 + case 2:
7469 + case 4:
7470 + case 8:
7471 + var->red.offset = var->green.offset = var->blue.offset = 0;
7472 + var->red.length = var->green.length = var->blue.length
7473 + = var->bits_per_pixel;
7474 + break;
7475 + case 15:
7476 + case 16:
7477 + var->red.offset = 0;
7478 + var->green.offset = 5;
7479 + var->blue.offset = 10;
7480 + var->red.length = var->green.length = var->blue.length = 5;
7481 + break;
7482 + case 24:
7483 + case 32:
7484 + var->red.offset = 0;
7485 + var->green.offset = 8;
7486 + var->blue.offset = 16;
7487 + var->red.length = var->green.length = var->blue.length = 8;
7488 + break;
7489 + default:
7490 + dev_err(dev, "color depth %d not supported\n",
7491 + var->bits_per_pixel);
7492 + return -EINVAL;
7493 + }
7494 +
7495 + return 0;
7496 +}
7497 +
7498 +/**
7499 + * atmel_lcdfb_set_par - Alters the hardware state.
7500 + * @info: frame buffer structure that represents a single frame buffer
7501 + *
7502 + * Using the fb_var_screeninfo in fb_info we set the resolution
7503 + * of the this particular framebuffer. This function alters the
7504 + * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
7505 + * not alter var in fb_info since we are using that data. This
7506 + * means we depend on the data in var inside fb_info to be
7507 + * supported by the hardware. atmel_lcdfb_check_var is always called
7508 + * before atmel_lcdfb_set_par to ensure this. Again if you can't
7509 + * change the resolution you don't need this function.
7510 + *
7511 + */
7512 +static int atmel_lcdfb_set_par(struct fb_info *info)
7513 +{
7514 + struct atmel_lcdfb_info *sinfo = info->par;
7515 + unsigned long value;
7516 + unsigned long clk_value_khz;
7517 +
7518 + dev_dbg(info->device, "%s:\n", __func__);
7519 + dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
7520 + info->var.xres, info->var.yres,
7521 + info->var.xres_virtual, info->var.yres_virtual);
7522 +
7523 + /* Turn off the LCD controller and the DMA controller */
7524 + lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
7525 +
7526 + lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
7527 +
7528 + if (info->var.bits_per_pixel <= 8)
7529 + info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
7530 + else
7531 + info->fix.visual = FB_VISUAL_TRUECOLOR;
7532 +
7533 + info->fix.line_length = info->var.xres_virtual * (info->var.bits_per_pixel / 8);
7534 +
7535 + /* Re-initialize the DMA engine... */
7536 + dev_dbg(info->device, " * update DMA engine\n");
7537 + atmel_lcdfb_update_dma(info, &info->var);
7538 +
7539 + /* ...set frame size and burst length = 8 words (?) */
7540 + value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
7541 + value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
7542 + lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
7543 +
7544 + /* Now, the LCDC core... */
7545 +
7546 + /* Set pixel clock */
7547 + clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
7548 +
7549 + value = clk_value_khz / PICOS2KHZ(info->var.pixclock);
7550 +
7551 + if (clk_value_khz % PICOS2KHZ(info->var.pixclock))
7552 + value++;
7553 +
7554 + value = (value / 2) - 1;
7555 +
7556 + if (value <= 0) {
7557 + dev_notice(info->device, "Bypassing pixel clock divider\n");
7558 + lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
7559 + } else
7560 + lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET);
7561 +
7562 + /* Initialize control register 2 */
7563 + value = sinfo->default_lcdcon2;
7564 +
7565 + if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
7566 + value |= ATMEL_LCDC_INVLINE_INVERTED;
7567 + if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
7568 + value |= ATMEL_LCDC_INVFRAME_INVERTED;
7569 +
7570 + switch (info->var.bits_per_pixel) {
7571 + case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
7572 + case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
7573 + case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
7574 + case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
7575 + case 15: /* fall through */
7576 + case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
7577 + case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
7578 + case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
7579 + default: BUG(); break;
7580 + }
7581 + dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
7582 + lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
7583 +
7584 + /* Vertical timing */
7585 + value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
7586 + value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
7587 + value |= info->var.lower_margin;
7588 + dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
7589 + lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
7590 +
7591 + /* Horizontal timing */
7592 + value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
7593 + value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
7594 + value |= (info->var.left_margin - 1);
7595 + dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
7596 + lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
7597 +
7598 + /* Display size */
7599 + value = (info->var.xres - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
7600 + value |= info->var.yres - 1;
7601 + lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
7602 +
7603 + /* FIFO Threshold: Use formula from data sheet */
7604 + value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
7605 + lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
7606 +
7607 + /* Toggle LCD_MODE every frame */
7608 + lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
7609 +
7610 + /* Disable all interrupts */
7611 + lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
7612 +
7613 + /* Set contrast */
7614 + value = ATMEL_LCDC_PS_DIV8 | ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE;
7615 + lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
7616 + lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
7617 + /* ...wait for DMA engine to become idle... */
7618 + while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
7619 + msleep(10);
7620 +
7621 + dev_dbg(info->device, " * re-enable DMA engine\n");
7622 + /* ...and enable it with updated configuration */
7623 + lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
7624 +
7625 + dev_dbg(info->device, " * re-enable LCDC core\n");
7626 + lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
7627 + (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
7628 +
7629 + dev_dbg(info->device, " * DONE\n");
7630 +
7631 + return 0;
7632 +}
7633 +
7634 +static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
7635 +{
7636 + chan &= 0xffff;
7637 + chan >>= 16 - bf->length;
7638 + return chan << bf->offset;
7639 +}
7640 +
7641 +/**
7642 + * atmel_lcdfb_setcolreg - Optional function. Sets a color register.
7643 + * @regno: Which register in the CLUT we are programming
7644 + * @red: The red value which can be up to 16 bits wide
7645 + * @green: The green value which can be up to 16 bits wide
7646 + * @blue: The blue value which can be up to 16 bits wide.
7647 + * @transp: If supported the alpha value which can be up to 16 bits wide.
7648 + * @info: frame buffer info structure
7649 + *
7650 + * Set a single color register. The values supplied have a 16 bit
7651 + * magnitude which needs to be scaled in this function for the hardware.
7652 + * Things to take into consideration are how many color registers, if
7653 + * any, are supported with the current color visual. With truecolor mode
7654 + * no color palettes are supported. Here a psuedo palette is created
7655 + * which we store the value in pseudo_palette in struct fb_info. For
7656 + * pseudocolor mode we have a limited color palette. To deal with this
7657 + * we can program what color is displayed for a particular pixel value.
7658 + * DirectColor is similar in that we can program each color field. If
7659 + * we have a static colormap we don't need to implement this function.
7660 + *
7661 + * Returns negative errno on error, or zero on success. In an
7662 + * ideal world, this would have been the case, but as it turns
7663 + * out, the other drivers return 1 on failure, so that's what
7664 + * we're going to do.
7665 + */
7666 +static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
7667 + unsigned int green, unsigned int blue,
7668 + unsigned int transp, struct fb_info *info)
7669 +{
7670 + struct atmel_lcdfb_info *sinfo = info->par;
7671 + unsigned int val;
7672 + u32 *pal;
7673 + int ret = 1;
7674 +
7675 + if (info->var.grayscale)
7676 + red = green = blue = (19595 * red + 38470 * green
7677 + + 7471 * blue) >> 16;
7678 +
7679 + switch (info->fix.visual) {
7680 + case FB_VISUAL_TRUECOLOR:
7681 + if (regno < 16) {
7682 + pal = info->pseudo_palette;
7683 +
7684 + val = chan_to_field(red, &info->var.red);
7685 + val |= chan_to_field(green, &info->var.green);
7686 + val |= chan_to_field(blue, &info->var.blue);
7687 +
7688 + pal[regno] = val;
7689 + ret = 0;
7690 + }
7691 + break;
7692 +
7693 + case FB_VISUAL_PSEUDOCOLOR:
7694 + if (regno < 256) {
7695 + val = ((red >> 11) & 0x001f);
7696 + val |= ((green >> 6) & 0x03e0);
7697 + val |= ((blue >> 1) & 0x7c00);
7698 +
7699 + /*
7700 + * TODO: intensity bit. Maybe something like
7701 + * ~(red[10] ^ green[10] ^ blue[10]) & 1
7702 + */
7703 +
7704 + lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
7705 + ret = 0;
7706 + }
7707 + break;
7708 + }
7709 +
7710 + return ret;
7711 +}
7712 +
7713 +static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
7714 + struct fb_info *info)
7715 +{
7716 + dev_dbg(info->device, "%s\n", __func__);
7717 +
7718 + atmel_lcdfb_update_dma(info, var);
7719 +
7720 + return 0;
7721 +}
7722 +
7723 +static struct fb_ops atmel_lcdfb_ops = {
7724 + .owner = THIS_MODULE,
7725 + .fb_check_var = atmel_lcdfb_check_var,
7726 + .fb_set_par = atmel_lcdfb_set_par,
7727 + .fb_setcolreg = atmel_lcdfb_setcolreg,
7728 + .fb_pan_display = atmel_lcdfb_pan_display,
7729 + .fb_fillrect = cfb_fillrect,
7730 + .fb_copyarea = cfb_copyarea,
7731 + .fb_imageblit = cfb_imageblit,
7732 +};
7733 +
7734 +static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
7735 +{
7736 + struct fb_info *info = dev_id;
7737 + struct atmel_lcdfb_info *sinfo = info->par;
7738 + u32 status;
7739 +
7740 + status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
7741 + lcdc_writel(sinfo, ATMEL_LCDC_IDR, status);
7742 + return IRQ_HANDLED;
7743 +}
7744 +
7745 +static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
7746 +{
7747 + struct fb_info *info = sinfo->info;
7748 + int ret = 0;
7749 +
7750 + memset_io(info->screen_base, 0, info->fix.smem_len);
7751 + info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
7752 +
7753 + dev_info(info->device,
7754 + "%luKiB frame buffer at %08lx (mapped at %p)\n",
7755 + (unsigned long)info->fix.smem_len / 1024,
7756 + (unsigned long)info->fix.smem_start,
7757 + info->screen_base);
7758 +
7759 + /* Allocate colormap */
7760 + ret = fb_alloc_cmap(&info->cmap, 256, 0);
7761 + if (ret < 0)
7762 + dev_err(info->device, "Alloc color map failed\n");
7763 +
7764 + return ret;
7765 +}
7766 +
7767 +static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
7768 +{
7769 + if (sinfo->bus_clk)
7770 + clk_enable(sinfo->bus_clk);
7771 + clk_enable(sinfo->lcdc_clk);
7772 +}
7773 +
7774 +static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
7775 +{
7776 + if (sinfo->bus_clk)
7777 + clk_disable(sinfo->bus_clk);
7778 + clk_disable(sinfo->lcdc_clk);
7779 +}
7780 +
7781 +
7782 +static int __init atmel_lcdfb_probe(struct platform_device *pdev)
7783 +{
7784 + struct device *dev = &pdev->dev;
7785 + struct fb_info *info;
7786 + struct atmel_lcdfb_info *sinfo;
7787 + struct atmel_lcdfb_info *pdata_sinfo;
7788 + struct resource *regs = NULL;
7789 + struct resource *map = NULL;
7790 + int ret;
7791 +
7792 + dev_dbg(dev, "%s BEGIN\n", __func__);
7793 +
7794 + ret = -ENOMEM;
7795 + info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
7796 + if (!info) {
7797 + dev_err(dev, "cannot allocate memory\n");
7798 + goto out;
7799 + }
7800 +
7801 + sinfo = info->par;
7802 +
7803 + if (dev->platform_data) {
7804 + pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
7805 + sinfo->default_bpp = pdata_sinfo->default_bpp;
7806 + sinfo->default_dmacon = pdata_sinfo->default_dmacon;
7807 + sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
7808 + sinfo->default_monspecs = pdata_sinfo->default_monspecs;
7809 + sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
7810 + sinfo->guard_time = pdata_sinfo->guard_time;
7811 + } else {
7812 + dev_err(dev, "cannot get default configuration\n");
7813 + goto free_info;
7814 + }
7815 + sinfo->info = info;
7816 + sinfo->pdev = pdev;
7817 +
7818 + strcpy(info->fix.id, sinfo->pdev->name);
7819 + info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
7820 + info->pseudo_palette = sinfo->pseudo_palette;
7821 + info->fbops = &atmel_lcdfb_ops;
7822 +
7823 + memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
7824 + info->fix = atmel_lcdfb_fix;
7825 +
7826 + /* Enable LCDC Clocks */
7827 + if (cpu_is_at91sam9261()) {
7828 + sinfo->bus_clk = clk_get(dev, "hck1");
7829 + if (IS_ERR(sinfo->bus_clk)) {
7830 + ret = PTR_ERR(sinfo->bus_clk);
7831 + goto free_info;
7832 + }
7833 + }
7834 + sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
7835 + if (IS_ERR(sinfo->lcdc_clk)) {
7836 + ret = PTR_ERR(sinfo->lcdc_clk);
7837 + goto put_bus_clk;
7838 + }
7839 + atmel_lcdfb_start_clock(sinfo);
7840 +
7841 + ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
7842 + info->monspecs.modedb_len, info->monspecs.modedb,
7843 + sinfo->default_bpp);
7844 + if (!ret) {
7845 + dev_err(dev, "no suitable video mode found\n");
7846 + goto stop_clk;
7847 + }
7848 +
7849 +
7850 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7851 + if (!regs) {
7852 + dev_err(dev, "resources unusable\n");
7853 + ret = -ENXIO;
7854 + goto stop_clk;
7855 + }
7856 +
7857 + sinfo->irq_base = platform_get_irq(pdev, 0);
7858 + if (sinfo->irq_base < 0) {
7859 + dev_err(dev, "unable to get irq\n");
7860 + ret = sinfo->irq_base;
7861 + goto stop_clk;
7862 + }
7863 +
7864 + /* Initialize video memory */
7865 + map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7866 + if (map) {
7867 + /* use a pre-allocated memory buffer */
7868 + info->fix.smem_start = map->start;
7869 + info->fix.smem_len = map->end - map->start + 1;
7870 + if (!request_mem_region(info->fix.smem_start,
7871 + info->fix.smem_len, pdev->name)) {
7872 + ret = -EBUSY;
7873 + goto stop_clk;
7874 + }
7875 +
7876 + info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
7877 + if (!info->screen_base)
7878 + goto release_intmem;
7879 + } else {
7880 + /* alocate memory buffer */
7881 + ret = atmel_lcdfb_alloc_video_memory(sinfo);
7882 + if (ret < 0) {
7883 + dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
7884 + goto stop_clk;
7885 + }
7886 + }
7887 +
7888 + /* LCDC registers */
7889 + info->fix.mmio_start = regs->start;
7890 + info->fix.mmio_len = regs->end - regs->start + 1;
7891 +
7892 + if (!request_mem_region(info->fix.mmio_start,
7893 + info->fix.mmio_len, pdev->name)) {
7894 + ret = -EBUSY;
7895 + goto free_fb;
7896 + }
7897 +
7898 + sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
7899 + if (!sinfo->mmio) {
7900 + dev_err(dev, "cannot map LCDC registers\n");
7901 + goto release_mem;
7902 + }
7903 +
7904 + /* interrupt */
7905 + ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
7906 + if (ret) {
7907 + dev_err(dev, "request_irq failed: %d\n", ret);
7908 + goto unmap_mmio;
7909 + }
7910 +
7911 + ret = atmel_lcdfb_init_fbinfo(sinfo);
7912 + if (ret < 0) {
7913 + dev_err(dev, "init fbinfo failed: %d\n", ret);
7914 + goto unregister_irqs;
7915 + }
7916 +
7917 + /*
7918 + * This makes sure that our colour bitfield
7919 + * descriptors are correctly initialised.
7920 + */
7921 + atmel_lcdfb_check_var(&info->var, info);
7922 +
7923 + ret = fb_set_var(info, &info->var);
7924 + if (ret) {
7925 + dev_warn(dev, "unable to set display parameters\n");
7926 + goto free_cmap;
7927 + }
7928 +
7929 + dev_set_drvdata(dev, info);
7930 +
7931 + /*
7932 + * Tell the world that we're ready to go
7933 + */
7934 + ret = register_framebuffer(info);
7935 + if (ret < 0) {
7936 + dev_err(dev, "failed to register framebuffer device: %d\n", ret);
7937 + goto free_cmap;
7938 + }
7939 +
7940 + /* Power up the LCDC screen */
7941 + if (sinfo->atmel_lcdfb_power_control)
7942 + sinfo->atmel_lcdfb_power_control(1);
7943 +
7944 + dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %lu\n",
7945 + info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
7946 +
7947 + return 0;
7948 +
7949 +
7950 +free_cmap:
7951 + fb_dealloc_cmap(&info->cmap);
7952 +unregister_irqs:
7953 + free_irq(sinfo->irq_base, info);
7954 +unmap_mmio:
7955 + iounmap(sinfo->mmio);
7956 +release_mem:
7957 + release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
7958 +free_fb:
7959 + if (map)
7960 + iounmap(info->screen_base);
7961 + else
7962 + atmel_lcdfb_free_video_memory(sinfo);
7963 +
7964 +release_intmem:
7965 + if (map)
7966 + release_mem_region(info->fix.smem_start, info->fix.smem_len);
7967 +stop_clk:
7968 + atmel_lcdfb_stop_clock(sinfo);
7969 + clk_put(sinfo->lcdc_clk);
7970 +put_bus_clk:
7971 + if (sinfo->bus_clk)
7972 + clk_put(sinfo->bus_clk);
7973 +free_info:
7974 + framebuffer_release(info);
7975 +out:
7976 + dev_dbg(dev, "%s FAILED\n", __func__);
7977 + return ret;
7978 +}
7979 +
7980 +static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
7981 +{
7982 + struct device *dev = &pdev->dev;
7983 + struct fb_info *info = dev_get_drvdata(dev);
7984 + struct atmel_lcdfb_info *sinfo = info->par;
7985 +
7986 + if (!sinfo)
7987 + return 0;
7988 +
7989 + if (sinfo->atmel_lcdfb_power_control)
7990 + sinfo->atmel_lcdfb_power_control(0);
7991 + unregister_framebuffer(info);
7992 + atmel_lcdfb_stop_clock(sinfo);
7993 + clk_put(sinfo->lcdc_clk);
7994 + if (sinfo->bus_clk)
7995 + clk_put(sinfo->bus_clk);
7996 + fb_dealloc_cmap(&info->cmap);
7997 + free_irq(sinfo->irq_base, info);
7998 + iounmap(sinfo->mmio);
7999 + release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
8000 + if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
8001 + iounmap(info->screen_base);
8002 + release_mem_region(info->fix.smem_start, info->fix.smem_len);
8003 + } else {
8004 + atmel_lcdfb_free_video_memory(sinfo);
8005 + }
8006 +
8007 + dev_set_drvdata(dev, NULL);
8008 + framebuffer_release(info);
8009 +
8010 + return 0;
8011 +}
8012 +
8013 +static struct platform_driver atmel_lcdfb_driver = {
8014 + .remove = __exit_p(atmel_lcdfb_remove),
8015 + .driver = {
8016 + .name = "atmel_lcdfb",
8017 + .owner = THIS_MODULE,
8018 + },
8019 +};
8020 +
8021 +static int __init atmel_lcdfb_init(void)
8022 +{
8023 + return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe);
8024 +}
8025 +
8026 +static void __exit atmel_lcdfb_exit(void)
8027 +{
8028 + platform_driver_unregister(&atmel_lcdfb_driver);
8029 +}
8030 +
8031 +module_init(atmel_lcdfb_init);
8032 +module_exit(atmel_lcdfb_exit);
8033 +
8034 +MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
8035 +MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@rfo.atmel.com>");
8036 +MODULE_LICENSE("GPL");
8037 diff -urN -x CVS linux-2.6.21/drivers/video/backlight/Kconfig linux-2.6-stable/drivers/video/backlight/Kconfig
8038 --- linux-2.6.21/drivers/video/backlight/Kconfig Thu Apr 26 05:08:32 2007
8039 +++ linux-2.6-stable/drivers/video/backlight/Kconfig Tue May 8 12:13:31 2007
8040 @@ -63,3 +63,11 @@
8041 help
8042 If you have a Frontpath ProGear say Y to enable the
8043 backlight driver.
8044 +
8045 +config BACKLIGHT_KB920x
8046 + tristate "KwikByte KB9202 Backlight Driver"
8047 + depends on BACKLIGHT_CLASS_DEVICE && MACH_KB9200
8048 + default y
8049 + help
8050 + If you have a KwikByte KB9202 board, say Y to enable the
8051 + backlight driver.
8052 diff -urN -x CVS linux-2.6.21/drivers/video/backlight/Makefile linux-2.6-stable/drivers/video/backlight/Makefile
8053 --- linux-2.6.21/drivers/video/backlight/Makefile Thu Apr 26 05:08:32 2007
8054 +++ linux-2.6-stable/drivers/video/backlight/Makefile Tue May 8 12:13:31 2007
8055 @@ -6,3 +6,4 @@
8056 obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o
8057 obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
8058 obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
8059 +obj-$(CONFIG_BACKLIGHT_KB920x) += kb920x_bl.o
8060 diff -urN -x CVS linux-2.6.21/drivers/video/backlight/kb920x_bl.c linux-2.6-stable/drivers/video/backlight/kb920x_bl.c
8061 --- linux-2.6.21/drivers/video/backlight/kb920x_bl.c Thu Jan 1 02:00:00 1970
8062 +++ linux-2.6-stable/drivers/video/backlight/kb920x_bl.c Tue May 8 12:13:31 2007
8063 @@ -0,0 +1,164 @@
8064 +/*
8065 + * Backlight Driver for KB9202
8066 + *
8067 + * Copyright (c) 2006 KwikByte
8068 + *
8069 + * Based on Sharp's Corgi Backlight Driver
8070 + *
8071 + * This file is subject to the terms and conditions of the GNU General Public
8072 + * License. See the file "COPYING" in the main directory of this archive
8073 + * for more details.
8074 + */
8075 +
8076 +#include <linux/module.h>
8077 +#include <linux/kernel.h>
8078 +#include <linux/init.h>
8079 +#include <linux/platform_device.h>
8080 +#include <linux/spinlock.h>
8081 +#include <linux/fb.h>
8082 +#include <linux/backlight.h>
8083 +
8084 +#include <asm/arch/gpio.h>
8085 +
8086 +/* The backlight is on(1)/off(0) */
8087 +#define KB9202_DEFAULT_INTENSITY 1
8088 +#define KB9202_MAX_INTENSITY 1
8089 +
8090 +static int kb9202bl_suspended;
8091 +static int current_intensity = 0;
8092 +static DEFINE_SPINLOCK(bl_lock);
8093 +
8094 +static int kb9202bl_set_intensity(struct backlight_device *bd)
8095 +{
8096 + unsigned long flags;
8097 + int intensity = bd->props.brightness;
8098 +
8099 + if (bd->props.power != FB_BLANK_UNBLANK)
8100 + intensity = 0;
8101 + if (bd->props.fb_blank != FB_BLANK_UNBLANK)
8102 + intensity = 0;
8103 + if (kb9202bl_suspended)
8104 + intensity = 0;
8105 +
8106 + if ((!current_intensity) && (bd->props.power == FB_BLANK_UNBLANK))
8107 + intensity = 1;
8108 +
8109 + spin_lock_irqsave(&bl_lock, flags);
8110 + if (intensity)
8111 + gpio_set_value(AT91_PIN_PC23, 1);
8112 + else
8113 + gpio_set_value(AT91_PIN_PC23, 0);
8114 + spin_unlock_irqrestore(&bl_lock, flags);
8115 +
8116 + current_intensity = intensity;
8117 +
8118 + return 0;
8119 +}
8120 +
8121 +static int kb9202bl_get_intensity(struct backlight_device *bd)
8122 +{
8123 + return current_intensity;
8124 +}
8125 +
8126 +static struct backlight_ops kb9202bl_ops = {
8127 + .get_brightness = kb9202bl_get_intensity,
8128 + .update_status = kb9202bl_set_intensity,
8129 +};
8130 +
8131 +static int __init kb9202bl_probe(struct platform_device *pdev)
8132 +{
8133 + struct backlight_device *bd;
8134 +
8135 + bd = backlight_device_register ("kb9202-bl", &pdev->dev, NULL, &kb9202bl_ops);
8136 + if (IS_ERR(bd))
8137 + return PTR_ERR(bd);
8138 +
8139 + platform_set_drvdata(pdev, bd);
8140 +
8141 + bd->props.max_brightness = KB9202_MAX_INTENSITY;
8142 + bd->props.brightness = KB9202_DEFAULT_INTENSITY;
8143 + (void) kb9202bl_set_intensity(bd);
8144 +
8145 + return 0;
8146 +}
8147 +
8148 +static int kb9202bl_remove(struct platform_device *pdev)
8149 +{
8150 + struct backlight_device *bd = platform_get_drvdata(pdev);
8151 +
8152 + bd->props.brightness = 0;
8153 + bd->props.power = 0;
8154 + (void) kb9202bl_set_intensity(bd);
8155 +
8156 + backlight_device_unregister(bd);
8157 +
8158 + return 0;
8159 +}
8160 +
8161 +#ifdef CONFIG_PM
8162 +static int kb9202bl_suspend(struct platform_device *dev, pm_message_t state)
8163 +{
8164 + struct backlight_device *bd = platform_get_drvdata(pdev);
8165 +
8166 + kb9202bl_suspended = 1;
8167 + (void) kb9202bl_set_intensity(bd);
8168 + return 0;
8169 +}
8170 +
8171 +static int kb9202bl_resume(struct platform_device *dev)
8172 +{
8173 + struct backlight_device *bd = platform_get_drvdata(pdev);
8174 +
8175 + kb9202bl_suspended = 0;
8176 + (void) kb9202bl_set_intensity(bd);
8177 + return 0;
8178 +}
8179 +#else
8180 +#define kb9202bl_suspend NULL
8181 +#define kb9202bl_resume NULL
8182 +#endif
8183 +
8184 +static struct platform_driver kb9202bl_driver = {
8185 + .probe = kb9202bl_probe,
8186 + .remove = kb9202bl_remove,
8187 + .suspend = kb9202bl_suspend,
8188 + .resume = kb9202bl_resume,
8189 + .driver = {
8190 + .name = "kb9202-bl",
8191 + .owner = THIS_MODULE,
8192 + },
8193 +};
8194 +
8195 +static struct platform_device *kb9202bl_device;
8196 +
8197 +static int __init kb9202bl_init(void)
8198 +{
8199 + int ret;
8200 +
8201 + ret = platform_driver_register(&kb9202bl_driver);
8202 + if (!ret) {
8203 + kb9202bl_device = platform_device_alloc("kb9202-bl", -1);
8204 + if (!kb9202bl_device)
8205 + return -ENOMEM;
8206 +
8207 + ret = platform_device_add(kb9202bl_device);
8208 + if (ret) {
8209 + platform_device_put(kb9202bl_device);
8210 + platform_driver_unregister(&kb9202bl_driver);
8211 + }
8212 + }
8213 + return ret;
8214 +}
8215 +
8216 +static void __exit kb9202bl_exit(void)
8217 +{
8218 + platform_device_unregister(kb9202bl_device);
8219 + platform_driver_unregister(&kb9202bl_driver);
8220 +}
8221 +
8222 +module_init(kb9202bl_init);
8223 +module_exit(kb9202bl_exit);
8224 +
8225 +MODULE_AUTHOR("KwikByte <kb9200_dev@kwikbyte.com>");
8226 +MODULE_DESCRIPTION("KB9202 Backlight Driver");
8227 +MODULE_LICENSE("GPL");
8228 diff -urN -x CVS linux-2.6.21/drivers/video/s1d15605fb.c linux-2.6-stable/drivers/video/s1d15605fb.c
8229 --- linux-2.6.21/drivers/video/s1d15605fb.c Thu Jan 1 02:00:00 1970
8230 +++ linux-2.6-stable/drivers/video/s1d15605fb.c Tue May 8 12:13:31 2007
8231 @@ -0,0 +1,659 @@
8232 +/*
8233 + * drivers/video/s1d15605.c
8234 + *
8235 + * Adapted from several sources including:
8236 + * 1) Driver for AT91 LCD Controller
8237 + * Copyright (C) 2006 Atmel
8238 + *
8239 + * 2) Copyright (C) 2005 S. Kevin Hester
8240 + *
8241 + * This file is subject to the terms and conditions of the GNU General Public
8242 + * License. See the file COPYING in the main directory of this archive for
8243 + * more details.
8244 + *
8245 + * This is a basic framebuffer driver for the Optrex F-51320 128x64 mono LCD
8246 + * display. This display uses a clone of the common Epson SED 1531 display
8247 + * controller.
8248 + *
8249 + * I've heavily borrowed code from the vfb.c driver.
8250 + *
8251 + * This program is free software; you can redistribute it and/or modify
8252 + * it under the terms of the GNU General Public License as published by
8253 + * the Free Software Foundation; either version 2 of the License, or
8254 + * (at your option) any later version.
8255 + *
8256 + * This program is distributed in the hope that it will be useful,
8257 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8258 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8259 + * GNU General Public License for more details.
8260 + *
8261 + * You should have received a copy of the GNU General Public License
8262 + * along with this program; if not, write to the Free Software
8263 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
8264 + */
8265 +
8266 +#ifdef DEBUG
8267 +#define MSG(string, args...) printk("s1d15605fb:" string, ##args)
8268 +#else
8269 +#define MSG(string, args...)
8270 +#endif
8271 +
8272 +#include <linux/kernel.h>
8273 +#include <linux/platform_device.h>
8274 +#include <linux/dma-mapping.h>
8275 +#include <linux/interrupt.h>
8276 +#include <linux/clk.h>
8277 +#include <linux/fb.h>
8278 +#include <linux/init.h>
8279 +#include <linux/delay.h>
8280 +
8281 +#include <asm/uaccess.h>
8282 +
8283 +#include <asm/arch/board.h>
8284 +#include <asm/arch/gpio.h>
8285 +
8286 +#ifdef CONFIG_PMAC_BACKLIGHT
8287 +#include <asm/backlight.h>
8288 +#endif
8289 +
8290 +#define VIDEOWIDTH 128
8291 +#define VIDEOHEIGHT 64
8292 +#define VIDEODEPTH 1 /* bits/pixel */
8293 +#define VIDEOWIDTH_BYTES ((VIDEOWIDTH * VIDEODEPTH) / 8)
8294 +
8295 +/* The number of bytes that actually go to the device */
8296 +#define ACTUALVIDEOMEMSIZE (VIDEOWIDTH_BYTES * VIDEOHEIGHT)
8297 +#define VIDEOMEMSIZE PAGE_SIZE
8298 +
8299 +static struct fb_var_screeninfo s1d15605_default __initdata = {
8300 + .xres = VIDEOWIDTH,
8301 + .yres = VIDEOHEIGHT,
8302 + .xres_virtual = VIDEOWIDTH,
8303 + .yres_virtual = VIDEOHEIGHT,
8304 + .bits_per_pixel = VIDEODEPTH,
8305 + .red = { 0, 1, 0 },
8306 + .green = { 0, 1, 0 },
8307 + .blue = { 0, 1, 0 },
8308 + .activate = FB_ACTIVATE_NOW,
8309 + .pixclock = 20000,
8310 + .vmode = FB_VMODE_NONINTERLACED,
8311 +};
8312 +
8313 +static struct fb_fix_screeninfo s1d15605_fix __initdata = {
8314 + .id = "s1d15605",
8315 + .type = FB_TYPE_PACKED_PIXELS,
8316 + .visual = FB_VISUAL_MONO10,
8317 + .xpanstep = 0,
8318 + .ypanstep = 0,
8319 + .ywrapstep = 0,
8320 + .accel = FB_ACCEL_NONE,
8321 +};
8322 +
8323 +struct s1d15605fb_info {
8324 + struct fb_info *info;
8325 + char *mmio;
8326 + unsigned long reset_pin;
8327 + struct platform_device *pdev;
8328 +};
8329 +
8330 +/*
8331 + * LCD device interface
8332 + */
8333 +#define RESET_DISPLAY 0xE2
8334 +#define LCD_BIAS_1_9 0xA2
8335 +#define ADC_SELECT_REVERSE 0xA1
8336 +#define COMMON_OUTPUT_NORMAL 0xC0
8337 +#define V5_RESISTOR_RATIO 0x26
8338 +#define ELECTRONIC_VOLUME_SET 0x81
8339 +#define ELECTRONIC_VOLUME_INIT 0x20
8340 +#define POWER_CONTROL_SET 0x28
8341 +#define VOLTAGE_REGULATOR 0x02
8342 +#define VOLTAGE_FOLLOWER 0x01
8343 +#define BOOSTER_CIRCUIT 0x04
8344 +#define DISPLAY_ON 0xAF
8345 +#define START_LINE_SET 0x40
8346 +#define PAGE_ADDRESS_SET 0xB0
8347 +#define COLUMN_ADDRESS_HIGH 0x10
8348 +#define COLUMN_ADDRESS_LOW 0x00
8349 +#define RESISTOR_RATIO_START 0x20
8350 +
8351 +#define NUM_OF_PAGES 8
8352 +#define NUM_OF_COLUMNS 128
8353 +
8354 +#define WRITE_COMMAND(x) __raw_writeb((x), (sinfo)->mmio)
8355 +#define READ_COMMAND __raw_readb((sinfo)->mmio)
8356 +#define WRITE_DATA(x) __raw_writeb((x), (sinfo)->mmio + (0x10000))
8357 +#define READ_DATA __raw_readb((sinfo)->mmio + (0x10000))
8358 +
8359 +
8360 +/*
8361 + * s1d15605fb_resize_framebuffer
8362 + *
8363 + * Free allocated space if different. Allocate on new of changed.
8364 + * Returns -ENOMEM if the new framebuffer can not be allocated,
8365 + * zero on success.
8366 + */
8367 +static int s1d15605fb_resize_framebuffer(struct s1d15605fb_info *sinfo)
8368 +{
8369 + struct fb_info *info = sinfo->info;
8370 + struct fb_fix_screeninfo *fix = &info->fix;
8371 + struct fb_var_screeninfo *var = &info->var;
8372 + unsigned int new_size;
8373 + void *new_vaddr;
8374 +
8375 + new_size = ((var->xres_virtual * var->yres_virtual * var->bits_per_pixel) / 8);
8376 +
8377 + MSG("%s: x (%d) y (%d) bpp (%d): new size 0x%08x\n", __FUNCTION__,
8378 + var->xres_virtual, var->yres_virtual, var->bits_per_pixel, new_size);
8379 +
8380 + if (new_size == fix->smem_len)
8381 + return 0;
8382 +
8383 + if (fix->smem_len) {
8384 + kfree(info->screen_base);
8385 + }
8386 +
8387 + new_vaddr = kmalloc(new_size, GFP_KERNEL);
8388 +
8389 + if (!new_vaddr) {
8390 + fix->smem_len = 0;
8391 + return -ENOMEM;
8392 + }
8393 +
8394 + info->screen_base = new_vaddr;
8395 + fix->smem_start = (unsigned)new_vaddr;
8396 + fix->smem_len = new_size;
8397 + fix->line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
8398 +
8399 + dev_info(info->device,
8400 + "%luKiB frame buffer at %08lx (mapped at %p)\n",
8401 + (unsigned long)info->fix.smem_len / 1024,
8402 + (unsigned long)info->fix.smem_start,
8403 + info->screen_base);
8404 +
8405 + return 0;
8406 +}
8407 +
8408 +
8409 +/*
8410 + * The s1d15605 seems to be divided into eight 128 pixel wide pages (from top to
8411 + * bottom) each page seems to be eight pixels high, where these eight pixels are
8412 + * one byte
8413 + */
8414 +static void s1d15605_update(struct fb_info *info)
8415 +{
8416 + struct s1d15605fb_info *sinfo = info->par;
8417 + int page, i, row, colmask;
8418 + u8 retVal, *rowPtr;
8419 +
8420 + WRITE_COMMAND(START_LINE_SET);
8421 + for (page = 0; page < NUM_OF_PAGES; ++page) {
8422 + WRITE_COMMAND(PAGE_ADDRESS_SET + page);
8423 + WRITE_COMMAND(COLUMN_ADDRESS_HIGH);
8424 + WRITE_COMMAND(COLUMN_ADDRESS_LOW);
8425 +
8426 + for (i = 0; i < NUM_OF_COLUMNS; ++i)
8427 + {
8428 + /* point of opportunity: optimization */
8429 + colmask = (1 << (i & 0x7));
8430 + rowPtr = (u8*)(info->screen_base);
8431 + rowPtr += (VIDEOWIDTH_BYTES * 8 * page);
8432 + rowPtr += (i >> 3);
8433 + retVal = 0;
8434 + for (row = 0; row < 8; ++row)
8435 + {
8436 + retVal = (retVal >> 1) | (((*rowPtr) & colmask) ? 0x80 : 0);
8437 + rowPtr += VIDEOWIDTH_BYTES;
8438 + }
8439 + WRITE_DATA(retVal);
8440 + }
8441 + }
8442 +
8443 + WRITE_COMMAND(DISPLAY_ON);
8444 +}
8445 +
8446 +
8447 +/*
8448 + * Setting the video mode has been split into two parts.
8449 + * First part, xxxfb_check_var, must not write anything
8450 + * to hardware, it should only verify and adjust var.
8451 + * This means it doesn't alter par but it does use hardware
8452 + * data from it to check this var.
8453 + */
8454 +static int s1d15605_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
8455 +{
8456 + /*
8457 + * Some very basic checks
8458 + */
8459 + if (!var->xres)
8460 + var->xres = 1;
8461 + if (!var->yres)
8462 + var->yres = 1;
8463 + if (var->xres > var->xres_virtual)
8464 + var->xres_virtual = var->xres;
8465 + if (var->yres > var->yres_virtual)
8466 + var->yres_virtual = var->yres;
8467 +
8468 + if(var->bits_per_pixel > VIDEODEPTH)
8469 + return -EINVAL;
8470 +
8471 + /*
8472 + * Memory limit
8473 + */
8474 + if (((var->yres_virtual * var->bits_per_pixel * var->yres_virtual) >> 3) >
8475 + ACTUALVIDEOMEMSIZE)
8476 + return -ENOMEM;
8477 +
8478 + /*
8479 + * Now that we checked it we alter var. The reason being is that the video
8480 + * mode passed in might not work but slight changes to it might make it
8481 + * work. This way we let the user know what is acceptable.
8482 + */
8483 + switch (var->bits_per_pixel) {
8484 + case 1:
8485 + var->red.offset = var->green.offset = var->blue.offset = 0;
8486 + var->red.length = var->green.length = var->blue.length
8487 + = var->bits_per_pixel;
8488 + break;
8489 + default:
8490 + return -EINVAL;
8491 + }
8492 +
8493 + var->xoffset = var->yoffset = 0;
8494 + var->red.msb_right = var->green.msb_right = var->blue.msb_right =
8495 + var->transp.msb_right = 0;
8496 +
8497 + return 0;
8498 +}
8499 +
8500 +
8501 +/*
8502 + * This routine actually sets the video mode. It's in here where we
8503 + * the hardware state info->par and fix which can be affected by the
8504 + * change in par. For this driver it doesn't do much.
8505 + */
8506 +static int s1d15605_set_par(struct fb_info *info)
8507 +{
8508 + int ret;
8509 +
8510 + MSG("%s:\n", __func__);
8511 + MSG(" * resolution: %ux%u (%ux%u virtual)\n",
8512 + info->var.xres, info->var.yres,
8513 + info->var.xres_virtual, info->var.yres_virtual);
8514 +
8515 + ret = s1d15605fb_resize_framebuffer(info->par);
8516 +
8517 + info->fix.visual = FB_VISUAL_MONO10;
8518 + return ret;
8519 +}
8520 +
8521 +
8522 +/*
8523 + * Set a single color register. The values supplied are already
8524 + * rounded down to the hardware's capabilities (according to the
8525 + * entries in the var structure). Return != 0 for invalid regno.
8526 + */
8527 +static int s1d15605_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
8528 + u_int transp, struct fb_info *info)
8529 +{
8530 + if (regno > 1) /* no. of hw registers - we only do mono now */
8531 + return 1;
8532 +
8533 + return 0;
8534 +}
8535 +
8536 +
8537 +/*
8538 + * Currently, the routine will simply shut-off the backlight and prevent
8539 + * updates/refreshes. Modify according to application.
8540 + *
8541 + * 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off
8542 + */
8543 +static int s1d15605_blank(int blank, struct fb_info *info)
8544 +{
8545 +#ifdef CONFIG_PMAC_BACKLIGHT
8546 + if (blank)
8547 + pmac_backlight->props.power = FB_BLANK_POWERDOWN;
8548 + else
8549 + pmac_backlight->props.power = FB_BLANK_UNBLANK;
8550 + backlight_update_status(pmac_backlight);
8551 +#endif
8552 + return 1;
8553 +}
8554 +
8555 +
8556 +/*
8557 + * Pan or Wrap the Display
8558 + *
8559 + * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
8560 + */
8561 +/*
8562 +static int s1d15605_pan_display(struct fb_var_screeninfo *var,
8563 + struct fb_info *info)
8564 +{
8565 + if (var->vmode & FB_VMODE_YWRAP) {
8566 + if (var->yoffset < 0
8567 + || var->yoffset >= info->var.yres_virtual
8568 + || var->xoffset)
8569 + return -EINVAL;
8570 + } else {
8571 + if (var->xoffset + var->xres > info->var.xres_virtual ||
8572 + var->yoffset + var->yres > info->var.yres_virtual)
8573 + return -EINVAL;
8574 + }
8575 + info->var.xoffset = var->xoffset;
8576 + info->var.yoffset = var->yoffset;
8577 + if (var->vmode & FB_VMODE_YWRAP)
8578 + info->var.vmode |= FB_VMODE_YWRAP;
8579 + else
8580 + info->var.vmode &= ~FB_VMODE_YWRAP;
8581 + return 0;
8582 +}
8583 +*/
8584 +
8585 +
8586 +static void s1d15605_copyarea(struct fb_info *info, const struct fb_copyarea *region)
8587 +{
8588 + cfb_copyarea(info, region);
8589 + s1d15605_update(info);
8590 +}
8591 +
8592 +
8593 +static void s1d15605_fillrect (struct fb_info *info, const struct fb_fillrect *rect)
8594 +{
8595 + cfb_fillrect(info, rect);
8596 + s1d15605_update(info);
8597 +}
8598 +
8599 +
8600 +static void s1d15605_imageblit(struct fb_info *p, const struct fb_image *image)
8601 +{
8602 + cfb_imageblit(p, image);
8603 + s1d15605_update(p);
8604 +}
8605 +
8606 +
8607 +/*
8608 + * Write the users data to our framebuffer, and then trigger a psuedo DMA
8609 + */
8610 +static ssize_t s1d15605_write(struct file *file, const char *buf,
8611 + size_t count, loff_t *ppos)
8612 +{
8613 + unsigned long p = *ppos;
8614 + struct inode *inode = file->f_dentry->d_inode;
8615 + int fbidx = iminor(inode);
8616 + struct fb_info *info = registered_fb[fbidx];
8617 + int err;
8618 +
8619 + if (p > info->fix.smem_len)
8620 + return -ENOSPC;
8621 + if (count >= info->fix.smem_len)
8622 + count = info->fix.smem_len;
8623 + err = 0;
8624 + if (count + p > info->fix.smem_len) {
8625 + count = info->fix.smem_len - p;
8626 + err = -ENOSPC;
8627 + }
8628 + if (count) {
8629 + char *base_addr;
8630 +
8631 + base_addr = info->screen_base;
8632 + count -= copy_from_user(base_addr+p, buf, count);
8633 + *ppos += count;
8634 + err = -EFAULT;
8635 + }
8636 +
8637 + s1d15605_update(info);
8638 +
8639 + if (count)
8640 + return count;
8641 +
8642 + return err;
8643 +}
8644 +
8645 +#ifdef USE_PRIVATE_VMA_FXS
8646 +static void s1d15605_vma_open(struct vm_area_struct *vma)
8647 +{
8648 + // FIXME - store stats in the device data via vm_private_data
8649 +}
8650 +
8651 +
8652 +static void s1d15605_vma_close(struct vm_area_struct *vma)
8653 +{
8654 + // FIXME - store stats in the device data via vm_private_data
8655 +}
8656 +
8657 +
8658 +static struct page *s1d15605_vma_nopage(struct vm_area_struct *vma,
8659 + unsigned long address, int *type)
8660 +{
8661 + struct page *page;
8662 + struct fb_info *info = vma->vm_private_data;
8663 +
8664 + page = virt_to_page(info->screen_base);
8665 + get_page(page);
8666 +
8667 + // FIXME - now someone has a link to our page, start periodically blitting
8668 + // latest updates to the actual device.
8669 +
8670 + return page;
8671 +}
8672 +
8673 +
8674 +static struct vm_operations_struct s1d15605_vm_ops = {
8675 + .open = s1d15605_vma_open,
8676 + .close = s1d15605_vma_close,
8677 + .nopage = s1d15605_vma_nopage
8678 +};
8679 +
8680 +
8681 +/* We don't do much here - because we have special vm_ops */
8682 +static int s1d15605_mmap(struct fb_info *info, struct vm_area_struct *vma)
8683 +{
8684 + vma->vm_ops = &s1d15605_vm_ops;
8685 + vma->vm_flags |= VM_RESERVED;
8686 + vma->vm_private_data = info;
8687 + s1d15605_vma_open(vma);
8688 +
8689 + return 0;
8690 +}
8691 +#endif /* USE_PRIVATE_VMA_FXS */
8692 +
8693 +
8694 +static struct fb_ops s1d15605fb_ops = {
8695 + .owner = THIS_MODULE,
8696 + .fb_check_var = s1d15605_check_var,
8697 + .fb_set_par = s1d15605_set_par,
8698 + .fb_setcolreg = s1d15605_setcolreg,
8699 + .fb_blank = s1d15605_blank,
8700 +// .fb_pan_display = s1d15605_pan_display,
8701 + .fb_fillrect = s1d15605_fillrect,
8702 + .fb_copyarea = s1d15605_copyarea,
8703 + .fb_imageblit = s1d15605_imageblit,
8704 + .fb_write = s1d15605_write,
8705 +#ifdef USE_PRIVATE_VMA_FXS
8706 + .fb_mmap = s1d15605_mmap,
8707 +#endif
8708 +};
8709 +
8710 +
8711 +static void s1d15605_device_init(struct s1d15605fb_info *sinfo) {
8712 +
8713 + char value;
8714 +
8715 + /* release the reset line by reading the device - proto hardware */
8716 + value = READ_COMMAND;
8717 + value = READ_COMMAND;
8718 +
8719 +#ifdef CONFIG_MACH_KB9200
8720 + /* new boards have dedicated reset line */
8721 + gpio_set_value(sinfo->reset_pin, 1);
8722 +#endif
8723 +
8724 + /* initialize the device within 5ms */
8725 + WRITE_COMMAND(RESET_DISPLAY);
8726 + WRITE_COMMAND(LCD_BIAS_1_9);
8727 + WRITE_COMMAND(ADC_SELECT_REVERSE);
8728 + WRITE_COMMAND(COMMON_OUTPUT_NORMAL);
8729 + WRITE_COMMAND(V5_RESISTOR_RATIO);
8730 + WRITE_COMMAND(ELECTRONIC_VOLUME_SET);
8731 + WRITE_COMMAND(ELECTRONIC_VOLUME_INIT);
8732 + WRITE_COMMAND(POWER_CONTROL_SET | VOLTAGE_REGULATOR | VOLTAGE_FOLLOWER | BOOSTER_CIRCUIT);
8733 + WRITE_COMMAND(DISPLAY_ON);
8734 +
8735 + WRITE_COMMAND(RESISTOR_RATIO_START + 4);
8736 + WRITE_COMMAND(ELECTRONIC_VOLUME_SET);
8737 + WRITE_COMMAND(0x33);
8738 +}
8739 +
8740 +
8741 +static int s1d15605fb_probe(struct platform_device *pdev)
8742 +{
8743 + struct device *dev = &pdev->dev;
8744 + struct fb_info *info;
8745 + struct s1d15605fb_info *sinfo;
8746 + int ret;
8747 +
8748 + MSG("%s\n", __func__);
8749 +
8750 + if (!(info = framebuffer_alloc(sizeof(struct s1d15605fb_info), dev))) {
8751 + dev_err(dev, "Cannot allocate framebuffer struct\n");
8752 + return -ENOMEM;
8753 + }
8754 +
8755 + sinfo = info->par;
8756 + sinfo->info = info;
8757 + sinfo->pdev = pdev;
8758 +
8759 + if (pdev->num_resources < 2) {
8760 + dev_err(dev, "Resources unusable\n");
8761 + ret = -ENODEV;
8762 + goto free_info;
8763 + }
8764 +
8765 + info->fbops = &s1d15605fb_ops;
8766 + strcpy(info->fix.id, pdev->name);
8767 +
8768 + info->fix.mmio_start = pdev->resource[0].start;
8769 + info->fix.mmio_len = pdev->resource[0].end - pdev->resource[0].start + 1;
8770 + sinfo->reset_pin = pdev->resource[1].start;
8771 +
8772 + ret = s1d15605fb_resize_framebuffer(sinfo);
8773 + if (ret < 0) {
8774 + dev_err(dev, "Cannot resize framebuffer: %d\n", ret);
8775 + goto free_fb;
8776 + }
8777 +
8778 + if (!request_mem_region(info->fix.mmio_start,
8779 + info->fix.mmio_len, pdev->name)) {
8780 + ret = -EBUSY;
8781 + goto free_fb;
8782 + }
8783 +
8784 + sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
8785 + if (!sinfo->mmio) {
8786 + dev_err(dev, "Cannot map LCD memory region\n");
8787 + goto release_mem;
8788 + }
8789 +
8790 + s1d15605_device_init(sinfo);
8791 +
8792 + ret = fb_find_mode(&info->var, info, NULL, NULL, 0, NULL, 1);
8793 +
8794 + if (!ret || (ret == 4))
8795 + info->var = s1d15605_default;
8796 +
8797 + info->fix = s1d15605_fix;
8798 + info->flags = FBINFO_FLAG_DEFAULT |
8799 +/* FBINFO_HWACCEL_YPAN | */
8800 + FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
8801 +
8802 + ret = register_framebuffer(info);
8803 + if (ret < 0) {
8804 + dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
8805 + goto unmap_mmio;
8806 + }
8807 +
8808 + dev_set_drvdata(dev, info);
8809 +
8810 + memset(info->screen_base, 0, info->fix.smem_len);
8811 + info->var.activate |= FB_ACTIVATE_NOW;
8812 + ret = fb_set_var(info, &info->var);
8813 + if (ret) {
8814 + dev_warn(dev, "Unable to set display parameters\n");
8815 + }
8816 +
8817 + info->var.activate &= ~(FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW);
8818 +
8819 + dev_dbg(dev, "%s SUCCESS\n", __func__);
8820 +
8821 + dev_info(dev, "Driver $Revision: 1.1 $\n");
8822 +
8823 + return 0;
8824 +
8825 +unmap_mmio:
8826 + iounmap(sinfo->mmio);
8827 +release_mem:
8828 + release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
8829 +free_fb:
8830 + kfree(info->screen_base);
8831 +
8832 +free_info:
8833 + framebuffer_release(info);
8834 +
8835 + dev_dbg(dev, "%s FAILED\n", __func__);
8836 + return ret;
8837 +}
8838 +
8839 +
8840 +static int s1d15605fb_remove(struct platform_device *pdev)
8841 +{
8842 + struct device *dev = &pdev->dev;
8843 + struct fb_info *info = dev_get_drvdata(dev);
8844 + struct s1d15605fb_info *sinfo = info->par;
8845 +
8846 + if (!sinfo)
8847 + return 0;
8848 +
8849 + unregister_framebuffer(info);
8850 +
8851 + iounmap(sinfo->mmio);
8852 + release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
8853 +
8854 + kfree(info->screen_base);
8855 +
8856 + dev_set_drvdata(dev, NULL);
8857 + framebuffer_release(info);
8858 + return 0;
8859 +}
8860 +
8861 +
8862 +static struct platform_driver s1d15605fb_driver = {
8863 + .probe = s1d15605fb_probe,
8864 + .remove = s1d15605fb_remove,
8865 + .driver = {
8866 + .name = "s1d15605fb",
8867 + .owner = THIS_MODULE,
8868 + },
8869 +};
8870 +
8871 +
8872 +static int __init s1d15605fb_init(void)
8873 +{
8874 + return platform_driver_register(&s1d15605fb_driver);
8875 +}
8876 +
8877 +
8878 +static void __exit s1d15605fb_exit(void)
8879 +{
8880 + platform_driver_unregister(&s1d15605fb_driver);
8881 +}
8882 +
8883 +
8884 +module_init(s1d15605fb_init);
8885 +module_exit(s1d15605fb_exit);
8886 +
8887 +
8888 +MODULE_AUTHOR("KwikByte");
8889 +MODULE_DESCRIPTION("Epson S1D15605 LCD Controller framebuffer driver");
8890 +MODULE_LICENSE("GPL");
8891 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91_adc.h linux-2.6-stable/include/asm-arm/arch-at91/at91_adc.h
8892 --- linux-2.6.21/include/asm-arm/arch-at91/at91_adc.h Thu Jan 1 02:00:00 1970
8893 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91_adc.h Tue May 8 12:13:31 2007
8894 @@ -0,0 +1,61 @@
8895 +/*
8896 + * include/asm-arm/arch-at91/at91_adc.h
8897 + *
8898 + * Copyright (C) SAN People
8899 + *
8900 + * Analog-to-Digital Converter (ADC) registers.
8901 + * Based on AT91SAM9260 datasheet revision D.
8902 + *
8903 + * This program is free software; you can redistribute it and/or modify
8904 + * it under the terms of the GNU General Public License as published by
8905 + * the Free Software Foundation; either version 2 of the License, or
8906 + * (at your option) any later version.
8907 + */
8908 +
8909 +#ifndef AT91_ADC_H
8910 +#define AT91_ADC_H
8911 +
8912 +#define AT91_ADC_CR 0x00 /* Control Register */
8913 +#define AT91_ADC_SWRST (1 << 0) /* Software Reset */
8914 +#define AT91_ADC_START (1 << 1) /* Start Conversion */
8915 +
8916 +#define AT91_ADC_MR 0x04 /* Mode Register */
8917 +#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
8918 +#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
8919 +#define AT91_ADC_TRGSEL_TC0 (0 << 1)
8920 +#define AT91_ADC_TRGSEL_TC1 (1 << 1)
8921 +#define AT91_ADC_TRGSEL_TC2 (2 << 1)
8922 +#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
8923 +#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
8924 +#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
8925 +#define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */
8926 +#define AT91_ADC_PRESCAL_(x) ((x) << 8)
8927 +#define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */
8928 +#define AT91_ADC_STARTUP_(x) ((x) << 16)
8929 +#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
8930 +#define AT91_ADC_SHTIM_(x) ((x) << 24)
8931 +
8932 +#define AT91_ADC_CHER 0x10 /* Channel Enable Register */
8933 +#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
8934 +#define AT91_ADC_CHSR 0x18 /* Channel Status Register */
8935 +#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
8936 +
8937 +#define AT91_ADC_SR 0x1C /* Status Register */
8938 +#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
8939 +#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
8940 +#define AT91_ADC_DRDY (1 << 16) /* Data Ready */
8941 +#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
8942 +#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
8943 +#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
8944 +
8945 +#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
8946 +#define AT91_ADC_LDATA (0x3ff)
8947 +
8948 +#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
8949 +#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
8950 +#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
8951 +
8952 +#define AT91_ADC_CHR(n) (0x30 + ((n) * 4) /* Channel Data Register N */
8953 +#define AT91_ADC_DATA (0x3ff)
8954 +
8955 +#endif
8956 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91_mci.h linux-2.6-stable/include/asm-arm/arch-at91/at91_mci.h
8957 --- linux-2.6.21/include/asm-arm/arch-at91/at91_mci.h Thu Apr 26 05:08:32 2007
8958 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91_mci.h Tue May 8 12:13:31 2007
8959 @@ -26,6 +26,9 @@
8960 #define AT91_MCI_MR 0x04 /* Mode Register */
8961 #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
8962 #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
8963 +#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
8964 +#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
8965 +#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
8966 #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
8967 #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
8968 #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
8969 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91_pmc.h linux-2.6-stable/include/asm-arm/arch-at91/at91_pmc.h
8970 --- linux-2.6.21/include/asm-arm/arch-at91/at91_pmc.h Thu Apr 26 05:08:32 2007
8971 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91_pmc.h Fri May 11 16:45:00 2007
8972 @@ -37,7 +37,9 @@
8973 #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
8974 #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
8975
8976 -#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
8977 +#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL only] */
8978 +
8979 +#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
8980 #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
8981 #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
8982 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
8983 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91rm9200.h linux-2.6-stable/include/asm-arm/arch-at91/at91rm9200.h
8984 --- linux-2.6.21/include/asm-arm/arch-at91/at91rm9200.h Thu Apr 26 05:08:32 2007
8985 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91rm9200.h Tue May 8 12:56:33 2007
8986 @@ -107,185 +107,4 @@
8987 #define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
8988
8989
8990 -#if 0
8991 -/*
8992 - * PIO pin definitions (peripheral A/B multiplexing).
8993 - */
8994 -#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */
8995 -#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */
8996 -#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */
8997 -#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */
8998 -#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */
8999 -#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */
9000 -#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */
9001 -#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */
9002 -#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */
9003 -#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */
9004 -#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */
9005 -#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */
9006 -#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */
9007 -#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */
9008 -#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */
9009 -#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */
9010 -#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */
9011 -#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */
9012 -#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */
9013 -#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */
9014 -#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */
9015 -#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */
9016 -#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */
9017 -#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */
9018 -#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */
9019 -#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */
9020 -#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */
9021 -#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */
9022 -#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */
9023 -#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */
9024 -#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */
9025 -#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */
9026 -#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */
9027 -#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */
9028 -#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */
9029 -#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */
9030 -#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */
9031 -#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */
9032 -#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */
9033 -#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */
9034 -#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */
9035 -#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */
9036 -#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
9037 -#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */
9038 -#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */
9039 -#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */
9040 -#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */
9041 -#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */
9042 -#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */
9043 -#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */
9044 -#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */
9045 -#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */
9046 -#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */
9047 -#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */
9048 -#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */
9049 -#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */
9050 -#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */
9051 -#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */
9052 -#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */
9053 -#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */
9054 -#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */
9055 -#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */
9056 -#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */
9057 -#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */
9058 -
9059 -#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */
9060 -#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */
9061 -#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */
9062 -#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */
9063 -#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */
9064 -#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */
9065 -#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */
9066 -#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */
9067 -#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */
9068 -#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */
9069 -#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */
9070 -#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */
9071 -#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */
9072 -#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */
9073 -#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */
9074 -#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */
9075 -#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */
9076 -#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */
9077 -#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */
9078 -#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */
9079 -#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */
9080 -#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */
9081 -#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */
9082 -#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */
9083 -#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */
9084 -#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */
9085 -#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */
9086 -#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */
9087 -#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */
9088 -#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */
9089 -#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */
9090 -#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */
9091 -#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */
9092 -#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */
9093 -#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */
9094 -#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */
9095 -#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */
9096 -#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */
9097 -#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */
9098 -#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */
9099 -#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */
9100 -#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */
9101 -#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */
9102 -#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */
9103 -#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */
9104 -#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */
9105 -#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */
9106 -#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */
9107 -#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */
9108 -#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */
9109 -#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */
9110 -
9111 -#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */
9112 -#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */
9113 -#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */
9114 -#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */
9115 -#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */
9116 -#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */
9117 -#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */
9118 -#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */
9119 -#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */
9120 -#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */
9121 -#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */
9122 -#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
9123 -#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
9124 -#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */
9125 -
9126 -#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */
9127 -#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */
9128 -#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */
9129 -#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */
9130 -#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */
9131 -#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */
9132 -#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */
9133 -#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */
9134 -#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */
9135 -#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */
9136 -#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */
9137 -#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */
9138 -#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */
9139 -#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */
9140 -#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */
9141 -#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */
9142 -#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */
9143 -#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */
9144 -#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */
9145 -#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */
9146 -#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */
9147 -#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */
9148 -#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */
9149 -#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */
9150 -#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */
9151 -#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */
9152 -#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */
9153 -#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */
9154 -#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */
9155 -#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */
9156 -#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */
9157 -#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
9158 -#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */
9159 -#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */
9160 -#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */
9161 -#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */
9162 -#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */
9163 -#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */
9164 -#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */
9165 -#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */
9166 -#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
9167 -#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
9168 -#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
9169 -#endif
9170 -
9171 #endif
9172 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9260.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260.h
9173 --- linux-2.6.21/include/asm-arm/arch-at91/at91sam9260.h Thu Apr 26 05:08:32 2007
9174 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260.h Tue May 8 12:56:33 2007
9175 @@ -117,13 +117,4 @@
9176 #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
9177
9178
9179 -#if 0
9180 -/*
9181 - * PIO pin definitions (peripheral A/B multiplexing).
9182 - */
9183 -
9184 -// TODO: Add
9185 -
9186 -#endif
9187 -
9188 #endif
9189 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9260_matrix.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260_matrix.h
9190 --- linux-2.6.21/include/asm-arm/arch-at91/at91sam9260_matrix.h Thu Apr 26 05:08:32 2007
9191 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9260_matrix.h Fri May 11 16:20:33 2007
9192 @@ -67,7 +67,7 @@
9193 #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
9194 #define AT91_MATRIX_CS4A_SMC (0 << 4)
9195 #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
9196 -#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
9197 +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
9198 #define AT91_MATRIX_CS5A_SMC (0 << 5)
9199 #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
9200 #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
9201 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9261.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9261.h
9202 --- linux-2.6.21/include/asm-arm/arch-at91/at91sam9261.h Thu Apr 26 05:08:32 2007
9203 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9261.h Tue May 8 12:56:33 2007
9204 @@ -98,195 +98,4 @@
9205 #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
9206
9207
9208 -#if 0
9209 -/*
9210 - * PIO pin definitions (peripheral A/B multiplexing).
9211 - */
9212 -#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */
9213 -#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */
9214 -#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */
9215 -#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */
9216 -#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */
9217 -#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */
9218 -#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */
9219 -#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */
9220 -#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */
9221 -#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */
9222 -#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */
9223 -#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */
9224 -#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */
9225 -#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */
9226 -#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */
9227 -#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */
9228 -#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */
9229 -#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */
9230 -#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */
9231 -#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */
9232 -#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */
9233 -#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */
9234 -#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */
9235 -#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */
9236 -#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */
9237 -#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */
9238 -#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */
9239 -#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */
9240 -#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */
9241 -#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */
9242 -#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */
9243 -#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */
9244 -#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */
9245 -#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */
9246 -#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */
9247 -#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */
9248 -#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */
9249 -#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */
9250 -#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */
9251 -#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */
9252 -#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */
9253 -#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */
9254 -#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */
9255 -#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */
9256 -#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */
9257 -#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */
9258 -#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */
9259 -#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */
9260 -#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */
9261 -#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */
9262 -#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */
9263 -#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */
9264 -#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */
9265 -#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */
9266 -#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */
9267 -#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */
9268 -#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */
9269 -#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */
9270 -#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */
9271 -#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */
9272 -#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */
9273 -#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */
9274 -#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */
9275 -
9276 -#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */
9277 -#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */
9278 -#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */
9279 -#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */
9280 -#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */
9281 -#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */
9282 -#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */
9283 -#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */
9284 -#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */
9285 -#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */
9286 -#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */
9287 -#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */
9288 -#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */
9289 -#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */
9290 -#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */
9291 -#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */
9292 -#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */
9293 -#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */
9294 -#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */
9295 -#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */
9296 -#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */
9297 -#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */
9298 -#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */
9299 -#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */
9300 -#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */
9301 -#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */
9302 -#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */
9303 -#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */
9304 -#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */
9305 -#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */
9306 -#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */
9307 -#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */
9308 -#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */
9309 -#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */
9310 -#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */
9311 -#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */
9312 -#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */
9313 -#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */
9314 -#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */
9315 -#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */
9316 -#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */
9317 -#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */
9318 -#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */
9319 -#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */
9320 -#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */
9321 -#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */
9322 -#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */
9323 -#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */
9324 -#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */
9325 -#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */
9326 -#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */
9327 -#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */
9328 -#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */
9329 -#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */
9330 -#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */
9331 -#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */
9332 -#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */
9333 -#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */
9334 -#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */
9335 -#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */
9336 -#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */
9337 -
9338 -#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */
9339 -#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */
9340 -#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */
9341 -#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */
9342 -#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */
9343 -#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */
9344 -#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */
9345 -#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */
9346 -#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */
9347 -#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */
9348 -#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */
9349 -#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */
9350 -#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */
9351 -#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */
9352 -#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */
9353 -#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */
9354 -#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */
9355 -#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */
9356 -#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */
9357 -#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */
9358 -#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */
9359 -#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */
9360 -#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */
9361 -#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */
9362 -#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */
9363 -#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */
9364 -#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */
9365 -#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */
9366 -#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */
9367 -#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */
9368 -#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */
9369 -#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */
9370 -#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */
9371 -#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */
9372 -#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
9373 -#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */
9374 -#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
9375 -#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */
9376 -#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
9377 -#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */
9378 -#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
9379 -#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */
9380 -#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
9381 -#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */
9382 -#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
9383 -#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */
9384 -#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */
9385 -#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */
9386 -#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */
9387 -#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */
9388 -#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */
9389 -#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */
9390 -#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */
9391 -#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */
9392 -#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */
9393 -#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */
9394 -#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */
9395 -#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */
9396 -#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */
9397 -#endif
9398 -
9399 #endif
9400 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9263.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9263.h
9401 --- linux-2.6.21/include/asm-arm/arch-at91/at91sam9263.h Thu Apr 26 05:08:32 2007
9402 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9263.h Tue May 8 12:56:33 2007
9403 @@ -119,13 +119,5 @@
9404 #define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
9405 #define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
9406
9407 -#if 0
9408 -/*
9409 - * PIO pin definitions (peripheral A/B multiplexing).
9410 - */
9411 -
9412 -// TODO: Add
9413 -
9414 -#endif
9415
9416 #endif
9417 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9rl.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9rl.h
9418 --- linux-2.6.21/include/asm-arm/arch-at91/at91sam9rl.h Thu Jan 1 02:00:00 1970
9419 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9rl.h Fri May 11 14:53:48 2007
9420 @@ -0,0 +1,110 @@
9421 +/*
9422 + * include/asm-arm/arch-at91/at91sam9260.h
9423 + *
9424 + * Copyright (C) 2007 Atmel Corporation
9425 + *
9426 + * Common definitions.
9427 + * Based on AT91SAM9RL datasheet revision A. (Preliminary)
9428 + *
9429 + * This file is subject to the terms and conditions of the GNU General Public
9430 + * License. See the file COPYING in the main directory of this archive for
9431 + * more details.
9432 + */
9433 +
9434 +#ifndef AT91SAM9RL_H
9435 +#define AT91SAM9RL_H
9436 +
9437 +/*
9438 + * Peripheral identifiers/interrupts.
9439 + */
9440 +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
9441 +#define AT91_ID_SYS 1 /* System Controller */
9442 +#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
9443 +#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
9444 +#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
9445 +#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
9446 +#define AT91SAM9RL_ID_US0 6 /* USART 0 */
9447 +#define AT91SAM9RL_ID_US1 7 /* USART 1 */
9448 +#define AT91SAM9RL_ID_US2 8 /* USART 2 */
9449 +#define AT91SAM9RL_ID_US3 9 /* USART 3 */
9450 +#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
9451 +#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
9452 +#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
9453 +#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
9454 +#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
9455 +#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
9456 +#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
9457 +#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
9458 +#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
9459 +#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
9460 +#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
9461 +#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
9462 +#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
9463 +#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
9464 +#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
9465 +#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
9466 +
9467 +
9468 +/*
9469 + * User Peripheral physical base addresses.
9470 + */
9471 +#define AT91SAM9RL_BASE_TCB0 0xfffa0000
9472 +#define AT91SAM9RL_BASE_TC0 0xfffa0000
9473 +#define AT91SAM9RL_BASE_TC1 0xfffa0040
9474 +#define AT91SAM9RL_BASE_TC2 0xfffa0080
9475 +#define AT91SAM9RL_BASE_MCI 0xfffa4000
9476 +#define AT91SAM9RL_BASE_TWI0 0xfffa8000
9477 +#define AT91SAM9RL_BASE_TWI1 0xfffac000
9478 +#define AT91SAM9RL_BASE_US0 0xfffb0000
9479 +#define AT91SAM9RL_BASE_US1 0xfffb4000
9480 +#define AT91SAM9RL_BASE_US2 0xfffb8000
9481 +#define AT91SAM9RL_BASE_US3 0xfffbc000
9482 +#define AT91SAM9RL_BASE_SSC0 0xfffc0000
9483 +#define AT91SAM9RL_BASE_SSC1 0xfffc4000
9484 +#define AT91SAM9RL_BASE_PWMC 0xfffc8000
9485 +#define AT91SAM9RL_BASE_SPI 0xfffcc000
9486 +#define AT91SAM9RL_BASE_TSC 0xfffd0000
9487 +#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
9488 +#define AT91SAM9RL_BASE_AC97C 0xfffd8000
9489 +#define AT91_BASE_SYS 0xffffc000
9490 +
9491 +
9492 +/*
9493 + * System Peripherals (offset from AT91_BASE_SYS)
9494 + */
9495 +#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
9496 +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
9497 +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
9498 +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
9499 +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
9500 +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
9501 +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
9502 +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
9503 +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
9504 +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
9505 +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
9506 +#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
9507 +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
9508 +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
9509 +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
9510 +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
9511 +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
9512 +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
9513 +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
9514 +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
9515 +#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
9516 +
9517 +
9518 +/*
9519 + * Internal Memory.
9520 + */
9521 +#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
9522 +#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
9523 +
9524 +#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
9525 +#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
9526 +
9527 +#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
9528 +#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
9529 +
9530 +#endif
9531 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/at91sam9rl_matrix.h linux-2.6-stable/include/asm-arm/arch-at91/at91sam9rl_matrix.h
9532 --- linux-2.6.21/include/asm-arm/arch-at91/at91sam9rl_matrix.h Thu Jan 1 02:00:00 1970
9533 +++ linux-2.6-stable/include/asm-arm/arch-at91/at91sam9rl_matrix.h Fri May 11 16:18:45 2007
9534 @@ -0,0 +1,96 @@
9535 +/*
9536 + * include/asm-arm/arch-at91/at91sam9rl_matrix.h
9537 + *
9538 + * Copyright (C) 2007 Atmel Corporation
9539 + *
9540 + * Memory Controllers (MATRIX, EBI) - System peripherals registers.
9541 + * Based on AT91SAM9RL datasheet revision A. (Preliminary)
9542 + *
9543 + * This file is subject to the terms and conditions of the GNU General Public
9544 + * License. See the file COPYING in the main directory of this archive for
9545 + * more details.
9546 + */
9547 +
9548 +#ifndef AT91SAM9RL_MATRIX_H
9549 +#define AT91SAM9RL_MATRIX_H
9550 +
9551 +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
9552 +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
9553 +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
9554 +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
9555 +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
9556 +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
9557 +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
9558 +#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
9559 +#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
9560 +#define AT91_MATRIX_ULBT_FOUR (2 << 0)
9561 +#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
9562 +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
9563 +
9564 +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
9565 +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
9566 +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
9567 +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
9568 +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
9569 +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
9570 +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
9571 +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
9572 +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
9573 +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
9574 +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
9575 +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
9576 +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
9577 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
9578 +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
9579 +
9580 +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
9581 +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
9582 +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
9583 +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
9584 +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
9585 +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
9586 +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
9587 +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
9588 +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
9589 +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
9590 +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
9591 +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
9592 +
9593 +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
9594 +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
9595 +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
9596 +#define AT91_MATRIX_RCB2 (1 << 2)
9597 +#define AT91_MATRIX_RCB3 (1 << 3)
9598 +#define AT91_MATRIX_RCB4 (1 << 4)
9599 +#define AT91_MATRIX_RCB5 (1 << 5)
9600 +
9601 +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
9602 +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
9603 +#define AT91_MATRIX_ITCM_0 (0 << 0)
9604 +#define AT91_MATRIX_ITCM_16 (5 << 0)
9605 +#define AT91_MATRIX_ITCM_32 (6 << 0)
9606 +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
9607 +#define AT91_MATRIX_DTCM_0 (0 << 4)
9608 +#define AT91_MATRIX_DTCM_16 (5 << 4)
9609 +#define AT91_MATRIX_DTCM_32 (6 << 4)
9610 +
9611 +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
9612 +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
9613 +#define AT91_MATRIX_CS1A_SMC (0 << 1)
9614 +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
9615 +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
9616 +#define AT91_MATRIX_CS3A_SMC (0 << 3)
9617 +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
9618 +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
9619 +#define AT91_MATRIX_CS4A_SMC (0 << 4)
9620 +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
9621 +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
9622 +#define AT91_MATRIX_CS5A_SMC (0 << 5)
9623 +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
9624 +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
9625 +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
9626 +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
9627 +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
9628 +
9629 +
9630 +#endif
9631 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/board.h linux-2.6-stable/include/asm-arm/arch-at91/board.h
9632 --- linux-2.6.21/include/asm-arm/arch-at91/board.h Thu Apr 26 05:08:32 2007
9633 +++ linux-2.6-stable/include/asm-arm/arch-at91/board.h Thu May 10 12:21:10 2007
9634 @@ -62,7 +62,7 @@
9635 };
9636 extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
9637
9638 - /* Ethernet */
9639 + /* Ethernet (EMAC & MACB) */
9640 struct at91_eth_data {
9641 u8 phy_irq_pin; /* PHY IRQ */
9642 u8 is_rmii; /* using RMII interface? */
9643 @@ -114,9 +114,31 @@
9644 };
9645 extern void __init at91_add_device_serial(void);
9646
9647 + /* LCD Controller */
9648 +struct atmel_lcdfb_info;
9649 +extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
9650 +
9651 + /* AC97 */
9652 +struct atmel_ac97_data {
9653 + u8 reset_pin; /* reset */
9654 +};
9655 +extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
9656 +
9657 + /* ISI */
9658 +extern void __init at91_add_device_isi(void);
9659 +
9660 /* LEDs */
9661 extern u8 at91_leds_cpu;
9662 extern u8 at91_leds_timer;
9663 extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
9664
9665 +struct at91_gpio_led {
9666 + u8 index; /* index of LED */
9667 + char* name; /* name of LED */
9668 + u8 gpio; /* AT91_PIN_xx */
9669 + u8 flags; /* 1=active-high */
9670 + char* trigger; /* default trigger */
9671 +};
9672 +extern void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr);
9673 +
9674 #endif
9675 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/cpu.h linux-2.6-stable/include/asm-arm/arch-at91/cpu.h
9676 --- linux-2.6.21/include/asm-arm/arch-at91/cpu.h Thu Apr 26 05:08:32 2007
9677 +++ linux-2.6-stable/include/asm-arm/arch-at91/cpu.h Wed May 9 10:20:54 2007
9678 @@ -26,6 +26,8 @@
9679 #define ARCH_ID_AT91SAM9XE256 0x329a93a0
9680 #define ARCH_ID_AT91SAM9XE512 0x329aa3a0
9681
9682 +#define ARCH_ID_AT91SAM9RL64 0x019b03a0
9683 +
9684 static inline unsigned long at91_cpu_identify(void)
9685 {
9686 return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
9687 @@ -68,4 +70,10 @@
9688 #define cpu_is_at91sam9263() (0)
9689 #endif
9690
9691 +#ifdef CONFIG_ARCH_AT91SAM9RL
9692 +#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
9693 +#else
9694 +#define cpu_is_at91sam9rl() (0)
9695 +#endif
9696 +
9697 #endif
9698 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/hardware.h linux-2.6-stable/include/asm-arm/arch-at91/hardware.h
9699 --- linux-2.6.21/include/asm-arm/arch-at91/hardware.h Thu Apr 26 05:08:32 2007
9700 +++ linux-2.6-stable/include/asm-arm/arch-at91/hardware.h Fri May 11 14:45:12 2007
9701 @@ -24,6 +24,8 @@
9702 #include <asm/arch/at91sam9261.h>
9703 #elif defined(CONFIG_ARCH_AT91SAM9263)
9704 #include <asm/arch/at91sam9263.h>
9705 +#elif defined(CONFIG_ARCH_AT91SAM9RL)
9706 +#include <asm/arch/at91sam9rl.h>
9707 #else
9708 #error "Unsupported AT91 processor"
9709 #endif
9710 @@ -69,22 +71,5 @@
9711 /* Clocks */
9712 #define AT91_SLOW_CLOCK 32768 /* slow clock */
9713
9714 -#ifndef __ASSEMBLY__
9715 -#include <asm/io.h>
9716 -
9717 -static inline unsigned int at91_sys_read(unsigned int reg_offset)
9718 -{
9719 - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
9720 -
9721 - return __raw_readl(addr + reg_offset);
9722 -}
9723 -
9724 -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
9725 -{
9726 - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
9727 -
9728 - __raw_writel(value, addr + reg_offset);
9729 -}
9730 -#endif
9731
9732 #endif
9733 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/ics1523.h linux-2.6-stable/include/asm-arm/arch-at91/ics1523.h
9734 --- linux-2.6.21/include/asm-arm/arch-at91/ics1523.h Thu Jan 1 02:00:00 1970
9735 +++ linux-2.6-stable/include/asm-arm/arch-at91/ics1523.h Tue May 8 12:13:31 2007
9736 @@ -0,0 +1,154 @@
9737 +//*----------------------------------------------------------------------------
9738 +//* ATMEL Microcontroller Software Support - ROUSSET -
9739 +//*----------------------------------------------------------------------------
9740 +//* The software is delivered "AS IS" without warranty or condition of any
9741 +//* kind, either express, implied or statutory. This includes without
9742 +//* limitation any warranty or condition with respect to merchantability or
9743 +//* fitness for any particular purpose, or against the infringements of
9744 +//* intellectual property rights of others.
9745 +//*----------------------------------------------------------------------------
9746 +//* File Name : ics1523.h
9747 +//* Object : Clock Generator Prototyping File.
9748 +//*
9749 +//* 1.0 08/28/02 ED : Creation
9750 +//* 1.2 13/01/03 FB : Update on lib V3
9751 +//*----------------------------------------------------------------------------
9752 +
9753 +#ifndef ics1523_h
9754 +#define ics1523_h
9755 +
9756 +/*-------------------------------------------*/
9757 +/* ICS1523 TWI Serial Clock Definition */
9758 +/*-------------------------------------------*/
9759 +
9760 +#define ICS_MIN_CLOCK 100 /* Min Frequency Access Clock KHz */
9761 +#define ICS_MAX_CLOCK 400 /* Max Frequency Access Clock KHz */
9762 +#define ICS_TRANSFER_RATE ICS_MAX_CLOCK /* Transfer speed to apply */
9763 +
9764 +#define ICS_WRITE_CLK_PNB 30 /* TWCK Clock Periods required to write */
9765 +#define ICS_READ_CLK_PNB 40 /* TWCK Clock Periods required to read */
9766 +
9767 +/*-------------------------------------------*/
9768 +/* ICS1523 Write Operation Definition */
9769 +/*-------------------------------------------*/
9770 +
9771 +#define ICS1523_ACCESS_OK 0 /* OK */
9772 +#define ICS1523_ACCESS_ERROR -1 /* NOK */
9773 +
9774 +/*-------------------------------------------*/
9775 +/* ICS1523 Device Addresses Definition */
9776 +/*-------------------------------------------*/
9777 +
9778 +#define ICS_ADDR 0x26 /* Device Address */
9779 +
9780 +/*--------------------------------------------------*/
9781 +/* ICS1523 Registers Internal Addresses Definition */
9782 +/*--------------------------------------------------*/
9783 +
9784 +#define ICS_ICR 0x0 /* Input Control Register */
9785 +#define ICS_LCR 0x1 /* Loop Control Register */
9786 +#define ICS_FD0 0x2 /* PLL FeedBack Divider LSBs */
9787 +#define ICS_FD1 0x3 /* PLL FeedBack Divider MSBs */
9788 +#define ICS_DPAO 0x4 /* Dynamic Phase Aligner Offset */
9789 +#define ICS_DPAC 0x5 /* Dynamic Phase Aligner Resolution */
9790 +#define ICS_OE 0x6 /* Output Enables Register */
9791 +#define ICS_OD 0x7 /* Osc Divider Register */
9792 +#define ICS_SWRST 0x8 /* DPA & PLL Reset Register */
9793 +#define ICS_VID 0x10 /* Chip Version Register */
9794 +#define ICS_RID 0x11 /* Chip Revision Register */
9795 +#define ICS_SR 0x12 /* Status Register */
9796 +
9797 +/*------------------------------------------------------*/
9798 +/* ICS1523 Input Control Register Bits Definition */
9799 +/*------------------------------------------------------*/
9800 +
9801 +#define ICS_PDEN 0x1 /* Phase Detector Enable */
9802 +#define ICS_PDPOL 0x2 /* Phase Detector Enable Polarity */
9803 +#define ICS_REFPOL 0x4 /* External Reference Polarity */
9804 +#define ICS_FBKPOL 0x8 /* External Feedback Polarity */
9805 +#define ICS_FBKSEL 0x10 /* External Feedback Select */
9806 +#define ICS_FUNCSEL 0x20 /* Function Out Select */
9807 +#define ICS_ENPLS 0x40 /* Enable PLL Lock/Ref Status Output */
9808 +#define ICS_ENDLS 0x80 /* Enable DPA Lock/Ref Status Output */
9809 +
9810 +/*-----------------------------------------------------*/
9811 +/* ICS1523 Loop Control Register Bits Definition */
9812 +/*-----------------------------------------------------*/
9813 +
9814 +#define ICS_PFD 0x7 /* Phase Detector Gain */
9815 +#define ICS_PSD 0x30 /* Post-Scaler Divider */
9816 +
9817 +/*----------------------------------------------------*/
9818 +/* ICS1523 PLL FeedBack Divider LSBs Definition */
9819 +/*----------------------------------------------------*/
9820 +
9821 +#define ICS_FBDL 0xFF /* PLL FeedBack Divider LSBs */
9822 +
9823 +/*----------------------------------------------------*/
9824 +/* ICS1523 PLL FeedBack Divider MSBs Definition */
9825 +/*----------------------------------------------------*/
9826 +
9827 +#define ICS_FBDM 0xF /* PLL FeedBack Divider MSBs */
9828 +
9829 +/*------------------------------------------------------------*/
9830 +/* ICS1523 Dynamic Phase Aligner Offset Bits Definition */
9831 +/*------------------------------------------------------------*/
9832 +
9833 +#define ICS_DPAOS 0x2F /* Dynamic Phase Aligner Offset */
9834 +#define ICS_FILSEL 0x80 /* Loop Filter Select */
9835 +
9836 +/*----------------------------------------------------------------*/
9837 +/* ICS1523 Dynamic Phase Aligner Resolution Bits Definition */
9838 +/*----------------------------------------------------------------*/
9839 +
9840 +#define ICS_DPARES 0x3 /* Dynamic Phase Aligner Resolution */
9841 +#define ICS_MMREV 0xFC /* Metal Mask Revision Number */
9842 +
9843 +/*-------------------------------------------------------*/
9844 +/* ICS1523 Output Enables Register Bits Definition */
9845 +/*-------------------------------------------------------*/
9846 +
9847 +#define ICS_OEPCK 0x1 /* Output Enable for PECL PCLK Outputs */
9848 +#define ICS_OETCK 0x2 /* Output Enable for STTL CLK Output */
9849 +#define ICS_OEP2 0x4 /* Output Enable for PECL CLK/2 Outputs */
9850 +#define ICS_OET2 0x8 /* Output Enable for STTL CLK/2 Output */
9851 +#define ICS_OEF 0x10 /* Output Enable for STTL FUNC Output */
9852 +#define ICS_CLK2INV 0x20 /* CLK/2 Invert */
9853 +#define ICS_OSCL 0xC0 /* SSTL Clock Scaler */
9854 +
9855 +/*----------------------------------------------------*/
9856 +/* ICS1523 Osc Divider Register Bits Definition */
9857 +/*----------------------------------------------------*/
9858 +
9859 +#define ICS_OSCDIV 0x7F /* Oscillator Divider Modulus */
9860 +#define ICS_INSEL 0x80 /* Input Select */
9861 +
9862 +/*---------------------------------------------------*/
9863 +/* ICS1523 DPA & PLL Reset Register Definition */
9864 +/*---------------------------------------------------*/
9865 +
9866 +#define ICS_DPAR 0x0A /* DPA Reset Command */
9867 +#define ICS_PLLR 0x50 /* PLL Reset Command */
9868 +
9869 +/*------------------------------------------------*/
9870 +/* ICS1523 Chip Version Register Definition */
9871 +/*------------------------------------------------*/
9872 +
9873 +#define ICS_CHIPV 0xFF /* Chip Version */
9874 +
9875 +/*-------------------------------------------------*/
9876 +/* ICS1523 Chip Revision Register Definition */
9877 +/*-------------------------------------------------*/
9878 +
9879 +#define ICS_CHIPR 0xFF /* Chip Revision */
9880 +
9881 +/*------------------------------------------*/
9882 +/* ICS1523 Status Register Definition */
9883 +/*------------------------------------------*/
9884 +
9885 +#define ICS_DPALOCK 0x1 /* DPA Lock Status */
9886 +#define ICS_PLLLOCK 0x2 /* PLL Lock Status */
9887 +
9888 +int at91_ics1523_init(void);
9889 +
9890 +#endif /* ics1523_h */
9891 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/io.h linux-2.6-stable/include/asm-arm/arch-at91/io.h
9892 --- linux-2.6.21/include/asm-arm/arch-at91/io.h Thu Apr 26 05:08:32 2007
9893 +++ linux-2.6-stable/include/asm-arm/arch-at91/io.h Fri May 11 14:45:12 2007
9894 @@ -29,4 +29,22 @@
9895 #define __mem_pci(a) (a)
9896
9897
9898 +#ifndef __ASSEMBLY__
9899 +
9900 +static inline unsigned int at91_sys_read(unsigned int reg_offset)
9901 +{
9902 + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
9903 +
9904 + return __raw_readl(addr + reg_offset);
9905 +}
9906 +
9907 +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
9908 +{
9909 + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
9910 +
9911 + __raw_writel(value, addr + reg_offset);
9912 +}
9913 +
9914 +#endif
9915 +
9916 #endif
9917 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/irqs.h linux-2.6-stable/include/asm-arm/arch-at91/irqs.h
9918 --- linux-2.6.21/include/asm-arm/arch-at91/irqs.h Thu Apr 26 05:08:32 2007
9919 +++ linux-2.6-stable/include/asm-arm/arch-at91/irqs.h Fri May 11 14:45:12 2007
9920 @@ -21,6 +21,7 @@
9921 #ifndef __ASM_ARCH_IRQS_H
9922 #define __ASM_ARCH_IRQS_H
9923
9924 +#include <asm/io.h>
9925 #include <asm/arch/at91_aic.h>
9926
9927 #define NR_AIC_IRQS 32
9928 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/spi.h linux-2.6-stable/include/asm-arm/arch-at91/spi.h
9929 --- linux-2.6.21/include/asm-arm/arch-at91/spi.h Thu Jan 1 02:00:00 1970
9930 +++ linux-2.6-stable/include/asm-arm/arch-at91/spi.h Tue May 8 14:31:24 2007
9931 @@ -0,0 +1,54 @@
9932 +/*
9933 + * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200
9934 + *
9935 + * (c) SAN People (Pty) Ltd
9936 + *
9937 + * This program is free software; you can redistribute it and/or
9938 + * modify it under the terms of the GNU General Public License
9939 + * as published by the Free Software Foundation; either version
9940 + * 2 of the License, or (at your option) any later version.
9941 + */
9942 +
9943 +#ifndef AT91_LEGACY_SPI_H
9944 +#define AT91_LEGACY_SPI_H
9945 +
9946 +#define SPI_MAJOR 153 /* registered device number */
9947 +
9948 +#define DEFAULT_SPI_CLK 6000000
9949 +
9950 +
9951 +/* Maximum number of buffers in a single SPI transfer.
9952 + * DataFlash uses maximum of 2
9953 + * spidev interface supports up to 8.
9954 + */
9955 +#define MAX_SPI_TRANSFERS 8
9956 +#define NR_SPI_DEVICES 4 /* number of devices on SPI bus */
9957 +
9958 +/*
9959 + * Describes the buffers for a SPI transfer.
9960 + * A transmit & receive buffer must be specified for each transfer
9961 + */
9962 +struct spi_transfer_list {
9963 + void* tx[MAX_SPI_TRANSFERS]; /* transmit */
9964 + int txlen[MAX_SPI_TRANSFERS];
9965 + void* rx[MAX_SPI_TRANSFERS]; /* receive */
9966 + int rxlen[MAX_SPI_TRANSFERS];
9967 + int nr_transfers; /* number of transfers */
9968 + int curr; /* current transfer */
9969 +};
9970 +
9971 +struct spi_local {
9972 + unsigned int pcs; /* Peripheral Chip Select value */
9973 +
9974 + struct spi_transfer_list *xfers; /* current transfer list */
9975 + dma_addr_t tx, rx; /* DMA address for current transfer */
9976 + dma_addr_t txnext, rxnext; /* DMA address for next transfer */
9977 +};
9978 +
9979 +
9980 +/* Exported functions */
9981 +extern void spi_access_bus(short device);
9982 +extern void spi_release_bus(short device);
9983 +extern int spi_transfer(struct spi_transfer_list* list);
9984 +
9985 +#endif
9986 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/timex.h linux-2.6-stable/include/asm-arm/arch-at91/timex.h
9987 --- linux-2.6.21/include/asm-arm/arch-at91/timex.h Thu Apr 26 05:08:32 2007
9988 +++ linux-2.6-stable/include/asm-arm/arch-at91/timex.h Wed May 9 10:20:53 2007
9989 @@ -37,6 +37,11 @@
9990 #define AT91SAM9_MASTER_CLOCK 99959500
9991 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
9992
9993 +#elif defined(CONFIG_ARCH_AT91SAM9RL)
9994 +
9995 +#define AT91SAM9_MASTER_CLOCK 100000000
9996 +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
9997 +
9998 #endif
9999
10000 #endif
10001 diff -urN -x CVS linux-2.6.21/include/asm-arm/arch-at91/uncompress.h linux-2.6-stable/include/asm-arm/arch-at91/uncompress.h
10002 --- linux-2.6.21/include/asm-arm/arch-at91/uncompress.h Thu Apr 26 05:08:32 2007
10003 +++ linux-2.6-stable/include/asm-arm/arch-at91/uncompress.h Fri May 11 14:45:12 2007
10004 @@ -21,7 +21,7 @@
10005 #ifndef __ASM_ARCH_UNCOMPRESS_H
10006 #define __ASM_ARCH_UNCOMPRESS_H
10007
10008 -#include <asm/hardware.h>
10009 +#include <asm/io.h>
10010 #include <asm/arch/at91_dbgu.h>
10011
10012 /*
10013 diff -urN -x CVS linux-2.6.21/include/linux/clk.h linux-2.6-stable/include/linux/clk.h
10014 --- linux-2.6.21/include/linux/clk.h Thu Apr 26 05:08:32 2007
10015 +++ linux-2.6-stable/include/linux/clk.h Tue May 8 12:13:31 2007
10016 @@ -121,4 +121,24 @@
10017 */
10018 struct clk *clk_get_parent(struct clk *clk);
10019
10020 +/**
10021 + * clk_must_disable - report whether a clock's users must disable it
10022 + * @clk: one node in the clock tree
10023 + *
10024 + * This routine returns true only if the upcoming system state requires
10025 + * disabling the specified clock.
10026 + *
10027 + * It's common for platform power states to constrain certain clocks (and
10028 + * their descendants) to be unavailable, while other states allow that
10029 + * clock to be active. A platform's power states often include an "all on"
10030 + * mode; system wide sleep states like "standby" or "suspend-to-RAM"; and
10031 + * operating states which sacrifice functionality for lower power usage.
10032 + *
10033 + * The constraint value is commonly tested in device driver suspend(), to
10034 + * leave clocks active if they are needed for features like wakeup events.
10035 + * On platforms that support reduced functionality operating states, the
10036 + * constraint may also need to be tested during resume() and probe() calls.
10037 + */
10038 +int clk_must_disable(struct clk *clk);
10039 +
10040 #endif
10041 diff -urN -x CVS linux-2.6.21/include/linux/i2c-id.h linux-2.6-stable/include/linux/i2c-id.h
10042 --- linux-2.6.21/include/linux/i2c-id.h Thu Apr 26 05:08:32 2007
10043 +++ linux-2.6-stable/include/linux/i2c-id.h Tue May 8 12:13:31 2007
10044 @@ -202,6 +202,7 @@
10045
10046 /* --- PCA 9564 based algorithms */
10047 #define I2C_HW_A_ISA 0x1a0000 /* generic ISA Bus interface card */
10048 +#define I2C_HW_A_PLAT 0x1a0001 /* generic platform_bus interface */
10049
10050 /* --- ACPI Embedded controller algorithms */
10051 #define I2C_HW_ACPI_EC 0x1f0000
10052 diff -urN -x CVS linux-2.6.21/include/video/atmel_lcdc.h linux-2.6-stable/include/video/atmel_lcdc.h
10053 --- linux-2.6.21/include/video/atmel_lcdc.h Thu Jan 1 02:00:00 1970
10054 +++ linux-2.6-stable/include/video/atmel_lcdc.h Thu May 10 12:34:01 2007
10055 @@ -0,0 +1,196 @@
10056 +/*
10057 + * Header file for AT91/AT32 LCD Controller
10058 + *
10059 + * Data structure and register user interface
10060 + *
10061 + * Copyright (C) 2007 Atmel Corporation
10062 + *
10063 + * This program is free software; you can redistribute it and/or modify
10064 + * it under the terms of the GNU General Public License as published by
10065 + * the Free Software Foundation; either version 2 of the License, or
10066 + * (at your option) any later version.
10067 + *
10068 + * This program is distributed in the hope that it will be useful,
10069 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10070 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10071 + * GNU General Public License for more details.
10072 + *
10073 + * You should have received a copy of the GNU General Public License
10074 + * along with this program; if not, write to the Free Software
10075 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
10076 + */
10077 +#ifndef __ATMEL_LCDC_H__
10078 +#define __ATMEL_LCDC_H__
10079 +
10080 + /* LCD Controller info data structure */
10081 +struct atmel_lcdfb_info {
10082 + spinlock_t lock;
10083 + struct fb_info *info;
10084 + void __iomem *mmio;
10085 + unsigned long irq_base;
10086 +
10087 + unsigned int guard_time;
10088 + struct platform_device *pdev;
10089 + struct clk *bus_clk;
10090 + struct clk *lcdc_clk;
10091 + unsigned int default_bpp;
10092 + unsigned int default_lcdcon2;
10093 + unsigned int default_dmacon;
10094 + void (*atmel_lcdfb_power_control)(int on);
10095 + struct fb_monspecs *default_monspecs;
10096 + u32 pseudo_palette[16];
10097 +};
10098 +
10099 +#define ATMEL_LCDC_DMABADDR1 0x00
10100 +#define ATMEL_LCDC_DMABADDR2 0x04
10101 +#define ATMEL_LCDC_DMAFRMPT1 0x08
10102 +#define ATMEL_LCDC_DMAFRMPT2 0x0c
10103 +#define ATMEL_LCDC_DMAFRMADD1 0x10
10104 +#define ATMEL_LCDC_DMAFRMADD2 0x14
10105 +
10106 +#define ATMEL_LCDC_DMAFRMCFG 0x18
10107 +#define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
10108 +#define ATMEL_LCDC_BLENGTH_OFFSET 24
10109 +#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
10110 +
10111 +#define ATMEL_LCDC_DMACON 0x1c
10112 +#define ATMEL_LCDC_DMAEN (0x1 << 0)
10113 +#define ATMEL_LCDC_DMARST (0x1 << 1)
10114 +#define ATMEL_LCDC_DMABUSY (0x1 << 2)
10115 +#define ATMEL_LCDC_DMAUPDT (0x1 << 3)
10116 +#define ATMEL_LCDC_DMA2DEN (0x1 << 4)
10117 +
10118 +#define ATMEL_LCDC_DMA2DCFG 0x20
10119 +#define ATMEL_LCDC_ADDRINC_OFFSET 0
10120 +#define ATMEL_LCDC_ADDRINC (0xffff)
10121 +#define ATMEL_LCDC_PIXELOFF_OFFSET 24
10122 +#define ATMEL_LCDC_PIXELOFF (0x1f << 24)
10123 +
10124 +#define ATMEL_LCDC_LCDCON1 0x0800
10125 +#define ATMEL_LCDC_BYPASS (1 << 0)
10126 +#define ATMEL_LCDC_CLKVAL_OFFSET 12
10127 +#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
10128 +#define ATMEL_LCDC_LINCNT (0x7ff << 21)
10129 +
10130 +#define ATMEL_LCDC_LCDCON2 0x0804
10131 +#define ATMEL_LCDC_DISTYPE (3 << 0)
10132 +#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0)
10133 +#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0)
10134 +#define ATMEL_LCDC_DISTYPE_TFT (2 << 0)
10135 +#define ATMEL_LCDC_SCANMOD (1 << 2)
10136 +#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2)
10137 +#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2)
10138 +#define ATMEL_LCDC_IFWIDTH (3 << 3)
10139 +#define ATMEL_LCDC_IFWIDTH_4 (0 << 3)
10140 +#define ATMEL_LCDC_IFWIDTH_8 (1 << 3)
10141 +#define ATMEL_LCDC_IFWIDTH_16 (2 << 3)
10142 +#define ATMEL_LCDC_PIXELSIZE (7 << 5)
10143 +#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5)
10144 +#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5)
10145 +#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5)
10146 +#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5)
10147 +#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5)
10148 +#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5)
10149 +#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5)
10150 +#define ATMEL_LCDC_INVVD (1 << 8)
10151 +#define ATMEL_LCDC_INVVD_NORMAL (0 << 8)
10152 +#define ATMEL_LCDC_INVVD_INVERTED (1 << 8)
10153 +#define ATMEL_LCDC_INVFRAME (1 << 9 )
10154 +#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9)
10155 +#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9)
10156 +#define ATMEL_LCDC_INVLINE (1 << 10)
10157 +#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10)
10158 +#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10)
10159 +#define ATMEL_LCDC_INVCLK (1 << 11)
10160 +#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11)
10161 +#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11)
10162 +#define ATMEL_LCDC_INVDVAL (1 << 12)
10163 +#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12)
10164 +#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12)
10165 +#define ATMEL_LCDC_CLKMOD (1 << 15)
10166 +#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
10167 +#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
10168 +#define ATMEL_LCDC_MEMOR (1 << 31)
10169 +#define ATMEL_LCDC_MEMOR_BIG (0 << 31)
10170 +#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31)
10171 +
10172 +#define ATMEL_LCDC_TIM1 0x0808
10173 +#define ATMEL_LCDC_VFP (0xff << 0)
10174 +#define ATMEL_LCDC_VBP_OFFSET 8
10175 +#define ATMEL_LCDC_VBP (0xff << ATMEL_LCDC_VBP_OFFSET)
10176 +#define ATMEL_LCDC_VPW_OFFSET 16
10177 +#define ATMEL_LCDC_VPW (0x3f << ATMEL_LCDC_VPW_OFFSET)
10178 +#define ATMEL_LCDC_VHDLY_OFFSET 24
10179 +#define ATMEL_LCDC_VHDLY (0xf << ATMEL_LCDC_VHDLY_OFFSET)
10180 +
10181 +#define ATMEL_LCDC_TIM2 0x080c
10182 +#define ATMEL_LCDC_HBP (0xff << 0)
10183 +#define ATMEL_LCDC_HPW_OFFSET 8
10184 +#define ATMEL_LCDC_HPW (0x3f << ATMEL_LCDC_HPW_OFFSET)
10185 +#define ATMEL_LCDC_HFP_OFFSET 21
10186 +#define ATMEL_LCDC_HFP (0x7ff << ATMEL_LCDC_HFP_OFFSET)
10187 +
10188 +#define ATMEL_LCDC_LCDFRMCFG 0x0810
10189 +#define ATMEL_LCDC_LINEVAL (0x7ff << 0)
10190 +#define ATMEL_LCDC_HOZVAL_OFFSET 21
10191 +#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
10192 +
10193 +#define ATMEL_LCDC_FIFO 0x0814
10194 +#define ATMEL_LCDC_FIFOTH (0xffff)
10195 +
10196 +#define ATMEL_LCDC_MVAL 0x0818
10197 +
10198 +#define ATMEL_LCDC_DP1_2 0x081c
10199 +#define ATMEL_LCDC_DP4_7 0x0820
10200 +#define ATMEL_LCDC_DP3_5 0x0824
10201 +#define ATMEL_LCDC_DP2_3 0x0828
10202 +#define ATMEL_LCDC_DP5_7 0x082c
10203 +#define ATMEL_LCDC_DP3_4 0x0830
10204 +#define ATMEL_LCDC_DP4_5 0x0834
10205 +#define ATMEL_LCDC_DP6_7 0x0838
10206 +#define ATMEL_LCDC_DP1_2_VAL (0xff)
10207 +#define ATMEL_LCDC_DP4_7_VAL (0xfffffff)
10208 +#define ATMEL_LCDC_DP3_5_VAL (0xfffff)
10209 +#define ATMEL_LCDC_DP2_3_VAL (0xfff)
10210 +#define ATMEL_LCDC_DP5_7_VAL (0xfffffff)
10211 +#define ATMEL_LCDC_DP3_4_VAL (0xffff)
10212 +#define ATMEL_LCDC_DP4_5_VAL (0xfffff)
10213 +#define ATMEL_LCDC_DP6_7_VAL (0xfffffff)
10214 +
10215 +#define ATMEL_LCDC_PWRCON 0x083c
10216 +#define ATMEL_LCDC_PWR (1 << 0)
10217 +#define ATMEL_LCDC_GUARDT_OFFSET 1
10218 +#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET)
10219 +#define ATMEL_LCDC_BUSY (1 << 31)
10220 +
10221 +#define ATMEL_LCDC_CONTRAST_CTR 0x0840
10222 +#define ATMEL_LCDC_PS (3 << 0)
10223 +#define ATMEL_LCDC_PS_DIV1 (0 << 0)
10224 +#define ATMEL_LCDC_PS_DIV2 (1 << 0)
10225 +#define ATMEL_LCDC_PS_DIV4 (2 << 0)
10226 +#define ATMEL_LCDC_PS_DIV8 (3 << 0)
10227 +#define ATMEL_LCDC_POL (1 << 2)
10228 +#define ATMEL_LCDC_POL_NEGATIVE (0 << 2)
10229 +#define ATMEL_LCDC_POL_POSITIVE (1 << 2)
10230 +#define ATMEL_LCDC_ENA (1 << 3)
10231 +#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3)
10232 +#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3)
10233 +
10234 +#define ATMEL_LCDC_CONTRAST_VAL 0x0844
10235 +#define ATMEL_LCDC_CVAL (0xff)
10236 +
10237 +#define ATMEL_LCDC_IER 0x0848
10238 +#define ATMEL_LCDC_IDR 0x084c
10239 +#define ATMEL_LCDC_IMR 0x0850
10240 +#define ATMEL_LCDC_ISR 0x0854
10241 +#define ATMEL_LCDC_ICR 0x0858
10242 +#define ATMEL_LCDC_LNI (1 << 0)
10243 +#define ATMEL_LCDC_LSTLNI (1 << 1)
10244 +#define ATMEL_LCDC_EOFI (1 << 2)
10245 +#define ATMEL_LCDC_UFLWI (1 << 4)
10246 +#define ATMEL_LCDC_OWRI (1 << 5)
10247 +#define ATMEL_LCDC_MERI (1 << 6)
10248 +
10249 +#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4))
10250 +
10251 +#endif /* __ATMEL_LCDC_H__ */
10252 diff -urN -x CVS linux-2.6.21/sound/soc/at91/eti_b1_wm8731.c linux-2.6-stable/sound/soc/at91/eti_b1_wm8731.c
10253 --- linux-2.6.21/sound/soc/at91/eti_b1_wm8731.c Thu Apr 26 05:08:32 2007
10254 +++ linux-2.6-stable/sound/soc/at91/eti_b1_wm8731.c Tue May 8 12:13:58 2007
10255 @@ -34,8 +34,7 @@
10256 #include <sound/soc.h>
10257 #include <sound/soc-dapm.h>
10258
10259 -#include <asm/arch/hardware.h>
10260 -#include <asm/arch/at91_pio.h>
10261 +#include <asm/hardware.h>
10262 #include <asm/arch/gpio.h>
10263
10264 #include "../codecs/wm8731.h"
10265 @@ -48,13 +47,6 @@
10266 #define DBG(x...)
10267 #endif
10268
10269 -#define AT91_PIO_TF1 (1 << (AT91_PIN_PB6 - PIN_BASE) % 32)
10270 -#define AT91_PIO_TK1 (1 << (AT91_PIN_PB7 - PIN_BASE) % 32)
10271 -#define AT91_PIO_TD1 (1 << (AT91_PIN_PB8 - PIN_BASE) % 32)
10272 -#define AT91_PIO_RD1 (1 << (AT91_PIN_PB9 - PIN_BASE) % 32)
10273 -#define AT91_PIO_RK1 (1 << (AT91_PIN_PB10 - PIN_BASE) % 32)
10274 -#define AT91_PIO_RF1 (1 << (AT91_PIN_PB11 - PIN_BASE) % 32)
10275 -
10276 static struct clk *pck1_clk;
10277 static struct clk *pllb_clk;
10278
10279 @@ -277,7 +269,6 @@
10280 static int __init eti_b1_init(void)
10281 {
10282 int ret;
10283 - u32 ssc_pio_lines;
10284 struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data;
10285
10286 if (!request_mem_region(AT91RM9200_BASE_SSC1, SZ_16K, "soc-audio")) {
10287 @@ -311,19 +302,12 @@
10288 goto fail_io_unmap;
10289 }
10290
10291 - ssc_pio_lines = AT91_PIO_TF1 | AT91_PIO_TK1 | AT91_PIO_TD1
10292 - | AT91_PIO_RD1 /* | AT91_PIO_RK1 */ | AT91_PIO_RF1;
10293 -
10294 - /* Reset all PIO registers and assign lines to peripheral A */
10295 - at91_sys_write(AT91_PIOB + PIO_PDR, ssc_pio_lines);
10296 - at91_sys_write(AT91_PIOB + PIO_ODR, ssc_pio_lines);
10297 - at91_sys_write(AT91_PIOB + PIO_IFDR, ssc_pio_lines);
10298 - at91_sys_write(AT91_PIOB + PIO_CODR, ssc_pio_lines);
10299 - at91_sys_write(AT91_PIOB + PIO_IDR, ssc_pio_lines);
10300 - at91_sys_write(AT91_PIOB + PIO_MDDR, ssc_pio_lines);
10301 - at91_sys_write(AT91_PIOB + PIO_PUDR, ssc_pio_lines);
10302 - at91_sys_write(AT91_PIOB + PIO_ASR, ssc_pio_lines);
10303 - at91_sys_write(AT91_PIOB + PIO_OWDR, ssc_pio_lines);
10304 + at91_set_A_periph(AT91_PIN_PB6, 0); /* TF1 */
10305 + at91_set_A_periph(AT91_PIN_PB7, 0); /* TK1 */
10306 + at91_set_A_periph(AT91_PIN_PB8, 0); /* TD1 */
10307 + at91_set_A_periph(AT91_PIN_PB9, 0); /* RD1 */
10308 +/* at91_set_A_periph(AT91_PIN_PB10, 0);*/ /* RK1 */
10309 + at91_set_A_periph(AT91_PIN_PB11, 0); /* RF1 */
10310
10311 /*
10312 * Set PCK1 parent to PLLB and its rate to 12 Mhz.
Personal OpenWRT clone
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