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98195f55dbd41885335c96463579e9fc6f89b1eb
[openwrt.git] / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
2 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-10-02 21:19:59.000000000 +0200
4 @@ -0,0 +1,1212 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2006, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <bcmdefs.h>
20 +#include <osl.h>
21 +#include <bcmutils.h>
22 +#include <bcmsrom.h>
23 +#include <bcmdevs.h>
24 +#include <bcmendian.h>
25 +#include <sbpcmcia.h>
26 +#include <pcicfg.h>
27 +#include <sbutils.h>
28 +#include <bcmnvram.h>
29 +
30 +/* debug/trace */
31 +#if defined(WLTEST)
32 +#define BS_ERROR(args) printf args
33 +#else
34 +#define BS_ERROR(args)
35 +#endif /* BCMDBG_ERR || WLTEST */
36 +
37 +#define VARS_MAX 4096 /* should be reduced */
38 +
39 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
40 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
41 +
42 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
43 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
44 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
45 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
46 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
47 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
48 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
49 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
50 + bool check_crc);
51 +
52 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
53 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
54 +
55 +/*
56 + * Initialize local vars from the right source for this platform.
57 + * Return 0 on success, nonzero on error.
58 + */
59 +int
60 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
61 +{
62 + ASSERT(bustype == BUSTYPE(bustype));
63 + if (vars == NULL || count == NULL)
64 + return (0);
65 +
66 + switch (BUSTYPE(bustype)) {
67 + case SB_BUS:
68 + case JTAG_BUS:
69 + return initvars_flash_sb(sbh, vars, count);
70 +
71 + case PCI_BUS:
72 + ASSERT(curmap); /* can not be NULL */
73 + return initvars_srom_pci(sbh, curmap, vars, count);
74 +
75 + case PCMCIA_BUS:
76 + return initvars_cis_pcmcia(sbh, osh, vars, count);
77 +
78 +
79 + default:
80 + ASSERT(0);
81 + }
82 + return (-1);
83 +}
84 +
85 +/* support only 16-bit word read from srom */
86 +int
87 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
88 +{
89 + void *srom;
90 + uint i, off, nw;
91 +
92 + ASSERT(bustype == BUSTYPE(bustype));
93 +
94 + /* check input - 16-bit access only */
95 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
96 + return 1;
97 +
98 + off = byteoff / 2;
99 + nw = nbytes / 2;
100 +
101 + if (BUSTYPE(bustype) == PCI_BUS) {
102 + if (!curmap)
103 + return 1;
104 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
105 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
106 + return 1;
107 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
108 + for (i = 0; i < nw; i++) {
109 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
110 + return 1;
111 + }
112 + } else {
113 + return 1;
114 + }
115 +
116 + return 0;
117 +}
118 +
119 +/* support only 16-bit word write into srom */
120 +int
121 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
122 +{
123 + uint16 *srom;
124 + uint i, nw, crc_range;
125 + uint16 image[SPROM_SIZE];
126 + uint8 crc;
127 + volatile uint32 val32;
128 +
129 + ASSERT(bustype == BUSTYPE(bustype));
130 +
131 + /* check input - 16-bit access only */
132 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
133 + return 1;
134 +
135 + /* Are we writing the whole thing at once? */
136 + if ((byteoff == 0) &&
137 + ((nbytes == SPROM_SIZE) ||
138 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
139 + (nbytes == (SROM4_WORDS * 2)))) {
140 + crc_range = nbytes;
141 + bcopy((void*)buf, (void*)image, nbytes);
142 + nw = nbytes / 2;
143 + } else {
144 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
145 + crc_range = SPROM_SIZE;
146 + else
147 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
148 +
149 + nw = crc_range / 2;
150 + /* read first 64 words from srom */
151 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
152 + return 1;
153 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
154 + crc_range = SROM4_WORDS;
155 + nw = crc_range / 2;
156 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
157 + return 1;
158 + }
159 + /* make changes */
160 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
161 + }
162 +
163 + /* calculate crc */
164 + htol16_buf(image, crc_range);
165 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
166 + ltoh16_buf(image, crc_range);
167 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
168 +
169 + if (BUSTYPE(bustype) == PCI_BUS) {
170 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
171 + /* enable writes to the SPROM */
172 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
173 + val32 |= SPROM_WRITEEN;
174 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
175 + bcm_mdelay(WRITE_ENABLE_DELAY);
176 + /* write srom */
177 + for (i = 0; i < nw; i++) {
178 + W_REG(osh, &srom[i], image[i]);
179 + bcm_mdelay(WRITE_WORD_DELAY);
180 + }
181 + /* disable writes to the SPROM */
182 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
183 + ~SPROM_WRITEEN);
184 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
185 + /* enable writes to the SPROM */
186 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
187 + return 1;
188 + bcm_mdelay(WRITE_ENABLE_DELAY);
189 + /* write srom */
190 + for (i = 0; i < nw; i++) {
191 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
192 + bcm_mdelay(WRITE_WORD_DELAY);
193 + }
194 + /* disable writes to the SPROM */
195 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
196 + return 1;
197 + } else {
198 + return 1;
199 + }
200 +
201 + bcm_mdelay(WRITE_ENABLE_DELAY);
202 + return 0;
203 +}
204 +
205 +
206 +static int
207 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
208 +{
209 + char eabuf[32];
210 + char *vp, *base;
211 + uint8 *cis, tup, tlen, sromrev = 1;
212 + int i, j;
213 + uint varsize;
214 + bool ag_init = FALSE;
215 + uint32 w32;
216 +
217 + ASSERT(vars);
218 + ASSERT(count);
219 +
220 + base = vp = MALLOC(osh, VARS_MAX);
221 + ASSERT(vp);
222 + if (!vp)
223 + return -2;
224 +
225 + while (ciscnt--) {
226 + cis = *pcis++;
227 + i = 0;
228 + do {
229 + tup = cis[i++];
230 + tlen = cis[i++];
231 + if ((i + tlen) >= CIS_SIZE)
232 + break;
233 +
234 + switch (tup) {
235 + case CISTPL_MANFID:
236 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
237 + vp++;
238 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
239 + vp++;
240 + break;
241 +
242 + case CISTPL_FUNCE:
243 + switch (cis[i]) {
244 + case LAN_NID:
245 + ASSERT(cis[i + 1] == 6);
246 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
247 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
248 + vp++;
249 + break;
250 + case 1: /* SDIO Extended Data */
251 + vp += sprintf(vp, "sdmaxblk=%d",
252 + (cis[i + 13] << 8) | cis[i + 12]);
253 + vp++;
254 + break;
255 + }
256 + break;
257 +
258 + case CISTPL_CFTABLE:
259 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
260 + vp++;
261 + break;
262 +
263 + case CISTPL_BRCM_HNBU:
264 + switch (cis[i]) {
265 + case HNBU_SROMREV:
266 + sromrev = cis[i + 1];
267 + break;
268 +
269 + case HNBU_CHIPID:
270 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
271 + cis[i + 1]);
272 + vp++;
273 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
274 + cis[i + 3]);
275 + vp++;
276 + if (tlen == 7) {
277 + vp += sprintf(vp, "chiprev=%d",
278 + (cis[i + 6] << 8) + cis[i + 5]);
279 + vp++;
280 + }
281 + break;
282 +
283 + case HNBU_BOARDREV:
284 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
285 + vp++;
286 + break;
287 +
288 + case HNBU_AA:
289 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
290 + vp++;
291 + break;
292 +
293 + case HNBU_AG:
294 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
295 + vp++;
296 + ag_init = TRUE;
297 + break;
298 +
299 + case HNBU_CC:
300 + ASSERT(sromrev == 1);
301 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
302 + vp++;
303 + break;
304 +
305 + case HNBU_PAPARMS:
306 + if (tlen == 2) {
307 + ASSERT(sromrev == 1);
308 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
309 + vp++;
310 + } else if (tlen >= 9) {
311 + if (tlen == 10) {
312 + ASSERT(sromrev == 2);
313 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
314 + vp++;
315 + } else
316 + ASSERT(tlen == 9);
317 +
318 + for (j = 0; j < 3; j++) {
319 + vp += sprintf(vp, "pa0b%d=%d", j,
320 + (cis[i + (j * 2) + 2] << 8) +
321 + cis[i + (j * 2) + 1]);
322 + vp++;
323 + }
324 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
325 + vp++;
326 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
327 + vp++;
328 + } else
329 + ASSERT(tlen >= 9);
330 + break;
331 +
332 + case HNBU_OEM:
333 + ASSERT(sromrev == 1);
334 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
335 + cis[i + 1], cis[i + 2],
336 + cis[i + 3], cis[i + 4],
337 + cis[i + 5], cis[i + 6],
338 + cis[i + 7], cis[i + 8]);
339 + vp++;
340 + break;
341 +
342 + case HNBU_BOARDFLAGS:
343 + w32 = (cis[i + 2] << 8) + cis[i + 1];
344 + if (tlen == 5)
345 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
346 + vp += sprintf(vp, "boardflags=0x%x", w32);
347 + vp++;
348 + break;
349 +
350 + case HNBU_LEDS:
351 + if (cis[i + 1] != 0xff) {
352 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
353 + vp++;
354 + }
355 + if (cis[i + 2] != 0xff) {
356 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
357 + vp++;
358 + }
359 + if (cis[i + 3] != 0xff) {
360 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
361 + vp++;
362 + }
363 + if (cis[i + 4] != 0xff) {
364 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
365 + vp++;
366 + }
367 + break;
368 +
369 + case HNBU_CCODE:
370 + {
371 + char str[3];
372 + ASSERT(sromrev > 1);
373 + str[0] = cis[i + 1];
374 + str[1] = cis[i + 2];
375 + str[2] = 0;
376 + vp += sprintf(vp, "ccode=%s", str);
377 + vp++;
378 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
379 + vp++;
380 + break;
381 + }
382 +
383 + case HNBU_CCKPO:
384 + ASSERT(sromrev > 2);
385 + vp += sprintf(vp, "cckpo=0x%x",
386 + (cis[i + 2] << 8) | cis[i + 1]);
387 + vp++;
388 + break;
389 +
390 + case HNBU_OFDMPO:
391 + ASSERT(sromrev > 2);
392 + vp += sprintf(vp, "ofdmpo=0x%x",
393 + (cis[i + 4] << 24) |
394 + (cis[i + 3] << 16) |
395 + (cis[i + 2] << 8) |
396 + cis[i + 1]);
397 + vp++;
398 + break;
399 + }
400 + break;
401 +
402 + }
403 + i += tlen;
404 + } while (tup != 0xff);
405 + }
406 +
407 + /* Set the srom version */
408 + vp += sprintf(vp, "sromrev=%d", sromrev);
409 + vp++;
410 +
411 + /* if there is no antenna gain field, set default */
412 + if (ag_init == FALSE) {
413 + ASSERT(sromrev == 1);
414 + vp += sprintf(vp, "ag0=%d", 0xff);
415 + vp++;
416 + }
417 +
418 + /* final nullbyte terminator */
419 + *vp++ = '\0';
420 + varsize = (uint)(vp - base);
421 +
422 + ASSERT((vp - base) < VARS_MAX);
423 +
424 + if (varsize == VARS_MAX) {
425 + *vars = base;
426 + } else {
427 + vp = MALLOC(osh, varsize);
428 + ASSERT(vp);
429 + if (vp)
430 + bcopy(base, vp, varsize);
431 + MFREE(osh, base, VARS_MAX);
432 + *vars = vp;
433 + if (!vp) {
434 + *count = 0;
435 + return -2;
436 + }
437 + }
438 + *count = varsize;
439 +
440 + return (0);
441 +}
442 +
443 +
444 +/* set PCMCIA sprom command register */
445 +static int
446 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
447 +{
448 + uint8 status = 0;
449 + uint wait_cnt = 1000;
450 +
451 + /* write sprom command register */
452 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
453 +
454 + /* wait status */
455 + while (wait_cnt--) {
456 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
457 + if (status & SROM_DONE)
458 + return 0;
459 + }
460 +
461 + return 1;
462 +}
463 +
464 +/* read a word from the PCMCIA srom */
465 +static int
466 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
467 +{
468 + uint8 addr_l, addr_h, data_l, data_h;
469 +
470 + addr_l = (uint8)((addr * 2) & 0xff);
471 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
472 +
473 + /* set address */
474 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
475 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
476 +
477 + /* do read */
478 + if (sprom_cmd_pcmcia(osh, SROM_READ))
479 + return 1;
480 +
481 + /* read data */
482 + data_h = data_l = 0;
483 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
484 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
485 +
486 + *data = (data_h << 8) | data_l;
487 + return 0;
488 +}
489 +
490 +/* write a word to the PCMCIA srom */
491 +static int
492 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
493 +{
494 + uint8 addr_l, addr_h, data_l, data_h;
495 +
496 + addr_l = (uint8)((addr * 2) & 0xff);
497 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
498 + data_l = (uint8)(data & 0xff);
499 + data_h = (uint8)((data >> 8) & 0xff);
500 +
501 + /* set address */
502 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
503 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
504 +
505 + /* write data */
506 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
507 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
508 +
509 + /* do write */
510 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
511 +}
512 +
513 +/*
514 + * Read in and validate sprom.
515 + * Return 0 on success, nonzero on error.
516 + */
517 +static int
518 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
519 +{
520 + int err = 0;
521 + uint i;
522 +
523 + /* read the sprom */
524 + for (i = 0; i < nwords; i++)
525 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
526 +
527 + if (check_crc) {
528 + /* fixup the endianness so crc8 will pass */
529 + htol16_buf(buf, nwords * 2);
530 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
531 + err = 1;
532 + /* now correct the endianness of the byte array */
533 + ltoh16_buf(buf, nwords * 2);
534 + }
535 +
536 + return err;
537 +}
538 +
539 +/*
540 +* Create variable table from memory.
541 +* Return 0 on success, nonzero on error.
542 +*/
543 +static int
544 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
545 +{
546 + int c = (int)(end - start);
547 +
548 + /* do it only when there is more than just the null string */
549 + if (c > 1) {
550 + char *vp = MALLOC(osh, c);
551 + ASSERT(vp);
552 + if (!vp)
553 + return BCME_NOMEM;
554 + bcopy(start, vp, c);
555 + *vars = vp;
556 + *count = c;
557 + }
558 + else {
559 + *vars = NULL;
560 + *count = 0;
561 + }
562 +
563 + return 0;
564 +}
565 +
566 +/*
567 + * Find variables with <devpath> from flash. 'base' points to the beginning
568 + * of the table upon enter and to the end of the table upon exit when success.
569 + * Return 0 on success, nonzero on error.
570 + */
571 +static int
572 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
573 +{
574 + char *vp = *base;
575 + char *flash;
576 + int err;
577 + char *s;
578 + uint l, dl, copy_len;
579 +
580 + /* allocate memory and read in flash */
581 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
582 + return BCME_NOMEM;
583 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
584 + goto exit;
585 +
586 + /* grab vars with the <devpath> prefix in name */
587 + dl = strlen(devpath);
588 + for (s = flash; s && *s; s += l + 1) {
589 + l = strlen(s);
590 +
591 + /* skip non-matching variable */
592 + if (strncmp(s, devpath, dl))
593 + continue;
594 +
595 + /* is there enough room to copy? */
596 + copy_len = l - dl + 1;
597 + if (len < copy_len) {
598 + err = BCME_BUFTOOSHORT;
599 + goto exit;
600 + }
601 +
602 + /* no prefix, just the name=value */
603 + strcpy(vp, &s[dl]);
604 + vp += copy_len;
605 + len -= copy_len;
606 + }
607 +
608 + /* add null string as terminator */
609 + if (len < 1) {
610 + err = BCME_BUFTOOSHORT;
611 + goto exit;
612 + }
613 + *vp++ = '\0';
614 +
615 + *base = vp;
616 +
617 +exit: MFREE(osh, flash, NVRAM_SPACE);
618 + return err;
619 +}
620 +
621 +/*
622 + * Initialize nonvolatile variable table from flash.
623 + * Return 0 on success, nonzero on error.
624 + */
625 +static int
626 +initvars_flash_sb(void *sbh, char **vars, uint *count)
627 +{
628 + osl_t *osh = sb_osh(sbh);
629 + char devpath[SB_DEVPATH_BUFSZ];
630 + char *vp, *base;
631 + int err;
632 +
633 + ASSERT(vars);
634 + ASSERT(count);
635 +
636 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
637 + return err;
638 +
639 + base = vp = MALLOC(osh, VARS_MAX);
640 + ASSERT(vp);
641 + if (!vp)
642 + return BCME_NOMEM;
643 +
644 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
645 + goto err;
646 +
647 + err = initvars_table(osh, base, vp, vars, count);
648 +
649 +err: MFREE(osh, base, VARS_MAX);
650 + return err;
651 +}
652 +
653 +#ifdef WLTEST
654 +char mfgsromvars[256];
655 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
656 + "et0macaddr=00:11:22:33:44:52\0"
657 + "et1macaddr=00:11:22:33:44:53\0"
658 + "boardtype=0xffff\0"
659 + "boardrev=0x10\0"
660 + "boardflags=8\0"
661 + "sromrev=2\0"
662 + "aa2g=3";
663 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
664 +#endif /* WL_TEST */
665 +
666 +/*
667 + * Initialize nonvolatile variable table from sprom.
668 + * Return 0 on success, nonzero on error.
669 + */
670 +static int
671 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
672 +{
673 + uint16 w, *b;
674 + uint8 sromrev = 0;
675 + struct ether_addr ea;
676 + char eabuf[32];
677 + uint32 w32;
678 + int woff, i;
679 + char *vp, *base;
680 + osl_t *osh = sb_osh(sbh);
681 + bool flash = FALSE;
682 + char name[SB_DEVPATH_BUFSZ+16], *value;
683 + char devpath[SB_DEVPATH_BUFSZ];
684 + int err;
685 +
686 + /*
687 + * Apply CRC over SROM content regardless SROM is present or not,
688 + * and use variable <devpath>sromrev's existance in flash to decide
689 + * if we should return an error when CRC fails or read SROM variables
690 + * from flash.
691 + */
692 + b = MALLOC(osh, SROM_MAX);
693 + ASSERT(b);
694 + if (!b)
695 + return -2;
696 +
697 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
698 + 64, TRUE);
699 + if (err == 0) {
700 + /* srom is good and is rev < 4 */
701 + /* top word of sprom contains version and crc8 */
702 + sromrev = b[63] & 0xff;
703 + /* bcm4401 sroms misprogrammed */
704 + if (sromrev == 0x10)
705 + sromrev = 1;
706 + } else if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
707 + /* If sromrev >= 4, read more */
708 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
709 + SROM4_WORDS, TRUE);
710 + sromrev = b[SROM4_WORDS - 1] & 0xff;
711 + }
712 +
713 + if (err) {
714 +#ifdef WLTEST
715 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
716 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
717 + if (w32 & SPROM_OTPIN_USE) {
718 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
719 + vp = base = mfgsromvars;
720 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
721 + BS_ERROR(("setting the devid to be 4311\n"));
722 + vp += sprintf(vp, "devid=0x4311");
723 + vp++;
724 + }
725 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
726 + vp += MFGSROM_DEFVARSLEN;
727 + goto varsdone;
728 + } else {
729 + BS_ERROR(("srom crc failed with SPROM....\n"));
730 +#endif /* WLTEST */
731 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
732 + return err;
733 + sprintf(name, "%ssromrev", devpath);
734 + if (!(value = getvar(NULL, name)))
735 + return (-1);
736 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
737 + flash = TRUE;
738 +#ifdef WLTEST
739 + }
740 +#endif /* WLTEST */
741 + }
742 +
743 + /* srom version check */
744 + if (sromrev > 4)
745 + return (-2);
746 +
747 + ASSERT(vars);
748 + ASSERT(count);
749 +
750 + base = vp = MALLOC(osh, VARS_MAX);
751 + ASSERT(vp);
752 + if (!vp)
753 + return -2;
754 +
755 + /* read variables from flash */
756 + if (flash) {
757 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
758 + goto err;
759 + goto varsdone;
760 + }
761 +
762 + vp += sprintf(vp, "sromrev=%d", sromrev);
763 + vp++;
764 +
765 + if (sromrev >= 4) {
766 + uint path, pathbase;
767 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
768 + SROM4_PATH2, SROM4_PATH3};
769 +
770 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
771 + vp++;
772 +
773 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
774 + vp++;
775 +
776 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
777 + vp++;
778 +
779 + /* The macaddr */
780 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
781 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
782 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
783 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
784 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
785 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
786 + bcm_ether_ntoa(&ea, eabuf);
787 + vp += sprintf(vp, "macaddr=%s", eabuf);
788 + vp++;
789 +
790 + w = b[SROM4_CCODE];
791 + if (w == 0)
792 + vp += sprintf(vp, "ccode=");
793 + else
794 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
795 + vp++;
796 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
797 + vp++;
798 +
799 + w = b[SROM4_LEDBH10];
800 + if ((w != 0) && (w != 0xffff)) {
801 + /* ledbh0 */
802 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
803 + vp++;
804 +
805 + /* ledbh1 */
806 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
807 + vp++;
808 + }
809 + w = b[SROM4_LEDBH32];
810 + if ((w != 0) && (w != 0xffff)) {
811 + /* ledbh2 */
812 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
813 + vp++;
814 +
815 + /* ledbh3 */
816 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
817 + vp++;
818 + }
819 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
820 + w = b[SROM4_LEDDC];
821 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
822 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
823 + vp += sprintf(vp, "leddc=%d", w32);
824 + vp++;
825 +
826 + w = b[SROM4_AA];
827 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
828 + vp++;
829 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
830 + vp++;
831 +
832 + w = b[SROM4_AG10];
833 + vp += sprintf(vp, "ag0=%d", w & 0xff);
834 + vp++;
835 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
836 + vp++;
837 + w = b[SROM4_AG32];
838 + vp += sprintf(vp, "ag2=%d", w & 0xff);
839 + vp++;
840 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
841 + vp++;
842 +
843 + /* Fixed power indices when power control is disabled */
844 + for (i = 0; i < 2; i++) {
845 + w = b[SROM4_TXPID2G + i];
846 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
847 + vp++;
848 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
849 + vp++;
850 + w = b[SROM4_TXPID5G + i];
851 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
852 + vp++;
853 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
854 + vp++;
855 + w = b[SROM4_TXPID5GL + i];
856 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
857 + vp++;
858 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
859 + vp++;
860 + w = b[SROM4_TXPID5GH + i];
861 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
862 + vp++;
863 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
864 + vp++;
865 + }
866 +
867 + /* Per path variables */
868 + for (path = 0; path < MAX_PATH; path++) {
869 + pathbase = pathbases[path];
870 + w = b[pathbase + SROM4_2G_ITT_MAXP];
871 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
872 + vp++;
873 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
874 + vp++;
875 +
876 + for (i = 0; i < 4; i++) {
877 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
878 + b[pathbase + SROM4_2G_PA + i]);
879 + vp++;
880 + }
881 +
882 + w = b[pathbase + SROM4_5G_ITT_MAXP];
883 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
884 + vp++;
885 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
886 + vp++;
887 +
888 + w = b[pathbase + SROM4_5GLH_MAXP];
889 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
890 + vp++;
891 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
892 + vp++;
893 +
894 + for (i = 0; i < 4; i++) {
895 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
896 + b[pathbase + SROM4_5G_PA + i]);
897 + vp++;
898 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
899 + b[pathbase + SROM4_5GL_PA + i]);
900 + vp++;
901 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
902 + b[pathbase + SROM4_5GH_PA + i]);
903 + vp++;
904 + }
905 + }
906 +
907 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
908 + vp++;
909 +
910 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
911 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
912 + vp++;
913 +
914 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
915 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
916 + vp++;
917 +
918 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
919 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
920 + vp++;
921 +
922 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
923 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
924 + vp++;
925 +
926 + for (i = 0; i < 8; i++) {
927 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
928 + vp++;
929 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
930 + vp++;
931 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
932 + vp++;
933 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
934 + vp++;
935 + }
936 +
937 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
938 + vp++;
939 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
940 + vp++;
941 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
942 + vp++;
943 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
944 + vp++;
945 +
946 + goto done;
947 + }
948 + if (sromrev >= 3) {
949 + /* New section takes over the 3th hardware function space */
950 +
951 + /* Words 22+23 are 11a (mid) ofdm power offsets */
952 + w32 = ((uint32)b[23] << 16) | b[22];
953 + vp += sprintf(vp, "ofdmapo=%d", w32);
954 + vp++;
955 +
956 + /* Words 24+25 are 11a (low) ofdm power offsets */
957 + w32 = ((uint32)b[25] << 16) | b[24];
958 + vp += sprintf(vp, "ofdmalpo=%d", w32);
959 + vp++;
960 +
961 + /* Words 26+27 are 11a (high) ofdm power offsets */
962 + w32 = ((uint32)b[27] << 16) | b[26];
963 + vp += sprintf(vp, "ofdmahpo=%d", w32);
964 + vp++;
965 +
966 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
967 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
968 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
969 + vp += sprintf(vp, "leddc=%d", w32);
970 +
971 + vp++;
972 + }
973 +
974 + if (sromrev >= 2) {
975 + /* New section takes over the 4th hardware function space */
976 +
977 + /* Word 29 is max power 11a high/low */
978 + w = b[29];
979 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
980 + vp++;
981 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
982 + vp++;
983 +
984 + /* Words 30-32 set the 11alow pa settings,
985 + * 33-35 are the 11ahigh ones.
986 + */
987 + for (i = 0; i < 3; i++) {
988 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
989 + vp++;
990 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
991 + vp++;
992 + }
993 + w = b[59];
994 + if (w == 0)
995 + vp += sprintf(vp, "ccode=");
996 + else
997 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
998 + vp++;
999 +
1000 + }
1001 +
1002 + /* parameter section of sprom starts at byte offset 72 */
1003 + woff = 72/2;
1004 +
1005 + /* first 6 bytes are il0macaddr */
1006 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1007 + ea.octet[1] = b[woff] & 0xff;
1008 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1009 + ea.octet[3] = b[woff+1] & 0xff;
1010 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1011 + ea.octet[5] = b[woff+2] & 0xff;
1012 + woff += 3;
1013 + bcm_ether_ntoa(&ea, eabuf);
1014 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1015 + vp++;
1016 +
1017 + /* next 6 bytes are et0macaddr */
1018 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1019 + ea.octet[1] = b[woff] & 0xff;
1020 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1021 + ea.octet[3] = b[woff+1] & 0xff;
1022 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1023 + ea.octet[5] = b[woff+2] & 0xff;
1024 + woff += 3;
1025 + bcm_ether_ntoa(&ea, eabuf);
1026 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1027 + vp++;
1028 +
1029 + /* next 6 bytes are et1macaddr */
1030 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1031 + ea.octet[1] = b[woff] & 0xff;
1032 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1033 + ea.octet[3] = b[woff+1] & 0xff;
1034 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1035 + ea.octet[5] = b[woff+2] & 0xff;
1036 + woff += 3;
1037 + bcm_ether_ntoa(&ea, eabuf);
1038 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1039 + vp++;
1040 +
1041 + /*
1042 + * Enet phy settings one or two singles or a dual
1043 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1044 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1045 + * Bit 14 : Mdio for enet0
1046 + * Bit 15 : Mdio for enet1
1047 + */
1048 + w = b[woff];
1049 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1050 + vp++;
1051 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1052 + vp++;
1053 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1054 + vp++;
1055 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1056 + vp++;
1057 +
1058 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1059 + w = b[46];
1060 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1061 + vp++;
1062 +
1063 + if (sromrev > 1)
1064 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1065 + else
1066 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1067 + vp++;
1068 +
1069 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1070 + vp++;
1071 +
1072 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1073 + vp++;
1074 +
1075 + /* Words 47-49 set the (wl) pa settings */
1076 + woff = 47;
1077 +
1078 + for (i = 0; i < 3; i++) {
1079 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1080 + vp++;
1081 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1082 + vp++;
1083 + }
1084 +
1085 + /*
1086 + * Words 50-51 set the customer-configured wl led behavior.
1087 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1088 + * LED behavior values defined in wlioctl.h .
1089 + */
1090 + w = b[50];
1091 + if ((w != 0) && (w != 0xffff)) {
1092 + /* ledbh0 */
1093 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1094 + vp++;
1095 +
1096 + /* ledbh1 */
1097 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1098 + vp++;
1099 + }
1100 + w = b[51];
1101 + if ((w != 0) && (w != 0xffff)) {
1102 + /* ledbh2 */
1103 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1104 + vp++;
1105 +
1106 + /* ledbh */
1107 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1108 + vp++;
1109 + }
1110 +
1111 + /* Word 52 is max power 0/1 */
1112 + w = b[52];
1113 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1114 + vp++;
1115 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1116 + vp++;
1117 +
1118 + /* Word 56 is idle tssi target 0/1 */
1119 + w = b[56];
1120 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1121 + vp++;
1122 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1123 + vp++;
1124 +
1125 + /* Word 57 is boardflags, if not programmed make it zero */
1126 + w32 = (uint32)b[57];
1127 + if (w32 == 0xffff) w32 = 0;
1128 + if (sromrev > 1) {
1129 + /* Word 28 is the high bits of boardflags */
1130 + w32 |= (uint32)b[28] << 16;
1131 + }
1132 + vp += sprintf(vp, "boardflags=%d", w32);
1133 + vp++;
1134 +
1135 + /* Word 58 is antenna gain 0/1 */
1136 + w = b[58];
1137 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1138 + vp++;
1139 +
1140 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1141 + vp++;
1142 +
1143 + if (sromrev == 1) {
1144 + /* set the oem string */
1145 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1146 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1147 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1148 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1149 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1150 + vp++;
1151 + } else if (sromrev == 2) {
1152 + /* Word 60 OFDM tx power offset from CCK level */
1153 + /* OFDM Power Offset - opo */
1154 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1155 + vp++;
1156 + } else {
1157 + /* Word 60: cck power offsets */
1158 + vp += sprintf(vp, "cckpo=%d", b[60]);
1159 + vp++;
1160 +
1161 + /* Words 61+62: 11g ofdm power offsets */
1162 + w32 = ((uint32)b[62] << 16) | b[61];
1163 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1164 + vp++;
1165 + }
1166 +
1167 + /* final nullbyte terminator */
1168 +done: *vp++ = '\0';
1169 +
1170 + ASSERT((vp - base) <= VARS_MAX);
1171 +
1172 +varsdone:
1173 + err = initvars_table(osh, base, vp, vars, count);
1174 +
1175 +err:
1176 +#ifdef WLTEST
1177 + if (base != mfgsromvars)
1178 +#endif
1179 + MFREE(osh, base, VARS_MAX);
1180 + MFREE(osh, b, SROM_MAX);
1181 + return err;
1182 +}
1183 +
1184 +/*
1185 + * Read the cis and call parsecis to initialize the vars.
1186 + * Return 0 on success, nonzero on error.
1187 + */
1188 +static int
1189 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1190 +{
1191 + uint8 *cis = NULL;
1192 + int rc;
1193 + uint data_sz;
1194 +
1195 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1196 +
1197 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1198 + return (-2);
1199 +
1200 + if (sb_pcmciarev(sbh) == 1) {
1201 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1202 + MFREE(osh, cis, data_sz);
1203 + return (-1);
1204 + }
1205 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1206 + ltoh16_buf((uint16 *)cis, data_sz);
1207 + } else
1208 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1209 +
1210 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1211 +
1212 + MFREE(osh, cis, data_sz);
1213 +
1214 + return (rc);
1215 +}
1216 +
1217 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1218 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1219 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-10-02 21:19:59.000000000 +0200
1220 @@ -0,0 +1,247 @@
1221 +/*
1222 + * Misc useful OS-independent routines.
1223 + *
1224 + * Copyright 2006, Broadcom Corporation
1225 + * All Rights Reserved.
1226 + *
1227 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1228 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1229 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1230 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1231 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1232 + */
1233 +
1234 +#include <typedefs.h>
1235 +#include <bcmdefs.h>
1236 +#include <stdarg.h>
1237 +#include <bcmutils.h>
1238 +#include <osl.h>
1239 +#include <sbutils.h>
1240 +#include <bcmnvram.h>
1241 +#include <bcmendian.h>
1242 +#include <bcmdevs.h>
1243 +
1244 +unsigned char bcm_ctype[] = {
1245 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1246 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1247 + _BCM_C, /* 8-15 */
1248 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1249 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1250 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1251 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1252 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1253 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1254 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1255 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1256 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1257 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1258 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1259 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1260 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1261 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1262 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1263 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1264 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1265 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1266 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1267 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1268 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1269 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1270 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1271 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1272 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1273 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1274 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1275 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1276 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1277 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1278 +};
1279 +
1280 +
1281 +ulong
1282 +bcm_strtoul(char *cp, char **endp, uint base)
1283 +{
1284 + ulong result, value;
1285 + bool minus;
1286 +
1287 + minus = FALSE;
1288 +
1289 + while (bcm_isspace(*cp))
1290 + cp++;
1291 +
1292 + if (cp[0] == '+')
1293 + cp++;
1294 + else if (cp[0] == '-') {
1295 + minus = TRUE;
1296 + cp++;
1297 + }
1298 +
1299 + if (base == 0) {
1300 + if (cp[0] == '0') {
1301 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1302 + base = 16;
1303 + cp = &cp[2];
1304 + } else {
1305 + base = 8;
1306 + cp = &cp[1];
1307 + }
1308 + } else
1309 + base = 10;
1310 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1311 + cp = &cp[2];
1312 + }
1313 +
1314 + result = 0;
1315 +
1316 + while (bcm_isxdigit(*cp) &&
1317 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1318 + result = result*base + value;
1319 + cp++;
1320 + }
1321 +
1322 + if (minus)
1323 + result = (ulong)(result * -1);
1324 +
1325 + if (endp)
1326 + *endp = (char *)cp;
1327 +
1328 + return (result);
1329 +}
1330 +
1331 +uchar
1332 +bcm_toupper(uchar c)
1333 +{
1334 + if (bcm_islower(c))
1335 + c -= 'a'-'A';
1336 + return (c);
1337 +}
1338 +
1339 +char*
1340 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1341 +{
1342 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1343 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1344 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1345 + return (buf);
1346 +}
1347 +
1348 +
1349 +/*
1350 + * Search the name=value vars for a specific one and return its value.
1351 + * Returns NULL if not found.
1352 + */
1353 +char*
1354 +getvar(char *vars, char *name)
1355 +{
1356 + char *s;
1357 + int len;
1358 +
1359 + len = strlen(name);
1360 +
1361 + /* first look in vars[] */
1362 + for (s = vars; s && *s;) {
1363 + /* CSTYLED */
1364 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1365 + return (&s[len+1]);
1366 +
1367 + while (*s++)
1368 + ;
1369 + }
1370 +
1371 + /* then query nvram */
1372 + return (nvram_get(name));
1373 +}
1374 +
1375 +/*
1376 + * Search the vars for a specific one and return its value as
1377 + * an integer. Returns 0 if not found.
1378 + */
1379 +int
1380 +getintvar(char *vars, char *name)
1381 +{
1382 + char *val;
1383 +
1384 + if ((val = getvar(vars, name)) == NULL)
1385 + return (0);
1386 +
1387 + return (bcm_strtoul(val, NULL, 0));
1388 +}
1389 +
1390 +
1391 +/*******************************************************************************
1392 + * crc8
1393 + *
1394 + * Computes a crc8 over the input data using the polynomial:
1395 + *
1396 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1397 + *
1398 + * The caller provides the initial value (either CRC8_INIT_VALUE
1399 + * or the previous returned value) to allow for processing of
1400 + * discontiguous blocks of data. When generating the CRC the
1401 + * caller is responsible for complementing the final return value
1402 + * and inserting it into the byte stream. When checking, a final
1403 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1404 + *
1405 + * Reference: Dallas Semiconductor Application Note 27
1406 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1407 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1408 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1409 + *
1410 + * ****************************************************************************
1411 + */
1412 +
1413 +static uint8 crc8_table[256] = {
1414 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1415 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1416 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1417 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1418 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1419 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1420 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1421 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1422 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1423 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1424 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1425 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1426 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1427 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1428 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1429 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1430 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1431 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1432 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1433 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1434 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1435 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1436 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1437 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1438 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1439 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1440 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1441 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1442 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1443 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1444 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1445 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1446 +};
1447 +
1448 +#define CRC_INNER_LOOP(n, c, x) \
1449 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1450 +
1451 +uint8
1452 +hndcrc8(
1453 + uint8 *pdata, /* pointer to array of data to process */
1454 + uint nbytes, /* number of input data bytes to process */
1455 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1456 +)
1457 +{
1458 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1459 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1460 + */
1461 + while (nbytes-- > 0)
1462 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1463 +
1464 + return crc;
1465 +}
1466 +
1467 +
1468 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1469 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1470 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-10-02 21:19:59.000000000 +0200
1471 @@ -0,0 +1,234 @@
1472 +/*
1473 + * NVRAM variable manipulation (Linux kernel half)
1474 + *
1475 + * Copyright 2001-2003, Broadcom Corporation
1476 + * All Rights Reserved.
1477 + *
1478 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1479 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1480 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1481 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1482 + *
1483 + * $Id$
1484 + */
1485 +
1486 +#include <linux/config.h>
1487 +#include <linux/init.h>
1488 +#include <linux/module.h>
1489 +#include <linux/kernel.h>
1490 +#include <linux/string.h>
1491 +#include <asm/io.h>
1492 +#include <asm/uaccess.h>
1493 +
1494 +#include <typedefs.h>
1495 +#include <osl.h>
1496 +#include <bcmendian.h>
1497 +#include <bcmutils.h>
1498 +
1499 +#define NVRAM_SIZE (0x1ff0)
1500 +static char _nvdata[NVRAM_SIZE] __initdata;
1501 +static char _valuestr[256] __initdata;
1502 +
1503 +/*
1504 + * TLV types. These codes are used in the "type-length-value"
1505 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1506 + *
1507 + * The layout of the flash/nvram is as follows:
1508 + *
1509 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1510 + *
1511 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1512 + * The "length" field marks the length of the data section, not
1513 + * including the type and length fields.
1514 + *
1515 + * Environment variables are stored as follows:
1516 + *
1517 + * <type_env> <length> <flags> <name> = <value>
1518 + *
1519 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1520 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1521 + *
1522 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1523 + * indicates the size of the length field.
1524 + *
1525 + * Flags are from the constants below:
1526 + *
1527 + */
1528 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1529 +#define ENV_LENGTH_8BITS 0x01
1530 +
1531 +#define ENV_TYPE_USER 0x80
1532 +
1533 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1534 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1535 +
1536 +/*
1537 + * The actual TLV types we support
1538 + */
1539 +
1540 +#define ENV_TLV_TYPE_END 0x00
1541 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1542 +
1543 +/*
1544 + * Environment variable flags
1545 + */
1546 +
1547 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1548 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1549 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1550 +
1551 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1552 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1553 +
1554 +
1555 +/* *********************************************************************
1556 + * _nvram_read(buffer,offset,length)
1557 + *
1558 + * Read data from the NVRAM device
1559 + *
1560 + * Input parameters:
1561 + * buffer - destination buffer
1562 + * offset - offset of data to read
1563 + * length - number of bytes to read
1564 + *
1565 + * Return value:
1566 + * number of bytes read, or <0 if error occured
1567 + ********************************************************************* */
1568 +static int
1569 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1570 +{
1571 + int i;
1572 + if (offset > NVRAM_SIZE)
1573 + return -1;
1574 +
1575 + for ( i = 0; i < length; i++) {
1576 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1577 + }
1578 + return length;
1579 +}
1580 +
1581 +
1582 +static char*
1583 +_strnchr(const char *dest,int c,size_t cnt)
1584 +{
1585 + while (*dest && (cnt > 0)) {
1586 + if (*dest == c) return (char *) dest;
1587 + dest++;
1588 + cnt--;
1589 + }
1590 + return NULL;
1591 +}
1592 +
1593 +
1594 +
1595 +/*
1596 + * Core support API: Externally visible.
1597 + */
1598 +
1599 +/*
1600 + * Get the value of an NVRAM variable
1601 + * @param name name of variable to get
1602 + * @return value of variable or NULL if undefined
1603 + */
1604 +
1605 +char*
1606 +cfe_env_get(unsigned char *nv_buf, char* name)
1607 +{
1608 + int size;
1609 + unsigned char *buffer;
1610 + unsigned char *ptr;
1611 + unsigned char *envval;
1612 + unsigned int reclen;
1613 + unsigned int rectype;
1614 + int offset;
1615 + int flg;
1616 +
1617 + size = NVRAM_SIZE;
1618 + buffer = &_nvdata[0];
1619 +
1620 + ptr = buffer;
1621 + offset = 0;
1622 +
1623 + /* Read the record type and length */
1624 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1625 + goto error;
1626 + }
1627 +
1628 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1629 +
1630 + /* Adjust pointer for TLV type */
1631 + rectype = *(ptr);
1632 + offset++;
1633 + size--;
1634 +
1635 + /*
1636 + * Read the length. It can be either 1 or 2 bytes
1637 + * depending on the code
1638 + */
1639 + if (rectype & ENV_LENGTH_8BITS) {
1640 + /* Read the record type and length - 8 bits */
1641 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1642 + goto error;
1643 + }
1644 + reclen = *(ptr);
1645 + size--;
1646 + offset++;
1647 + }
1648 + else {
1649 + /* Read the record type and length - 16 bits, MSB first */
1650 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1651 + goto error;
1652 + }
1653 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1654 + size -= 2;
1655 + offset += 2;
1656 + }
1657 +
1658 + if (reclen > size)
1659 + break; /* should not happen, bad NVRAM */
1660 +
1661 + switch (rectype) {
1662 + case ENV_TLV_TYPE_ENV:
1663 + /* Read the TLV data */
1664 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1665 + goto error;
1666 + flg = *ptr++;
1667 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1668 + if (envval) {
1669 + *envval++ = '\0';
1670 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1671 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1672 +#if 0
1673 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1674 +#endif
1675 + if(!strcmp(ptr, name)){
1676 + return _valuestr;
1677 + }
1678 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1679 + return _valuestr;
1680 + }
1681 + break;
1682 +
1683 + default:
1684 + /* Unknown TLV type, skip it. */
1685 + break;
1686 + }
1687 +
1688 + /*
1689 + * Advance to next TLV
1690 + */
1691 +
1692 + size -= (int)reclen;
1693 + offset += reclen;
1694 +
1695 + /* Read the next record type */
1696 + ptr = buffer;
1697 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1698 + goto error;
1699 + }
1700 +
1701 +error:
1702 + return NULL;
1703 +
1704 +}
1705 +
1706 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1707 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1708 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-10-02 21:19:59.000000000 +0200
1709 @@ -0,0 +1,33 @@
1710 +#
1711 +# Makefile for Broadcom BCM947XX boards
1712 +#
1713 +# Copyright 2001-2003, Broadcom Corporation
1714 +# All Rights Reserved.
1715 +#
1716 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1717 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1718 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1719 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1720 +#
1721 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1722 +#
1723 +
1724 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1725 +SYSTEM ?= $(TOPDIR)/vmlinux
1726 +
1727 +all: vmlinuz
1728 +
1729 +# Don't build dependencies, this may die if $(CC) isn't gcc
1730 +dep:
1731 +
1732 +# Create a gzipped version named vmlinuz for compatibility
1733 +vmlinuz: piggy
1734 + gzip -c9 $< > $@
1735 +
1736 +piggy: $(SYSTEM)
1737 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1738 +
1739 +mrproper: clean
1740 +
1741 +clean:
1742 + rm -f vmlinuz piggy
1743 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1744 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1745 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-10-02 21:19:59.000000000 +0200
1746 @@ -0,0 +1,70 @@
1747 +#include <linux/module.h>
1748 +
1749 +#define _export(n) \
1750 + void n(void); \
1751 + EXPORT_SYMBOL(n);
1752 +
1753 +_export(bcm947xx_sbh)
1754 +
1755 +_export(sb_attach)
1756 +_export(sb_kattach)
1757 +_export(sb_boardtype)
1758 +_export(sb_boardvendor)
1759 +_export(sb_btcgpiowar)
1760 +_export(sb_bus)
1761 +_export(sb_chip)
1762 +_export(sb_chiprev)
1763 +_export(sb_chipcrev)
1764 +_export(sb_chippkg)
1765 +_export(sb_clkctl_clk)
1766 +_export(sb_clkctl_fast_pwrup_delay)
1767 +_export(sb_clkctl_init)
1768 +_export(sb_clkctl_xtal)
1769 +_export(sb_core_disable)
1770 +_export(sb_core_reset)
1771 +_export(sb_core_tofixup)
1772 +_export(sb_coreflags)
1773 +_export(sb_coreflagshi)
1774 +_export(sb_coreidx)
1775 +_export(sb_coreregs)
1776 +_export(sb_corerev)
1777 +_export(sb_coreunit)
1778 +_export(sb_detach)
1779 +_export(sb_deviceremoved)
1780 +_export(sb_gpiosetcore)
1781 +_export(sb_gpiocontrol)
1782 +_export(sb_gpiointmask)
1783 +_export(sb_gpiointpolarity)
1784 +_export(sb_gpioled)
1785 +_export(sb_gpioin)
1786 +_export(sb_gpioout)
1787 +_export(sb_gpioouten)
1788 +_export(sb_gpiotimerval)
1789 +_export(sb_irq)
1790 +_export(sb_iscoreup)
1791 +_export(sb_pci_setup)
1792 +_export(sb_pcirev)
1793 +_export(sb_pcmcia_init)
1794 +_export(sb_pcmciarev)
1795 +_export(sb_register_intr_callback)
1796 +_export(sb_setcore)
1797 +_export(sb_setcoreidx)
1798 +_export(sb_war16165)
1799 +_export(sb_osh)
1800 +
1801 +_export(getvar)
1802 +_export(getintvar)
1803 +_export(bcm_strtoul)
1804 +_export(bcm_ctype)
1805 +_export(bcm_toupper)
1806 +_export(bcm_ether_ntoa)
1807 +
1808 +_export(nvram_get)
1809 +_export(nvram_getall)
1810 +_export(nvram_set)
1811 +_export(nvram_unset)
1812 +_export(nvram_commit)
1813 +
1814 +_export(srom_read)
1815 +_export(srom_write)
1816 +
1817 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1818 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1819 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-10-02 21:19:59.000000000 +0200
1820 @@ -0,0 +1,51 @@
1821 +/*
1822 + * Generic interrupt handler for Broadcom MIPS boards
1823 + *
1824 + * Copyright 2004, Broadcom Corporation
1825 + * All Rights Reserved.
1826 + *
1827 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1828 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1829 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1830 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1831 + *
1832 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1833 + */
1834 +
1835 +#include <linux/config.h>
1836 +
1837 +#include <asm/asm.h>
1838 +#include <asm/mipsregs.h>
1839 +#include <asm/regdef.h>
1840 +#include <asm/stackframe.h>
1841 +
1842 +/*
1843 + * MIPS IRQ Source
1844 + * -------- ------
1845 + * 0 Software (ignored)
1846 + * 1 Software (ignored)
1847 + * 2 Combined hardware interrupt (hw0)
1848 + * 3 Hardware
1849 + * 4 Hardware
1850 + * 5 Hardware
1851 + * 6 Hardware
1852 + * 7 R4k timer
1853 + */
1854 +
1855 + .text
1856 + .set noreorder
1857 + .set noat
1858 + .align 5
1859 + NESTED(brcmIRQ, PT_SIZE, sp)
1860 + SAVE_ALL
1861 + CLI
1862 + .set at
1863 + .set noreorder
1864 +
1865 + jal brcm_irq_dispatch
1866 + move a0, sp
1867 +
1868 + j ret_from_irq
1869 + nop
1870 +
1871 + END(brcmIRQ)
1872 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1873 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1874 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-10-02 21:19:59.000000000 +0200
1875 @@ -0,0 +1,130 @@
1876 +/*
1877 + * Generic interrupt control functions for Broadcom MIPS boards
1878 + *
1879 + * Copyright 2004, Broadcom Corporation
1880 + * All Rights Reserved.
1881 + *
1882 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1883 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1884 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1885 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1886 + *
1887 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1888 + */
1889 +
1890 +#include <linux/config.h>
1891 +#include <linux/init.h>
1892 +#include <linux/kernel.h>
1893 +#include <linux/types.h>
1894 +#include <linux/interrupt.h>
1895 +#include <linux/irq.h>
1896 +
1897 +#include <asm/irq.h>
1898 +#include <asm/mipsregs.h>
1899 +#include <asm/gdb-stub.h>
1900 +
1901 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1902 +
1903 +extern asmlinkage void brcmIRQ(void);
1904 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1905 +
1906 +void
1907 +brcm_irq_dispatch(struct pt_regs *regs)
1908 +{
1909 + u32 cause;
1910 +
1911 + cause = read_c0_cause() &
1912 + read_c0_status() &
1913 + CAUSEF_IP;
1914 +
1915 +#ifdef CONFIG_KERNPROF
1916 + change_c0_status(cause | 1, 1);
1917 +#else
1918 + clear_c0_status(cause);
1919 +#endif
1920 +
1921 + if (cause & CAUSEF_IP7)
1922 + do_IRQ(7, regs);
1923 + if (cause & CAUSEF_IP2)
1924 + do_IRQ(2, regs);
1925 + if (cause & CAUSEF_IP3)
1926 + do_IRQ(3, regs);
1927 + if (cause & CAUSEF_IP4)
1928 + do_IRQ(4, regs);
1929 + if (cause & CAUSEF_IP5)
1930 + do_IRQ(5, regs);
1931 + if (cause & CAUSEF_IP6)
1932 + do_IRQ(6, regs);
1933 +}
1934 +
1935 +static void
1936 +enable_brcm_irq(unsigned int irq)
1937 +{
1938 + if (irq < 8)
1939 + set_c0_status(1 << (irq + 8));
1940 + else
1941 + set_c0_status(IE_IRQ0);
1942 +}
1943 +
1944 +static void
1945 +disable_brcm_irq(unsigned int irq)
1946 +{
1947 + if (irq < 8)
1948 + clear_c0_status(1 << (irq + 8));
1949 + else
1950 + clear_c0_status(IE_IRQ0);
1951 +}
1952 +
1953 +static void
1954 +ack_brcm_irq(unsigned int irq)
1955 +{
1956 + /* Already done in brcm_irq_dispatch */
1957 +}
1958 +
1959 +static unsigned int
1960 +startup_brcm_irq(unsigned int irq)
1961 +{
1962 + enable_brcm_irq(irq);
1963 +
1964 + return 0; /* never anything pending */
1965 +}
1966 +
1967 +static void
1968 +end_brcm_irq(unsigned int irq)
1969 +{
1970 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1971 + enable_brcm_irq(irq);
1972 +}
1973 +
1974 +static struct hw_interrupt_type brcm_irq_type = {
1975 + typename: "MIPS",
1976 + startup: startup_brcm_irq,
1977 + shutdown: disable_brcm_irq,
1978 + enable: enable_brcm_irq,
1979 + disable: disable_brcm_irq,
1980 + ack: ack_brcm_irq,
1981 + end: end_brcm_irq,
1982 + NULL
1983 +};
1984 +
1985 +void __init
1986 +init_IRQ(void)
1987 +{
1988 + int i;
1989 +
1990 + for (i = 0; i < NR_IRQS; i++) {
1991 + irq_desc[i].status = IRQ_DISABLED;
1992 + irq_desc[i].action = 0;
1993 + irq_desc[i].depth = 1;
1994 + irq_desc[i].handler = &brcm_irq_type;
1995 + }
1996 +
1997 + set_except_vector(0, brcmIRQ);
1998 + change_c0_status(ST0_IM, ALLINTS);
1999 +
2000 +#ifdef CONFIG_REMOTE_DEBUG
2001 + printk("Breaking into debugger...\n");
2002 + set_debug_traps();
2003 + breakpoint();
2004 +#endif
2005 +}
2006 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
2007 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
2008 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-10-02 21:26:29.000000000 +0200
2009 @@ -0,0 +1,12 @@
2010 +#
2011 +# Makefile for the BCM947xx specific kernel interface routines
2012 +# under Linux.
2013 +#
2014 +EXTRA_CFLAGS += -fno-delayed-branch
2015 +USE_STANDARD_AS_RULE := true
2016 +
2017 +O_TARGET := brcm.o
2018 +
2019 +obj-y := int-handler.o irq.o
2020 +
2021 +include $(TOPDIR)/Rules.make
2022 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2023 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2024 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-10-02 21:19:59.000000000 +0200
2025 @@ -0,0 +1,159 @@
2026 +/*
2027 + * GPIO char driver
2028 + *
2029 + * Copyright 2005, Broadcom Corporation
2030 + * All Rights Reserved.
2031 + *
2032 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2033 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2034 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2035 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2036 + *
2037 + * $Id$
2038 + */
2039 +
2040 +#include <linux/module.h>
2041 +#include <linux/init.h>
2042 +#include <linux/fs.h>
2043 +#include <linux/miscdevice.h>
2044 +#include <asm/uaccess.h>
2045 +
2046 +#include <typedefs.h>
2047 +#include <osl.h>
2048 +#include <bcmutils.h>
2049 +#include <sbutils.h>
2050 +#include <bcmdevs.h>
2051 +
2052 +static sb_t *gpio_sbh;
2053 +static int gpio_major;
2054 +static devfs_handle_t gpio_dir;
2055 +static struct {
2056 + char *name;
2057 + devfs_handle_t handle;
2058 +} gpio_file[] = {
2059 + { "in", NULL },
2060 + { "out", NULL },
2061 + { "outen", NULL },
2062 + { "control", NULL }
2063 +};
2064 +
2065 +static int
2066 +gpio_open(struct inode *inode, struct file * file)
2067 +{
2068 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2069 + return -ENODEV;
2070 +
2071 + MOD_INC_USE_COUNT;
2072 + return 0;
2073 +}
2074 +
2075 +static int
2076 +gpio_release(struct inode *inode, struct file * file)
2077 +{
2078 + MOD_DEC_USE_COUNT;
2079 + return 0;
2080 +}
2081 +
2082 +static ssize_t
2083 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2084 +{
2085 + u32 val;
2086 +
2087 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2088 + case 0:
2089 + val = sb_gpioin(gpio_sbh);
2090 + break;
2091 + case 1:
2092 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2093 + break;
2094 + case 2:
2095 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2096 + break;
2097 + case 3:
2098 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2099 + break;
2100 + default:
2101 + return -ENODEV;
2102 + }
2103 +
2104 + if (put_user(val, (u32 *) buf))
2105 + return -EFAULT;
2106 +
2107 + return sizeof(val);
2108 +}
2109 +
2110 +static ssize_t
2111 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2112 +{
2113 + u32 val;
2114 +
2115 + if (get_user(val, (u32 *) buf))
2116 + return -EFAULT;
2117 +
2118 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2119 + case 0:
2120 + return -EACCES;
2121 + case 1:
2122 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2123 + break;
2124 + case 2:
2125 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2126 + break;
2127 + case 3:
2128 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2129 + break;
2130 + default:
2131 + return -ENODEV;
2132 + }
2133 +
2134 + return sizeof(val);
2135 +}
2136 +
2137 +static struct file_operations gpio_fops = {
2138 + owner: THIS_MODULE,
2139 + open: gpio_open,
2140 + release: gpio_release,
2141 + read: gpio_read,
2142 + write: gpio_write,
2143 +};
2144 +
2145 +static int __init
2146 +gpio_init(void)
2147 +{
2148 + int i;
2149 +
2150 + if (!(gpio_sbh = sb_kattach()))
2151 + return -ENODEV;
2152 +
2153 + sb_gpiosetcore(gpio_sbh);
2154 +
2155 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2156 + return gpio_major;
2157 +
2158 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2159 +
2160 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2161 + gpio_file[i].handle = devfs_register(gpio_dir,
2162 + gpio_file[i].name,
2163 + DEVFS_FL_DEFAULT, gpio_major, i,
2164 + S_IFCHR | S_IRUGO | S_IWUGO,
2165 + &gpio_fops, NULL);
2166 + }
2167 +
2168 + return 0;
2169 +}
2170 +
2171 +static void __exit
2172 +gpio_exit(void)
2173 +{
2174 + int i;
2175 +
2176 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2177 + devfs_unregister(gpio_file[i].handle);
2178 + devfs_unregister(gpio_dir);
2179 + devfs_unregister_chrdev(gpio_major, "gpio");
2180 + sb_detach(gpio_sbh);
2181 +}
2182 +
2183 +module_init(gpio_init);
2184 +module_exit(gpio_exit);
2185 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2186 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2187 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-10-02 21:19:59.000000000 +0200
2188 @@ -0,0 +1,158 @@
2189 +/*
2190 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2191 + *
2192 + * Copyright 2006, Broadcom Corporation
2193 + * All Rights Reserved.
2194 + *
2195 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2196 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2197 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2198 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2199 + *
2200 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2201 + */
2202 +
2203 +#include <typedefs.h>
2204 +#include <bcmdefs.h>
2205 +#include <osl.h>
2206 +#include <bcmutils.h>
2207 +#include <sbutils.h>
2208 +#include <bcmdevs.h>
2209 +#include <bcmnvram.h>
2210 +#include <sbconfig.h>
2211 +#include <sbextif.h>
2212 +#include <sbchipc.h>
2213 +#include <hndcpu.h>
2214 +
2215 +/*
2216 + * Returns TRUE if an external UART exists at the given base
2217 + * register.
2218 + */
2219 +static bool
2220 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2221 +{
2222 + uint8 save_mcr, status1;
2223 +
2224 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2225 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2226 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2227 + W_REG(osh, &regs[UART_MCR], save_mcr);
2228 +
2229 + return (status1 == 0x90);
2230 +}
2231 +
2232 +/*
2233 + * Initializes UART access. The callback function will be called once
2234 + * per found UART.
2235 + */
2236 +void
2237 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2238 + uint reg_shift))
2239 +{
2240 + osl_t *osh;
2241 + void *regs;
2242 + ulong base;
2243 + uint irq;
2244 + int i, n;
2245 +
2246 + osh = sb_osh(sbh);
2247 +
2248 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2249 + extifregs_t *eir = (extifregs_t *) regs;
2250 + sbconfig_t *sb;
2251 +
2252 + /* Determine external UART register base */
2253 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2254 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2255 +
2256 + /* Determine IRQ */
2257 + irq = sb_irq(sbh);
2258 +
2259 + /* Disable GPIO interrupt initially */
2260 + W_REG(osh, &eir->gpiointpolarity, 0);
2261 + W_REG(osh, &eir->gpiointmask, 0);
2262 +
2263 + /* Search for external UARTs */
2264 + n = 2;
2265 + for (i = 0; i < 2; i++) {
2266 + regs = (void *) REG_MAP(base + (i * 8), 8);
2267 + if (serial_exists(osh, regs)) {
2268 + /* Set GPIO 1 to be the external UART IRQ */
2269 + W_REG(osh, &eir->gpiointmask, 2);
2270 + /* XXXDetermine external UART clock */
2271 + if (add)
2272 + add(regs, irq, 13500000, 0);
2273 + }
2274 + }
2275 +
2276 + /* Add internal UART if enabled */
2277 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2278 + if (add)
2279 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2280 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2281 + chipcregs_t *cc = (chipcregs_t *) regs;
2282 + uint32 rev, cap, pll, baud_base, div;
2283 +
2284 + /* Determine core revision and capabilities */
2285 + rev = sb_corerev(sbh);
2286 + cap = R_REG(osh, &cc->capabilities);
2287 + pll = cap & CAP_PLL_MASK;
2288 +
2289 + /* Determine IRQ */
2290 + irq = sb_irq(sbh);
2291 +
2292 + if (pll == PLL_TYPE1) {
2293 + /* PLL clock */
2294 + baud_base = sb_clock_rate(pll,
2295 + R_REG(osh, &cc->clockcontrol_n),
2296 + R_REG(osh, &cc->clockcontrol_m2));
2297 + div = 1;
2298 + } else {
2299 + /* Fixed ALP clock */
2300 + if (rev >= 11 && rev != 15) {
2301 + baud_base = 20000000;
2302 + div = 1;
2303 + /* Set the override bit so we don't divide it */
2304 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2305 + }
2306 + /* Internal backplane clock */
2307 + else if (rev >= 3) {
2308 + baud_base = sb_clock(sbh);
2309 + div = 2; /* Minimum divisor */
2310 + W_REG(osh, &cc->clkdiv,
2311 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2312 + }
2313 + /* Fixed internal backplane clock */
2314 + else {
2315 + baud_base = 88000000;
2316 + div = 48;
2317 + }
2318 +
2319 + /* Clock source depends on strapping if UartClkOverride is unset */
2320 + if ((rev > 0) &&
2321 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2322 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2323 + /* Internal divided backplane clock */
2324 + baud_base /= div;
2325 + } else {
2326 + /* Assume external clock of 1.8432 MHz */
2327 + baud_base = 1843200;
2328 + }
2329 + }
2330 + }
2331 +
2332 + /* Add internal UARTs */
2333 + n = cap & CAP_UARTS_MASK;
2334 + for (i = 0; i < n; i++) {
2335 + /* Register offset changed after revision 0 */
2336 + if (rev)
2337 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2338 + else
2339 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2340 +
2341 + if (add)
2342 + add(regs, irq, baud_base, 0);
2343 + }
2344 + }
2345 +}
2346 +
2347 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2348 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2349 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-10-02 21:19:59.000000000 +0200
2350 @@ -0,0 +1,91 @@
2351 +/*
2352 + * BCM4710 address space map and definitions
2353 + * Think twice before adding to this file, this is not the kitchen sink
2354 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2355 + *
2356 + * Copyright 2004, Broadcom Corporation
2357 + * All Rights Reserved.
2358 + *
2359 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2360 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2361 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2362 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2363 + *
2364 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2365 + */
2366 +
2367 +#ifndef _bcm4710_h_
2368 +#define _bcm4710_h_
2369 +
2370 +/* Address map */
2371 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2372 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2373 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2374 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2375 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2376 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2377 +
2378 +/* Core register space */
2379 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2380 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2381 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2382 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2383 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2384 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2385 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2386 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2387 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2388 +
2389 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2390 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2391 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2392 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2393 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2394 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2395 +
2396 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2397 +
2398 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2399 +
2400 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2401 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2402 +
2403 +#define SBFLAG_PCI 0
2404 +#define SBFLAG_ENET0 1
2405 +#define SBFLAG_ILINE20 2
2406 +#define SBFLAG_CODEC 3
2407 +#define SBFLAG_USB 4
2408 +#define SBFLAG_EXTIF 5
2409 +#define SBFLAG_ENET1 6
2410 +
2411 +#ifdef CONFIG_HWSIM
2412 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2413 +#else
2414 +#define BCM4710_TRACE(trval)
2415 +#endif
2416 +
2417 +
2418 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2419 +
2420 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2421 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2422 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2423 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2424 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2425 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2426 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2427 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2428 +
2429 +#define LED_REG(x) \
2430 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2431 +
2432 +/*
2433 + * Reset function implemented in PLD. Read or write should trigger hard reset
2434 + */
2435 +#define SYS_HARD_RESET() \
2436 + { for (;;) \
2437 + *( (volatile unsigned char *)\
2438 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2439 + }
2440 +
2441 +#endif /* _bcm4710_h_ */
2442 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2443 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2444 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-10-02 21:19:59.000000000 +0200
2445 @@ -0,0 +1,106 @@
2446 +/*
2447 + * Misc system wide definitions
2448 + *
2449 + * Copyright 2006, Broadcom Corporation
2450 + * All Rights Reserved.
2451 + *
2452 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2453 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2454 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2455 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2456 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2457 + */
2458 +
2459 +#ifndef _bcmdefs_h_
2460 +#define _bcmdefs_h_
2461 +
2462 +/*
2463 + * One doesn't need to include this file explicitly, gets included automatically if
2464 + * typedefs.h is included.
2465 + */
2466 +
2467 +/* Reclaiming text and data :
2468 + * The following macros specify special linker sections that can be reclaimed
2469 + * after a system is considered 'up'.
2470 + */
2471 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2472 +extern bool bcmreclaimed;
2473 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2474 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2475 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2476 +#define BCMINITDATA(_data) _data
2477 +#define BCMINITFN(_fn) _fn
2478 +#define bcmreclaimed 0
2479 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2480 +
2481 +/* Reclaim uninit functions if BCMNODOWN is defined */
2482 +/* and if they are not already removed by -gc-sections */
2483 +#ifdef BCMNODOWN
2484 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2485 +#else
2486 +#define BCMUNINITFN(_fn) _fn
2487 +#endif
2488 +
2489 +#ifdef BCMRECLAIM
2490 +#define CONST
2491 +#else
2492 +#define CONST const
2493 +#endif /* BCMRECLAIM */
2494 +
2495 +/* Compatibility with old-style BCMRECLAIM */
2496 +#define BCMINIT(_id) _id
2497 +
2498 +
2499 +/* Put some library data/code into ROM to reduce RAM requirements */
2500 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2501 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2502 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2503 +#else
2504 +#define BCMROMDATA(_data) _data
2505 +#define BCMROMFN(_fn) _fn
2506 +#endif
2507 +
2508 +/* Bus types */
2509 +#define SB_BUS 0 /* Silicon Backplane */
2510 +#define PCI_BUS 1 /* PCI target */
2511 +#define PCMCIA_BUS 2 /* PCMCIA target */
2512 +#define SDIO_BUS 3 /* SDIO target */
2513 +#define JTAG_BUS 4 /* JTAG */
2514 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2515 +
2516 +/* Allows optimization for single-bus support */
2517 +#ifdef BCMBUSTYPE
2518 +#define BUSTYPE(bus) (BCMBUSTYPE)
2519 +#else
2520 +#define BUSTYPE(bus) (bus)
2521 +#endif
2522 +
2523 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2524 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2525 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2526 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2527 +
2528 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2529 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2530 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2531 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2532 +
2533 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2534 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2535 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2536 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2537 + */
2538 +#define BCMEXTRAHDROOM 160
2539 +
2540 +/* Headroom required for dongle-to-host communication. Packets allocated
2541 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2542 + * leave this much room in front for low-level message headers which may
2543 + * be needed to get across the dongle bus to the host. (These messages
2544 + * don't go over the network, so room for the full WL header above would
2545 + * be a waste.)
2546 + */
2547 +#define BCMDONGLEHDRSZ 8
2548 +
2549 +
2550 +
2551 +#endif /* _bcmdefs_h_ */
2552 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2553 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2554 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-10-02 21:19:59.000000000 +0200
2555 @@ -0,0 +1,391 @@
2556 +/*
2557 + * Broadcom device-specific manifest constants.
2558 + *
2559 + * Copyright 2005, Broadcom Corporation
2560 + * All Rights Reserved.
2561 + *
2562 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2563 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2564 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2565 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2566 + * $Id$
2567 + */
2568 +
2569 +#ifndef _BCMDEVS_H
2570 +#define _BCMDEVS_H
2571 +
2572 +
2573 +/* Known PCI vendor Id's */
2574 +#define VENDOR_EPIGRAM 0xfeda
2575 +#define VENDOR_BROADCOM 0x14e4
2576 +#define VENDOR_3COM 0x10b7
2577 +#define VENDOR_NETGEAR 0x1385
2578 +#define VENDOR_DIAMOND 0x1092
2579 +#define VENDOR_DELL 0x1028
2580 +#define VENDOR_HP 0x0e11
2581 +#define VENDOR_APPLE 0x106b
2582 +
2583 +/* PCI Device Id's */
2584 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2585 +#define BCM4211_DEVICE_ID 0x4211
2586 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2587 +#define BCM4231_DEVICE_ID 0x4231
2588 +
2589 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2590 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2591 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2592 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2593 +
2594 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2595 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2596 +
2597 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2598 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2599 +
2600 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2601 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2602 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2603 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2604 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2605 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2606 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2607 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2608 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2609 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2610 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2611 +
2612 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2613 +
2614 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
2615 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
2616 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
2617 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
2618 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
2619 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
2620 +
2621 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
2622 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2623 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2624 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2625 +
2626 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
2627 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
2628 +
2629 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
2630 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
2631 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
2632 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
2633 +
2634 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
2635 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2636 +#define BCM4306_D11G_ID2 0x4325
2637 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2638 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2639 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2640 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2641 +
2642 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2643 +
2644 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2645 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2646 +
2647 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
2648 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
2649 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
2650 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
2651 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
2652 +
2653 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2654 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2655 +
2656 +
2657 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
2658 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2659 +
2660 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
2661 +
2662 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
2663 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
2664 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
2665 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
2666 +
2667 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
2668 +
2669 +/* Address map */
2670 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2671 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2672 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2673 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2674 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2675 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2676 +
2677 +/* Core register space */
2678 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2679 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2680 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2681 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2682 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2683 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2684 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2685 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2686 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2687 +
2688 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2689 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2690 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2691 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2692 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2693 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2694 +
2695 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2696 +
2697 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2698 +
2699 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2700 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2701 +
2702 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
2703 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2704 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2705 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2706 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2707 +
2708 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
2709 +
2710 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
2711 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
2712 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
2713 +
2714 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
2715 +
2716 +/* PCMCIA vendor Id's */
2717 +
2718 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2719 +
2720 +/* SDIO vendor Id's */
2721 +#define VENDOR_BROADCOM_SDIO 0x00BF
2722 +
2723 +
2724 +/* boardflags */
2725 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2726 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2727 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2728 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2729 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2730 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2731 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2732 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2733 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2734 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2735 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2736 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2737 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2738 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2739 +
2740 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2741 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
2742 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2743 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2744 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2745 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2746 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2747 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2748 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2749 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2750 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2751 +
2752 +/* Bus types */
2753 +#define SB_BUS 0 /* Silicon Backplane */
2754 +#define PCI_BUS 1 /* PCI target */
2755 +#define PCMCIA_BUS 2 /* PCMCIA target */
2756 +#define SDIO_BUS 3 /* SDIO target */
2757 +#define JTAG_BUS 4 /* JTAG */
2758 +
2759 +/* Allows optimization for single-bus support */
2760 +#ifdef BCMBUSTYPE
2761 +#define BUSTYPE(bus) (BCMBUSTYPE)
2762 +#else
2763 +#define BUSTYPE(bus) (bus)
2764 +#endif
2765 +
2766 +/* power control defines */
2767 +#define PLL_DELAY 150 /* us pll on delay */
2768 +#define FREF_DELAY 200 /* us fref change delay */
2769 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2770 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2771 +
2772 +/* Reference Board Types */
2773 +
2774 +#define BU4710_BOARD 0x0400
2775 +#define VSIM4710_BOARD 0x0401
2776 +#define QT4710_BOARD 0x0402
2777 +
2778 +#define BU4610_BOARD 0x0403
2779 +#define VSIM4610_BOARD 0x0404
2780 +
2781 +#define BU4307_BOARD 0x0405
2782 +#define BCM94301CB_BOARD 0x0406
2783 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
2784 +#define BCM94301MP_BOARD 0x0407
2785 +#define BCM94307MP_BOARD 0x0408
2786 +#define BCMAP4307_BOARD 0x0409
2787 +
2788 +#define BU4309_BOARD 0x040a
2789 +#define BCM94309CB_BOARD 0x040b
2790 +#define BCM94309MP_BOARD 0x040c
2791 +#define BCM4309AP_BOARD 0x040d
2792 +
2793 +#define BCM94302MP_BOARD 0x040e
2794 +
2795 +#define VSIM4310_BOARD 0x040f
2796 +#define BU4711_BOARD 0x0410
2797 +#define BCM94310U_BOARD 0x0411
2798 +#define BCM94310AP_BOARD 0x0412
2799 +#define BCM94310MP_BOARD 0x0414
2800 +
2801 +#define BU4306_BOARD 0x0416
2802 +#define BCM94306CB_BOARD 0x0417
2803 +#define BCM94306MP_BOARD 0x0418
2804 +
2805 +#define BCM94710D_BOARD 0x041a
2806 +#define BCM94710R1_BOARD 0x041b
2807 +#define BCM94710R4_BOARD 0x041c
2808 +#define BCM94710AP_BOARD 0x041d
2809 +
2810 +
2811 +#define BU2050_BOARD 0x041f
2812 +
2813 +
2814 +#define BCM94309G_BOARD 0x0421
2815 +
2816 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
2817 +
2818 +#define BU4704_BOARD 0x0423
2819 +#define BU4702_BOARD 0x0424
2820 +
2821 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2822 +
2823 +#define BU4317_BOARD 0x0426
2824 +
2825 +
2826 +#define BCM94702MN_BOARD 0x0428
2827 +
2828 +/* BCM4702 1U CompactPCI Board */
2829 +#define BCM94702CPCI_BOARD 0x0429
2830 +
2831 +/* BCM4702 with BCM95380 VLAN Router */
2832 +#define BCM95380RR_BOARD 0x042a
2833 +
2834 +/* cb4306 with SiGe PA */
2835 +#define BCM94306CBSG_BOARD 0x042b
2836 +
2837 +/* mp4301 with 2050 radio */
2838 +#define BCM94301MPL_BOARD 0x042c
2839 +
2840 +/* cb4306 with SiGe PA */
2841 +#define PCSG94306_BOARD 0x042d
2842 +
2843 +/* bu4704 with sdram */
2844 +#define BU4704SD_BOARD 0x042e
2845 +
2846 +/* Dual 11a/11g Router */
2847 +#define BCM94704AGR_BOARD 0x042f
2848 +
2849 +/* 11a-only minipci */
2850 +#define BCM94308MP_BOARD 0x0430
2851 +
2852 +
2853 +
2854 +/* BCM94317 boards */
2855 +#define BCM94317CB_BOARD 0x0440
2856 +#define BCM94317MP_BOARD 0x0441
2857 +#define BCM94317PCMCIA_BOARD 0x0442
2858 +#define BCM94317SDIO_BOARD 0x0443
2859 +
2860 +#define BU4712_BOARD 0x0444
2861 +#define BU4712SD_BOARD 0x045d
2862 +#define BU4712L_BOARD 0x045f
2863 +
2864 +/* BCM4712 boards */
2865 +#define BCM94712AP_BOARD 0x0445
2866 +#define BCM94712P_BOARD 0x0446
2867 +
2868 +/* BCM4318 boards */
2869 +#define BU4318_BOARD 0x0447
2870 +#define CB4318_BOARD 0x0448
2871 +#define MPG4318_BOARD 0x0449
2872 +#define MP4318_BOARD 0x044a
2873 +#define SD4318_BOARD 0x044b
2874 +
2875 +/* BCM63XX boards */
2876 +#define BCM96338_BOARD 0x6338
2877 +#define BCM96345_BOARD 0x6345
2878 +#define BCM96348_BOARD 0x6348
2879 +
2880 +/* Another mp4306 with SiGe */
2881 +#define BCM94306P_BOARD 0x044c
2882 +
2883 +/* CF-like 4317 modules */
2884 +#define BCM94317CF_BOARD 0x044d
2885 +
2886 +/* mp4303 */
2887 +#define BCM94303MP_BOARD 0x044e
2888 +
2889 +/* mpsgh4306 */
2890 +#define BCM94306MPSGH_BOARD 0x044f
2891 +
2892 +/* BRCM 4306 w/ Front End Modules */
2893 +#define BCM94306MPM 0x0450
2894 +#define BCM94306MPL 0x0453
2895 +
2896 +/* 4712agr */
2897 +#define BCM94712AGR_BOARD 0x0451
2898 +
2899 +/* The real CF 4317 board */
2900 +#define CFI4317_BOARD 0x0452
2901 +
2902 +/* pcmcia 4303 */
2903 +#define PC4303_BOARD 0x0454
2904 +
2905 +/* 5350K */
2906 +#define BCM95350K_BOARD 0x0455
2907 +
2908 +/* 5350R */
2909 +#define BCM95350R_BOARD 0x0456
2910 +
2911 +/* 4306mplna */
2912 +#define BCM94306MPLNA_BOARD 0x0457
2913 +
2914 +/* 4320 boards */
2915 +#define BU4320_BOARD 0x0458
2916 +#define BU4320S_BOARD 0x0459
2917 +#define BCM94320PH_BOARD 0x045a
2918 +
2919 +/* 4306mph */
2920 +#define BCM94306MPH_BOARD 0x045b
2921 +
2922 +/* 4306pciv */
2923 +#define BCM94306PCIV_BOARD 0x045c
2924 +
2925 +#define BU4712SD_BOARD 0x045d
2926 +
2927 +#define BCM94320PFLSH_BOARD 0x045e
2928 +
2929 +#define BU4712L_BOARD 0x045f
2930 +#define BCM94712LGR_BOARD 0x0460
2931 +#define BCM94320R_BOARD 0x0461
2932 +
2933 +#define BU5352_BOARD 0x0462
2934 +
2935 +#define BCM94318MPGH_BOARD 0x0463
2936 +
2937 +
2938 +#define BCM95352GR_BOARD 0x0467
2939 +
2940 +/* bcm95351agr */
2941 +#define BCM95351AGR_BOARD 0x0470
2942 +
2943 +/* # of GPIO pins */
2944 +#define GPIO_NUMPINS 16
2945 +
2946 +#endif /* _BCMDEVS_H */
2947 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2948 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2949 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-10-02 21:19:59.000000000 +0200
2950 @@ -0,0 +1,369 @@
2951 +/*
2952 + * Broadcom device-specific manifest constants.
2953 + *
2954 + * Copyright 2006, Broadcom Corporation
2955 + * All Rights Reserved.
2956 + *
2957 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2958 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2959 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2960 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2961 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2962 + */
2963 +
2964 +#ifndef _BCMDEVS_H
2965 +#define _BCMDEVS_H
2966 +
2967 +#include "bcm4710.h"
2968 +
2969 +/* Known PCI vendor Id's */
2970 +#define VENDOR_EPIGRAM 0xfeda
2971 +#define VENDOR_BROADCOM 0x14e4
2972 +#define VENDOR_3COM 0x10b7
2973 +#define VENDOR_NETGEAR 0x1385
2974 +#define VENDOR_DIAMOND 0x1092
2975 +#define VENDOR_DELL 0x1028
2976 +#define VENDOR_HP 0x0e11
2977 +#define VENDOR_APPLE 0x106b
2978 +
2979 +/* PCI Device Id's */
2980 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2981 +#define BCM4211_DEVICE_ID 0x4211
2982 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2983 +#define BCM4231_DEVICE_ID 0x4231
2984 +
2985 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2986 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2987 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2988 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2989 +
2990 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2991 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2992 +
2993 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2994 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2995 +
2996 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2997 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2998 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2999 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
3000 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
3001 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
3002 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3003 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3004 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3005 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3006 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3007 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
3008 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
3009 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
3010 +
3011 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
3012 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
3013 +
3014 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
3015 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3016 +
3017 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
3018 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3019 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3020 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3021 +
3022 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
3023 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3024 +#define BCM4306_D11G_ID2 0x4325
3025 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3026 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3027 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3028 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3029 +
3030 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3031 +
3032 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
3033 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
3034 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
3035 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
3036 +
3037 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3038 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3039 +
3040 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3041 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3042 +
3043 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
3044 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3045 +
3046 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
3047 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
3048 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
3049 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
3050 +
3051 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
3052 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
3053 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
3054 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
3055 +
3056 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
3057 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
3058 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
3059 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
3060 +
3061 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
3062 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
3063 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
3064 +
3065 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
3066 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3067 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3068 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3069 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3070 +
3071 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
3072 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
3073 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
3074 +
3075 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
3076 +
3077 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
3078 +
3079 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
3080 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
3081 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
3082 +
3083 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
3084 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
3085 +
3086 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
3087 +
3088 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
3089 +
3090 +/* PCMCIA vendor Id's */
3091 +
3092 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3093 +
3094 +/* SDIO vendor Id's */
3095 +#define VENDOR_BROADCOM_SDIO 0x00BF
3096 +
3097 +
3098 +/* boardflags */
3099 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3100 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3101 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3102 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3103 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3104 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3105 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3106 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3107 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3108 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3109 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3110 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3111 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3112 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3113 +
3114 +/* boardflags2 */
3115 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
3116 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
3117 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
3118 +
3119 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3120 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3121 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3122 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3123 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3124 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3125 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3126 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3127 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3128 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3129 +
3130 +/* power control defines */
3131 +#define PLL_DELAY 150 /* us pll on delay */
3132 +#define FREF_DELAY 200 /* us fref change delay */
3133 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3134 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3135 +
3136 +/* Reference Board Types */
3137 +
3138 +#define BU4710_BOARD 0x0400
3139 +#define VSIM4710_BOARD 0x0401
3140 +#define QT4710_BOARD 0x0402
3141 +
3142 +#define BU4309_BOARD 0x040a
3143 +#define BCM94309CB_BOARD 0x040b
3144 +#define BCM94309MP_BOARD 0x040c
3145 +#define BCM4309AP_BOARD 0x040d
3146 +
3147 +#define BCM94302MP_BOARD 0x040e
3148 +
3149 +#define BU4306_BOARD 0x0416
3150 +#define BCM94306CB_BOARD 0x0417
3151 +#define BCM94306MP_BOARD 0x0418
3152 +
3153 +#define BCM94710D_BOARD 0x041a
3154 +#define BCM94710R1_BOARD 0x041b
3155 +#define BCM94710R4_BOARD 0x041c
3156 +#define BCM94710AP_BOARD 0x041d
3157 +
3158 +#define BU2050_BOARD 0x041f
3159 +
3160 +
3161 +#define BCM94309G_BOARD 0x0421
3162 +
3163 +#define BU4704_BOARD 0x0423
3164 +#define BU4702_BOARD 0x0424
3165 +
3166 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3167 +
3168 +
3169 +#define BCM94702MN_BOARD 0x0428
3170 +
3171 +/* BCM4702 1U CompactPCI Board */
3172 +#define BCM94702CPCI_BOARD 0x0429
3173 +
3174 +/* BCM4702 with BCM95380 VLAN Router */
3175 +#define BCM95380RR_BOARD 0x042a
3176 +
3177 +/* cb4306 with SiGe PA */
3178 +#define BCM94306CBSG_BOARD 0x042b
3179 +
3180 +/* cb4306 with SiGe PA */
3181 +#define PCSG94306_BOARD 0x042d
3182 +
3183 +/* bu4704 with sdram */
3184 +#define BU4704SD_BOARD 0x042e
3185 +
3186 +/* Dual 11a/11g Router */
3187 +#define BCM94704AGR_BOARD 0x042f
3188 +
3189 +/* 11a-only minipci */
3190 +#define BCM94308MP_BOARD 0x0430
3191 +
3192 +
3193 +
3194 +#define BU4712_BOARD 0x0444
3195 +#define BU4712SD_BOARD 0x045d
3196 +#define BU4712L_BOARD 0x045f
3197 +
3198 +/* BCM4712 boards */
3199 +#define BCM94712AP_BOARD 0x0445
3200 +#define BCM94712P_BOARD 0x0446
3201 +
3202 +/* BCM4318 boards */
3203 +#define BU4318_BOARD 0x0447
3204 +#define CB4318_BOARD 0x0448
3205 +#define MPG4318_BOARD 0x0449
3206 +#define MP4318_BOARD 0x044a
3207 +#define SD4318_BOARD 0x044b
3208 +
3209 +/* BCM63XX boards */
3210 +#define BCM96338_BOARD 0x6338
3211 +#define BCM96348_BOARD 0x6348
3212 +
3213 +/* Another mp4306 with SiGe */
3214 +#define BCM94306P_BOARD 0x044c
3215 +
3216 +/* mp4303 */
3217 +#define BCM94303MP_BOARD 0x044e
3218 +
3219 +/* mpsgh4306 */
3220 +#define BCM94306MPSGH_BOARD 0x044f
3221 +
3222 +/* BRCM 4306 w/ Front End Modules */
3223 +#define BCM94306MPM 0x0450
3224 +#define BCM94306MPL 0x0453
3225 +
3226 +/* 4712agr */
3227 +#define BCM94712AGR_BOARD 0x0451
3228 +
3229 +/* pcmcia 4303 */
3230 +#define PC4303_BOARD 0x0454
3231 +
3232 +/* 5350K */
3233 +#define BCM95350K_BOARD 0x0455
3234 +
3235 +/* 5350R */
3236 +#define BCM95350R_BOARD 0x0456
3237 +
3238 +/* 4306mplna */
3239 +#define BCM94306MPLNA_BOARD 0x0457
3240 +
3241 +/* 4320 boards */
3242 +#define BU4320_BOARD 0x0458
3243 +#define BU4320S_BOARD 0x0459
3244 +#define BCM94320PH_BOARD 0x045a
3245 +
3246 +/* 4306mph */
3247 +#define BCM94306MPH_BOARD 0x045b
3248 +
3249 +/* 4306pciv */
3250 +#define BCM94306PCIV_BOARD 0x045c
3251 +
3252 +#define BU4712SD_BOARD 0x045d
3253 +
3254 +#define BCM94320PFLSH_BOARD 0x045e
3255 +
3256 +#define BU4712L_BOARD 0x045f
3257 +#define BCM94712LGR_BOARD 0x0460
3258 +#define BCM94320R_BOARD 0x0461
3259 +
3260 +#define BU5352_BOARD 0x0462
3261 +
3262 +#define BCM94318MPGH_BOARD 0x0463
3263 +
3264 +#define BU4311_BOARD 0x0464
3265 +#define BCM94311MC_BOARD 0x0465
3266 +#define BCM94311MCAG_BOARD 0x0466
3267 +
3268 +#define BCM95352GR_BOARD 0x0467
3269 +
3270 +/* bcm95351agr */
3271 +#define BCM95351AGR_BOARD 0x0470
3272 +
3273 +/* bcm94704mpcb */
3274 +#define BCM94704MPCB_BOARD 0x0472
3275 +
3276 +/* 4785 boards */
3277 +#define BU4785_BOARD 0x0478
3278 +
3279 +/* 4321 boards */
3280 +#define BU4321_BOARD 0x046b
3281 +#define BU4321E_BOARD 0x047c
3282 +#define MP4321_BOARD 0x046c
3283 +#define CB2_4321_BOARD 0x046d
3284 +#define MC4321_BOARD 0x046e
3285 +
3286 +/* # of GPIO pins */
3287 +#define GPIO_NUMPINS 16
3288 +
3289 +/* radio ID codes */
3290 +#define NORADIO_ID 0xe4f5
3291 +#define NORADIO_IDCODE 0x4e4f5246
3292 +
3293 +#define BCM2050_ID 0x2050
3294 +#define BCM2050_IDCODE 0x02050000
3295 +#define BCM2050A0_IDCODE 0x1205017f
3296 +#define BCM2050A1_IDCODE 0x2205017f
3297 +#define BCM2050R8_IDCODE 0x8205017f
3298 +
3299 +#define BCM2055_ID 0x2055
3300 +#define BCM2055_IDCODE 0x02055000
3301 +#define BCM2055A0_IDCODE 0x1205517f
3302 +
3303 +#define BCM2060_ID 0x2060
3304 +#define BCM2060_IDCODE 0x02060000
3305 +#define BCM2060WW_IDCODE 0x1206017f
3306 +
3307 +#define BCM2062_ID 0x2062
3308 +#define BCM2062_IDCODE 0x02062000
3309 +#define BCM2062A0_IDCODE 0x0206217f
3310 +
3311 +/* parts of an idcode: */
3312 +#define IDCODE_MFG_MASK 0x00000fff
3313 +#define IDCODE_MFG_SHIFT 0
3314 +#define IDCODE_ID_MASK 0x0ffff000
3315 +#define IDCODE_ID_SHIFT 12
3316 +#define IDCODE_REV_MASK 0xf0000000
3317 +#define IDCODE_REV_SHIFT 28
3318 +
3319 +#endif /* _BCMDEVS_H */
3320 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3321 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3322 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-10-02 21:19:59.000000000 +0200
3323 @@ -0,0 +1,198 @@
3324 +/*
3325 + * local version of endian.h - byte order defines
3326 + *
3327 + * Copyright 2006, Broadcom Corporation
3328 + * All Rights Reserved.
3329 + *
3330 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3331 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3332 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3333 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3334 + *
3335 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3336 +*/
3337 +
3338 +#ifndef _BCMENDIAN_H_
3339 +#define _BCMENDIAN_H_
3340 +
3341 +#include <typedefs.h>
3342 +
3343 +/* Byte swap a 16 bit value */
3344 +#define BCMSWAP16(val) \
3345 + ((uint16)(\
3346 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3347 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3348 +
3349 +/* Byte swap a 32 bit value */
3350 +#define BCMSWAP32(val) \
3351 + ((uint32)(\
3352 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3353 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3354 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3355 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3356 +
3357 +/* 2 Byte swap a 32 bit value */
3358 +#define BCMSWAP32BY16(val) \
3359 + ((uint32)(\
3360 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3361 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3362 +
3363 +
3364 +static INLINE uint16
3365 +bcmswap16(uint16 val)
3366 +{
3367 + return BCMSWAP16(val);
3368 +}
3369 +
3370 +static INLINE uint32
3371 +bcmswap32(uint32 val)
3372 +{
3373 + return BCMSWAP32(val);
3374 +}
3375 +
3376 +static INLINE uint32
3377 +bcmswap32by16(uint32 val)
3378 +{
3379 + return BCMSWAP32BY16(val);
3380 +}
3381 +
3382 +/* buf - start of buffer of shorts to swap */
3383 +/* len - byte length of buffer */
3384 +static INLINE void
3385 +bcmswap16_buf(uint16 *buf, uint len)
3386 +{
3387 + len = len/2;
3388 +
3389 + while (len--) {
3390 + *buf = bcmswap16(*buf);
3391 + buf++;
3392 + }
3393 +}
3394 +
3395 +#ifndef hton16
3396 +#ifndef IL_BIGENDIAN
3397 +#define HTON16(i) BCMSWAP16(i)
3398 +#define hton16(i) bcmswap16(i)
3399 +#define hton32(i) bcmswap32(i)
3400 +#define ntoh16(i) bcmswap16(i)
3401 +#define ntoh32(i) bcmswap32(i)
3402 +#define ltoh16(i) (i)
3403 +#define ltoh32(i) (i)
3404 +#define htol16(i) (i)
3405 +#define htol32(i) (i)
3406 +#else
3407 +#define HTON16(i) (i)
3408 +#define hton16(i) (i)
3409 +#define hton32(i) (i)
3410 +#define ntoh16(i) (i)
3411 +#define ntoh32(i) (i)
3412 +#define ltoh16(i) bcmswap16(i)
3413 +#define ltoh32(i) bcmswap32(i)
3414 +#define htol16(i) bcmswap16(i)
3415 +#define htol32(i) bcmswap32(i)
3416 +#endif /* IL_BIGENDIAN */
3417 +#endif /* hton16 */
3418 +
3419 +#ifndef IL_BIGENDIAN
3420 +#define ltoh16_buf(buf, i)
3421 +#define htol16_buf(buf, i)
3422 +#else
3423 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3424 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3425 +#endif /* IL_BIGENDIAN */
3426 +
3427 +/*
3428 +* store 16-bit value to unaligned little endian byte array.
3429 +*/
3430 +static INLINE void
3431 +htol16_ua_store(uint16 val, uint8 *bytes)
3432 +{
3433 + bytes[0] = val&0xff;
3434 + bytes[1] = val>>8;
3435 +}
3436 +
3437 +/*
3438 +* store 32-bit value to unaligned little endian byte array.
3439 +*/
3440 +static INLINE void
3441 +htol32_ua_store(uint32 val, uint8 *bytes)
3442 +{
3443 + bytes[0] = val&0xff;
3444 + bytes[1] = (val>>8)&0xff;
3445 + bytes[2] = (val>>16)&0xff;
3446 + bytes[3] = val>>24;
3447 +}
3448 +
3449 +/*
3450 +* store 16-bit value to unaligned network(big) endian byte array.
3451 +*/
3452 +static INLINE void
3453 +hton16_ua_store(uint16 val, uint8 *bytes)
3454 +{
3455 + bytes[1] = val&0xff;
3456 + bytes[0] = val>>8;
3457 +}
3458 +
3459 +/*
3460 +* store 32-bit value to unaligned network(big) endian byte array.
3461 +*/
3462 +static INLINE void
3463 +hton32_ua_store(uint32 val, uint8 *bytes)
3464 +{
3465 + bytes[3] = val&0xff;
3466 + bytes[2] = (val>>8)&0xff;
3467 + bytes[1] = (val>>16)&0xff;
3468 + bytes[0] = val>>24;
3469 +}
3470 +
3471 +/*
3472 +* load 16-bit value from unaligned little endian byte array.
3473 +*/
3474 +static INLINE uint16
3475 +ltoh16_ua(void *bytes)
3476 +{
3477 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3478 +}
3479 +
3480 +/*
3481 +* load 32-bit value from unaligned little endian byte array.
3482 +*/
3483 +static INLINE uint32
3484 +ltoh32_ua(void *bytes)
3485 +{
3486 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3487 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3488 +}
3489 +
3490 +/*
3491 +* load 16-bit value from unaligned big(network) endian byte array.
3492 +*/
3493 +static INLINE uint16
3494 +ntoh16_ua(void *bytes)
3495 +{
3496 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3497 +}
3498 +
3499 +/*
3500 +* load 32-bit value from unaligned big(network) endian byte array.
3501 +*/
3502 +static INLINE uint32
3503 +ntoh32_ua(void *bytes)
3504 +{
3505 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3506 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3507 +}
3508 +
3509 +#define ltoh_ua(ptr) (\
3510 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3511 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3512 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3513 +)
3514 +
3515 +#define ntoh_ua(ptr) (\
3516 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3517 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3518 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3519 +)
3520 +
3521 +#endif /* _BCMENDIAN_H_ */
3522 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3523 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3524 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-10-02 21:19:59.000000000 +0200
3525 @@ -0,0 +1,159 @@
3526 +/*
3527 + * NVRAM variable manipulation
3528 + *
3529 + * Copyright 2006, Broadcom Corporation
3530 + * All Rights Reserved.
3531 + *
3532 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3533 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3534 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3535 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3536 + *
3537 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3538 + */
3539 +
3540 +#ifndef _bcmnvram_h_
3541 +#define _bcmnvram_h_
3542 +
3543 +#ifndef _LANGUAGE_ASSEMBLY
3544 +
3545 +#include <typedefs.h>
3546 +#include <bcmdefs.h>
3547 +
3548 +struct nvram_header {
3549 + uint32 magic;
3550 + uint32 len;
3551 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3552 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3553 + uint32 config_ncdl; /* ncdl values for memc */
3554 +};
3555 +
3556 +struct nvram_tuple {
3557 + char *name;
3558 + char *value;
3559 + struct nvram_tuple *next;
3560 +};
3561 +
3562 +/*
3563 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3564 + * platforms.
3565 + */
3566 +extern int nvram_init(void *sbh);
3567 +
3568 +/*
3569 + * Disable NVRAM access. May be unnecessary or undefined on certain
3570 + * platforms.
3571 + */
3572 +extern void nvram_exit(void *sbh);
3573 +
3574 +/*
3575 + * Get the value of an NVRAM variable. The pointer returned may be
3576 + * invalid after a set.
3577 + * @param name name of variable to get
3578 + * @return value of variable or NULL if undefined
3579 + */
3580 +extern char * nvram_get(const char *name);
3581 +
3582 +/*
3583 + * Read the reset GPIO value from the nvram and set the GPIO
3584 + * as input
3585 + */
3586 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3587 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3588 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3589 +
3590 +/*
3591 + * Get the value of an NVRAM variable.
3592 + * @param name name of variable to get
3593 + * @return value of variable or NUL if undefined
3594 + */
3595 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3596 +
3597 +#define nvram_safe_unset(name) ({ \
3598 + if(nvram_get(name)) \
3599 + nvram_unset(name); \
3600 +})
3601 +
3602 +#define nvram_safe_set(name, value) ({ \
3603 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3604 + nvram_set(name, value); \
3605 +})
3606 +
3607 +/*
3608 + * Match an NVRAM variable.
3609 + * @param name name of variable to match
3610 + * @param match value to compare against value of variable
3611 + * @return TRUE if variable is defined and its value is string equal
3612 + * to match or FALSE otherwise
3613 + */
3614 +static INLINE int
3615 +nvram_match(char *name, char *match) {
3616 + const char *value = nvram_get(name);
3617 + return (value && !strcmp(value, match));
3618 +}
3619 +
3620 +/*
3621 + * Inversely match an NVRAM variable.
3622 + * @param name name of variable to match
3623 + * @param match value to compare against value of variable
3624 + * @return TRUE if variable is defined and its value is not string
3625 + * equal to invmatch or FALSE otherwise
3626 + */
3627 +static INLINE int
3628 +nvram_invmatch(char *name, char *invmatch) {
3629 + const char *value = nvram_get(name);
3630 + return (value && strcmp(value, invmatch));
3631 +}
3632 +
3633 +/*
3634 + * Set the value of an NVRAM variable. The name and value strings are
3635 + * copied into private storage. Pointers to previously set values
3636 + * may become invalid. The new value may be immediately
3637 + * retrieved but will not be permanently stored until a commit.
3638 + * @param name name of variable to set
3639 + * @param value value of variable
3640 + * @return 0 on success and errno on failure
3641 + */
3642 +extern int nvram_set(const char *name, const char *value);
3643 +
3644 +/*
3645 + * Unset an NVRAM variable. Pointers to previously set values
3646 + * remain valid until a set.
3647 + * @param name name of variable to unset
3648 + * @return 0 on success and errno on failure
3649 + * NOTE: use nvram_commit to commit this change to flash.
3650 + */
3651 +extern int nvram_unset(const char *name);
3652 +
3653 +/*
3654 + * Commit NVRAM variables to permanent storage. All pointers to values
3655 + * may be invalid after a commit.
3656 + * NVRAM values are undefined after a commit.
3657 + * @return 0 on success and errno on failure
3658 + */
3659 +extern int nvram_commit(void);
3660 +
3661 +/*
3662 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3663 + * @param buf buffer to store variables
3664 + * @param count size of buffer in bytes
3665 + * @return 0 on success and errno on failure
3666 + */
3667 +extern int nvram_getall(char *buf, int count);
3668 +
3669 +extern int file2nvram(char *filename, char *varname);
3670 +extern int nvram2file(char *varname, char *filename);
3671 +
3672 +#endif /* _LANGUAGE_ASSEMBLY */
3673 +
3674 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3675 +#define NVRAM_CLEAR_MAGIC 0x0
3676 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3677 +#define NVRAM_VERSION 1
3678 +#define NVRAM_HEADER_SIZE 20
3679 +#define NVRAM_SPACE 0x8000
3680 +
3681 +#define NVRAM_MAX_VALUE_LEN 255
3682 +#define NVRAM_MAX_PARAM_LEN 64
3683 +
3684 +#endif /* _bcmnvram_h_ */
3685 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3686 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3687 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-10-02 21:19:59.000000000 +0200
3688 @@ -0,0 +1,108 @@
3689 +/*
3690 + * Misc useful routines to access NIC local SROM/OTP .
3691 + *
3692 + * Copyright 2006, Broadcom Corporation
3693 + * All Rights Reserved.
3694 + *
3695 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3696 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3697 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3698 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3699 + *
3700 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3701 + */
3702 +
3703 +#ifndef _bcmsrom_h_
3704 +#define _bcmsrom_h_
3705 +
3706 +/* Maximum srom: 4 Kilobits == 512 bytes */
3707 +#define SROM_MAX 512
3708 +
3709 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3710 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3711 + * of useable srom i.e. the useable storage in chips with OTP that
3712 + * implements hardware redundancy.
3713 + */
3714 +
3715 +#define SROM4_WORDS 220
3716 +
3717 +#define SROM4_SIGN 32
3718 +#define SROM4_SIGNATURE 0x5372
3719 +
3720 +#define SROM4_BREV 33
3721 +
3722 +#define SROM4_BFL0 34
3723 +#define SROM4_BFL1 35
3724 +#define SROM4_BFL2 36
3725 +#define SROM4_BFL3 37
3726 +
3727 +#define SROM4_MACHI 38
3728 +#define SROM4_MACMID 39
3729 +#define SROM4_MACLO 40
3730 +
3731 +#define SROM4_CCODE 41
3732 +#define SROM4_REGREV 42
3733 +
3734 +#define SROM4_LEDBH10 43
3735 +#define SROM4_LEDBH32 44
3736 +
3737 +#define SROM4_LEDDC 45
3738 +
3739 +#define SROM4_AA 46
3740 +#define SROM4_AA2G_MASK 0x00ff
3741 +#define SROM4_AA2G_SHIFT 0
3742 +#define SROM4_AA5G_MASK 0xff00
3743 +#define SROM4_AA5G_SHIFT 8
3744 +
3745 +#define SROM4_AG10 47
3746 +#define SROM4_AG32 48
3747 +
3748 +#define SROM4_TXPID2G 49
3749 +#define SROM4_TXPID5G 51
3750 +#define SROM4_TXPID5GL 53
3751 +#define SROM4_TXPID5GH 55
3752 +
3753 +/* Per-path fields */
3754 +#define MAX_PATH 4
3755 +#define SROM4_PATH0 64
3756 +#define SROM4_PATH1 87
3757 +#define SROM4_PATH2 110
3758 +#define SROM4_PATH3 133
3759 +
3760 +#define SROM4_2G_ITT_MAXP 0
3761 +#define SROM4_2G_PA 1
3762 +#define SROM4_5G_ITT_MAXP 5
3763 +#define SROM4_5GLH_MAXP 6
3764 +#define SROM4_5G_PA 7
3765 +#define SROM4_5GL_PA 11
3766 +#define SROM4_5GH_PA 15
3767 +
3768 +/* Fields in the ITT_MAXP and 5GLH_MAXP words */
3769 +#define B2G_MAXP_MASK 0xff
3770 +#define B2G_ITT_SHIFT 8
3771 +#define B5G_MAXP_MASK 0xff
3772 +#define B5G_ITT_SHIFT 8
3773 +#define B5GH_MAXP_MASK 0xff
3774 +#define B5GL_MAXP_SHIFT 8
3775 +
3776 +/* All the miriad power offsets */
3777 +#define SROM4_2G_CCKPO 156
3778 +#define SROM4_2G_OFDMPO 157
3779 +#define SROM4_5G_OFDMPO 159
3780 +#define SROM4_5GL_OFDMPO 161
3781 +#define SROM4_5GH_OFDMPO 163
3782 +#define SROM4_2G_MCSPO 165
3783 +#define SROM4_5G_MCSPO 173
3784 +#define SROM4_5GL_MCSPO 181
3785 +#define SROM4_5GH_MCSPO 189
3786 +#define SROM4_CCDPO 197
3787 +#define SROM4_STBCPO 198
3788 +#define SROM4_BW40PO 199
3789 +#define SROM4_BWDUPPO 200
3790 +
3791 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
3792 +
3793 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3794 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3795 +
3796 +#endif /* _bcmsrom_h_ */
3797 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
3798 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
3799 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-10-02 21:19:59.000000000 +0200
3800 @@ -0,0 +1,433 @@
3801 +/*
3802 + * Misc useful os-independent macros and functions.
3803 + *
3804 + * Copyright 2006, Broadcom Corporation
3805 + * All Rights Reserved.
3806 + *
3807 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3808 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3809 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3810 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3811 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
3812 + */
3813 +
3814 +#ifndef _bcmutils_h_
3815 +#define _bcmutils_h_
3816 +
3817 +/* ** driver-only section ** */
3818 +#ifdef BCMDRIVER
3819 +
3820 +#define _BCM_U 0x01 /* upper */
3821 +#define _BCM_L 0x02 /* lower */
3822 +#define _BCM_D 0x04 /* digit */
3823 +#define _BCM_C 0x08 /* cntrl */
3824 +#define _BCM_P 0x10 /* punct */
3825 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
3826 +#define _BCM_X 0x40 /* hex digit */
3827 +#define _BCM_SP 0x80 /* hard space (0x20) */
3828 +
3829 +#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
3830 +
3831 +extern unsigned char bcm_ctype[];
3832 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
3833 +
3834 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
3835 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
3836 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
3837 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
3838 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
3839 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
3840 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
3841 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
3842 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
3843 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
3844 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
3845 +
3846 +/*
3847 + * Spin at most 'us' microseconds while 'exp' is true.
3848 + * Caller should explicitly test 'exp' when this completes
3849 + * and take appropriate error action if 'exp' is still true.
3850 + */
3851 +#define SPINWAIT(exp, us) { \
3852 + uint countdown = (us) + 9; \
3853 + while ((exp) && (countdown >= 10)) {\
3854 + OSL_DELAY(10); \
3855 + countdown -= 10; \
3856 + } \
3857 +}
3858 +
3859 +struct ether_addr {
3860 + uint8 octet[6];
3861 +} __attribute__((packed));
3862 +
3863 +/* string */
3864 +extern uchar bcm_toupper(uchar c);
3865 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
3866 +extern char *bcmstrstr(char *haystack, char *needle);
3867 +extern char *bcmstrcat(char *dest, const char *src);
3868 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
3869 +/* ethernet address */
3870 +extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
3871 +/* variable access */
3872 +extern char *getvar(char *vars, char *name);
3873 +extern int getintvar(char *vars, char *name);
3874 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
3875 +#ifdef BCMPERFSTATS
3876 +extern void bcm_perf_enable(void);
3877 +extern void bcmstats(char *fmt);
3878 +extern void bcmlog(char *fmt, uint a1, uint a2);
3879 +extern void bcmdumplog(char *buf, int size);
3880 +extern int bcmdumplogent(char *buf, uint idx);
3881 +#else
3882 +#define bcm_perf_enable()
3883 +#define bcmstats(fmt)
3884 +#define bcmlog(fmt, a1, a2)
3885 +#define bcmdumplog(buf, size) *buf = '\0'
3886 +#define bcmdumplogent(buf, idx) -1
3887 +#endif /* BCMPERFSTATS */
3888 +extern char *bcm_nvram_vars(uint *length);
3889 +extern int bcm_nvram_cache(void *sbh);
3890 +
3891 +/* Support for sharing code across in-driver iovar implementations.
3892 + * The intent is that a driver use this structure to map iovar names
3893 + * to its (private) iovar identifiers, and the lookup function to
3894 + * find the entry. Macros are provided to map ids and get/set actions
3895 + * into a single number space for a switch statement.
3896 + */
3897 +
3898 +/* iovar structure */
3899 +typedef struct bcm_iovar {
3900 + const char *name; /* name for lookup and display */
3901 + uint16 varid; /* id for switch */
3902 + uint16 flags; /* driver-specific flag bits */
3903 + uint16 type; /* base type of argument */
3904 + uint16 minlen; /* min length for buffer vars */
3905 +} bcm_iovar_t;
3906 +
3907 +/* varid definitions are per-driver, may use these get/set bits */
3908 +
3909 +/* IOVar action bits for id mapping */
3910 +#define IOV_GET 0 /* Get an iovar */
3911 +#define IOV_SET 1 /* Set an iovar */
3912 +
3913 +/* Varid to actionid mapping */
3914 +#define IOV_GVAL(id) ((id)*2)
3915 +#define IOV_SVAL(id) (((id)*2)+IOV_SET)
3916 +#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
3917 +
3918 +/* flags are per-driver based on driver attributes */
3919 +
3920 +/* Base type definitions */
3921 +#define IOVT_VOID 0 /* no value (implictly set only) */
3922 +#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
3923 +#define IOVT_INT8 2 /* integer values are range-checked */
3924 +#define IOVT_UINT8 3 /* unsigned int 8 bits */
3925 +#define IOVT_INT16 4 /* int 16 bits */
3926 +#define IOVT_UINT16 5 /* unsigned int 16 bits */
3927 +#define IOVT_INT32 6 /* int 32 bits */
3928 +#define IOVT_UINT32 7 /* unsigned int 32 bits */
3929 +#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
3930 +
3931 +extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
3932 +extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
3933 +
3934 +#endif /* #ifdef BCMDRIVER */
3935 +
3936 +/* ** driver/apps-shared section ** */
3937 +
3938 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
3939 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
3940 +
3941 +
3942 +/*
3943 + * error codes could be added but the defined ones shouldn't be changed/deleted
3944 + * these error codes are exposed to the user code
3945 + * when ever a new error code is added to this list
3946 + * please update errorstring table with the related error string and
3947 + * update osl files with os specific errorcode map
3948 +*/
3949 +
3950 +#define BCME_OK 0 /* Success */
3951 +#define BCME_ERROR -1 /* Error generic */
3952 +#define BCME_BADARG -2 /* Bad Argument */
3953 +#define BCME_BADOPTION -3 /* Bad option */
3954 +#define BCME_NOTUP -4 /* Not up */
3955 +#define BCME_NOTDOWN -5 /* Not down */
3956 +#define BCME_NOTAP -6 /* Not AP */
3957 +#define BCME_NOTSTA -7 /* Not STA */
3958 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
3959 +#define BCME_RADIOOFF -9 /* Radio Off */
3960 +#define BCME_NOTBANDLOCKED -10 /* Not band locked */
3961 +#define BCME_NOCLK -11 /* No Clock */
3962 +#define BCME_BADRATESET -12 /* BAD Rate valueset */
3963 +#define BCME_BADBAND -13 /* BAD Band */
3964 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
3965 +#define BCME_BUFTOOLONG -15 /* Buffer too long */
3966 +#define BCME_BUSY -16 /* Busy */
3967 +#define BCME_NOTASSOCIATED -17 /* Not Associated */
3968 +#define BCME_BADSSIDLEN -18 /* Bad SSID len */
3969 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
3970 +#define BCME_BADCHAN -20 /* Bad Channel */
3971 +#define BCME_BADADDR -21 /* Bad Address */
3972 +#define BCME_NORESOURCE -22 /* Not Enough Resources */
3973 +#define BCME_UNSUPPORTED -23 /* Unsupported */
3974 +#define BCME_BADLEN -24 /* Bad length */
3975 +#define BCME_NOTREADY -25 /* Not Ready */
3976 +#define BCME_EPERM -26 /* Not Permitted */
3977 +#define BCME_NOMEM -27 /* No Memory */
3978 +#define BCME_ASSOCIATED -28 /* Associated */
3979 +#define BCME_RANGE -29 /* Not In Range */
3980 +#define BCME_NOTFOUND -30 /* Not Found */
3981 +#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
3982 +#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
3983 +#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
3984 +#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
3985 +#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
3986 +#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
3987 +#define BCME_LAST BCME_DONGLE_DOWN
3988 +
3989 +/* These are collection of BCME Error strings */
3990 +#define BCMERRSTRINGTABLE { \
3991 + "OK", \
3992 + "Undefined error", \
3993 + "Bad Argument", \
3994 + "Bad Option", \
3995 + "Not up", \
3996 + "Not down", \
3997 + "Not AP", \
3998 + "Not STA", \
3999 + "Bad Key Index", \
4000 + "Radio Off", \
4001 + "Not band locked", \
4002 + "No clock", \
4003 + "Bad Rate valueset", \
4004 + "Bad Band", \
4005 + "Buffer too short", \
4006 + "Buffer too long", \
4007 + "Busy", \
4008 + "Not Associated", \
4009 + "Bad SSID len", \
4010 + "Out of Range Channel", \
4011 + "Bad Channel", \
4012 + "Bad Address", \
4013 + "Not Enough Resources", \
4014 + "Unsupported", \
4015 + "Bad length", \
4016 + "Not Ready", \
4017 + "Not Permitted", \
4018 + "No Memory", \
4019 + "Associated", \
4020 + "Not In Range", \
4021 + "Not Found", \
4022 + "WME Not Enabled", \
4023 + "TSPEC Not Found", \
4024 + "ACM Not Supported", \
4025 + "Not WME Association", \
4026 + "SDIO Bus Error", \
4027 + "Dongle Not Accessible" \
4028 +}
4029 +
4030 +#ifndef ABS
4031 +#define ABS(a) (((a) < 0)?-(a):(a))
4032 +#endif /* ABS */
4033 +
4034 +#ifndef MIN
4035 +#define MIN(a, b) (((a) < (b))?(a):(b))
4036 +#endif /* MIN */
4037 +
4038 +#ifndef MAX
4039 +#define MAX(a, b) (((a) > (b))?(a):(b))
4040 +#endif /* MAX */
4041 +
4042 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
4043 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
4044 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
4045 +#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
4046 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
4047 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
4048 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
4049 +
4050 +/* bit map related macros */
4051 +#ifndef setbit
4052 +#ifndef NBBY /* the BSD family defines NBBY */
4053 +#define NBBY 8 /* 8 bits per byte */
4054 +#endif /* #ifndef NBBY */
4055 +#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
4056 +#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
4057 +#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
4058 +#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
4059 +#endif /* setbit */
4060 +
4061 +#define NBITS(type) (sizeof(type) * 8)
4062 +#define NBITVAL(nbits) (1 << (nbits))
4063 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
4064 +#define NBITMASK(nbits) MAXBITVAL(nbits)
4065 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
4066 +
4067 +/* basic mux operation - can be optimized on several architectures */
4068 +#define MUX(pred, true, false) ((pred) ? (true) : (false))
4069 +
4070 +/* modulo inc/dec - assumes x E [0, bound - 1] */
4071 +#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
4072 +#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
4073 +
4074 +/* modulo inc/dec, bound = 2^k */
4075 +#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
4076 +#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
4077 +
4078 +/* modulo add/sub - assumes x, y E [0, bound - 1] */
4079 +#define MODADD(x, y, bound) \
4080 + MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
4081 +#define MODSUB(x, y, bound) \
4082 + MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
4083 +
4084 +/* module add/sub, bound = 2^k */
4085 +#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
4086 +#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
4087 +
4088 +/* crc defines */
4089 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
4090 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
4091 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
4092 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
4093 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
4094 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
4095 +
4096 +/* bcm_format_flags() bit description structure */
4097 +typedef struct bcm_bit_desc {
4098 + uint32 bit;
4099 + char* name;
4100 +} bcm_bit_desc_t;
4101 +
4102 +/* tag_ID/length/value_buffer tuple */
4103 +typedef struct bcm_tlv {
4104 + uint8 id;
4105 + uint8 len;
4106 + uint8 data[1];
4107 +} bcm_tlv_t;
4108 +
4109 +/* Check that bcm_tlv_t fits into the given buflen */
4110 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
4111 +
4112 +/* buffer length for ethernet address from bcm_ether_ntoa() */
4113 +#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
4114 +
4115 +/* unaligned load and store macros */
4116 +#ifdef IL_BIGENDIAN
4117 +static INLINE uint32
4118 +load32_ua(uint8 *a)
4119 +{
4120 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
4121 +}
4122 +
4123 +static INLINE void
4124 +store32_ua(uint8 *a, uint32 v)
4125 +{
4126 + a[0] = (v >> 24) & 0xff;
4127 + a[1] = (v >> 16) & 0xff;
4128 + a[2] = (v >> 8) & 0xff;
4129 + a[3] = v & 0xff;
4130 +}
4131 +
4132 +static INLINE uint16
4133 +load16_ua(uint8 *a)
4134 +{
4135 + return ((a[0] << 8) | a[1]);
4136 +}
4137 +
4138 +static INLINE void
4139 +store16_ua(uint8 *a, uint16 v)
4140 +{
4141 + a[0] = (v >> 8) & 0xff;
4142 + a[1] = v & 0xff;
4143 +}
4144 +
4145 +#else
4146 +
4147 +static INLINE uint32
4148 +load32_ua(uint8 *a)
4149 +{
4150 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
4151 +}
4152 +
4153 +static INLINE void
4154 +store32_ua(uint8 *a, uint32 v)
4155 +{
4156 + a[3] = (v >> 24) & 0xff;
4157 + a[2] = (v >> 16) & 0xff;
4158 + a[1] = (v >> 8) & 0xff;
4159 + a[0] = v & 0xff;
4160 +}
4161 +
4162 +static INLINE uint16
4163 +load16_ua(uint8 *a)
4164 +{
4165 + return ((a[1] << 8) | a[0]);
4166 +}
4167 +
4168 +static INLINE void
4169 +store16_ua(uint8 *a, uint16 v)
4170 +{
4171 + a[1] = (v >> 8) & 0xff;
4172 + a[0] = v & 0xff;
4173 +}
4174 +
4175 +#endif /* IL_BIGENDIAN */
4176 +
4177 +/* externs */
4178 +/* crc */
4179 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
4180 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
4181 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
4182 +/* format/print */
4183 +extern void printfbig(char *buf);
4184 +
4185 +/* IE parsing */
4186 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
4187 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
4188 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
4189 +
4190 +/* bcmerror */
4191 +extern const char *bcmerrorstr(int bcmerror);
4192 +
4193 +/* multi-bool data type: set of bools, mbool is true if any is set */
4194 +typedef uint32 mbool;
4195 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
4196 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
4197 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
4198 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
4199 +
4200 +/* power conversion */
4201 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
4202 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
4203 +
4204 +/* generic datastruct to help dump routines */
4205 +struct fielddesc {
4206 + char *nameandfmt;
4207 + uint32 offset;
4208 + uint32 len;
4209 +};
4210 +
4211 +/* Buffer structure for collecting string-formatted data
4212 +* using bcm_bprintf() API.
4213 +* Use bcm_binit() to initialize before use
4214 +*/
4215 +struct bcmstrbuf
4216 +{
4217 + char *buf; /* pointer to current position in origbuf */
4218 + uint size; /* current (residual) size in bytes */
4219 + char *origbuf; /* unmodified pointer to orignal buffer */
4220 + uint origsize; /* unmodified orignal buffer size in bytes */
4221 +};
4222 +
4223 +extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
4224 +extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
4225 +
4226 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
4227 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
4228 + char *buf, uint32 bufsize);
4229 +
4230 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
4231 +extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
4232 +
4233 +#endif /* _bcmutils_h_ */
4234 diff -urN linux.old/arch/mips/bcm947xx/include/hndcpu.h linux.dev/arch/mips/bcm947xx/include/hndcpu.h
4235 --- linux.old/arch/mips/bcm947xx/include/hndcpu.h 1970-01-01 01:00:00.000000000 +0100
4236 +++ linux.dev/arch/mips/bcm947xx/include/hndcpu.h 2006-10-02 21:19:59.000000000 +0200
4237 @@ -0,0 +1,28 @@
4238 +/*
4239 + * HND SiliconBackplane MIPS/ARM cores software interface.
4240 + *
4241 + * Copyright 2006, Broadcom Corporation
4242 + * All Rights Reserved.
4243 + *
4244 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4245 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4246 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4247 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4248 + *
4249 + * $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4250 + */
4251 +
4252 +#ifndef _hndcpu_h_
4253 +#define _hndcpu_h_
4254 +
4255 +#if defined(mips)
4256 +#include <hndmips.h>
4257 +#elif defined(__ARM_ARCH_4T__)
4258 +#include <hndarm.h>
4259 +#endif
4260 +
4261 +extern uint sb_irq(sb_t *sbh);
4262 +extern uint32 sb_cpu_clock(sb_t *sbh);
4263 +extern void sb_cpu_wait(void);
4264 +
4265 +#endif /* _hndcpu_h_ */
4266 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
4267 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
4268 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-10-02 21:19:59.000000000 +0200
4269 @@ -0,0 +1,45 @@
4270 +/*
4271 + * HND SiliconBackplane MIPS core software interface.
4272 + *
4273 + * Copyright 2006, Broadcom Corporation
4274 + * All Rights Reserved.
4275 + *
4276 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4277 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4278 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4279 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4280 + *
4281 + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
4282 + */
4283 +
4284 +#ifndef _hndmips_h_
4285 +#define _hndmips_h_
4286 +
4287 +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
4288 +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4289 +extern void enable_pfc(uint32 mode);
4290 +extern uint32 sb_memc_get_ncdl(sb_t *sbh);
4291 +
4292 +#if defined(BCMPERFSTATS)
4293 +/* enable counting - exclusive version. Only one set of counters allowed at a time */
4294 +extern void hndmips_perf_instrcount_enable(void);
4295 +extern void hndmips_perf_icachecount_enable(void);
4296 +extern void hndmips_perf_dcachecount_enable(void);
4297 +/* start and stop counting */
4298 +#define hndmips_perf_start01() \
4299 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
4300 +#define hndmips_perf_stop01() \
4301 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
4302 +/* retrieve coutners - counters *decrement* */
4303 +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
4304 +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
4305 +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
4306 +/* enable counting - modular version. Each counters can be enabled separately. */
4307 +extern void hndmips_perf_icache_hit_enable(void);
4308 +extern void hndmips_perf_icache_miss_enable(void);
4309 +extern uint32 hndmips_perf_read_instrcount(void);
4310 +extern uint32 hndmips_perf_read_cache_miss(void);
4311 +extern uint32 hndmips_perf_read_cache_hit(void);
4312 +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
4313 +
4314 +#endif /* _hndmips_h_ */
4315 diff -urN linux.old/arch/mips/bcm947xx/include/hndpci.h linux.dev/arch/mips/bcm947xx/include/hndpci.h
4316 --- linux.old/arch/mips/bcm947xx/include/hndpci.h 1970-01-01 01:00:00.000000000 +0100
4317 +++ linux.dev/arch/mips/bcm947xx/include/hndpci.h 2006-10-02 21:19:59.000000000 +0200
4318 @@ -0,0 +1,30 @@
4319 +/*
4320 + * HND SiliconBackplane PCI core software interface.
4321 + *
4322 + * $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4323 + * Copyright 2006, Broadcom Corporation
4324 + * All Rights Reserved.
4325 + *
4326 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4327 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4328 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4329 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4330 + */
4331 +
4332 +#ifndef _hndpci_h_
4333 +#define _hndpci_h_
4334 +
4335 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4336 + int len);
4337 +extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4338 + int len);
4339 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4340 + int len);
4341 +extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4342 + int len);
4343 +extern void sbpci_ban(uint16 core);
4344 +extern int sbpci_init(sb_t *sbh);
4345 +extern int sbpci_init_pci(sb_t *sbh);
4346 +extern void sbpci_check(sb_t *sbh);
4347 +
4348 +#endif /* _hndpci_h_ */
4349 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
4350 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
4351 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-10-02 21:19:59.000000000 +0200
4352 @@ -0,0 +1,417 @@
4353 +/*
4354 + * Linux-specific abstractions to gain some independence from linux kernel versions.
4355 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
4356 + *
4357 + * Copyright 2006, Broadcom Corporation
4358 + * All Rights Reserved.
4359 + *
4360 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4361 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4362 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4363 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4364 + *
4365 + * $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
4366 + */
4367 +
4368 +#ifndef _linuxver_h_
4369 +#define _linuxver_h_
4370 +
4371 +#include <linux/config.h>
4372 +#include <linux/version.h>
4373 +
4374 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
4375 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
4376 +#ifdef __UNDEF_NO_VERSION__
4377 +#undef __NO_VERSION__
4378 +#else
4379 +#define __NO_VERSION__
4380 +#endif
4381 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
4382 +
4383 +#if defined(MODULE) && defined(MODVERSIONS)
4384 +#include <linux/modversions.h>
4385 +#endif
4386 +
4387 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
4388 +#include <linux/moduleparam.h>
4389 +#endif
4390 +
4391 +
4392 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
4393 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
4394 +#define module_param_string(_name_, _string_, _size_, _perm_) \
4395 + MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
4396 +#endif
4397 +
4398 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
4399 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
4400 +#include <linux/malloc.h>
4401 +#else
4402 +#include <linux/slab.h>
4403 +#endif
4404 +
4405 +#include <linux/types.h>
4406 +#include <linux/init.h>
4407 +#include <linux/mm.h>
4408 +#include <linux/string.h>
4409 +#include <linux/pci.h>
4410 +#include <linux/interrupt.h>
4411 +#include <linux/netdevice.h>
4412 +#include <asm/io.h>
4413 +
4414 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
4415 +#include <linux/workqueue.h>
4416 +#else
4417 +#include <linux/tqueue.h>
4418 +#ifndef work_struct
4419 +#define work_struct tq_struct
4420 +#endif
4421 +#ifndef INIT_WORK
4422 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
4423 +#endif
4424 +#ifndef schedule_work
4425 +#define schedule_work(_work) schedule_task((_work))
4426 +#endif
4427 +#ifndef flush_scheduled_work
4428 +#define flush_scheduled_work() flush_scheduled_tasks()
4429 +#endif
4430 +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
4431 +
4432 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4433 +/* Some distributions have their own 2.6.x compatibility layers */
4434 +#ifndef IRQ_NONE
4435 +typedef void irqreturn_t;
4436 +#define IRQ_NONE
4437 +#define IRQ_HANDLED
4438 +#define IRQ_RETVAL(x)
4439 +#endif
4440 +#else
4441 +typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
4442 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
4443 +
4444 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
4445 +
4446 +#include <pcmcia/version.h>
4447 +#include <pcmcia/cs_types.h>
4448 +#include <pcmcia/cs.h>
4449 +#include <pcmcia/cistpl.h>
4450 +#include <pcmcia/cisreg.h>
4451 +#include <pcmcia/ds.h>
4452 +
4453 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
4454 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
4455 + * does this, but it's not in 2.4 so we do our own for now.
4456 + */
4457 +static inline void
4458 +cs_error(client_handle_t handle, int func, int ret)
4459 +{
4460 + error_info_t err = { func, ret };
4461 + CardServices(ReportError, handle, &err);
4462 +}
4463 +#endif
4464 +
4465 +#endif /* CONFIG_PCMCIA */
4466 +
4467 +#ifndef __exit
4468 +#define __exit
4469 +#endif
4470 +#ifndef __devexit
4471 +#define __devexit
4472 +#endif
4473 +#ifndef __devinit
4474 +#define __devinit __init
4475 +#endif
4476 +#ifndef __devinitdata
4477 +#define __devinitdata
4478 +#endif
4479 +#ifndef __devexit_p
4480 +#define __devexit_p(x) x
4481 +#endif
4482 +
4483 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
4484 +
4485 +#define pci_get_drvdata(dev) (dev)->sysdata
4486 +#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
4487 +
4488 +/*
4489 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
4490 + */
4491 +
4492 +struct pci_device_id {
4493 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
4494 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
4495 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
4496 + unsigned long driver_data; /* Data private to the driver */
4497 +};
4498 +
4499 +struct pci_driver {
4500 + struct list_head node;
4501 + char *name;
4502 + const struct pci_device_id *id_table; /* NULL if wants all devices */
4503 + int (*probe)(struct pci_dev *dev,
4504 + const struct pci_device_id *id); /* New device inserted */
4505 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
4506 + * capable driver)
4507 + */
4508 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
4509 + void (*resume)(struct pci_dev *dev); /* Device woken up */
4510 +};
4511 +
4512 +#define MODULE_DEVICE_TABLE(type, name)
4513 +#define PCI_ANY_ID (~0)
4514 +
4515 +/* compatpci.c */
4516 +#define pci_module_init pci_register_driver
4517 +extern int pci_register_driver(struct pci_driver *drv);
4518 +extern void pci_unregister_driver(struct pci_driver *drv);
4519 +
4520 +#endif /* PCI registration */
4521 +
4522 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
4523 +#ifdef MODULE
4524 +#define module_init(x) int init_module(void) { return x(); }
4525 +#define module_exit(x) void cleanup_module(void) { x(); }
4526 +#else
4527 +#define module_init(x) __initcall(x);
4528 +#define module_exit(x) __exitcall(x);
4529 +#endif
4530 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
4531 +
4532 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
4533 +#define list_for_each(pos, head) \
4534 + for (pos = (head)->next; pos != (head); pos = pos->next)
4535 +#endif
4536 +
4537 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
4538 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
4539 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
4540 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
4541 +#endif
4542 +
4543 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
4544 +#define pci_enable_device(dev) do { } while (0)
4545 +#endif
4546 +
4547 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
4548 +#define net_device device
4549 +#endif
4550 +
4551 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
4552 +
4553 +/*
4554 + * DMA mapping
4555 + *
4556 + * See linux/Documentation/DMA-mapping.txt
4557 + */
4558 +
4559 +#ifndef PCI_DMA_TODEVICE
4560 +#define PCI_DMA_TODEVICE 1
4561 +#define PCI_DMA_FROMDEVICE 2
4562 +#endif
4563 +
4564 +typedef u32 dma_addr_t;
4565 +
4566 +/* Pure 2^n version of get_order */
4567 +static inline int get_order(unsigned long size)
4568 +{
4569 + int order;
4570 +
4571 + size = (size-1) >> (PAGE_SHIFT-1);
4572 + order = -1;
4573 + do {
4574 + size >>= 1;
4575 + order++;
4576 + } while (size);
4577 + return order;
4578 +}
4579 +
4580 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
4581 + dma_addr_t *dma_handle)
4582 +{
4583 + void *ret;
4584 + int gfp = GFP_ATOMIC | GFP_DMA;
4585 +
4586 + ret = (void *)__get_free_pages(gfp, get_order(size));
4587 +
4588 + if (ret != NULL) {
4589 + memset(ret, 0, size);
4590 + *dma_handle = virt_to_bus(ret);
4591 + }
4592 + return ret;
4593 +}
4594 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
4595 + void *vaddr, dma_addr_t dma_handle)
4596 +{
4597 + free_pages((unsigned long)vaddr, get_order(size));
4598 +}
4599 +#ifdef ILSIM
4600 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
4601 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
4602 +#else
4603 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
4604 +#define pci_unmap_single(cookie, address, size, dir)
4605 +#endif
4606 +
4607 +#endif /* DMA mapping */
4608 +
4609 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
4610 +
4611 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
4612 +#define netif_down(dev) do { (dev)->start = 0; } while (0)
4613 +
4614 +/* pcmcia-cs provides its own netdevice compatibility layer */
4615 +#ifndef _COMPAT_NETDEVICE_H
4616 +
4617 +/*
4618 + * SoftNet
4619 + *
4620 + * For pre-softnet kernels we need to tell the upper layer not to
4621 + * re-enter start_xmit() while we are in there. However softnet
4622 + * guarantees not to enter while we are in there so there is no need
4623 + * to do the netif_stop_queue() dance unless the transmit queue really
4624 + * gets stuck. This should also improve performance according to tests
4625 + * done by Aman Singla.
4626 + */
4627 +
4628 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
4629 +#define netif_wake_queue(dev) \
4630 + do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
4631 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
4632 +
4633 +static inline void netif_start_queue(struct net_device *dev)
4634 +{
4635 + dev->tbusy = 0;
4636 + dev->interrupt = 0;
4637 + dev->start = 1;
4638 +}
4639 +
4640 +#define netif_queue_stopped(dev) (dev)->tbusy
4641 +#define netif_running(dev) (dev)->start
4642 +
4643 +#endif /* _COMPAT_NETDEVICE_H */
4644 +
4645 +#define netif_device_attach(dev) netif_start_queue(dev)
4646 +#define netif_device_detach(dev) netif_stop_queue(dev)
4647 +
4648 +/* 2.4.x renamed bottom halves to tasklets */
4649 +#define tasklet_struct tq_struct
4650 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
4651 +{
4652 + queue_task(tasklet, &tq_immediate);
4653 + mark_bh(IMMEDIATE_BH);
4654 +}
4655 +
4656 +static inline void tasklet_init(struct tasklet_struct *tasklet,
4657 + void (*func)(unsigned long),
4658 + unsigned long data)
4659 +{
4660 + tasklet->next = NULL;
4661 + tasklet->sync = 0;
4662 + tasklet->routine = (void (*)(void *))func;
4663 + tasklet->data = (void *)data;
4664 +}
4665 +#define tasklet_kill(tasklet) { do{} while (0); }
4666 +
4667 +/* 2.4.x introduced del_timer_sync() */
4668 +#define del_timer_sync(timer) del_timer(timer)
4669 +
4670 +#else
4671 +
4672 +#define netif_down(dev)
4673 +
4674 +#endif /* SoftNet */
4675 +
4676 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
4677 +
4678 +/*
4679 + * Emit code to initialise a tq_struct's routine and data pointers
4680 + */
4681 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
4682 + do { \
4683 + (_tq)->routine = _routine; \
4684 + (_tq)->data = _data; \
4685 + } while (0)
4686 +
4687 +/*
4688 + * Emit code to initialise all of a tq_struct
4689 + */
4690 +#define INIT_TQUEUE(_tq, _routine, _data) \
4691 + do { \
4692 + INIT_LIST_HEAD(&(_tq)->list); \
4693 + (_tq)->sync = 0; \
4694 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
4695 + } while (0)
4696 +
4697 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
4698 +
4699 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
4700 +
4701 +/* Power management related routines */
4702 +
4703 +static inline int
4704 +pci_save_state(struct pci_dev *dev, u32 *buffer)
4705 +{
4706 + int i;
4707 + if (buffer) {
4708 + for (i = 0; i < 16; i++)
4709 + pci_read_config_dword(dev, i * 4, &buffer[i]);
4710 + }
4711 + return 0;
4712 +}
4713 +
4714 +static inline int
4715 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
4716 +{
4717 + int i;
4718 +
4719 + if (buffer) {
4720 + for (i = 0; i < 16; i++)
4721 + pci_write_config_dword(dev, i * 4, buffer[i]);
4722 + }
4723 + /*
4724 + * otherwise, write the context information we know from bootup.
4725 + * This works around a problem where warm-booting from Windows
4726 + * combined with a D3(hot)->D0 transition causes PCI config
4727 + * header data to be forgotten.
4728 + */
4729 + else {
4730 + for (i = 0; i < 6; i ++)
4731 + pci_write_config_dword(dev,
4732 + PCI_BASE_ADDRESS_0 + (i * 4),
4733 + pci_resource_start(dev, i));
4734 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4735 + }
4736 + return 0;
4737 +}
4738 +
4739 +#endif /* PCI power management */
4740 +
4741 +/* Old cp0 access macros deprecated in 2.4.19 */
4742 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
4743 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
4744 +#endif
4745 +
4746 +/* Module refcount handled internally in 2.6.x */
4747 +#ifndef SET_MODULE_OWNER
4748 +#define SET_MODULE_OWNER(dev) do {} while (0)
4749 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
4750 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
4751 +#else
4752 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
4753 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
4754 +#endif
4755 +
4756 +#ifndef SET_NETDEV_DEV
4757 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
4758 +#endif
4759 +
4760 +#ifndef HAVE_FREE_NETDEV
4761 +#define free_netdev(dev) kfree(dev)
4762 +#endif
4763 +
4764 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4765 +/* struct packet_type redefined in 2.6.x */
4766 +#define af_packet_priv data
4767 +#endif
4768 +
4769 +#endif /* _linuxver_h_ */
4770 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
4771 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
4772 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-10-02 21:19:59.000000000 +0200
4773 @@ -0,0 +1,541 @@
4774 +/*
4775 + * HND Run Time Environment for standalone MIPS programs.
4776 + *
4777 + * Copyright 2006, Broadcom Corporation
4778 + * All Rights Reserved.
4779 + *
4780 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4781 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4782 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4783 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4784 + *
4785 + * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
4786 + */
4787 +
4788 +#ifndef _MISPINC_H
4789 +#define _MISPINC_H
4790 +
4791 +
4792 +/* MIPS defines */
4793 +
4794 +#ifdef _LANGUAGE_ASSEMBLY
4795 +
4796 +/*
4797 + * Symbolic register names for 32 bit ABI
4798 + */
4799 +#define zero $0 /* wired zero */
4800 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
4801 +#define v0 $2 /* return value */
4802 +#define v1 $3
4803 +#define a0 $4 /* argument registers */
4804 +#define a1 $5
4805 +#define a2 $6
4806 +#define a3 $7
4807 +#define t0 $8 /* caller saved */
4808 +#define t1 $9
4809 +#define t2 $10
4810 +#define t3 $11
4811 +#define t4 $12
4812 +#define t5 $13
4813 +#define t6 $14
4814 +#define t7 $15
4815 +#define s0 $16 /* callee saved */
4816 +#define s1 $17
4817 +#define s2 $18
4818 +#define s3 $19
4819 +#define s4 $20
4820 +#define s5 $21
4821 +#define s6 $22
4822 +#define s7 $23
4823 +#define t8 $24 /* caller saved */
4824 +#define t9 $25
4825 +#define jp $25 /* PIC jump register */
4826 +#define k0 $26 /* kernel scratch */
4827 +#define k1 $27
4828 +#define gp $28 /* global pointer */
4829 +#define sp $29 /* stack pointer */
4830 +#define fp $30 /* frame pointer */
4831 +#define s8 $30 /* same like fp! */
4832 +#define ra $31 /* return address */
4833 +
4834 +
4835 +/* CP0 Registers */
4836 +
4837 +#define C0_INX $0
4838 +#define C0_RAND $1
4839 +#define C0_TLBLO0 $2
4840 +#define C0_TLBLO C0_TLBLO0
4841 +#define C0_TLBLO1 $3
4842 +#define C0_CTEXT $4
4843 +#define C0_PGMASK $5
4844 +#define C0_WIRED $6
4845 +#define C0_BADVADDR $8
4846 +#define C0_COUNT $9
4847 +#define C0_TLBHI $10
4848 +#define C0_COMPARE $11
4849 +#define C0_SR $12
4850 +#define C0_STATUS C0_SR
4851 +#define C0_CAUSE $13
4852 +#define C0_EPC $14
4853 +#define C0_PRID $15
4854 +#define C0_CONFIG $16
4855 +#define C0_LLADDR $17
4856 +#define C0_WATCHLO $18
4857 +#define C0_WATCHHI $19
4858 +#define C0_XCTEXT $20
4859 +#define C0_DIAGNOSTIC $22
4860 +#define C0_BROADCOM C0_DIAGNOSTIC
4861 +#define C0_PERFORMANCE $25
4862 +#define C0_ECC $26
4863 +#define C0_CACHEERR $27
4864 +#define C0_TAGLO $28
4865 +#define C0_TAGHI $29
4866 +#define C0_ERREPC $30
4867 +#define C0_DESAVE $31
4868 +
4869 +/*
4870 + * LEAF - declare leaf routine
4871 + */
4872 +#define LEAF(symbol) \
4873 + .globl symbol; \
4874 + .align 2; \
4875 + .type symbol, @function; \
4876 + .ent symbol, 0; \
4877 +symbol: .frame sp, 0, ra
4878 +
4879 +/*
4880 + * END - mark end of function
4881 + */
4882 +#define END(function) \
4883 + .end function; \
4884 + .size function, . - function
4885 +
4886 +#define _ULCAST_
4887 +
4888 +#define MFC0_SEL(dst, src, sel) \
4889 + .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
4890 +
4891 +
4892 +#define MTC0_SEL(dst, src, sel) \
4893 + .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
4894 +
4895 +#else
4896 +
4897 +/*
4898 + * The following macros are especially useful for __asm__
4899 + * inline assembler.
4900 + */
4901 +#ifndef __STR
4902 +#define __STR(x) #x
4903 +#endif
4904 +#ifndef STR
4905 +#define STR(x) __STR(x)
4906 +#endif
4907 +
4908 +#define _ULCAST_ (unsigned long)
4909 +
4910 +
4911 +/* CP0 Registers */
4912 +
4913 +#define C0_INX 0 /* CP0: TLB Index */
4914 +#define C0_RAND 1 /* CP0: TLB Random */
4915 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4916 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4917 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4918 +#define C0_CTEXT 4 /* CP0: Context */
4919 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4920 +#define C0_WIRED 6 /* CP0: TLB Wired */
4921 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4922 +#define C0_COUNT 9 /* CP0: Count */
4923 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4924 +#define C0_COMPARE 11 /* CP0: Compare */
4925 +#define C0_SR 12 /* CP0: Processor Status */
4926 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4927 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4928 +#define C0_EPC 14 /* CP0: Exception PC */
4929 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4930 +#define C0_CONFIG 16 /* CP0: Config */
4931 +#define C0_LLADDR 17 /* CP0: LLAddr */
4932 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4933 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4934 +#define C0_XCTEXT 20 /* CP0: XContext */
4935 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4936 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4937 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4938 +#define C0_ECC 26 /* CP0: ECC */
4939 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4940 +#define C0_TAGLO 28 /* CP0: TagLo */
4941 +#define C0_TAGHI 29 /* CP0: TagHi */
4942 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4943 +#define C0_DESAVE 31 /* CP0: DebugSave */
4944 +
4945 +#endif /* _LANGUAGE_ASSEMBLY */
4946 +
4947 +/*
4948 + * Memory segments (32bit kernel mode addresses)
4949 + */
4950 +#undef KUSEG
4951 +#undef KSEG0
4952 +#undef KSEG1
4953 +#undef KSEG2
4954 +#undef KSEG3
4955 +#define KUSEG 0x00000000
4956 +#define KSEG0 0x80000000
4957 +#define KSEG1 0xa0000000
4958 +#define KSEG2 0xc0000000
4959 +#define KSEG3 0xe0000000
4960 +#define PHYSADDR_MASK 0x1fffffff
4961 +
4962 +/*
4963 + * Map an address to a certain kernel segment
4964 + */
4965 +#undef PHYSADDR
4966 +#undef KSEG0ADDR
4967 +#undef KSEG1ADDR
4968 +#undef KSEG2ADDR
4969 +#undef KSEG3ADDR
4970 +
4971 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
4972 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
4973 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
4974 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
4975 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
4976 +
4977 +
4978 +#ifndef Index_Invalidate_I
4979 +/*
4980 + * Cache Operations
4981 + */
4982 +#define Index_Invalidate_I 0x00
4983 +#define Index_Writeback_Inv_D 0x01
4984 +#define Index_Invalidate_SI 0x02
4985 +#define Index_Writeback_Inv_SD 0x03
4986 +#define Index_Load_Tag_I 0x04
4987 +#define Index_Load_Tag_D 0x05
4988 +#define Index_Load_Tag_SI 0x06
4989 +#define Index_Load_Tag_SD 0x07
4990 +#define Index_Store_Tag_I 0x08
4991 +#define Index_Store_Tag_D 0x09
4992 +#define Index_Store_Tag_SI 0x0A
4993 +#define Index_Store_Tag_SD 0x0B
4994 +#define Create_Dirty_Excl_D 0x0d
4995 +#define Create_Dirty_Excl_SD 0x0f
4996 +#define Hit_Invalidate_I 0x10
4997 +#define Hit_Invalidate_D 0x11
4998 +#define Hit_Invalidate_SI 0x12
4999 +#define Hit_Invalidate_SD 0x13
5000 +#define Fill_I 0x14
5001 +#define Hit_Writeback_Inv_D 0x15
5002 + /* 0x16 is unused */
5003 +#define Hit_Writeback_Inv_SD 0x17
5004 +#define R5K_Page_Invalidate_S 0x17
5005 +#define Hit_Writeback_I 0x18
5006 +#define Hit_Writeback_D 0x19
5007 + /* 0x1a is unused */
5008 +#define Hit_Writeback_SD 0x1b
5009 + /* 0x1c is unused */
5010 + /* 0x1e is unused */
5011 +#define Hit_Set_Virtual_SI 0x1e
5012 +#define Hit_Set_Virtual_SD 0x1f
5013 +#endif /* !Index_Invalidate_I */
5014 +
5015 +
5016 +/*
5017 + * R4x00 interrupt enable / cause bits
5018 + */
5019 +#define IE_SW0 (_ULCAST_(1) << 8)
5020 +#define IE_SW1 (_ULCAST_(1) << 9)
5021 +#define IE_IRQ0 (_ULCAST_(1) << 10)
5022 +#define IE_IRQ1 (_ULCAST_(1) << 11)
5023 +#define IE_IRQ2 (_ULCAST_(1) << 12)
5024 +#define IE_IRQ3 (_ULCAST_(1) << 13)
5025 +#define IE_IRQ4 (_ULCAST_(1) << 14)
5026 +#define IE_IRQ5 (_ULCAST_(1) << 15)
5027 +
5028 +#ifndef ST0_UM
5029 +/*
5030 + * Bitfields in the mips32 cp0 status register
5031 + */
5032 +#define ST0_IE 0x00000001
5033 +#define ST0_EXL 0x00000002
5034 +#define ST0_ERL 0x00000004
5035 +#define ST0_UM 0x00000010
5036 +#define ST0_SWINT0 0x00000100
5037 +#define ST0_SWINT1 0x00000200
5038 +#define ST0_HWINT0 0x00000400
5039 +#define ST0_HWINT1 0x00000800
5040 +#define ST0_HWINT2 0x00001000
5041 +#define ST0_HWINT3 0x00002000
5042 +#define ST0_HWINT4 0x00004000
5043 +#define ST0_HWINT5 0x00008000
5044 +#define ST0_IM 0x0000ff00
5045 +#define ST0_NMI 0x00080000
5046 +#define ST0_SR 0x00100000
5047 +#define ST0_TS 0x00200000
5048 +#define ST0_BEV 0x00400000
5049 +#define ST0_RE 0x02000000
5050 +#define ST0_RP 0x08000000
5051 +#define ST0_CU 0xf0000000
5052 +#define ST0_CU0 0x10000000
5053 +#define ST0_CU1 0x20000000
5054 +#define ST0_CU2 0x40000000
5055 +#define ST0_CU3 0x80000000
5056 +#endif /* !ST0_UM */
5057 +
5058 +
5059 +/*
5060 + * Bitfields in the mips32 cp0 cause register
5061 + */
5062 +#define C_EXC 0x0000007c
5063 +#define C_EXC_SHIFT 2
5064 +#define C_INT 0x0000ff00
5065 +#define C_INT_SHIFT 8
5066 +#define C_SW0 (_ULCAST_(1) << 8)
5067 +#define C_SW1 (_ULCAST_(1) << 9)
5068 +#define C_IRQ0 (_ULCAST_(1) << 10)
5069 +#define C_IRQ1 (_ULCAST_(1) << 11)
5070 +#define C_IRQ2 (_ULCAST_(1) << 12)
5071 +#define C_IRQ3 (_ULCAST_(1) << 13)
5072 +#define C_IRQ4 (_ULCAST_(1) << 14)
5073 +#define C_IRQ5 (_ULCAST_(1) << 15)
5074 +#define C_WP 0x00400000
5075 +#define C_IV 0x00800000
5076 +#define C_CE 0x30000000
5077 +#define C_CE_SHIFT 28
5078 +#define C_BD 0x80000000
5079 +
5080 +/* Values in C_EXC */
5081 +#define EXC_INT 0
5082 +#define EXC_TLBM 1
5083 +#define EXC_TLBL 2
5084 +#define EXC_TLBS 3
5085 +#define EXC_AEL 4
5086 +#define EXC_AES 5
5087 +#define EXC_IBE 6
5088 +#define EXC_DBE 7
5089 +#define EXC_SYS 8
5090 +#define EXC_BPT 9
5091 +#define EXC_RI 10
5092 +#define EXC_CU 11
5093 +#define EXC_OV 12
5094 +#define EXC_TR 13
5095 +#define EXC_WATCH 23
5096 +#define EXC_MCHK 24
5097 +
5098 +
5099 +/*
5100 + * Bits in the cp0 config register.
5101 + */
5102 +#define CONF_CM_CACHABLE_NO_WA 0
5103 +#define CONF_CM_CACHABLE_WA 1
5104 +#define CONF_CM_UNCACHED 2
5105 +#define CONF_CM_CACHABLE_NONCOHERENT 3
5106 +#define CONF_CM_CACHABLE_CE 4
5107 +#define CONF_CM_CACHABLE_COW 5
5108 +#define CONF_CM_CACHABLE_CUW 6
5109 +#define CONF_CM_CACHABLE_ACCELERATED 7
5110 +#define CONF_CM_CMASK 7
5111 +#define CONF_CU (_ULCAST_(1) << 3)
5112 +#define CONF_DB (_ULCAST_(1) << 4)
5113 +#define CONF_IB (_ULCAST_(1) << 5)
5114 +#define CONF_SE (_ULCAST_(1) << 12)
5115 +#ifndef CONF_BE /* duplicate in mipsregs.h */
5116 +#define CONF_BE (_ULCAST_(1) << 15)
5117 +#endif
5118 +#define CONF_SC (_ULCAST_(1) << 17)
5119 +#define CONF_AC (_ULCAST_(1) << 23)
5120 +#define CONF_HALT (_ULCAST_(1) << 25)
5121 +#ifndef CONF_M /* duplicate in mipsregs.h */
5122 +#define CONF_M (_ULCAST_(1) << 31)
5123 +#endif
5124 +
5125 +
5126 +/*
5127 + * Bits in the cp0 config register select 1.
5128 + */
5129 +#define CONF1_FP 0x00000001 /* FPU present */
5130 +#define CONF1_EP 0x00000002 /* EJTAG present */
5131 +#define CONF1_CA 0x00000004 /* mips16 implemented */
5132 +#define CONF1_WR 0x00000008 /* Watch registers present */
5133 +#define CONF1_PC 0x00000010 /* Performance counters present */
5134 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
5135 +#define CONF1_DA_MASK 0x00000380
5136 +#define CONF1_DA_BASE 1
5137 +#define CONF1_DL_SHIFT 10 /* D$ line size */
5138 +#define CONF1_DL_MASK 0x00001c00
5139 +#define CONF1_DL_BASE 2
5140 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
5141 +#define CONF1_DS_MASK 0x0000e000
5142 +#define CONF1_DS_BASE 64
5143 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
5144 +#define CONF1_IA_MASK 0x00070000
5145 +#define CONF1_IA_BASE 1
5146 +#define CONF1_IL_SHIFT 19 /* I$ line size */
5147 +#define CONF1_IL_MASK 0x00380000
5148 +#define CONF1_IL_BASE 2
5149 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
5150 +#define CONF1_IS_MASK 0x01c00000
5151 +#define CONF1_IS_BASE 64
5152 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
5153 +#define CONF1_MS_SHIFT 25
5154 +
5155 +/* PRID register */
5156 +#define PRID_COPT_MASK 0xff000000
5157 +#define PRID_COMP_MASK 0x00ff0000
5158 +#define PRID_IMP_MASK 0x0000ff00
5159 +#define PRID_REV_MASK 0x000000ff
5160 +
5161 +#define PRID_COMP_LEGACY 0x000000
5162 +#define PRID_COMP_MIPS 0x010000
5163 +#define PRID_COMP_BROADCOM 0x020000
5164 +#define PRID_COMP_ALCHEMY 0x030000
5165 +#define PRID_COMP_SIBYTE 0x040000
5166 +#define PRID_IMP_BCM4710 0x4000
5167 +#define PRID_IMP_BCM3302 0x9000
5168 +#define PRID_IMP_BCM3303 0x9100
5169 +
5170 +#define PRID_IMP_UNKNOWN 0xff00
5171 +
5172 +#define BCM330X(id) \
5173 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5174 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
5175 + ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5176 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
5177 +
5178 +/* Bits in C0_BROADCOM */
5179 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
5180 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
5181 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
5182 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
5183 +#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
5184 +
5185 +/* PreFetch Cache aka Read Ahead Cache */
5186 +
5187 +#define PFC_CR0 0xff400000 /* control reg 0 */
5188 +#define PFC_CR1 0xff400004 /* control reg 1 */
5189 +
5190 +/* PFC operations */
5191 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
5192 +#define PFC_D 0x00000002 /* Enable PFC use for data */
5193 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
5194 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
5195 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
5196 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
5197 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
5198 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
5199 +#define PFC_BRR 0x40000000 /* Bus error indication */
5200 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
5201 +
5202 +/* Handy defaults */
5203 +#define PFC_DISABLED 0
5204 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
5205 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
5206 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
5207 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
5208 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
5209 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
5210 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
5211 +
5212 +#ifndef _LANGUAGE_ASSEMBLY
5213 +
5214 +/*
5215 + * Macros to access the system control coprocessor
5216 + */
5217 +
5218 +#define MFC0(source, sel) \
5219 +({ \
5220 + int __res; \
5221 + __asm__ __volatile__(" \
5222 + .set\tnoreorder; \
5223 + .set\tnoat; \
5224 + .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
5225 + move\t%0, $1; \
5226 + .set\tat; \
5227 + .set\treorder" \
5228 + :"=r" (__res) \
5229 + : \
5230 + :"$1"); \
5231 + __res; \
5232 +})
5233 +
5234 +#define MTC0(source, sel, value) \
5235 +do { \
5236 + __asm__ __volatile__(" \
5237 + .set\tnoreorder; \
5238 + .set\tnoat; \
5239 + move\t$1, %z0; \
5240 + .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
5241 + .set\tat; \
5242 + .set\treorder" \
5243 + : \
5244 + :"jr" (value) \
5245 + :"$1"); \
5246 +} while (0)
5247 +
5248 +#define get_c0_count() \
5249 +({ \
5250 + int __res; \
5251 + __asm__ __volatile__(" \
5252 + .set\tnoreorder; \
5253 + .set\tnoat; \
5254 + mfc0\t%0, $9; \
5255 + .set\tat; \
5256 + .set\treorder" \
5257 + :"=r" (__res)); \
5258 + __res; \
5259 +})
5260 +
5261 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
5262 +{
5263 + uint lsz, sets, ways;
5264 +
5265 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
5266 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
5267 + lsz = CONF1_IL_BASE << lsz;
5268 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
5269 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
5270 + *size = lsz * sets * ways;
5271 + *lsize = lsz;
5272 +}
5273 +
5274 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
5275 +{
5276 + uint lsz, sets, ways;
5277 +
5278 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
5279 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
5280 + lsz = CONF1_DL_BASE << lsz;
5281 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
5282 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
5283 + *size = lsz * sets * ways;
5284 + *lsize = lsz;
5285 +}
5286 +
5287 +#define cache_op(base, op) \
5288 + __asm__ __volatile__(" \
5289 + .set noreorder; \
5290 + .set mips3; \
5291 + cache %1, (%0); \
5292 + .set mips0; \
5293 + .set reorder" \
5294 + : \
5295 + : "r" (base), \
5296 + "i" (op));
5297 +
5298 +#define cache_unroll4(base, delta, op) \
5299 + __asm__ __volatile__(" \
5300 + .set noreorder; \
5301 + .set mips3; \
5302 + cache %1, 0(%0); \
5303 + cache %1, delta(%0); \
5304 + cache %1, (2 * delta)(%0); \
5305 + cache %1, (3 * delta)(%0); \
5306 + .set mips0; \
5307 + .set reorder" \
5308 + : \
5309 + : "r" (base), \
5310 + "i" (op));
5311 +
5312 +#endif /* !_LANGUAGE_ASSEMBLY */
5313 +
5314 +#endif /* _MISPINC_H */
5315 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
5316 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
5317 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-10-02 21:19:59.000000000 +0200
5318 @@ -0,0 +1,179 @@
5319 +#ifndef __osl_h
5320 +#define __osl_h
5321 +
5322 +#include <linux/delay.h>
5323 +#include <typedefs.h>
5324 +#include <linuxver.h>
5325 +#include <bcmutils.h>
5326 +#include <pcicfg.h>
5327 +
5328 +#define ASSERT(n)
5329 +
5330 +/* Pkttag flag should be part of public information */
5331 +struct osl_pubinfo {
5332 + bool pkttag;
5333 + uint pktalloced; /* Number of allocated packet buffers */
5334 +};
5335 +
5336 +struct osl_info {
5337 + struct osl_pubinfo pub;
5338 + uint magic;
5339 + void *pdev;
5340 + uint malloced;
5341 + uint failed;
5342 + void *dbgmem_list;
5343 +};
5344 +
5345 +typedef struct osl_info osl_t;
5346 +
5347 +#define PCI_CFG_RETRY 10
5348 +
5349 +/* map/unmap direction */
5350 +#define DMA_TX 1 /* TX direction for DMA */
5351 +#define DMA_RX 2 /* RX direction for DMA */
5352 +
5353 +#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
5354 +#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
5355 +#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
5356 +
5357 +/* bcopy, bcmp, and bzero */
5358 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
5359 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
5360 +#define bzero(b, len) memset((b), '\0', (len))
5361 +
5362 +/* uncached virtual address */
5363 +#ifdef mips
5364 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
5365 +#include <asm/addrspace.h>
5366 +#else
5367 +#define OSL_UNCACHED(va) (va)
5368 +#endif /* mips */
5369 +
5370 +
5371 +#ifndef IL_BIGENDIAN
5372 +#define R_REG(osh, r) (\
5373 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
5374 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
5375 + readl((volatile uint32*)(r)) \
5376 +)
5377 +#define W_REG(osh, r, v) do { \
5378 + switch (sizeof(*(r))) { \
5379 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
5380 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
5381 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5382 + } \
5383 +} while (0)
5384 +#else /* IL_BIGENDIAN */
5385 +#define R_REG(osh, r) ({ \
5386 + __typeof(*(r)) __osl_v; \
5387 + switch (sizeof(*(r))) { \
5388 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
5389 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
5390 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
5391 + } \
5392 + __osl_v; \
5393 +})
5394 +#define W_REG(osh, r, v) do { \
5395 + switch (sizeof(*(r))) { \
5396 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
5397 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
5398 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5399 + } \
5400 +} while (0)
5401 +#endif /* IL_BIGENDIAN */
5402 +
5403 +/* dereference an address that may cause a bus exception */
5404 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
5405 +#include <asm/paccess.h>
5406 +
5407 +/* map/unmap physical to virtual I/O */
5408 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
5409 +#define REG_UNMAP(va) iounmap((void *)(va))
5410 +
5411 +/* shared (dma-able) memory access macros */
5412 +#define R_SM(r) *(r)
5413 +#define W_SM(r, v) (*(r) = (v))
5414 +#define BZERO_SM(r, len) memset((r), '\0', (len))
5415 +
5416 +#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
5417 +#define MFREE(osh, addr, size) kfree((addr))
5418 +#define MALLOCED(osh) (0)
5419 +
5420 +#define osl_delay OSL_DELAY
5421 +static inline void OSL_DELAY(uint usec)
5422 +{
5423 + uint d;
5424 +
5425 + while (usec > 0) {
5426 + d = MIN(usec, 1000);
5427 + udelay(d);
5428 + usec -= d;
5429 + }
5430 +}
5431 +
5432 +static inline void
5433 +bcm_mdelay(uint ms)
5434 +{
5435 + uint i;
5436 +
5437 + for (i = 0; i < ms; i++) {
5438 + OSL_DELAY(1000);
5439 + }
5440 +}
5441 +
5442 +
5443 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
5444 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5445 +
5446 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
5447 + osl_pci_read_config((osh), (offset), (size))
5448 +
5449 +static inline uint32
5450 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
5451 +{
5452 + uint val;
5453 + uint retry = PCI_CFG_RETRY;
5454 +
5455 + do {
5456 + pci_read_config_dword(osh->pdev, offset, &val);
5457 + if (val != 0xffffffff)
5458 + break;
5459 + } while (retry--);
5460 +
5461 + return (val);
5462 +}
5463 +
5464 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
5465 + osl_pci_write_config((osh), (offset), (size), (val))
5466 +static inline void
5467 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
5468 +{
5469 + uint retry = PCI_CFG_RETRY;
5470 +
5471 + do {
5472 + pci_write_config_dword(osh->pdev, offset, val);
5473 + if (offset != PCI_BAR0_WIN)
5474 + break;
5475 + if (osl_pci_read_config(osh, offset, size) == val)
5476 + break;
5477 + } while (retry--);
5478 +}
5479 +
5480 +
5481 +/* return bus # for the pci device pointed by osh->pdev */
5482 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
5483 +static inline uint
5484 +osl_pci_bus(osl_t *osh)
5485 +{
5486 + return ((struct pci_dev *)osh->pdev)->bus->number;
5487 +}
5488 +
5489 +/* return slot # for the pci device pointed by osh->pdev */
5490 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
5491 +static inline uint
5492 +osl_pci_slot(osl_t *osh)
5493 +{
5494 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
5495 +}
5496 +
5497 +#endif
5498 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
5499 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
5500 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-10-02 21:19:59.000000000 +0200
5501 @@ -0,0 +1,495 @@
5502 +/*
5503 + * pcicfg.h: PCI configuration constants and structures.
5504 + *
5505 + * Copyright 2006, Broadcom Corporation
5506 + * All Rights Reserved.
5507 + *
5508 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5509 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5510 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5511 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5512 + *
5513 + * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
5514 + */
5515 +
5516 +#ifndef _h_pcicfg_
5517 +#define _h_pcicfg_
5518 +
5519 +/* The following inside ifndef's so we don't collide with NTDDK.H */
5520 +#ifndef PCI_MAX_BUS
5521 +#define PCI_MAX_BUS 0x100
5522 +#endif
5523 +#ifndef PCI_MAX_DEVICES
5524 +#define PCI_MAX_DEVICES 0x20
5525 +#endif
5526 +#ifndef PCI_MAX_FUNCTION
5527 +#define PCI_MAX_FUNCTION 0x8
5528 +#endif
5529 +
5530 +#ifndef PCI_INVALID_VENDORID
5531 +#define PCI_INVALID_VENDORID 0xffff
5532 +#endif
5533 +#ifndef PCI_INVALID_DEVICEID
5534 +#define PCI_INVALID_DEVICEID 0xffff
5535 +#endif
5536 +
5537 +
5538 +/* Convert between bus-slot-function-register and config addresses */
5539 +
5540 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
5541 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
5542 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
5543 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
5544 +
5545 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
5546 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
5547 +#define PCICFG_FUN_MASK 7 /* Function mask */
5548 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
5549 +
5550 +#define PCI_CONFIG_ADDR(b, s, f, o) \
5551 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
5552 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
5553 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
5554 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
5555 +
5556 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
5557 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
5558 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
5559 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
5560 +
5561 +/* PCIE Config space accessing MACROS */
5562 +
5563 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
5564 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
5565 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
5566 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
5567 +
5568 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
5569 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
5570 +#define PCIECFG_FUN_MASK 7 /* Function mask */
5571 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
5572 +
5573 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
5574 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
5575 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
5576 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
5577 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
5578 +
5579 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
5580 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
5581 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
5582 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
5583 +
5584 +/* The actual config space */
5585 +
5586 +#define PCI_BAR_MAX 6
5587 +
5588 +#define PCI_ROM_BAR 8
5589 +
5590 +#define PCR_RSVDA_MAX 2
5591 +
5592 +/* Bits in PCI bars' flags */
5593 +
5594 +#define PCIBAR_FLAGS 0xf
5595 +#define PCIBAR_IO 0x1
5596 +#define PCIBAR_MEM1M 0x2
5597 +#define PCIBAR_MEM64 0x4
5598 +#define PCIBAR_PREFETCH 0x8
5599 +#define PCIBAR_MEM32_MASK 0xFFFFFF80
5600 +
5601 +/* pci config status reg has a bit to indicate that capability ptr is present */
5602 +
5603 +#define PCI_CAPPTR_PRESENT 0x0010
5604 +
5605 +typedef struct _pci_config_regs {
5606 + unsigned short vendor;
5607 + unsigned short device;
5608 + unsigned short command;
5609 + unsigned short status;
5610 + unsigned char rev_id;
5611 + unsigned char prog_if;
5612 + unsigned char sub_class;
5613 + unsigned char base_class;
5614 + unsigned char cache_line_size;
5615 + unsigned char latency_timer;
5616 + unsigned char header_type;
5617 + unsigned char bist;
5618 + unsigned long base[PCI_BAR_MAX];
5619 + unsigned long cardbus_cis;
5620 + unsigned short subsys_vendor;
5621 + unsigned short subsys_id;
5622 + unsigned long baserom;
5623 + unsigned long rsvd_a[PCR_RSVDA_MAX];
5624 + unsigned char int_line;
5625 + unsigned char int_pin;
5626 + unsigned char min_gnt;
5627 + unsigned char max_lat;
5628 + unsigned char dev_dep[192];
5629 +} pci_config_regs;
5630 +
5631 +#define SZPCR (sizeof (pci_config_regs))
5632 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
5633 +
5634 +/* A structure for the config registers is nice, but in most
5635 + * systems the config space is not memory mapped, so we need
5636 + * filed offsetts. :-(
5637 + */
5638 +#define PCI_CFG_VID 0
5639 +#define PCI_CFG_DID 2
5640 +#define PCI_CFG_CMD 4
5641 +#define PCI_CFG_STAT 6
5642 +#define PCI_CFG_REV 8
5643 +#define PCI_CFG_PROGIF 9
5644 +#define PCI_CFG_SUBCL 0xa
5645 +#define PCI_CFG_BASECL 0xb
5646 +#define PCI_CFG_CLSZ 0xc
5647 +#define PCI_CFG_LATTIM 0xd
5648 +#define PCI_CFG_HDR 0xe
5649 +#define PCI_CFG_BIST 0xf
5650 +#define PCI_CFG_BAR0 0x10
5651 +#define PCI_CFG_BAR1 0x14
5652 +#define PCI_CFG_BAR2 0x18
5653 +#define PCI_CFG_BAR3 0x1c
5654 +#define PCI_CFG_BAR4 0x20
5655 +#define PCI_CFG_BAR5 0x24
5656 +#define PCI_CFG_CIS 0x28
5657 +#define PCI_CFG_SVID 0x2c
5658 +#define PCI_CFG_SSID 0x2e
5659 +#define PCI_CFG_ROMBAR 0x30
5660 +#define PCI_CFG_CAPPTR 0x34
5661 +#define PCI_CFG_INT 0x3c
5662 +#define PCI_CFG_PIN 0x3d
5663 +#define PCI_CFG_MINGNT 0x3e
5664 +#define PCI_CFG_MAXLAT 0x3f
5665 +
5666 +#ifdef __NetBSD__
5667 +#undef PCI_CLASS_DISPLAY
5668 +#undef PCI_CLASS_MEMORY
5669 +#undef PCI_CLASS_BRIDGE
5670 +#undef PCI_CLASS_INPUT
5671 +#undef PCI_CLASS_DOCK
5672 +#endif /* __NetBSD__ */
5673 +
5674 +/* Classes and subclasses */
5675 +
5676 +typedef enum {
5677 + PCI_CLASS_OLD = 0,
5678 + PCI_CLASS_DASDI,
5679 + PCI_CLASS_NET,
5680 + PCI_CLASS_DISPLAY,
5681 + PCI_CLASS_MMEDIA,
5682 + PCI_CLASS_MEMORY,
5683 + PCI_CLASS_BRIDGE,
5684 + PCI_CLASS_COMM,
5685 + PCI_CLASS_BASE,
5686 + PCI_CLASS_INPUT,
5687 + PCI_CLASS_DOCK,
5688 + PCI_CLASS_CPU,
5689 + PCI_CLASS_SERIAL,
5690 + PCI_CLASS_INTELLIGENT = 0xe,
5691 + PCI_CLASS_SATELLITE,
5692 + PCI_CLASS_CRYPT,
5693 + PCI_CLASS_DSP,
5694 + PCI_CLASS_XOR = 0xfe
5695 +} pci_classes;
5696 +
5697 +typedef enum {
5698 + PCI_DASDI_SCSI,
5699 + PCI_DASDI_IDE,
5700 + PCI_DASDI_FLOPPY,
5701 + PCI_DASDI_IPI,
5702 + PCI_DASDI_RAID,
5703 + PCI_DASDI_OTHER = 0x80
5704 +} pci_dasdi_subclasses;
5705 +
5706 +typedef enum {
5707 + PCI_NET_ETHER,
5708 + PCI_NET_TOKEN,
5709 + PCI_NET_FDDI,
5710 + PCI_NET_ATM,
5711 + PCI_NET_OTHER = 0x80
5712 +} pci_net_subclasses;
5713 +
5714 +typedef enum {
5715 + PCI_DISPLAY_VGA,
5716 + PCI_DISPLAY_XGA,
5717 + PCI_DISPLAY_3D,
5718 + PCI_DISPLAY_OTHER = 0x80
5719 +} pci_display_subclasses;
5720 +
5721 +typedef enum {
5722 + PCI_MMEDIA_VIDEO,
5723 + PCI_MMEDIA_AUDIO,
5724 + PCI_MMEDIA_PHONE,
5725 + PCI_MEDIA_OTHER = 0x80
5726 +} pci_mmedia_subclasses;
5727 +
5728 +typedef enum {
5729 + PCI_MEMORY_RAM,
5730 + PCI_MEMORY_FLASH,
5731 + PCI_MEMORY_OTHER = 0x80
5732 +} pci_memory_subclasses;
5733 +
5734 +typedef enum {
5735 + PCI_BRIDGE_HOST,
5736 + PCI_BRIDGE_ISA,
5737 + PCI_BRIDGE_EISA,
5738 + PCI_BRIDGE_MC,
5739 + PCI_BRIDGE_PCI,
5740 + PCI_BRIDGE_PCMCIA,
5741 + PCI_BRIDGE_NUBUS,
5742 + PCI_BRIDGE_CARDBUS,
5743 + PCI_BRIDGE_RACEWAY,
5744 + PCI_BRIDGE_OTHER = 0x80
5745 +} pci_bridge_subclasses;
5746 +
5747 +typedef enum {
5748 + PCI_COMM_UART,
5749 + PCI_COMM_PARALLEL,
5750 + PCI_COMM_MULTIUART,
5751 + PCI_COMM_MODEM,
5752 + PCI_COMM_OTHER = 0x80
5753 +} pci_comm_subclasses;
5754 +
5755 +typedef enum {
5756 + PCI_BASE_PIC,
5757 + PCI_BASE_DMA,
5758 + PCI_BASE_TIMER,
5759 + PCI_BASE_RTC,
5760 + PCI_BASE_PCI_HOTPLUG,
5761 + PCI_BASE_OTHER = 0x80
5762 +} pci_base_subclasses;
5763 +
5764 +typedef enum {
5765 + PCI_INPUT_KBD,
5766 + PCI_INPUT_PEN,
5767 + PCI_INPUT_MOUSE,
5768 + PCI_INPUT_SCANNER,
5769 + PCI_INPUT_GAMEPORT,
5770 + PCI_INPUT_OTHER = 0x80
5771 +} pci_input_subclasses;
5772 +
5773 +typedef enum {
5774 + PCI_DOCK_GENERIC,
5775 + PCI_DOCK_OTHER = 0x80
5776 +} pci_dock_subclasses;
5777 +
5778 +typedef enum {
5779 + PCI_CPU_386,
5780 + PCI_CPU_486,
5781 + PCI_CPU_PENTIUM,
5782 + PCI_CPU_ALPHA = 0x10,
5783 + PCI_CPU_POWERPC = 0x20,
5784 + PCI_CPU_MIPS = 0x30,
5785 + PCI_CPU_COPROC = 0x40,
5786 + PCI_CPU_OTHER = 0x80
5787 +} pci_cpu_subclasses;
5788 +
5789 +typedef enum {
5790 + PCI_SERIAL_IEEE1394,
5791 + PCI_SERIAL_ACCESS,
5792 + PCI_SERIAL_SSA,
5793 + PCI_SERIAL_USB,
5794 + PCI_SERIAL_FIBER,
5795 + PCI_SERIAL_SMBUS,
5796 + PCI_SERIAL_OTHER = 0x80
5797 +} pci_serial_subclasses;
5798 +
5799 +typedef enum {
5800 + PCI_INTELLIGENT_I2O
5801 +} pci_intelligent_subclasses;
5802 +
5803 +typedef enum {
5804 + PCI_SATELLITE_TV,
5805 + PCI_SATELLITE_AUDIO,
5806 + PCI_SATELLITE_VOICE,
5807 + PCI_SATELLITE_DATA,
5808 + PCI_SATELLITE_OTHER = 0x80
5809 +} pci_satellite_subclasses;
5810 +
5811 +typedef enum {
5812 + PCI_CRYPT_NETWORK,
5813 + PCI_CRYPT_ENTERTAINMENT,
5814 + PCI_CRYPT_OTHER = 0x80
5815 +} pci_crypt_subclasses;
5816 +
5817 +typedef enum {
5818 + PCI_DSP_DPIO,
5819 + PCI_DSP_OTHER = 0x80
5820 +} pci_dsp_subclasses;
5821 +
5822 +typedef enum {
5823 + PCI_XOR_QDMA,
5824 + PCI_XOR_OTHER = 0x80
5825 +} pci_xor_subclasses;
5826 +
5827 +/* Header types */
5828 +typedef enum {
5829 + PCI_HEADER_NORMAL,
5830 + PCI_HEADER_BRIDGE,
5831 + PCI_HEADER_CARDBUS
5832 +} pci_header_types;
5833 +
5834 +
5835 +/* Overlay for a PCI-to-PCI bridge */
5836 +
5837 +#define PPB_RSVDA_MAX 2
5838 +#define PPB_RSVDD_MAX 8
5839 +
5840 +typedef struct _ppb_config_regs {
5841 + unsigned short vendor;
5842 + unsigned short device;
5843 + unsigned short command;
5844 + unsigned short status;
5845 + unsigned char rev_id;
5846 + unsigned char prog_if;
5847 + unsigned char sub_class;
5848 + unsigned char base_class;
5849 + unsigned char cache_line_size;
5850 + unsigned char latency_timer;
5851 + unsigned char header_type;
5852 + unsigned char bist;
5853 + unsigned long rsvd_a[PPB_RSVDA_MAX];
5854 + unsigned char prim_bus;
5855 + unsigned char sec_bus;
5856 + unsigned char sub_bus;
5857 + unsigned char sec_lat;
5858 + unsigned char io_base;
5859 + unsigned char io_lim;
5860 + unsigned short sec_status;
5861 + unsigned short mem_base;
5862 + unsigned short mem_lim;
5863 + unsigned short pf_mem_base;
5864 + unsigned short pf_mem_lim;
5865 + unsigned long pf_mem_base_hi;
5866 + unsigned long pf_mem_lim_hi;
5867 + unsigned short io_base_hi;
5868 + unsigned short io_lim_hi;
5869 + unsigned short subsys_vendor;
5870 + unsigned short subsys_id;
5871 + unsigned long rsvd_b;
5872 + unsigned char rsvd_c;
5873 + unsigned char int_pin;
5874 + unsigned short bridge_ctrl;
5875 + unsigned char chip_ctrl;
5876 + unsigned char diag_ctrl;
5877 + unsigned short arb_ctrl;
5878 + unsigned long rsvd_d[PPB_RSVDD_MAX];
5879 + unsigned char dev_dep[192];
5880 +} ppb_config_regs;
5881 +
5882 +
5883 +/* PCI CAPABILITY DEFINES */
5884 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
5885 +#define PCI_CAP_MSICAP_ID 0x05
5886 +#define PCI_CAP_PCIECAP_ID 0x10
5887 +
5888 +/* Data structure to define the Message Signalled Interrupt facility
5889 + * Valid for PCI and PCIE configurations
5890 + */
5891 +typedef struct _pciconfig_cap_msi {
5892 + unsigned char capID;
5893 + unsigned char nextptr;
5894 + unsigned short msgctrl;
5895 + unsigned int msgaddr;
5896 +} pciconfig_cap_msi;
5897 +
5898 +/* Data structure to define the Power managment facility
5899 + * Valid for PCI and PCIE configurations
5900 + */
5901 +typedef struct _pciconfig_cap_pwrmgmt {
5902 + unsigned char capID;
5903 + unsigned char nextptr;
5904 + unsigned short pme_cap;
5905 + unsigned short pme_sts_ctrl;
5906 + unsigned char pme_bridge_ext;
5907 + unsigned char data;
5908 +} pciconfig_cap_pwrmgmt;
5909 +
5910 +/* Data structure to define the PCIE capability */
5911 +typedef struct _pciconfig_cap_pcie {
5912 + unsigned char capID;
5913 + unsigned char nextptr;
5914 + unsigned short pcie_cap;
5915 + unsigned int dev_cap;
5916 + unsigned short dev_ctrl;
5917 + unsigned short dev_status;
5918 + unsigned int link_cap;
5919 + unsigned short link_ctrl;
5920 + unsigned short link_status;
5921 +} pciconfig_cap_pcie;
5922 +
5923 +/* PCIE Enhanced CAPABILITY DEFINES */
5924 +#define PCIE_EXTCFG_OFFSET 0x100
5925 +#define PCIE_ADVERRREP_CAPID 0x0001
5926 +#define PCIE_VC_CAPID 0x0002
5927 +#define PCIE_DEVSNUM_CAPID 0x0003
5928 +#define PCIE_PWRBUDGET_CAPID 0x0004
5929 +
5930 +/* Header to define the PCIE specific capabilities in the extended config space */
5931 +typedef struct _pcie_enhanced_caphdr {
5932 + unsigned short capID;
5933 + unsigned short cap_ver : 4;
5934 + unsigned short next_ptr : 12;
5935 +} pcie_enhanced_caphdr;
5936 +
5937 +
5938 +/* Everything below is BRCM HND proprietary */
5939 +
5940 +
5941 +/* Brcm PCI configuration registers */
5942 +#define cap_list rsvd_a[0]
5943 +#define bar0_window dev_dep[0x80 - 0x40]
5944 +#define bar1_window dev_dep[0x84 - 0x40]
5945 +#define sprom_control dev_dep[0x88 - 0x40]
5946 +
5947 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
5948 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
5949 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
5950 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
5951 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
5952 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
5953 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
5954 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
5955 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
5956 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
5957 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
5958 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
5959 +
5960 +#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
5961 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
5962 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
5963 +#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
5964 + * 8KB window, so their address is the "regular"
5965 + * address plus 4K
5966 + */
5967 +#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
5968 +
5969 +/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
5970 +#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
5971 +#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
5972 +#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
5973 +
5974 +/* PCI_INT_STATUS */
5975 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
5976 +
5977 +/* PCI_INT_MASK */
5978 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
5979 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
5980 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
5981 +
5982 +/* PCI_SPROM_CONTROL */
5983 +#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
5984 +#define SPROM_LOCKED 0x08 /* SPROM Locked */
5985 +#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
5986 +#define SPROM_WRITEEN 0x10 /* SPROM write enable */
5987 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
5988 +#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
5989 +
5990 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
5991 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
5992 +
5993 +/* PCI_CFG_CMD_STAT */
5994 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
5995 +
5996 +#endif /* _h_pcicfg_ */
5997 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
5998 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
5999 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-10-02 21:19:59.000000000 +0200
6000 @@ -0,0 +1,516 @@
6001 +/*
6002 + * SiliconBackplane Chipcommon core hardware definitions.
6003 + *
6004 + * The chipcommon core provides chip identification, SB control,
6005 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6006 + * gpio interface, extbus, and support for serial and parallel flashes.
6007 + *
6008 + * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
6009 + * Copyright 2006, Broadcom Corporation
6010 + * All Rights Reserved.
6011 + *
6012 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6013 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6014 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6015 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6016 + *
6017 + */
6018 +
6019 +#ifndef _SBCHIPC_H
6020 +#define _SBCHIPC_H
6021 +
6022 +
6023 +#ifndef _LANGUAGE_ASSEMBLY
6024 +
6025 +/* cpp contortions to concatenate w/arg prescan */
6026 +#ifndef PAD
6027 +#define _PADLINE(line) pad ## line
6028 +#define _XSTR(line) _PADLINE(line)
6029 +#define PAD _XSTR(__LINE__)
6030 +#endif /* PAD */
6031 +
6032 +typedef volatile struct {
6033 + uint32 chipid; /* 0x0 */
6034 + uint32 capabilities;
6035 + uint32 corecontrol; /* corerev >= 1 */
6036 + uint32 bist;
6037 +
6038 + /* OTP */
6039 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6040 + uint32 otpcontrol;
6041 + uint32 otpprog;
6042 + uint32 PAD;
6043 +
6044 + /* Interrupt control */
6045 + uint32 intstatus; /* 0x20 */
6046 + uint32 intmask;
6047 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6048 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6049 +
6050 + /* Jtag Master */
6051 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6052 + uint32 jtagir;
6053 + uint32 jtagdr;
6054 + uint32 jtagctrl;
6055 +
6056 + /* serial flash interface registers */
6057 + uint32 flashcontrol; /* 0x40 */
6058 + uint32 flashaddress;
6059 + uint32 flashdata;
6060 + uint32 PAD[1];
6061 +
6062 + /* Silicon backplane configuration broadcast control */
6063 + uint32 broadcastaddress; /* 0x50 */
6064 + uint32 broadcastdata;
6065 + uint32 PAD[2];
6066 +
6067 + /* gpio - cleared only by power-on-reset */
6068 + uint32 gpioin; /* 0x60 */
6069 + uint32 gpioout;
6070 + uint32 gpioouten;
6071 + uint32 gpiocontrol;
6072 + uint32 gpiointpolarity;
6073 + uint32 gpiointmask;
6074 + uint32 PAD[2];
6075 +
6076 + /* Watchdog timer */
6077 + uint32 watchdog; /* 0x80 */
6078 + uint32 PAD[1];
6079 +
6080 + /* GPIO based LED powersave registers corerev >= 16 */
6081 + uint32 gpiotimerval; /* 0x88 */
6082 + uint32 gpiotimeroutmask;
6083 +
6084 + /* clock control */
6085 + uint32 clockcontrol_n; /* 0x90 */
6086 + uint32 clockcontrol_sb; /* aka m0 */
6087 + uint32 clockcontrol_pci; /* aka m1 */
6088 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6089 + uint32 clockcontrol_m3; /* cpu */
6090 + uint32 clkdiv; /* corerev >= 3 */
6091 + uint32 PAD[2];
6092 +
6093 + /* pll delay registers (corerev >= 4) */
6094 + uint32 pll_on_delay; /* 0xb0 */
6095 + uint32 fref_sel_delay;
6096 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6097 + uint32 PAD[1];
6098 +
6099 + /* Instaclock registers (corerev >= 10) */
6100 + uint32 system_clk_ctl; /* 0xc0 */
6101 + uint32 clkstatestretch;
6102 + uint32 PAD[14];
6103 +
6104 + /* ExtBus control registers (corerev >= 3) */
6105 + uint32 pcmcia_config; /* 0x100 */
6106 + uint32 pcmcia_memwait;
6107 + uint32 pcmcia_attrwait;
6108 + uint32 pcmcia_iowait;
6109 + uint32 ide_config;
6110 + uint32 ide_memwait;
6111 + uint32 ide_attrwait;
6112 + uint32 ide_iowait;
6113 + uint32 prog_config;
6114 + uint32 prog_waitcount;
6115 + uint32 flash_config;
6116 + uint32 flash_waitcount;
6117 + uint32 PAD[44];
6118 +
6119 + /* Clock control and hardware workarounds */
6120 + uint32 clk_ctl_st;
6121 + uint32 hw_war;
6122 + uint32 PAD[70];
6123 +
6124 + /* uarts */
6125 + uint8 uart0data; /* 0x300 */
6126 + uint8 uart0imr;
6127 + uint8 uart0fcr;
6128 + uint8 uart0lcr;
6129 + uint8 uart0mcr;
6130 + uint8 uart0lsr;
6131 + uint8 uart0msr;
6132 + uint8 uart0scratch;
6133 + uint8 PAD[248]; /* corerev >= 1 */
6134 +
6135 + uint8 uart1data; /* 0x400 */
6136 + uint8 uart1imr;
6137 + uint8 uart1fcr;
6138 + uint8 uart1lcr;
6139 + uint8 uart1mcr;
6140 + uint8 uart1lsr;
6141 + uint8 uart1msr;
6142 + uint8 uart1scratch;
6143 +} chipcregs_t;
6144 +
6145 +#endif /* _LANGUAGE_ASSEMBLY */
6146 +
6147 +#define CC_CHIPID 0
6148 +#define CC_CAPABILITIES 4
6149 +#define CC_JTAGCMD 0x30
6150 +#define CC_JTAGIR 0x34
6151 +#define CC_JTAGDR 0x38
6152 +#define CC_JTAGCTRL 0x3c
6153 +#define CC_WATCHDOG 0x80
6154 +#define CC_CLKC_N 0x90
6155 +#define CC_CLKC_M0 0x94
6156 +#define CC_CLKC_M1 0x98
6157 +#define CC_CLKC_M2 0x9c
6158 +#define CC_CLKC_M3 0xa0
6159 +#define CC_CLKDIV 0xa4
6160 +#define CC_SYS_CLK_CTL 0xc0
6161 +#define CC_OTP 0x800
6162 +
6163 +/* chipid */
6164 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6165 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6166 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6167 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6168 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6169 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6170 +#define CID_CC_SHIFT 24
6171 +
6172 +/* capabilities */
6173 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6174 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6175 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6176 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6177 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6178 +#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
6179 +#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
6180 +#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
6181 +#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
6182 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6183 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6184 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6185 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6186 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6187 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6188 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6189 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6190 +#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
6191 +
6192 +/* PLL type */
6193 +#define PLL_NONE 0x00000000
6194 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6195 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6196 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6197 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6198 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6199 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6200 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6201 +
6202 +/* corecontrol */
6203 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6204 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6205 +
6206 +/* chipcontrol */
6207 +#define CHIPCTRL_4321A0_DEFAULT 0x3a4
6208 +#define CHIPCTRL_4321A1_DEFAULT 0x0a4
6209 +
6210 +/* Fields in the otpstatus register */
6211 +#define OTPS_PROGFAIL 0x80000000
6212 +#define OTPS_PROTECT 0x00000007
6213 +#define OTPS_HW_PROTECT 0x00000001
6214 +#define OTPS_SW_PROTECT 0x00000002
6215 +#define OTPS_CID_PROTECT 0x00000004
6216 +
6217 +/* Fields in the otpcontrol register */
6218 +#define OTPC_RECWAIT 0xff000000
6219 +#define OTPC_PROGWAIT 0x00ffff00
6220 +#define OTPC_PRW_SHIFT 8
6221 +#define OTPC_MAXFAIL 0x00000038
6222 +#define OTPC_VSEL 0x00000006
6223 +#define OTPC_SELVL 0x00000001
6224 +
6225 +/* Fields in otpprog */
6226 +#define OTPP_COL_MASK 0x000000ff
6227 +#define OTPP_ROW_MASK 0x0000ff00
6228 +#define OTPP_ROW_SHIFT 8
6229 +#define OTPP_READERR 0x10000000
6230 +#define OTPP_VALUE 0x20000000
6231 +#define OTPP_VALUE_SHIFT 29
6232 +#define OTPP_READ 0x40000000
6233 +#define OTPP_START 0x80000000
6234 +#define OTPP_BUSY 0x80000000
6235 +
6236 +/* jtagcmd */
6237 +#define JCMD_START 0x80000000
6238 +#define JCMD_BUSY 0x80000000
6239 +#define JCMD_PAUSE 0x40000000
6240 +#define JCMD0_ACC_MASK 0x0000f000
6241 +#define JCMD0_ACC_IRDR 0x00000000
6242 +#define JCMD0_ACC_DR 0x00001000
6243 +#define JCMD0_ACC_IR 0x00002000
6244 +#define JCMD0_ACC_RESET 0x00003000
6245 +#define JCMD0_ACC_IRPDR 0x00004000
6246 +#define JCMD0_ACC_PDR 0x00005000
6247 +#define JCMD0_IRW_MASK 0x00000f00
6248 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6249 +#define JCMD_ACC_IRDR 0x00000000
6250 +#define JCMD_ACC_DR 0x00010000
6251 +#define JCMD_ACC_IR 0x00020000
6252 +#define JCMD_ACC_RESET 0x00030000
6253 +#define JCMD_ACC_IRPDR 0x00040000
6254 +#define JCMD_ACC_PDR 0x00050000
6255 +#define JCMD_IRW_MASK 0x00001f00
6256 +#define JCMD_IRW_SHIFT 8
6257 +#define JCMD_DRW_MASK 0x0000003f
6258 +
6259 +/* jtagctrl */
6260 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6261 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6262 +#define JCTRL_EN 1 /* Enable Jtag master */
6263 +
6264 +/* Fields in clkdiv */
6265 +#define CLKD_SFLASH 0x0f000000
6266 +#define CLKD_SFLASH_SHIFT 24
6267 +#define CLKD_OTP 0x000f0000
6268 +#define CLKD_OTP_SHIFT 16
6269 +#define CLKD_JTAG 0x00000f00
6270 +#define CLKD_JTAG_SHIFT 8
6271 +#define CLKD_UART 0x000000ff
6272 +
6273 +/* intstatus/intmask */
6274 +#define CI_GPIO 0x00000001 /* gpio intr */
6275 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6276 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6277 +
6278 +/* slow_clk_ctl */
6279 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6280 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6281 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6282 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6283 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6284 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
6285 + * 0: LPO is enabled
6286 + */
6287 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
6288 + * 0: power logic control
6289 + */
6290 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
6291 + * PLL clock disable requests from core
6292 + */
6293 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
6294 + * disable crystal when appropriate
6295 + */
6296 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6297 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6298 +#define SCC_CD_SHIFT 16
6299 +
6300 +/* system_clk_ctl */
6301 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6302 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6303 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6304 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6305 +#define SYCC_HR 0x00000010 /* Force HT */
6306 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
6307 +#define SYCC_CD_SHIFT 16
6308 +
6309 +/* gpiotimerval */
6310 +#define GPIO_ONTIME_SHIFT 16
6311 +
6312 +/* clockcontrol_n */
6313 +#define CN_N1_MASK 0x3f /* n1 control */
6314 +#define CN_N2_MASK 0x3f00 /* n2 control */
6315 +#define CN_N2_SHIFT 8
6316 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6317 +#define CN_PLLC_SHIFT 16
6318 +
6319 +/* clockcontrol_sb/pci/uart */
6320 +#define CC_M1_MASK 0x3f /* m1 control */
6321 +#define CC_M2_MASK 0x3f00 /* m2 control */
6322 +#define CC_M2_SHIFT 8
6323 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6324 +#define CC_M3_SHIFT 16
6325 +#define CC_MC_MASK 0x1f000000 /* mux control */
6326 +#define CC_MC_SHIFT 24
6327 +
6328 +/* N3M Clock control magic field values */
6329 +#define CC_F6_2 0x02 /* A factor of 2 in */
6330 +#define CC_F6_3 0x03 /* 6-bit fields like */
6331 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6332 +#define CC_F6_5 0x09
6333 +#define CC_F6_6 0x11
6334 +#define CC_F6_7 0x21
6335 +
6336 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6337 +
6338 +#define CC_MC_BYPASS 0x08
6339 +#define CC_MC_M1 0x04
6340 +#define CC_MC_M1M2 0x02
6341 +#define CC_MC_M1M2M3 0x01
6342 +#define CC_MC_M1M3 0x11
6343 +
6344 +/* Type 2 Clock control magic field values */
6345 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6346 +#define CC_T2M2_BIAS 3 /* m2 bias */
6347 +
6348 +#define CC_T2MC_M1BYP 1
6349 +#define CC_T2MC_M2BYP 2
6350 +#define CC_T2MC_M3BYP 4
6351 +
6352 +/* Type 6 Clock control magic field values */
6353 +#define CC_T6_MMASK 1 /* bits of interest in m */
6354 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6355 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6356 +#define SB2MIPS_T6(sb) (2 * (sb))
6357 +
6358 +/* Common clock base */
6359 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6360 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6361 +
6362 +/* Clock control values for 200Mhz in 5350 */
6363 +#define CLKC_5350_N 0x0311
6364 +#define CLKC_5350_M 0x04020009
6365 +
6366 +/* Flash types in the chipcommon capabilities register */
6367 +#define FLASH_NONE 0x000 /* No flash */
6368 +#define SFLASH_ST 0x100 /* ST serial flash */
6369 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6370 +#define PFLASH 0x700 /* Parallel flash */
6371 +
6372 +/* Bits in the ExtBus config registers */
6373 +#define CC_CFG_EN 0x0001 /* Enable */
6374 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6375 +#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
6376 +#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
6377 +#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
6378 +#define CC_CFG_EM_IDE 0x0006 /* IDE */
6379 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6380 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6381 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6382 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6383 +
6384 +/* ExtBus address space */
6385 +#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
6386 +#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
6387 +#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
6388 +#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
6389 +#define CC_EB_IDE 0x1a800000 /* IDE memory base */
6390 +#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
6391 +#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
6392 +#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
6393 +#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
6394 +
6395 +
6396 +/* Start/busy bit in flashcontrol */
6397 +#define SFLASH_OPCODE 0x000000ff
6398 +#define SFLASH_ACTION 0x00000700
6399 +#define SFLASH_START 0x80000000
6400 +#define SFLASH_BUSY SFLASH_START
6401 +
6402 +/* flashcontrol action codes */
6403 +#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
6404 +#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
6405 +#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
6406 +#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
6407 +#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
6408 +#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
6409 +#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
6410 +
6411 +/* flashcontrol action+opcodes for ST flashes */
6412 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6413 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6414 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6415 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6416 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6417 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6418 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6419 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6420 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6421 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6422 +
6423 +/* Status register bits for ST flashes */
6424 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6425 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6426 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6427 +#define SFLASH_ST_BP_SHIFT 2
6428 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6429 +
6430 +/* flashcontrol action+opcodes for Atmel flashes */
6431 +#define SFLASH_AT_READ 0x07e8
6432 +#define SFLASH_AT_PAGE_READ 0x07d2
6433 +#define SFLASH_AT_BUF1_READ
6434 +#define SFLASH_AT_BUF2_READ
6435 +#define SFLASH_AT_STATUS 0x01d7
6436 +#define SFLASH_AT_BUF1_WRITE 0x0384
6437 +#define SFLASH_AT_BUF2_WRITE 0x0387
6438 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6439 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6440 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6441 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6442 +#define SFLASH_AT_PAGE_ERASE 0x0281
6443 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6444 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6445 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6446 +#define SFLASH_AT_BUF1_LOAD 0x0253
6447 +#define SFLASH_AT_BUF2_LOAD 0x0255
6448 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6449 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6450 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6451 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6452 +
6453 +/* Status register bits for Atmel flashes */
6454 +#define SFLASH_AT_READY 0x80
6455 +#define SFLASH_AT_MISMATCH 0x40
6456 +#define SFLASH_AT_ID_MASK 0x38
6457 +#define SFLASH_AT_ID_SHIFT 3
6458 +
6459 +/* OTP regions */
6460 +#define OTP_HW_REGION OTPS_HW_PROTECT
6461 +#define OTP_SW_REGION OTPS_SW_PROTECT
6462 +#define OTP_CID_REGION OTPS_CID_PROTECT
6463 +
6464 +/* OTP regions (Byte offsets from otp size) */
6465 +#define OTP_SWLIM_OFF (-8)
6466 +#define OTP_CIDBASE_OFF 0
6467 +#define OTP_CIDLIM_OFF 8
6468 +
6469 +/* Predefined OTP words (Word offset from otp size) */
6470 +#define OTP_BOUNDARY_OFF (-4)
6471 +#define OTP_HWSIGN_OFF (-3)
6472 +#define OTP_SWSIGN_OFF (-2)
6473 +#define OTP_CIDSIGN_OFF (-1)
6474 +
6475 +#define OTP_CID_OFF 0
6476 +#define OTP_PKG_OFF 1
6477 +#define OTP_FID_OFF 2
6478 +#define OTP_RSV_OFF 3
6479 +#define OTP_LIM_OFF 4
6480 +
6481 +#define OTP_SIGNATURE 0x578a
6482 +#define OTP_MAGIC 0x4e56
6483 +
6484 +/*
6485 + * These are the UART port assignments, expressed as offsets from the base
6486 + * register. These assignments should hold for any serial port based on
6487 + * a 8250, 16450, or 16550(A).
6488 + */
6489 +
6490 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
6491 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
6492 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
6493 +#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
6494 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
6495 +#define UART_IIR 2 /* In: Interrupt Identity Register */
6496 +#define UART_FCR 2 /* Out: FIFO Control Register */
6497 +#define UART_LCR 3 /* Out: Line Control Register */
6498 +#define UART_MCR 4 /* Out: Modem Control Register */
6499 +#define UART_LSR 5 /* In: Line Status Register */
6500 +#define UART_MSR 6 /* In: Modem Status Register */
6501 +#define UART_SCR 7 /* I/O: Scratch Register */
6502 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
6503 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
6504 +#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
6505 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
6506 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
6507 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
6508 +#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
6509 +
6510 +/* Interrupt Enable Register (IER) bits */
6511 +#define UART_IER_EDSSI 8 /* enable modem status interrupt */
6512 +#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
6513 +#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
6514 +#define UART_IER_ERBFI 1 /* enable data available interrupt */
6515 +
6516 +#endif /* _SBCHIPC_H */
6517 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6518 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6519 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-10-02 21:19:59.000000000 +0200
6520 @@ -0,0 +1,369 @@
6521 +/*
6522 + * Broadcom SiliconBackplane hardware register definitions.
6523 + *
6524 + * Copyright 2006, Broadcom Corporation
6525 + * All Rights Reserved.
6526 + *
6527 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6528 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6529 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6530 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6531 + *
6532 + * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
6533 + */
6534 +
6535 +#ifndef _SBCONFIG_H
6536 +#define _SBCONFIG_H
6537 +
6538 +/* cpp contortions to concatenate w/arg prescan */
6539 +#ifndef PAD
6540 +#define _PADLINE(line) pad ## line
6541 +#define _XSTR(line) _PADLINE(line)
6542 +#define PAD _XSTR(__LINE__)
6543 +#endif
6544 +
6545 +/*
6546 + * SiliconBackplane Address Map.
6547 + * All regions may not exist on all chips.
6548 + */
6549 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6550 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6551 +#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
6552 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6553 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6554 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6555 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6556 +
6557 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6558 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6559 +
6560 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6561 +#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
6562 +#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
6563 +
6564 +#define SB_ROM 0x20000000 /* ARM ROM */
6565 +#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
6566 +#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
6567 +#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
6568 +
6569 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6570 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6571 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
6572 + * (2 ZettaBytes), low 32 bits
6573 + */
6574 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
6575 + * (2 ZettaBytes), high 32 bits
6576 + */
6577 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6578 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6579 +
6580 +
6581 +/* enumeration space related defs */
6582 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6583 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6584 +#define SB_MAXFUNCS 4 /* max. # functions per core */
6585 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6586 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6587 +
6588 +/* mips address */
6589 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6590 +
6591 +/*
6592 + * Sonics Configuration Space Registers.
6593 + */
6594 +#define SBIPSFLAG 0x08
6595 +#define SBTPSFLAG 0x18
6596 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6597 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6598 +#define SBADMATCH3 0x60
6599 +#define SBADMATCH2 0x68
6600 +#define SBADMATCH1 0x70
6601 +#define SBIMSTATE 0x90
6602 +#define SBINTVEC 0x94
6603 +#define SBTMSTATELOW 0x98
6604 +#define SBTMSTATEHIGH 0x9c
6605 +#define SBBWA0 0xa0
6606 +#define SBIMCONFIGLOW 0xa8
6607 +#define SBIMCONFIGHIGH 0xac
6608 +#define SBADMATCH0 0xb0
6609 +#define SBTMCONFIGLOW 0xb8
6610 +#define SBTMCONFIGHIGH 0xbc
6611 +#define SBBCONFIG 0xc0
6612 +#define SBBSTATE 0xc8
6613 +#define SBACTCNFG 0xd8
6614 +#define SBFLAGST 0xe8
6615 +#define SBIDLOW 0xf8
6616 +#define SBIDHIGH 0xfc
6617 +
6618 +/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
6619 + * a few registers *below* that line. I think it would be very confusing to try
6620 + * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
6621 + */
6622 +
6623 +#define SBIMERRLOGA 0xea8
6624 +#define SBIMERRLOG 0xeb0
6625 +#define SBTMPORTCONNID0 0xed8
6626 +#define SBTMPORTLOCK0 0xef8
6627 +
6628 +#ifndef _LANGUAGE_ASSEMBLY
6629 +
6630 +typedef volatile struct _sbconfig {
6631 + uint32 PAD[2];
6632 + uint32 sbipsflag; /* initiator port ocp slave flag */
6633 + uint32 PAD[3];
6634 + uint32 sbtpsflag; /* target port ocp slave flag */
6635 + uint32 PAD[11];
6636 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6637 + uint32 PAD;
6638 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6639 + uint32 PAD[3];
6640 + uint32 sbadmatch3; /* address match3 */
6641 + uint32 PAD;
6642 + uint32 sbadmatch2; /* address match2 */
6643 + uint32 PAD;
6644 + uint32 sbadmatch1; /* address match1 */
6645 + uint32 PAD[7];
6646 + uint32 sbimstate; /* initiator agent state */
6647 + uint32 sbintvec; /* interrupt mask */
6648 + uint32 sbtmstatelow; /* target state */
6649 + uint32 sbtmstatehigh; /* target state */
6650 + uint32 sbbwa0; /* bandwidth allocation table0 */
6651 + uint32 PAD;
6652 + uint32 sbimconfiglow; /* initiator configuration */
6653 + uint32 sbimconfighigh; /* initiator configuration */
6654 + uint32 sbadmatch0; /* address match0 */
6655 + uint32 PAD;
6656 + uint32 sbtmconfiglow; /* target configuration */
6657 + uint32 sbtmconfighigh; /* target configuration */
6658 + uint32 sbbconfig; /* broadcast configuration */
6659 + uint32 PAD;
6660 + uint32 sbbstate; /* broadcast state */
6661 + uint32 PAD[3];
6662 + uint32 sbactcnfg; /* activate configuration */
6663 + uint32 PAD[3];
6664 + uint32 sbflagst; /* current sbflags */
6665 + uint32 PAD[3];
6666 + uint32 sbidlow; /* identification */
6667 + uint32 sbidhigh; /* identification */
6668 +} sbconfig_t;
6669 +
6670 +#endif /* _LANGUAGE_ASSEMBLY */
6671 +
6672 +/* sbipsflag */
6673 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6674 +#define SBIPS_INT1_SHIFT 0
6675 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6676 +#define SBIPS_INT2_SHIFT 8
6677 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6678 +#define SBIPS_INT3_SHIFT 16
6679 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6680 +#define SBIPS_INT4_SHIFT 24
6681 +
6682 +/* sbtpsflag */
6683 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6684 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6685 +
6686 +/* sbtmerrlog */
6687 +#define SBTMEL_CM 0x00000007 /* command */
6688 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6689 +#define SBTMEL_EC 0x0f000000 /* error code */
6690 +#define SBTMEL_ME 0x80000000 /* multiple error */
6691 +
6692 +/* sbimstate */
6693 +#define SBIM_PC 0xf /* pipecount */
6694 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6695 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6696 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6697 +#define SBIM_AP_TK 0x20 /* use token only */
6698 +#define SBIM_AP_RSV 0x30 /* reserved */
6699 +#define SBIM_IBE 0x20000 /* inbanderror */
6700 +#define SBIM_TO 0x40000 /* timeout */
6701 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6702 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6703 +
6704 +/* sbtmstatelow */
6705 +#define SBTML_RESET 0x1 /* reset */
6706 +#define SBTML_REJ_MASK 0x6 /* reject */
6707 +#define SBTML_REJ_SHIFT 1
6708 +#define SBTML_CLK 0x10000 /* clock enable */
6709 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6710 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6711 +#define SBTML_PE 0x40000000 /* pme enable */
6712 +#define SBTML_BE 0x80000000 /* bist enable */
6713 +
6714 +/* sbtmstatehigh */
6715 +#define SBTMH_SERR 0x1 /* serror */
6716 +#define SBTMH_INT 0x2 /* interrupt */
6717 +#define SBTMH_BUSY 0x4 /* busy */
6718 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6719 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6720 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
6721 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6722 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6723 +#define SBTMH_BISTD 0x80000000 /* bist done */
6724 +
6725 +
6726 +/* sbbwa0 */
6727 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6728 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6729 +#define SBBWA_TAB1_SHIFT 16
6730 +
6731 +/* sbimconfiglow */
6732 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6733 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6734 +#define SBIMCL_RTO_SHIFT 4
6735 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6736 +#define SBIMCL_CID_SHIFT 16
6737 +
6738 +/* sbimconfighigh */
6739 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6740 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6741 +#define SBIMCH_TEM_SHIFT 4
6742 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6743 +#define SBIMCH_BEM_SHIFT 6
6744 +
6745 +/* sbadmatch0 */
6746 +#define SBAM_TYPE_MASK 0x3 /* address type */
6747 +#define SBAM_AD64 0x4 /* reserved */
6748 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6749 +#define SBAM_ADINT0_SHIFT 3
6750 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6751 +#define SBAM_ADINT1_SHIFT 3
6752 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6753 +#define SBAM_ADINT2_SHIFT 3
6754 +#define SBAM_ADEN 0x400 /* enable */
6755 +#define SBAM_ADNEG 0x800 /* negative decode */
6756 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6757 +#define SBAM_BASE0_SHIFT 8
6758 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6759 +#define SBAM_BASE1_SHIFT 12
6760 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6761 +#define SBAM_BASE2_SHIFT 16
6762 +
6763 +/* sbtmconfiglow */
6764 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6765 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6766 +#define SBTMCL_CO_SHIFT 11
6767 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6768 +#define SBTMCL_IF_SHIFT 18
6769 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6770 +#define SBTMCL_IM_SHIFT 24
6771 +
6772 +/* sbtmconfighigh */
6773 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6774 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6775 +#define SBTMCH_RM_SHIFT 2
6776 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6777 +#define SBTMCH_SM_SHIFT 4
6778 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6779 +#define SBTMCH_EM_SHIFT 8
6780 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6781 +#define SBTMCH_IM_SHIFT 10
6782 +
6783 +/* sbbconfig */
6784 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6785 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6786 +#define SBBC_MAX0_SHIFT 16
6787 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6788 +#define SBBC_MAX1_SHIFT 20
6789 +
6790 +/* sbbstate */
6791 +#define SBBS_SRD 0x1 /* st reg disable */
6792 +#define SBBS_HRD 0x2 /* hold reg disable */
6793 +
6794 +/* sbidlow */
6795 +#define SBIDL_CS_MASK 0x3 /* config space */
6796 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6797 +#define SBIDL_AR_SHIFT 3
6798 +#define SBIDL_SYNCH 0x40 /* sync */
6799 +#define SBIDL_INIT 0x80 /* initiator */
6800 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6801 +#define SBIDL_MINLAT_SHIFT 8
6802 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6803 +#define SBIDL_MAXLAT_SHIFT 12
6804 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6805 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6806 +#define SBIDL_CW_SHIFT 18
6807 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6808 +#define SBIDL_TP_SHIFT 20
6809 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6810 +#define SBIDL_IP_SHIFT 24
6811 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6812 +#define SBIDL_RV_SHIFT 28
6813 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
6814 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
6815 +
6816 +/* sbidhigh */
6817 +#define SBIDH_RC_MASK 0x000f /* revision code */
6818 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
6819 +#define SBIDH_RCE_SHIFT 8
6820 +#define SBCOREREV(sbidh) \
6821 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
6822 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
6823 +#define SBIDH_CC_SHIFT 4
6824 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6825 +#define SBIDH_VC_SHIFT 16
6826 +
6827 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6828 +
6829 +/* vendor codes */
6830 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6831 +
6832 +/* core codes */
6833 +#define SB_NODEV 0x700 /* Invalid coreid */
6834 +#define SB_CC 0x800 /* chipcommon core */
6835 +#define SB_ILINE20 0x801 /* iline20 core */
6836 +#define SB_SDRAM 0x803 /* sdram core */
6837 +#define SB_PCI 0x804 /* pci core */
6838 +#define SB_MIPS 0x805 /* mips core */
6839 +#define SB_ENET 0x806 /* enet mac core */
6840 +#define SB_CODEC 0x807 /* v90 codec core */
6841 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6842 +#define SB_ADSL 0x809 /* ADSL core */
6843 +#define SB_ILINE100 0x80a /* iline100 core */
6844 +#define SB_IPSEC 0x80b /* ipsec core */
6845 +#define SB_PCMCIA 0x80d /* pcmcia core */
6846 +#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
6847 +#define SB_SOCRAM 0x80e /* internal memory core */
6848 +#define SB_MEMC 0x80f /* memc sdram core */
6849 +#define SB_EXTIF 0x811 /* external interface core */
6850 +#define SB_D11 0x812 /* 802.11 MAC core */
6851 +#define SB_MIPS33 0x816 /* mips3302 core */
6852 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6853 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6854 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6855 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6856 +#define SB_SDIOH 0x81b /* sdio host core */
6857 +#define SB_ROBO 0x81c /* roboswitch core */
6858 +#define SB_ATA100 0x81d /* parallel ATA core */
6859 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6860 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6861 +#define SB_PCIE 0x820 /* pci express core */
6862 +#define SB_MIMO 0x821 /* MIMO phy core */
6863 +#define SB_SRAMC 0x822 /* SRAM controller core */
6864 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
6865 +#define SB_ARM11 0x824 /* ARM 1176 core */
6866 +#define SB_ARM7 0x825 /* ARM 7tdmi core */
6867 +
6868 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
6869 +
6870 +/* Not really related to Silicon Backplane, but a couple of software
6871 + * conventions for the use the flash space:
6872 + */
6873 +
6874 +/* Minumum amount of flash we support */
6875 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6876 +
6877 +/* A boot/binary may have an embedded block that describes its size */
6878 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6879 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6880 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6881 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6882 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6883 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6884 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6885 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6886 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6887 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
6888 +
6889 +#endif /* _SBCONFIG_H */
6890 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
6891 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6892 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-10-02 21:19:59.000000000 +0200
6893 @@ -0,0 +1,243 @@
6894 +/*
6895 + * Hardware-specific External Interface I/O core definitions
6896 + * for the BCM47xx family of SiliconBackplane-based chips.
6897 + *
6898 + * The External Interface core supports a total of three external chip selects
6899 + * supporting external interfaces. One of the external chip selects is
6900 + * used for Flash, one is used for PCMCIA, and the other may be
6901 + * programmed to support either a synchronous interface or an
6902 + * asynchronous interface. The asynchronous interface can be used to
6903 + * support external devices such as UARTs and the BCM2019 Bluetooth
6904 + * baseband processor.
6905 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6906 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6907 + *
6908 + * Copyright 2006, Broadcom Corporation
6909 + * All Rights Reserved.
6910 + *
6911 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6912 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6913 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6914 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6915 + *
6916 + * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
6917 + */
6918 +
6919 +#ifndef _SBEXTIF_H
6920 +#define _SBEXTIF_H
6921 +
6922 +/* external interface address space */
6923 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6924 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6925 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6926 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6927 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6928 +
6929 +/* cpp contortions to concatenate w/arg prescan */
6930 +#ifndef PAD
6931 +#define _PADLINE(line) pad ## line
6932 +#define _XSTR(line) _PADLINE(line)
6933 +#define PAD _XSTR(__LINE__)
6934 +#endif /* PAD */
6935 +
6936 +/*
6937 + * The multiple instances of output and output enable registers
6938 + * are present to allow driver software for multiple cores to control
6939 + * gpio outputs without needing to share a single register pair.
6940 + */
6941 +struct gpiouser {
6942 + uint32 out;
6943 + uint32 outen;
6944 +};
6945 +#define NGPIOUSER 5
6946 +
6947 +typedef volatile struct {
6948 + uint32 corecontrol;
6949 + uint32 extstatus;
6950 + uint32 PAD[2];
6951 +
6952 + /* pcmcia control registers */
6953 + uint32 pcmcia_config;
6954 + uint32 pcmcia_memwait;
6955 + uint32 pcmcia_attrwait;
6956 + uint32 pcmcia_iowait;
6957 +
6958 + /* programmable interface control registers */
6959 + uint32 prog_config;
6960 + uint32 prog_waitcount;
6961 +
6962 + /* flash control registers */
6963 + uint32 flash_config;
6964 + uint32 flash_waitcount;
6965 + uint32 PAD[4];
6966 +
6967 + uint32 watchdog;
6968 +
6969 + /* clock control */
6970 + uint32 clockcontrol_n;
6971 + uint32 clockcontrol_sb;
6972 + uint32 clockcontrol_pci;
6973 + uint32 clockcontrol_mii;
6974 + uint32 PAD[3];
6975 +
6976 + /* gpio */
6977 + uint32 gpioin;
6978 + struct gpiouser gpio[NGPIOUSER];
6979 + uint32 PAD;
6980 + uint32 ejtagouten;
6981 + uint32 gpiointpolarity;
6982 + uint32 gpiointmask;
6983 + uint32 PAD[153];
6984 +
6985 + uint8 uartdata;
6986 + uint8 PAD[3];
6987 + uint8 uartimer;
6988 + uint8 PAD[3];
6989 + uint8 uartfcr;
6990 + uint8 PAD[3];
6991 + uint8 uartlcr;
6992 + uint8 PAD[3];
6993 + uint8 uartmcr;
6994 + uint8 PAD[3];
6995 + uint8 uartlsr;
6996 + uint8 PAD[3];
6997 + uint8 uartmsr;
6998 + uint8 PAD[3];
6999 + uint8 uartscratch;
7000 + uint8 PAD[3];
7001 +} extifregs_t;
7002 +
7003 +/* corecontrol */
7004 +#define CC_UE (1 << 0) /* uart enable */
7005 +
7006 +/* extstatus */
7007 +#define ES_EM (1 << 0) /* endian mode (ro) */
7008 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7009 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7010 +
7011 +/* gpio bit mask */
7012 +#define GPIO_BIT0 (1 << 0)
7013 +#define GPIO_BIT1 (1 << 1)
7014 +#define GPIO_BIT2 (1 << 2)
7015 +#define GPIO_BIT3 (1 << 3)
7016 +#define GPIO_BIT4 (1 << 4)
7017 +#define GPIO_BIT5 (1 << 5)
7018 +#define GPIO_BIT6 (1 << 6)
7019 +#define GPIO_BIT7 (1 << 7)
7020 +
7021 +
7022 +/* pcmcia/prog/flash_config */
7023 +#define CF_EN (1 << 0) /* enable */
7024 +#define CF_EM_MASK 0xe /* mode */
7025 +#define CF_EM_SHIFT 1
7026 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7027 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7028 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7029 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7030 +#define CF_BS (1 << 5) /* byteswap */
7031 +#define CF_CD_MASK 0xc0 /* clock divider */
7032 +#define CF_CD_SHIFT 6
7033 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7034 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7035 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7036 +#define CF_CE (1 << 8) /* clock enable */
7037 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7038 +
7039 +/* pcmcia_memwait */
7040 +#define PM_W0_MASK 0x3f /* waitcount0 */
7041 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7042 +#define PM_W1_SHIFT 8
7043 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7044 +#define PM_W2_SHIFT 16
7045 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7046 +#define PM_W3_SHIFT 24
7047 +
7048 +/* pcmcia_attrwait */
7049 +#define PA_W0_MASK 0x3f /* waitcount0 */
7050 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7051 +#define PA_W1_SHIFT 8
7052 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7053 +#define PA_W2_SHIFT 16
7054 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7055 +#define PA_W3_SHIFT 24
7056 +
7057 +/* pcmcia_iowait */
7058 +#define PI_W0_MASK 0x3f /* waitcount0 */
7059 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7060 +#define PI_W1_SHIFT 8
7061 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7062 +#define PI_W2_SHIFT 16
7063 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7064 +#define PI_W3_SHIFT 24
7065 +
7066 +/* prog_waitcount */
7067 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7068 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7069 +#define PW_W1_SHIFT 8
7070 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7071 +#define PW_W2_SHIFT 16
7072 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7073 +#define PW_W3_SHIFT 24
7074 +
7075 +#define PW_W0 0x0000000c
7076 +#define PW_W1 0x00000a00
7077 +#define PW_W2 0x00020000
7078 +#define PW_W3 0x01000000
7079 +
7080 +/* flash_waitcount */
7081 +#define FW_W0_MASK 0x1f /* waitcount0 */
7082 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7083 +#define FW_W1_SHIFT 8
7084 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7085 +#define FW_W2_SHIFT 16
7086 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7087 +#define FW_W3_SHIFT 24
7088 +
7089 +/* watchdog */
7090 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7091 +
7092 +/* clockcontrol_n */
7093 +#define CN_N1_MASK 0x3f /* n1 control */
7094 +#define CN_N2_MASK 0x3f00 /* n2 control */
7095 +#define CN_N2_SHIFT 8
7096 +
7097 +/* clockcontrol_sb/pci/mii */
7098 +#define CC_M1_MASK 0x3f /* m1 control */
7099 +#define CC_M2_MASK 0x3f00 /* m2 control */
7100 +#define CC_M2_SHIFT 8
7101 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7102 +#define CC_M3_SHIFT 16
7103 +#define CC_MC_MASK 0x1f000000 /* mux control */
7104 +#define CC_MC_SHIFT 24
7105 +
7106 +/* Clock control default values */
7107 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7108 +#define CC_DEF_100 0x04020011
7109 +#define CC_DEF_33 0x11030011
7110 +#define CC_DEF_25 0x11050011
7111 +
7112 +/* Clock control values for 125Mhz */
7113 +#define CC_125_N 0x0802
7114 +#define CC_125_M 0x04020009
7115 +#define CC_125_M25 0x11090009
7116 +#define CC_125_M33 0x11090005
7117 +
7118 +/* Clock control magic field values */
7119 +#define CC_F6_2 0x02 /* A factor of 2 in */
7120 +#define CC_F6_3 0x03 /* 6-bit fields like */
7121 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7122 +#define CC_F6_5 0x09
7123 +#define CC_F6_6 0x11
7124 +#define CC_F6_7 0x21
7125 +
7126 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7127 +
7128 +#define CC_MC_BYPASS 0x08
7129 +#define CC_MC_M1 0x04
7130 +#define CC_MC_M1M2 0x02
7131 +#define CC_MC_M1M2M3 0x01
7132 +#define CC_MC_M1M3 0x11
7133 +
7134 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7135 +
7136 +#endif /* _SBEXTIF_H */
7137 diff -urN linux.old/arch/mips/bcm947xx/include/sbhndmips.h linux.dev/arch/mips/bcm947xx/include/sbhndmips.h
7138 --- linux.old/arch/mips/bcm947xx/include/sbhndmips.h 1970-01-01 01:00:00.000000000 +0100
7139 +++ linux.dev/arch/mips/bcm947xx/include/sbhndmips.h 2006-10-02 21:19:59.000000000 +0200
7140 @@ -0,0 +1,47 @@
7141 +/*
7142 + * Broadcom SiliconBackplane MIPS definitions
7143 + *
7144 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7145 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7146 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7147 + * interface. The core revision is stored in the SB ID register in SB
7148 + * configuration space.
7149 + *
7150 + * Copyright 2006, Broadcom Corporation
7151 + * All Rights Reserved.
7152 + *
7153 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7154 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7155 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7156 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7157 + *
7158 + * $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
7159 + */
7160 +
7161 +#ifndef _sbhndmips_h_
7162 +#define _sbhndmips_h_
7163 +
7164 +#include <mipsinc.h>
7165 +
7166 +#ifndef _LANGUAGE_ASSEMBLY
7167 +
7168 +/* cpp contortions to concatenate w/arg prescan */
7169 +#ifndef PAD
7170 +#define _PADLINE(line) pad ## line
7171 +#define _XSTR(line) _PADLINE(line)
7172 +#define PAD _XSTR(__LINE__)
7173 +#endif /* PAD */
7174 +
7175 +typedef volatile struct {
7176 + uint32 corecontrol;
7177 + uint32 PAD[2];
7178 + uint32 biststatus;
7179 + uint32 PAD[4];
7180 + uint32 intstatus;
7181 + uint32 intmask;
7182 + uint32 timer;
7183 +} mipsregs_t;
7184 +
7185 +#endif /* _LANGUAGE_ASSEMBLY */
7186 +
7187 +#endif /* _sbhndmips_h_ */
7188 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7189 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7190 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-10-02 21:19:59.000000000 +0200
7191 @@ -0,0 +1,147 @@
7192 +/*
7193 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7194 + *
7195 + * Copyright 2006, Broadcom Corporation
7196 + * All Rights Reserved.
7197 + *
7198 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7199 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7200 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7201 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7202 + *
7203 + * $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
7204 + */
7205 +
7206 +#ifndef _SBMEMC_H
7207 +#define _SBMEMC_H
7208 +
7209 +#ifdef _LANGUAGE_ASSEMBLY
7210 +
7211 +#define MEMC_CONTROL 0x00
7212 +#define MEMC_CONFIG 0x04
7213 +#define MEMC_REFRESH 0x08
7214 +#define MEMC_BISTSTAT 0x0c
7215 +#define MEMC_MODEBUF 0x10
7216 +#define MEMC_BKCLS 0x14
7217 +#define MEMC_PRIORINV 0x18
7218 +#define MEMC_DRAMTIM 0x1c
7219 +#define MEMC_INTSTAT 0x20
7220 +#define MEMC_INTMASK 0x24
7221 +#define MEMC_INTINFO 0x28
7222 +#define MEMC_NCDLCTL 0x30
7223 +#define MEMC_RDNCDLCOR 0x34
7224 +#define MEMC_WRNCDLCOR 0x38
7225 +#define MEMC_MISCDLYCTL 0x3c
7226 +#define MEMC_DQSGATENCDL 0x40
7227 +#define MEMC_SPARE 0x44
7228 +#define MEMC_TPADDR 0x48
7229 +#define MEMC_TPDATA 0x4c
7230 +#define MEMC_BARRIER 0x50
7231 +#define MEMC_CORE 0x54
7232 +
7233 +#else /* !_LANGUAGE_ASSEMBLY */
7234 +
7235 +/* Sonics side: MEMC core registers */
7236 +typedef volatile struct sbmemcregs {
7237 + uint32 control;
7238 + uint32 config;
7239 + uint32 refresh;
7240 + uint32 biststat;
7241 + uint32 modebuf;
7242 + uint32 bkcls;
7243 + uint32 priorinv;
7244 + uint32 dramtim;
7245 + uint32 intstat;
7246 + uint32 intmask;
7247 + uint32 intinfo;
7248 + uint32 reserved1;
7249 + uint32 ncdlctl;
7250 + uint32 rdncdlcor;
7251 + uint32 wrncdlcor;
7252 + uint32 miscdlyctl;
7253 + uint32 dqsgatencdl;
7254 + uint32 spare;
7255 + uint32 tpaddr;
7256 + uint32 tpdata;
7257 + uint32 barrier;
7258 + uint32 core;
7259 +} sbmemcregs_t;
7260 +
7261 +#endif /* _LANGUAGE_ASSEMBLY */
7262 +
7263 +/* MEMC Core Init values (OCP ID 0x80f) */
7264 +
7265 +/* For sdr: */
7266 +#define MEMC_SD_CONFIG_INIT 0x00048000
7267 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7268 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7269 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7270 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7271 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7272 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7273 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7274 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7275 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7276 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7277 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7278 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7279 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7280 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7281 +
7282 +
7283 +/* This is for SDRM8X8X4 */
7284 +#define MEMC_SDR_INIT 0x0008
7285 +#define MEMC_SDR_MODE 0x32
7286 +#define MEMC_SDR_NCDL 0x00020032
7287 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7288 +
7289 +/* For ddr: */
7290 +#define MEMC_CONFIG_INIT 0x00048000
7291 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7292 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7293 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7294 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7295 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7296 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7297 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7298 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7299 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7300 +#define MEMC_NCDLCTL_INIT 0x00002001
7301 +#define MEMC_CONTROL_INIT0 0x00000002
7302 +#define MEMC_CONTROL_INIT1 0x00000008
7303 +#define MEMC_MODEBUF_INIT0 0x00004000
7304 +#define MEMC_CONTROL_INIT2 0x00000010
7305 +#define MEMC_MODEBUF_INIT1 0x00000100
7306 +#define MEMC_CONTROL_INIT3 0x00000010
7307 +#define MEMC_CONTROL_INIT4 0x00000008
7308 +#define MEMC_REFRESH_INIT 0x0000840f
7309 +#define MEMC_CONTROL_INIT5 0x00000004
7310 +#define MEMC_MODEBUF_INIT2 0x00000000
7311 +#define MEMC_CONTROL_INIT6 0x00000010
7312 +#define MEMC_CONTROL_INIT7 0x00000001
7313 +
7314 +
7315 +/* This is for DDRM16X16X2 */
7316 +#define MEMC_DDR_INIT 0x0009
7317 +#define MEMC_DDR_MODE 0x62
7318 +#define MEMC_DDR_NCDL 0x0005050a
7319 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7320 +
7321 +/* mask for sdr/ddr calibration registers */
7322 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7323 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7324 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7325 +
7326 +/* masks for miscdlyctl registers */
7327 +#define MEMC_MISC_SM_MASK 0x30000000
7328 +#define MEMC_MISC_SM_SHIFT 28
7329 +#define MEMC_MISC_SD_MASK 0x0f000000
7330 +#define MEMC_MISC_SD_SHIFT 24
7331 +
7332 +/* hw threshhold for calculating wr/rd for sdr memc */
7333 +#define MEMC_CD_THRESHOLD 128
7334 +
7335 +/* Low bit of init register says if memc is ddr or sdr */
7336 +#define MEMC_CONFIG_DDR 0x00000001
7337 +
7338 +#endif /* _SBMEMC_H */
7339 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
7340 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
7341 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-10-02 21:19:59.000000000 +0200
7342 @@ -0,0 +1,200 @@
7343 +/*
7344 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
7345 + *
7346 + * Copyright 2006, Broadcom Corporation
7347 + * All Rights Reserved.
7348 + *
7349 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7350 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7351 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7352 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7353 + *
7354 + * $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
7355 + */
7356 +
7357 +#ifndef _SBPCIE_H
7358 +#define _SBPCIE_H
7359 +
7360 +/* cpp contortions to concatenate w/arg prescan */
7361 +#ifndef PAD
7362 +#define _PADLINE(line) pad ## line
7363 +#define _XSTR(line) _PADLINE(line)
7364 +#define PAD _XSTR(__LINE__)
7365 +#endif
7366 +
7367 +/* PCIE Enumeration space offsets */
7368 +#define PCIE_CORE_CONFIG_OFFSET 0x0
7369 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
7370 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
7371 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
7372 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
7373 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
7374 +#define PCIE_SBCONFIG_OFFSET 0xE00
7375 +
7376 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
7377 +#define PCIE_DEV_BAR0_SIZE 0x4000
7378 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
7379 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
7380 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
7381 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
7382 +
7383 +/* SB side: PCIE core and host control registers */
7384 +typedef struct sbpcieregs {
7385 + uint32 PAD[3];
7386 + uint32 biststatus; /* bist Status: 0x00C */
7387 + uint32 PAD[6];
7388 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
7389 + uint32 PAD[54];
7390 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
7391 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
7392 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
7393 + uint32 PAD[4];
7394 +
7395 + /* pcie core supports in direct access to config space */
7396 + uint32 configaddr; /* pcie config space access: Address field: 0x120 */
7397 + uint32 configdata; /* pcie config space access: Data field: 0x124 */
7398 +
7399 + /* mdio access to serdes */
7400 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
7401 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
7402 +
7403 + /* pcie protocol phy/dllp/tlp register access mechanism */
7404 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
7405 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
7406 +
7407 + uint32 PAD[434];
7408 + uint16 sprom[36]; /* SPROM shadow Area */
7409 +} sbpcieregs_t;
7410 +
7411 +/* SB to PCIE translation masks */
7412 +#define SBTOPCIE0_MASK 0xfc000000
7413 +#define SBTOPCIE1_MASK 0xfc000000
7414 +#define SBTOPCIE2_MASK 0xc0000000
7415 +
7416 +/* Access type bits (0:1) */
7417 +#define SBTOPCIE_MEM 0
7418 +#define SBTOPCIE_IO 1
7419 +#define SBTOPCIE_CFG0 2
7420 +#define SBTOPCIE_CFG1 3
7421 +
7422 +/* Prefetch enable bit 2 */
7423 +#define SBTOPCIE_PF 4
7424 +
7425 +/* Write Burst enable for memory write bit 3 */
7426 +#define SBTOPCIE_WR_BURST 8
7427 +
7428 +/* config access */
7429 +#define CONFIGADDR_FUNC_MASK 0x7000
7430 +#define CONFIGADDR_FUNC_SHF 12
7431 +#define CONFIGADDR_REG_MASK 0x0FFF
7432 +#define CONFIGADDR_REG_SHF 0
7433 +
7434 +/* PCIE protocol regs Indirect Address */
7435 +#define PCIEADDR_PROT_MASK 0x300
7436 +#define PCIEADDR_PROT_SHF 8
7437 +#define PCIEADDR_PL_TLP 0
7438 +#define PCIEADDR_PL_DLLP 1
7439 +#define PCIEADDR_PL_PLP 2
7440 +
7441 +/* PCIE protocol PHY diagnostic registers */
7442 +#define PCIE_PLP_MODEREG 0x200 /* Mode */
7443 +#define PCIE_PLP_STATUSREG 0x204 /* Status */
7444 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
7445 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
7446 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
7447 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
7448 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
7449 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
7450 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
7451 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
7452 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
7453 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
7454 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
7455 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
7456 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
7457 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
7458 +
7459 +/* PCIE protocol DLLP diagnostic registers */
7460 +#define PCIE_DLLP_LCREG 0x100 /* Link Control */
7461 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
7462 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
7463 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
7464 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
7465 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
7466 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
7467 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
7468 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
7469 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
7470 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
7471 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
7472 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
7473 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
7474 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
7475 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
7476 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
7477 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
7478 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
7479 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
7480 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
7481 +
7482 +/* PCIE protocol TLP diagnostic registers */
7483 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
7484 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
7485 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
7486 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
7487 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
7488 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
7489 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
7490 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
7491 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
7492 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
7493 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
7494 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
7495 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
7496 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
7497 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
7498 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
7499 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
7500 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
7501 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
7502 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
7503 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
7504 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
7505 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
7506 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
7507 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
7508 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
7509 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
7510 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
7511 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
7512 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
7513 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
7514 +
7515 +/* MDIO control */
7516 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
7517 +#define MDIOCTL_DIVISOR_VAL 0x2
7518 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
7519 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
7520 +
7521 +/* MDIO Data */
7522 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
7523 +#define MDIODATA_TA 0x00020000 /* Turnaround */
7524 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
7525 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
7526 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
7527 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
7528 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
7529 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
7530 +#define MDIODATA_START 0x40000000 /* start of Transaction */
7531 +
7532 +/* MDIO devices (SERDES modules) */
7533 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
7534 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
7535 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
7536 +
7537 +/* SERDES registers */
7538 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
7539 +#define SERDES_RX_CDR 6 /* CDR */
7540 +#define SERDES_RX_CDRBW 7 /* CDR BW */
7541 +
7542 +#endif /* _SBPCIE_H */
7543 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7544 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7545 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-10-02 21:19:59.000000000 +0200
7546 @@ -0,0 +1,114 @@
7547 +/*
7548 + * HND SiliconBackplane PCI core hardware definitions.
7549 + *
7550 + * Copyright 2006, Broadcom Corporation
7551 + * All Rights Reserved.
7552 + *
7553 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7554 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7555 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7556 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7557 + *
7558 + * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
7559 + */
7560 +
7561 +#ifndef _sbpci_h_
7562 +#define _sbpci_h_
7563 +
7564 +#ifndef _LANGUAGE_ASSEMBLY
7565 +
7566 +/* cpp contortions to concatenate w/arg prescan */
7567 +#ifndef PAD
7568 +#define _PADLINE(line) pad ## line
7569 +#define _XSTR(line) _PADLINE(line)
7570 +#define PAD _XSTR(__LINE__)
7571 +#endif
7572 +
7573 +/* Sonics side: PCI core and host control registers */
7574 +typedef struct sbpciregs {
7575 + uint32 control; /* PCI control */
7576 + uint32 PAD[3];
7577 + uint32 arbcontrol; /* PCI arbiter control */
7578 + uint32 PAD[3];
7579 + uint32 intstatus; /* Interrupt status */
7580 + uint32 intmask; /* Interrupt mask */
7581 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7582 + uint32 PAD[9];
7583 + uint32 bcastaddr; /* Sonics broadcast address */
7584 + uint32 bcastdata; /* Sonics broadcast data */
7585 + uint32 PAD[2];
7586 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7587 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7588 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7589 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7590 + uint32 PAD[36];
7591 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7592 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7593 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7594 + uint32 PAD[189];
7595 + uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
7596 + uint16 sprom[36]; /* SPROM shadow Area */
7597 + uint32 PAD[46];
7598 +} sbpciregs_t;
7599 +
7600 +#endif /* _LANGUAGE_ASSEMBLY */
7601 +
7602 +/* PCI control */
7603 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7604 +#define PCI_RST 0x02 /* Value driven out to pin */
7605 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7606 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7607 +
7608 +/* PCI arbiter control */
7609 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7610 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7611 +/* ParkID - for PCI corerev >= 8 */
7612 +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
7613 +#define PCI_PARKID_SHIFT 2
7614 +#define PCI_PARKID_EXT0 0 /* External master 0 */
7615 +#define PCI_PARKID_EXT1 1 /* External master 1 */
7616 +#define PCI_PARKID_EXT2 2 /* External master 2 */
7617 +#define PCI_PARKID_INT 3 /* Internal master */
7618 +#define PCI_PARKID_LAST 4 /* Last active master */
7619 +
7620 +/* Interrupt status/mask */
7621 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7622 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7623 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7624 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7625 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7626 +
7627 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7628 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7629 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7630 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7631 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7632 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7633 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7634 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7635 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7636 +
7637 +/* Sonics broadcast address */
7638 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7639 +
7640 +/* Sonics to PCI translation types */
7641 +#define SBTOPCI0_MASK 0xfc000000
7642 +#define SBTOPCI1_MASK 0xfc000000
7643 +#define SBTOPCI2_MASK 0xc0000000
7644 +#define SBTOPCI_MEM 0
7645 +#define SBTOPCI_IO 1
7646 +#define SBTOPCI_CFG0 2
7647 +#define SBTOPCI_CFG1 3
7648 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7649 +#define SBTOPCI_BURST 0x8 /* burst enable */
7650 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7651 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7652 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7653 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7654 +
7655 +/* PCI core index in SROM shadow area */
7656 +#define SRSH_PI_OFFSET 0 /* first word */
7657 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
7658 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
7659 +
7660 +#endif /* _sbpci_h_ */
7661 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7662 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7663 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-10-02 21:19:59.000000000 +0200
7664 @@ -0,0 +1,147 @@
7665 +/*
7666 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7667 + *
7668 + * Copyright 2006, Broadcom Corporation
7669 + * All Rights Reserved.
7670 + *
7671 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7672 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7673 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7674 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7675 + *
7676 + * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
7677 + */
7678 +
7679 +#ifndef _SBPCMCIA_H
7680 +#define _SBPCMCIA_H
7681 +
7682 +
7683 +/* All the addresses that are offsets in attribute space are divided
7684 + * by two to account for the fact that odd bytes are invalid in
7685 + * attribute space and our read/write routines make the space appear
7686 + * as if they didn't exist. Still we want to show the original numbers
7687 + * as documented in the hnd_pcmcia core manual.
7688 + */
7689 +
7690 +/* PCMCIA Function Configuration Registers */
7691 +#define PCMCIA_FCR (0x700 / 2)
7692 +
7693 +#define FCR0_OFF 0
7694 +#define FCR1_OFF (0x40 / 2)
7695 +#define FCR2_OFF (0x80 / 2)
7696 +#define FCR3_OFF (0xc0 / 2)
7697 +
7698 +#define PCMCIA_FCR0 (0x700 / 2)
7699 +#define PCMCIA_FCR1 (0x740 / 2)
7700 +#define PCMCIA_FCR2 (0x780 / 2)
7701 +#define PCMCIA_FCR3 (0x7c0 / 2)
7702 +
7703 +/* Standard PCMCIA FCR registers */
7704 +
7705 +#define PCMCIA_COR 0
7706 +
7707 +#define COR_RST 0x80
7708 +#define COR_LEV 0x40
7709 +#define COR_IRQEN 0x04
7710 +#define COR_BLREN 0x01
7711 +#define COR_FUNEN 0x01
7712 +
7713 +
7714 +#define PCICIA_FCSR (2 / 2)
7715 +#define PCICIA_PRR (4 / 2)
7716 +#define PCICIA_SCR (6 / 2)
7717 +#define PCICIA_ESR (8 / 2)
7718 +
7719 +
7720 +#define PCM_MEMOFF 0x0000
7721 +#define F0_MEMOFF 0x1000
7722 +#define F1_MEMOFF 0x2000
7723 +#define F2_MEMOFF 0x3000
7724 +#define F3_MEMOFF 0x4000
7725 +
7726 +/* Memory base in the function fcr's */
7727 +#define MEM_ADDR0 (0x728 / 2)
7728 +#define MEM_ADDR1 (0x72a / 2)
7729 +#define MEM_ADDR2 (0x72c / 2)
7730 +
7731 +/* PCMCIA base plus Srom access in fcr0: */
7732 +#define PCMCIA_ADDR0 (0x072e / 2)
7733 +#define PCMCIA_ADDR1 (0x0730 / 2)
7734 +#define PCMCIA_ADDR2 (0x0732 / 2)
7735 +
7736 +#define MEM_SEG (0x0734 / 2)
7737 +#define SROM_CS (0x0736 / 2)
7738 +#define SROM_DATAL (0x0738 / 2)
7739 +#define SROM_DATAH (0x073a / 2)
7740 +#define SROM_ADDRL (0x073c / 2)
7741 +#define SROM_ADDRH (0x073e / 2)
7742 +
7743 +/* Values for srom_cs: */
7744 +#define SROM_IDLE 0
7745 +#define SROM_WRITE 1
7746 +#define SROM_READ 2
7747 +#define SROM_WEN 4
7748 +#define SROM_WDS 7
7749 +#define SROM_DONE 8
7750 +
7751 +/* CIS stuff */
7752 +
7753 +/* The CIS stops where the FCRs start */
7754 +#define CIS_SIZE PCMCIA_FCR
7755 +
7756 +/* Standard tuples we know about */
7757 +
7758 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7759 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7760 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7761 +
7762 +/* Function extensions for LANs */
7763 +
7764 +#define LAN_TECH 1 /* Technology type */
7765 +#define LAN_SPEED 2 /* Raw bit rate */
7766 +#define LAN_MEDIA 3 /* Transmission media */
7767 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7768 +#define LAN_CONN 5 /* Connector standard */
7769 +
7770 +
7771 +/* CFTable */
7772 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7773 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7774 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7775 +
7776 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7777 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7778 + */
7779 +
7780 +#define CISTPL_BRCM_HNBU 0x80
7781 +
7782 +/* Subtypes of BRCM_HNBU: */
7783 +
7784 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
7785 +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
7786 +#define HNBU_BOARDREV 0x02 /* One byte board revision */
7787 +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
7788 + * or 9 (sromrev > 1) bytes
7789 + */
7790 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
7791 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
7792 +#define HNBU_AA 0x06 /* Antennas available */
7793 +#define HNBU_AG 0x07 /* Antenna gain */
7794 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
7795 +#define HNBU_LEDS 0x09 /* LED set */
7796 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
7797 + * in rev 2
7798 + */
7799 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
7800 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
7801 +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
7802 +
7803 +
7804 +/* sbtmstatelow */
7805 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7806 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7807 +
7808 +/* sbtmstatehigh */
7809 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7810 +
7811 +#endif /* _SBPCMCIA_H */
7812 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7813 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7814 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-10-02 21:19:59.000000000 +0200
7815 @@ -0,0 +1,85 @@
7816 +/*
7817 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7818 + *
7819 + * Copyright 2006, Broadcom Corporation
7820 + * All Rights Reserved.
7821 + *
7822 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7823 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7824 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7825 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7826 + *
7827 + * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
7828 + */
7829 +
7830 +#ifndef _SBSDRAM_H
7831 +#define _SBSDRAM_H
7832 +
7833 +#ifndef _LANGUAGE_ASSEMBLY
7834 +
7835 +/* Sonics side: SDRAM core registers */
7836 +typedef volatile struct sbsdramregs {
7837 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7838 + uint32 config; /* Initializes external SDRAM mode register */
7839 + uint32 refresh; /* Controls external SDRAM refresh rate */
7840 + uint32 pad1;
7841 + uint32 pad2;
7842 +} sbsdramregs_t;
7843 +
7844 +/* SDRAM simulation */
7845 +#ifdef RAMSZ
7846 +#define SDRAMSZ RAMSZ
7847 +#else
7848 +#define SDRAMSZ (4 * 1024 * 1024)
7849 +#endif
7850 +
7851 +extern uchar sdrambuf[SDRAMSZ];
7852 +
7853 +#endif /* _LANGUAGE_ASSEMBLY */
7854 +
7855 +/* SDRAM initialization control (initcontrol) register bits */
7856 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7857 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7858 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7859 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7860 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7861 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7862 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7863 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7864 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7865 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7866 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7867 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7868 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7869 +
7870 +/* SDRAM configuration (config) register bits */
7871 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7872 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7873 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7874 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7875 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7876 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7877 +
7878 +/* SDRAM refresh control (refresh) register bits */
7879 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7880 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7881 +
7882 +/* SDRAM Core default Init values (OCP ID 0x803) */
7883 +#define SDRAM_INIT MEM4MX16X2
7884 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7885 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7886 +
7887 +#define MEM1MX16 0x009 /* 2 MB */
7888 +#define MEM1MX16X2 0x409 /* 4 MB */
7889 +#define MEM2MX8X2 0x809 /* 4 MB */
7890 +#define MEM2MX8X4 0xc09 /* 8 MB */
7891 +#define MEM2MX32 0x439 /* 8 MB */
7892 +#define MEM4MX16 0x019 /* 8 MB */
7893 +#define MEM4MX16X2 0x419 /* 16 MB */
7894 +#define MEM8MX8X2 0x819 /* 16 MB */
7895 +#define MEM8MX16 0x829 /* 16 MB */
7896 +#define MEM4MX32 0x429 /* 16 MB */
7897 +#define MEM8MX8X4 0xc19 /* 32 MB */
7898 +#define MEM8MX16X2 0xc29 /* 32 MB */
7899 +
7900 +#endif /* _SBSDRAM_H */
7901 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7902 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7903 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-10-02 21:19:59.000000000 +0200
7904 @@ -0,0 +1,64 @@
7905 +/*
7906 + * BCM47XX Sonics SiliconBackplane embedded ram core
7907 + *
7908 + * Copyright 2006, Broadcom Corporation
7909 + * All Rights Reserved.
7910 + *
7911 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7912 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7913 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7914 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7915 + *
7916 + * $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
7917 + */
7918 +
7919 +#ifndef _SBSOCRAM_H
7920 +#define _SBSOCRAM_H
7921 +
7922 +#define SR_COREINFO 0x00
7923 +#define SR_BWALLOC 0x04
7924 +#define SR_BISTSTAT 0x0c
7925 +#define SR_BANKINDEX 0x10
7926 +#define SR_BANKSTBYCTL 0x14
7927 +
7928 +
7929 +#ifndef _LANGUAGE_ASSEMBLY
7930 +
7931 +/* Memcsocram core registers */
7932 +typedef volatile struct sbsocramregs {
7933 + uint32 coreinfo;
7934 + uint32 bwalloc;
7935 + uint32 PAD;
7936 + uint32 biststat;
7937 + uint32 bankidx;
7938 + uint32 standbyctrl;
7939 +} sbsocramregs_t;
7940 +
7941 +#endif
7942 +
7943 +/* Coreinfo register */
7944 +#define SRCI_PT_MASK 0x30000
7945 +#define SRCI_PT_SHIFT 16
7946 +
7947 +/* In corerev 0, the memory size is 2 to the power of the
7948 + * base plus 16 plus to the contents of the memsize field plus 1.
7949 + */
7950 +#define SRCI_MS0_MASK 0xf
7951 +#define SR_MS0_BASE 16
7952 +
7953 +/*
7954 + * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
7955 + * the memory size is number of banks times bank size.
7956 + * The same applies to rom size.
7957 + */
7958 +#define SRCI_ROMNB_MASK 0xf000
7959 +#define SRCI_ROMNB_SHIFT 12
7960 +#define SRCI_ROMBSZ_MASK 0xf00
7961 +#define SRCI_ROMBSZ_SHIFT 8
7962 +#define SRCI_SRNB_MASK 0xf0
7963 +#define SRCI_SRNB_SHIFT 4
7964 +#define SRCI_SRBSZ_MASK 0xf
7965 +#define SRCI_SRBSZ_SHIFT 0
7966 +
7967 +#define SR_BSZ_BASE 14
7968 +#endif /* _SBSOCRAM_H */
7969 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
7970 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
7971 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-10-02 21:19:59.000000000 +0200
7972 @@ -0,0 +1,150 @@
7973 +/*
7974 + * Misc utility routines for accessing chip-specific features
7975 + * of Broadcom HNBU SiliconBackplane-based chips.
7976 + *
7977 + * Copyright 2006, Broadcom Corporation
7978 + * All Rights Reserved.
7979 + *
7980 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7981 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7982 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7983 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7984 + *
7985 + * $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
7986 + */
7987 +
7988 +#ifndef _sbutils_h_
7989 +#define _sbutils_h_
7990 +
7991 +/*
7992 + * Datastructure to export all chip specific common variables
7993 + * public (read-only) portion of sbutils handle returned by
7994 + * sb_attach()/sb_kattach()
7995 +*/
7996 +
7997 +struct sb_pub {
7998 +
7999 + uint bustype; /* SB_BUS, PCI_BUS */
8000 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
8001 + uint buscorerev; /* buscore rev */
8002 + uint buscoreidx; /* buscore index */
8003 + int ccrev; /* chip common core rev */
8004 + uint boardtype; /* board type */
8005 + uint boardvendor; /* board vendor */
8006 + uint chip; /* chip number */
8007 + uint chiprev; /* chip revision */
8008 + uint chippkg; /* chip package option */
8009 + uint sonicsrev; /* sonics backplane rev */
8010 +};
8011 +
8012 +typedef const struct sb_pub sb_t;
8013 +
8014 +/*
8015 + * Many of the routines below take an 'sbh' handle as their first arg.
8016 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8017 + * At any one time, the sbh is logically focused on one particular sb core
8018 + * (the "current core").
8019 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8020 + */
8021 +
8022 +#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
8023 +/* exported externs */
8024 +extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
8025 + void *sdh, char **vars, uint *varsz);
8026 +extern sb_t *sb_kattach(void);
8027 +extern void sb_detach(sb_t *sbh);
8028 +extern uint sb_chip(sb_t *sbh);
8029 +extern uint sb_chiprev(sb_t *sbh);
8030 +extern uint sb_chipcrev(sb_t *sbh);
8031 +extern uint sb_chippkg(sb_t *sbh);
8032 +extern uint sb_pcirev(sb_t *sbh);
8033 +extern bool sb_war16165(sb_t *sbh);
8034 +extern uint sb_pcmciarev(sb_t *sbh);
8035 +extern uint sb_boardvendor(sb_t *sbh);
8036 +extern uint sb_boardtype(sb_t *sbh);
8037 +extern uint sb_bus(sb_t *sbh);
8038 +extern uint sb_buscoretype(sb_t *sbh);
8039 +extern uint sb_buscorerev(sb_t *sbh);
8040 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8041 +extern uint sb_coreid(sb_t *sbh);
8042 +extern uint sb_coreidx(sb_t *sbh);
8043 +extern uint sb_coreunit(sb_t *sbh);
8044 +extern uint sb_corevendor(sb_t *sbh);
8045 +extern uint sb_corerev(sb_t *sbh);
8046 +extern void *sb_osh(sb_t *sbh);
8047 +extern void sb_setosh(sb_t *sbh, osl_t *osh);
8048 +extern void *sb_coreregs(sb_t *sbh);
8049 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8050 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8051 +extern bool sb_iscoreup(sb_t *sbh);
8052 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8053 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8054 +extern int sb_corebist(sb_t *sbh);
8055 +extern void sb_commit(sb_t *sbh);
8056 +extern uint32 sb_base(uint32 admatch);
8057 +extern uint32 sb_size(uint32 admatch);
8058 +extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
8059 +extern void sb_core_tofixup(sb_t *sbh);
8060 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8061 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8062 +extern uint32 sb_clock(sb_t *sbh);
8063 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8064 +extern void sb_pcmcia_init(sb_t *sbh);
8065 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8066 +extern void *sb_gpiosetcore(sb_t *sbh);
8067 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8068 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8069 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8070 +extern uint32 sb_gpioin(sb_t *sbh);
8071 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8072 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8073 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8074 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8075 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8076 +
8077 +extern void sb_clkctl_init(sb_t *sbh);
8078 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8079 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8080 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8081 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
8082 + void *intrsenabled_fn, void *intr_arg);
8083 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8084 +extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
8085 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
8086 + uint8 *pciheader);
8087 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8088 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8089 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8090 +extern bool sb_backplane64(sb_t *sbh);
8091 +extern void sb_btcgpiowar(sb_t *sbh);
8092 +
8093 +
8094 +
8095 +
8096 +extern bool sb_deviceremoved(sb_t *sbh);
8097 +extern uint32 sb_socram_size(sb_t *sbh);
8098 +
8099 +/*
8100 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8101 +* The returned path is NULL terminated and has trailing '/'.
8102 +* Return 0 on success, nonzero otherwise.
8103 +*/
8104 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8105 +
8106 +/* clkctl xtal what flags */
8107 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8108 +#define PLL 0x2 /* main chip pll */
8109 +
8110 +/* clkctl clk mode */
8111 +#define CLK_FAST 0 /* force fast (pll) clock */
8112 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8113 +
8114 +
8115 +/* GPIO usage priorities */
8116 +#define GPIO_DRV_PRIORITY 0 /* Driver */
8117 +#define GPIO_APP_PRIORITY 1 /* Application */
8118 +
8119 +/* device path */
8120 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8121 +
8122 +#endif /* _sbutils_h_ */
8123 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8124 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8125 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-10-02 21:19:59.000000000 +0200
8126 @@ -0,0 +1,36 @@
8127 +/*
8128 + * Broadcom SiliconBackplane chipcommon serial flash interface
8129 + *
8130 + * Copyright 2006, Broadcom Corporation
8131 + * All Rights Reserved.
8132 + *
8133 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8134 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8135 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8136 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8137 + *
8138 + * $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
8139 + */
8140 +
8141 +#ifndef _sflash_h_
8142 +#define _sflash_h_
8143 +
8144 +#include <typedefs.h>
8145 +#include <sbchipc.h>
8146 +
8147 +struct sflash {
8148 + uint blocksize; /* Block size */
8149 + uint numblocks; /* Number of blocks */
8150 + uint32 type; /* Type */
8151 + uint size; /* Total size in bytes */
8152 +};
8153 +
8154 +/* Utility functions */
8155 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8156 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8157 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8158 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8159 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8160 +extern struct sflash * sflash_init(chipcregs_t *cc);
8161 +
8162 +#endif /* _sflash_h_ */
8163 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8164 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8165 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-10-02 21:19:59.000000000 +0200
8166 @@ -0,0 +1,33 @@
8167 +/*
8168 + * TRX image file header format.
8169 + *
8170 + * Copyright 2005, Broadcom Corporation
8171 + * All Rights Reserved.
8172 + *
8173 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8174 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8175 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8176 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8177 + *
8178 + * $Id$
8179 + */
8180 +
8181 +#include <typedefs.h>
8182 +
8183 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8184 +#define TRX_VERSION 1
8185 +#define TRX_MAX_LEN 0x3A0000
8186 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8187 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8188 +#define TRX_MAX_OFFSET 3
8189 +
8190 +struct trx_header {
8191 + uint32 magic; /* "HDR0" */
8192 + uint32 len; /* Length of file including header */
8193 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8194 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8195 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8196 +};
8197 +
8198 +/* Compatibility */
8199 +typedef struct trx_header TRXHDR, *PTRXHDR;
8200 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8201 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8202 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-10-02 21:19:59.000000000 +0200
8203 @@ -0,0 +1,361 @@
8204 +/*
8205 + * Copyright 2006, Broadcom Corporation
8206 + * All Rights Reserved.
8207 + *
8208 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8209 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8210 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8211 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8212 + * $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
8213 + */
8214 +
8215 +#ifndef _TYPEDEFS_H_
8216 +#define _TYPEDEFS_H_
8217 +
8218 +
8219 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8220 + * typedef file "site_typedefs.h".
8221 + *
8222 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8223 + * section of this file makes inferences about the compile environment
8224 + * based on defined symbols and possibly compiler pragmas.
8225 + *
8226 + * Following these two sections is the "Default Typedefs"
8227 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8228 + * defined. This section has a default set of typedefs and a few
8229 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8230 + */
8231 +
8232 +#ifdef SITE_TYPEDEFS
8233 +
8234 +/*
8235 + * Site Specific Typedefs
8236 + *
8237 + */
8238 +
8239 +#include "site_typedefs.h"
8240 +
8241 +#else
8242 +
8243 +/*
8244 + * Inferred Typedefs
8245 + *
8246 + */
8247 +
8248 +/* Infer the compile environment based on preprocessor symbols and pramas.
8249 + * Override type definitions as needed, and include configuration dependent
8250 + * header files to define types.
8251 + */
8252 +
8253 +#ifdef __cplusplus
8254 +
8255 +#define TYPEDEF_BOOL
8256 +#ifndef FALSE
8257 +#define FALSE false
8258 +#endif
8259 +#ifndef TRUE
8260 +#define TRUE true
8261 +#endif
8262 +
8263 +#else /* ! __cplusplus */
8264 +
8265 +#if defined(_WIN32)
8266 +
8267 +#define TYPEDEF_BOOL
8268 +typedef unsigned char bool; /* consistent w/BOOL */
8269 +
8270 +#endif /* _WIN32 */
8271 +
8272 +#endif /* ! __cplusplus */
8273 +
8274 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8275 +#if defined(_WIN64)
8276 +#include <basetsd.h>
8277 +#define TYPEDEF_UINTPTR
8278 +typedef ULONG_PTR uintptr;
8279 +#endif
8280 +
8281 +
8282 +#if defined(_MINOSL_)
8283 +#define _NEED_SIZE_T_
8284 +#endif
8285 +
8286 +#if defined(_NEED_SIZE_T_)
8287 +typedef long unsigned int size_t;
8288 +#endif
8289 +
8290 +#ifdef __DJGPP__
8291 +typedef long unsigned int size_t;
8292 +#endif /* __DJGPP__ */
8293 +
8294 +#ifdef _MSC_VER /* Microsoft C */
8295 +#define TYPEDEF_INT64
8296 +#define TYPEDEF_UINT64
8297 +typedef signed __int64 int64;
8298 +typedef unsigned __int64 uint64;
8299 +#endif
8300 +
8301 +#if defined(MACOSX)
8302 +#define TYPEDEF_BOOL
8303 +#endif
8304 +
8305 +#if defined(__NetBSD__)
8306 +#define TYPEDEF_ULONG
8307 +#endif
8308 +
8309 +
8310 +#if defined(linux)
8311 +#define TYPEDEF_UINT
8312 +#define TYPEDEF_USHORT
8313 +#define TYPEDEF_ULONG
8314 +#endif
8315 +
8316 +#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
8317 + !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
8318 +#define TYPEDEF_UINT
8319 +#define TYPEDEF_USHORT
8320 +#endif
8321 +
8322 +
8323 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8324 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8325 +#define TYPEDEF_INT64
8326 +#define TYPEDEF_UINT64
8327 +#endif
8328 +
8329 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8330 + * for singned or unsigned
8331 + */
8332 +#if defined(__ICL)
8333 +
8334 +#define TYPEDEF_INT64
8335 +
8336 +#if defined(__STDC__)
8337 +#define TYPEDEF_UINT64
8338 +#endif
8339 +
8340 +#endif /* __ICL */
8341 +
8342 +#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
8343 + !defined(__DJGPP__)
8344 +
8345 +/* pick up ushort & uint from standard types.h */
8346 +#if defined(linux) && defined(__KERNEL__)
8347 +
8348 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8349 +
8350 +#else
8351 +
8352 +#include <sys/types.h>
8353 +
8354 +#endif
8355 +
8356 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
8357 +
8358 +#if defined(MACOSX)
8359 +
8360 +#ifdef __BIG_ENDIAN__
8361 +#define IL_BIGENDIAN
8362 +#else
8363 +#ifdef IL_BIGENDIAN
8364 +#error "IL_BIGENDIAN was defined for a little-endian compile"
8365 +#endif
8366 +#endif /* __BIG_ENDIAN__ */
8367 +
8368 +#if !defined(__cplusplus)
8369 +
8370 +#if defined(__i386__)
8371 +typedef unsigned char bool;
8372 +#else
8373 +typedef unsigned int bool;
8374 +#endif
8375 +#define TYPE_BOOL 1
8376 +enum {
8377 + false = 0,
8378 + true = 1
8379 +};
8380 +
8381 +#if defined(KERNEL)
8382 +#include <IOKit/IOTypes.h>
8383 +#endif /* KERNEL */
8384 +
8385 +#endif /* __cplusplus */
8386 +
8387 +#endif /* MACOSX */
8388 +
8389 +
8390 +/* use the default typedefs in the next section of this file */
8391 +#define USE_TYPEDEF_DEFAULTS
8392 +
8393 +#endif /* SITE_TYPEDEFS */
8394 +
8395 +
8396 +/*
8397 + * Default Typedefs
8398 + *
8399 + */
8400 +
8401 +#ifdef USE_TYPEDEF_DEFAULTS
8402 +#undef USE_TYPEDEF_DEFAULTS
8403 +
8404 +#ifndef TYPEDEF_BOOL
8405 +typedef /* @abstract@ */ unsigned char bool;
8406 +#endif
8407 +
8408 +/* define uchar, ushort, uint, ulong */
8409 +
8410 +#ifndef TYPEDEF_UCHAR
8411 +typedef unsigned char uchar;
8412 +#endif
8413 +
8414 +#ifndef TYPEDEF_USHORT
8415 +typedef unsigned short ushort;
8416 +#endif
8417 +
8418 +#ifndef TYPEDEF_UINT
8419 +typedef unsigned int uint;
8420 +#endif
8421 +
8422 +#ifndef TYPEDEF_ULONG
8423 +typedef unsigned long ulong;
8424 +#endif
8425 +
8426 +/* define [u]int8/16/32/64, uintptr */
8427 +
8428 +#ifndef TYPEDEF_UINT8
8429 +typedef unsigned char uint8;
8430 +#endif
8431 +
8432 +#ifndef TYPEDEF_UINT16
8433 +typedef unsigned short uint16;
8434 +#endif
8435 +
8436 +#ifndef TYPEDEF_UINT32
8437 +typedef unsigned int uint32;
8438 +#endif
8439 +
8440 +#ifndef TYPEDEF_UINT64
8441 +typedef unsigned long long uint64;
8442 +#endif
8443 +
8444 +#ifndef TYPEDEF_UINTPTR
8445 +typedef unsigned int uintptr;
8446 +#endif
8447 +
8448 +#ifndef TYPEDEF_INT8
8449 +typedef signed char int8;
8450 +#endif
8451 +
8452 +#ifndef TYPEDEF_INT16
8453 +typedef signed short int16;
8454 +#endif
8455 +
8456 +#ifndef TYPEDEF_INT32
8457 +typedef signed int int32;
8458 +#endif
8459 +
8460 +#ifndef TYPEDEF_INT64
8461 +typedef signed long long int64;
8462 +#endif
8463 +
8464 +/* define float32/64, float_t */
8465 +
8466 +#ifndef TYPEDEF_FLOAT32
8467 +typedef float float32;
8468 +#endif
8469 +
8470 +#ifndef TYPEDEF_FLOAT64
8471 +typedef double float64;
8472 +#endif
8473 +
8474 +/*
8475 + * abstracted floating point type allows for compile time selection of
8476 + * single or double precision arithmetic. Compiling with -DFLOAT32
8477 + * selects single precision; the default is double precision.
8478 + */
8479 +
8480 +#ifndef TYPEDEF_FLOAT_T
8481 +
8482 +#if defined(FLOAT32)
8483 +typedef float32 float_t;
8484 +#else /* default to double precision floating point */
8485 +typedef float64 float_t;
8486 +#endif
8487 +
8488 +#endif /* TYPEDEF_FLOAT_T */
8489 +
8490 +/* define macro values */
8491 +
8492 +#ifndef FALSE
8493 +#define FALSE 0
8494 +#endif
8495 +
8496 +#ifndef TRUE
8497 +#define TRUE 1 /* TRUE */
8498 +#endif
8499 +
8500 +#ifndef NULL
8501 +#define NULL 0
8502 +#endif
8503 +
8504 +#ifndef OFF
8505 +#define OFF 0
8506 +#endif
8507 +
8508 +#ifndef ON
8509 +#define ON 1 /* ON = 1 */
8510 +#endif
8511 +
8512 +#define AUTO (-1) /* Auto = -1 */
8513 +
8514 +/* define PTRSZ, INLINE */
8515 +
8516 +#ifndef PTRSZ
8517 +#define PTRSZ sizeof(char*)
8518 +#endif
8519 +
8520 +#ifndef INLINE
8521 +
8522 +#ifdef _MSC_VER
8523 +
8524 +#define INLINE __inline
8525 +
8526 +#elif __GNUC__
8527 +
8528 +#define INLINE __inline__
8529 +
8530 +#else
8531 +
8532 +#define INLINE
8533 +
8534 +#endif /* _MSC_VER */
8535 +
8536 +#endif /* INLINE */
8537 +
8538 +#undef TYPEDEF_BOOL
8539 +#undef TYPEDEF_UCHAR
8540 +#undef TYPEDEF_USHORT
8541 +#undef TYPEDEF_UINT
8542 +#undef TYPEDEF_ULONG
8543 +#undef TYPEDEF_UINT8
8544 +#undef TYPEDEF_UINT16
8545 +#undef TYPEDEF_UINT32
8546 +#undef TYPEDEF_UINT64
8547 +#undef TYPEDEF_UINTPTR
8548 +#undef TYPEDEF_INT8
8549 +#undef TYPEDEF_INT16
8550 +#undef TYPEDEF_INT32
8551 +#undef TYPEDEF_INT64
8552 +#undef TYPEDEF_FLOAT32
8553 +#undef TYPEDEF_FLOAT64
8554 +#undef TYPEDEF_FLOAT_T
8555 +
8556 +#endif /* USE_TYPEDEF_DEFAULTS */
8557 +
8558 +/*
8559 + * Including the bcmdefs.h here, to make sure everyone including typedefs.h
8560 + * gets this automatically
8561 +*/
8562 +#include "bcmdefs.h"
8563 +
8564 +#endif /* _TYPEDEFS_H_ */
8565 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
8566 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
8567 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-10-02 21:26:08.000000000 +0200
8568 @@ -0,0 +1,17 @@
8569 +#
8570 +# Makefile for the BCM947xx specific kernel interface routines
8571 +# under Linux.
8572 +#
8573 +
8574 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER -fno-delayed-branch
8575 +
8576 +O_TARGET := bcm947xx.o
8577 +
8578 +export-objs := export.o
8579 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
8580 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
8581 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
8582 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
8583 +obj-y += export.o
8584 +
8585 +include $(TOPDIR)/Rules.make
8586 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
8587 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
8588 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-10-02 21:19:59.000000000 +0200
8589 @@ -0,0 +1,315 @@
8590 +/*
8591 + * NVRAM variable manipulation (common)
8592 + *
8593 + * Copyright 2004, Broadcom Corporation
8594 + * All Rights Reserved.
8595 + *
8596 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8597 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8598 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8599 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8600 + *
8601 + */
8602 +
8603 +#include <typedefs.h>
8604 +#include <osl.h>
8605 +#include <bcmendian.h>
8606 +#include <bcmnvram.h>
8607 +#include <bcmutils.h>
8608 +#include <sbsdram.h>
8609 +
8610 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
8611 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
8612 +extern int BCMINIT(_nvram_read)(void *buf);
8613 +
8614 +char * BCMINIT(_nvram_get)(const char *name);
8615 +int BCMINIT(_nvram_set)(const char *name, const char *value);
8616 +int BCMINIT(_nvram_unset)(const char *name);
8617 +int BCMINIT(_nvram_getall)(char *buf, int count);
8618 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
8619 +int BCMINIT(_nvram_init)(void);
8620 +void BCMINIT(_nvram_exit)(void);
8621 +
8622 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
8623 +static struct nvram_tuple * nvram_dead;
8624 +
8625 +/* Free all tuples. Should be locked. */
8626 +static void
8627 +BCMINITFN(nvram_free)(void)
8628 +{
8629 + uint i;
8630 + struct nvram_tuple *t, *next;
8631 +
8632 + /* Free hash table */
8633 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8634 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
8635 + next = t->next;
8636 + BCMINIT(_nvram_free)(t);
8637 + }
8638 + BCMINIT(nvram_hash)[i] = NULL;
8639 + }
8640 +
8641 + /* Free dead table */
8642 + for (t = nvram_dead; t; t = next) {
8643 + next = t->next;
8644 + BCMINIT(_nvram_free)(t);
8645 + }
8646 + nvram_dead = NULL;
8647 +
8648 + /* Indicate to per-port code that all tuples have been freed */
8649 + BCMINIT(_nvram_free)(NULL);
8650 +}
8651 +
8652 +/* String hash */
8653 +static INLINE uint
8654 +hash(const char *s)
8655 +{
8656 + uint hash = 0;
8657 +
8658 + while (*s)
8659 + hash = 31 * hash + *s++;
8660 +
8661 + return hash;
8662 +}
8663 +
8664 +/* (Re)initialize the hash table. Should be locked. */
8665 +static int
8666 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
8667 +{
8668 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
8669 +
8670 + /* (Re)initialize hash table */
8671 + BCMINIT(nvram_free)();
8672 +
8673 + /* Parse and set "name=value\0 ... \0\0" */
8674 + name = (char *) &header[1];
8675 + end = (char *) header + NVRAM_SPACE - 2;
8676 + end[0] = end[1] = '\0';
8677 + for (; *name; name = value + strlen(value) + 1) {
8678 + if (!(eq = strchr(name, '=')))
8679 + break;
8680 + *eq = '\0';
8681 + value = eq + 1;
8682 + BCMINIT(_nvram_set)(name, value);
8683 + *eq = '=';
8684 + }
8685 +
8686 + /* Set special SDRAM parameters */
8687 + if (!BCMINIT(_nvram_get)("sdram_init")) {
8688 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
8689 + BCMINIT(_nvram_set)("sdram_init", buf);
8690 + }
8691 + if (!BCMINIT(_nvram_get)("sdram_config")) {
8692 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
8693 + BCMINIT(_nvram_set)("sdram_config", buf);
8694 + }
8695 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
8696 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
8697 + BCMINIT(_nvram_set)("sdram_refresh", buf);
8698 + }
8699 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
8700 + sprintf(buf, "0x%08X", header->config_ncdl);
8701 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
8702 + }
8703 +
8704 + return 0;
8705 +}
8706 +
8707 +/* Get the value of an NVRAM variable. Should be locked. */
8708 +char *
8709 +BCMINITFN(_nvram_get)(const char *name)
8710 +{
8711 + uint i;
8712 + struct nvram_tuple *t;
8713 + char *value;
8714 +
8715 + if (!name)
8716 + return NULL;
8717 +
8718 + /* Hash the name */
8719 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8720 +
8721 + /* Find the associated tuple in the hash table */
8722 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
8723 +
8724 + value = t ? t->value : NULL;
8725 +
8726 + return value;
8727 +}
8728 +
8729 +/* Get the value of an NVRAM variable. Should be locked. */
8730 +int
8731 +BCMINITFN(_nvram_set)(const char *name, const char *value)
8732 +{
8733 + uint i;
8734 + struct nvram_tuple *t, *u, **prev;
8735 +
8736 + /* Hash the name */
8737 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8738 +
8739 + /* Find the associated tuple in the hash table */
8740 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8741 +
8742 + /* (Re)allocate tuple */
8743 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
8744 + return -12; /* -ENOMEM */
8745 +
8746 + /* Value reallocated */
8747 + if (t && t == u)
8748 + return 0;
8749 +
8750 + /* Move old tuple to the dead table */
8751 + if (t) {
8752 + *prev = t->next;
8753 + t->next = nvram_dead;
8754 + nvram_dead = t;
8755 + }
8756 +
8757 + /* Add new tuple to the hash table */
8758 + u->next = BCMINIT(nvram_hash)[i];
8759 + BCMINIT(nvram_hash)[i] = u;
8760 +
8761 + return 0;
8762 +}
8763 +
8764 +/* Unset the value of an NVRAM variable. Should be locked. */
8765 +int
8766 +BCMINITFN(_nvram_unset)(const char *name)
8767 +{
8768 + uint i;
8769 + struct nvram_tuple *t, **prev;
8770 +
8771 + if (!name)
8772 + return 0;
8773 +
8774 + /* Hash the name */
8775 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8776 +
8777 + /* Find the associated tuple in the hash table */
8778 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8779 +
8780 + /* Move it to the dead table */
8781 + if (t) {
8782 + *prev = t->next;
8783 + t->next = nvram_dead;
8784 + nvram_dead = t;
8785 + }
8786 +
8787 + return 0;
8788 +}
8789 +
8790 +/* Get all NVRAM variables. Should be locked. */
8791 +int
8792 +BCMINITFN(_nvram_getall)(char *buf, int count)
8793 +{
8794 + uint i;
8795 + struct nvram_tuple *t;
8796 + int len = 0;
8797 +
8798 + bzero(buf, count);
8799 +
8800 + /* Write name=value\0 ... \0\0 */
8801 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8802 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8803 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
8804 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
8805 + else
8806 + break;
8807 + }
8808 + }
8809 +
8810 + return 0;
8811 +}
8812 +
8813 +/* Regenerate NVRAM. Should be locked. */
8814 +int
8815 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
8816 +{
8817 + char *init, *config, *refresh, *ncdl;
8818 + char *ptr, *end;
8819 + int i;
8820 + struct nvram_tuple *t;
8821 + struct nvram_header tmp;
8822 + uint8 crc;
8823 +
8824 + /* Regenerate header */
8825 + header->magic = NVRAM_MAGIC;
8826 + header->crc_ver_init = (NVRAM_VERSION << 8);
8827 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
8828 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
8829 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
8830 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
8831 + header->crc_ver_init |= SDRAM_INIT << 16;
8832 + header->config_refresh = SDRAM_CONFIG;
8833 + header->config_refresh |= SDRAM_REFRESH << 16;
8834 + header->config_ncdl = 0;
8835 + } else {
8836 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
8837 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
8838 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
8839 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
8840 + }
8841 +
8842 + /* Clear data area */
8843 + ptr = (char *) header + sizeof(struct nvram_header);
8844 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
8845 +
8846 + /* Leave space for a double NUL at the end */
8847 + end = (char *) header + NVRAM_SPACE - 2;
8848 +
8849 + /* Write out all tuples */
8850 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8851 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8852 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
8853 + break;
8854 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
8855 + }
8856 + }
8857 +
8858 + /* End with a double NUL */
8859 + ptr += 2;
8860 +
8861 + /* Set new length */
8862 + header->len = ROUNDUP(ptr - (char *) header, 4);
8863 +
8864 + /* Little-endian CRC8 over the last 11 bytes of the header */
8865 + tmp.crc_ver_init = htol32(header->crc_ver_init);
8866 + tmp.config_refresh = htol32(header->config_refresh);
8867 + tmp.config_ncdl = htol32(header->config_ncdl);
8868 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
8869 +
8870 + /* Continue CRC8 over data bytes */
8871 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
8872 +
8873 + /* Set new CRC8 */
8874 + header->crc_ver_init |= crc;
8875 +
8876 + /* Reinitialize hash table */
8877 + return BCMINIT(nvram_rehash)(header);
8878 +}
8879 +
8880 +/* Initialize hash table. Should be locked. */
8881 +int
8882 +BCMINITFN(_nvram_init)(void)
8883 +{
8884 + struct nvram_header *header;
8885 + int ret;
8886 +
8887 + if (!(header = (struct nvram_header *) kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
8888 + return -12; /* -ENOMEM */
8889 + }
8890 +
8891 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
8892 + header->magic == NVRAM_MAGIC)
8893 + BCMINIT(nvram_rehash)(header);
8894 +
8895 + kfree(header);
8896 + return ret;
8897 +}
8898 +
8899 +/* Free hash table. Should be locked. */
8900 +void
8901 +BCMINITFN(_nvram_exit)(void)
8902 +{
8903 + BCMINIT(nvram_free)();
8904 +}
8905 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
8906 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
8907 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-10-02 21:19:59.000000000 +0200
8908 @@ -0,0 +1,723 @@
8909 +/*
8910 + * NVRAM variable manipulation (Linux kernel half)
8911 + *
8912 + * Copyright 2006, Broadcom Corporation
8913 + * All Rights Reserved.
8914 + *
8915 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8916 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8917 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8918 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8919 + *
8920 + * $Id: nvram_linux.c,v 1.19 2006/04/08 07:12:42 honor Exp $
8921 + */
8922 +
8923 +#include <linux/config.h>
8924 +#include <linux/init.h>
8925 +#include <linux/module.h>
8926 +#include <linux/kernel.h>
8927 +#include <linux/string.h>
8928 +#include <linux/interrupt.h>
8929 +#include <linux/spinlock.h>
8930 +#include <linux/slab.h>
8931 +#include <linux/bootmem.h>
8932 +#include <linux/wrapper.h>
8933 +#include <linux/fs.h>
8934 +#include <linux/miscdevice.h>
8935 +#include <linux/mtd/mtd.h>
8936 +#include <asm/addrspace.h>
8937 +#include <asm/io.h>
8938 +#include <asm/uaccess.h>
8939 +
8940 +#include <typedefs.h>
8941 +#include <osl.h>
8942 +#include <bcmendian.h>
8943 +#include <bcmnvram.h>
8944 +#include <bcmutils.h>
8945 +#include <sbconfig.h>
8946 +#include <sbchipc.h>
8947 +#include <sbutils.h>
8948 +#include <hndmips.h>
8949 +#include <sflash.h>
8950 +
8951 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
8952 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
8953 +
8954 +#ifdef MODULE
8955 +
8956 +#define early_nvram_get(name) nvram_get(name)
8957 +
8958 +#else /* !MODULE */
8959 +
8960 +/* Global SB handle */
8961 +extern void *bcm947xx_sbh;
8962 +extern spinlock_t bcm947xx_sbh_lock;
8963 +
8964 +static int cfe_env;
8965 +extern char *cfe_env_get(char *nv_buf, const char *name);
8966 +
8967 +/* Convenience */
8968 +#define sbh bcm947xx_sbh
8969 +#define sbh_lock bcm947xx_sbh_lock
8970 +#define KB * 1024
8971 +#define MB * 1024 * 1024
8972 +
8973 +/* Probe for NVRAM header */
8974 +static void __init
8975 +early_nvram_init(void)
8976 +{
8977 + struct nvram_header *header;
8978 + chipcregs_t *cc;
8979 + struct sflash *info = NULL;
8980 + int i;
8981 + uint32 base, off, lim;
8982 + u32 *src, *dst;
8983 +
8984 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
8985 + base = KSEG1ADDR(SB_FLASH2);
8986 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
8987 + case PFLASH:
8988 + lim = SB_FLASH2_SZ;
8989 + break;
8990 +
8991 + case SFLASH_ST:
8992 + case SFLASH_AT:
8993 + if ((info = sflash_init(cc)) == NULL)
8994 + return;
8995 + lim = info->size;
8996 + break;
8997 +
8998 + case FLASH_NONE:
8999 + default:
9000 + return;
9001 + }
9002 + } else {
9003 + /* extif assumed, Stop at 4 MB */
9004 + base = KSEG1ADDR(SB_FLASH1);
9005 + lim = SB_FLASH1_SZ;
9006 + }
9007 +
9008 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
9009 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
9010 + dst = (u32 *) nvram_buf;
9011 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
9012 + printk("early_nvram_init: WGT634U NVRAM found.\n");
9013 +
9014 + for (i = 0; i < 0x1ff0; i++) {
9015 + if (*src == 0xFFFFFFFF)
9016 + break;
9017 + *dst++ = *src++;
9018 + }
9019 + cfe_env = 1;
9020 + return;
9021 + }
9022 +
9023 + off = FLASH_MIN;
9024 + while (off <= lim) {
9025 + /* Windowed flash access */
9026 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9027 + if (header->magic == NVRAM_MAGIC)
9028 + goto found;
9029 + off <<= 1;
9030 + }
9031 +
9032 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9033 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
9034 + if (header->magic == NVRAM_MAGIC)
9035 + goto found;
9036 +
9037 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
9038 + if (header->magic == NVRAM_MAGIC)
9039 + goto found;
9040 +
9041 + printk("early_nvram_init: NVRAM not found\n");
9042 + return;
9043 +
9044 +found:
9045 + src = (u32 *) header;
9046 + dst = (u32 *) nvram_buf;
9047 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9048 + *dst++ = *src++;
9049 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9050 + *dst++ = ltoh32(*src++);
9051 +}
9052 +
9053 +/* Early (before mm or mtd) read-only access to NVRAM */
9054 +static char * __init
9055 +early_nvram_get(const char *name)
9056 +{
9057 + char *var, *value, *end, *eq;
9058 +
9059 + if (!name)
9060 + return NULL;
9061 +
9062 + /* Too early? */
9063 + if (sbh == NULL)
9064 + return NULL;
9065 +
9066 + if (!nvram_buf[0])
9067 + early_nvram_init();
9068 +
9069 + if (cfe_env)
9070 + return cfe_env_get(nvram_buf, name);
9071 +
9072 + /* Look for name=value and return value */
9073 + var = &nvram_buf[sizeof(struct nvram_header)];
9074 + end = nvram_buf + sizeof(nvram_buf) - 2;
9075 + end[0] = end[1] = '\0';
9076 + for (; *var; var = value + strlen(value) + 1) {
9077 + if (!(eq = strchr(var, '=')))
9078 + break;
9079 + value = eq + 1;
9080 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9081 + return value;
9082 + }
9083 +
9084 + return NULL;
9085 +}
9086 +
9087 +static int __init
9088 +early_nvram_getall(char *buf, int count)
9089 +{
9090 + char *var, *end;
9091 + int len = 0;
9092 +
9093 + /* Too early? */
9094 + if (sbh == NULL)
9095 + return -1;
9096 +
9097 + if (!nvram_buf[0])
9098 + early_nvram_init();
9099 +
9100 + bzero(buf, count);
9101 +
9102 + /* Write name=value\0 ... \0\0 */
9103 + var = &nvram_buf[sizeof(struct nvram_header)];
9104 + end = nvram_buf + sizeof(nvram_buf) - 2;
9105 + end[0] = end[1] = '\0';
9106 + for (; *var; var += strlen(var) + 1) {
9107 + if ((count - len) <= (strlen(var) + 1))
9108 + break;
9109 + len += sprintf(buf + len, "%s", var) + 1;
9110 + }
9111 +
9112 + return 0;
9113 +}
9114 +#endif /* !MODULE */
9115 +
9116 +extern char * _nvram_get(const char *name);
9117 +extern int _nvram_set(const char *name, const char *value);
9118 +extern int _nvram_unset(const char *name);
9119 +extern int _nvram_getall(char *buf, int count);
9120 +extern int _nvram_commit(struct nvram_header *header);
9121 +extern int _nvram_init(void *sbh);
9122 +extern void _nvram_exit(void);
9123 +
9124 +/* Globals */
9125 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9126 +static struct semaphore nvram_sem;
9127 +static unsigned long nvram_offset = 0;
9128 +static int nvram_major = -1;
9129 +static devfs_handle_t nvram_handle = NULL;
9130 +static struct mtd_info *nvram_mtd = NULL;
9131 +
9132 +int
9133 +_nvram_read(char *buf)
9134 +{
9135 + struct nvram_header *header = (struct nvram_header *) buf;
9136 + size_t len;
9137 +
9138 + if (!nvram_mtd ||
9139 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9140 + len != NVRAM_SPACE ||
9141 + header->magic != NVRAM_MAGIC) {
9142 + /* Maybe we can recover some data from early initialization */
9143 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9144 + }
9145 +
9146 + return 0;
9147 +}
9148 +
9149 +struct nvram_tuple *
9150 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9151 +{
9152 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9153 + return NULL;
9154 +
9155 + if (!t) {
9156 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9157 + return NULL;
9158 +
9159 + /* Copy name */
9160 + t->name = (char *) &t[1];
9161 + strcpy(t->name, name);
9162 +
9163 + t->value = NULL;
9164 + }
9165 +
9166 + /* Copy value */
9167 + if (!t->value || strcmp(t->value, value)) {
9168 + t->value = &nvram_buf[nvram_offset];
9169 + strcpy(t->value, value);
9170 + nvram_offset += strlen(value) + 1;
9171 + }
9172 +
9173 + return t;
9174 +}
9175 +
9176 +void
9177 +_nvram_free(struct nvram_tuple *t)
9178 +{
9179 + if (!t)
9180 + nvram_offset = 0;
9181 + else
9182 + kfree(t);
9183 +}
9184 +
9185 +int
9186 +nvram_set(const char *name, const char *value)
9187 +{
9188 + unsigned long flags;
9189 + int ret;
9190 + struct nvram_header *header;
9191 +
9192 + spin_lock_irqsave(&nvram_lock, flags);
9193 + if ((ret = _nvram_set(name, value))) {
9194 + /* Consolidate space and try again */
9195 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9196 + if (_nvram_commit(header) == 0)
9197 + ret = _nvram_set(name, value);
9198 + kfree(header);
9199 + }
9200 + }
9201 + spin_unlock_irqrestore(&nvram_lock, flags);
9202 +
9203 + return ret;
9204 +}
9205 +
9206 +char *
9207 +real_nvram_get(const char *name)
9208 +{
9209 + unsigned long flags;
9210 + char *value;
9211 +
9212 + spin_lock_irqsave(&nvram_lock, flags);
9213 + value = _nvram_get(name);
9214 + spin_unlock_irqrestore(&nvram_lock, flags);
9215 +
9216 + return value;
9217 +}
9218 +
9219 +char *
9220 +nvram_get(const char *name)
9221 +{
9222 + if (nvram_major >= 0)
9223 + return real_nvram_get(name);
9224 + else
9225 + return early_nvram_get(name);
9226 +}
9227 +
9228 +int
9229 +nvram_unset(const char *name)
9230 +{
9231 + unsigned long flags;
9232 + int ret;
9233 +
9234 + spin_lock_irqsave(&nvram_lock, flags);
9235 + ret = _nvram_unset(name);
9236 + spin_unlock_irqrestore(&nvram_lock, flags);
9237 +
9238 + return ret;
9239 +}
9240 +
9241 +static void
9242 +erase_callback(struct erase_info *done)
9243 +{
9244 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9245 + wake_up(wait_q);
9246 +}
9247 +
9248 +int
9249 +nvram_commit(void)
9250 +{
9251 + char *buf;
9252 + size_t erasesize, len, magic_len;
9253 + unsigned int i;
9254 + int ret;
9255 + struct nvram_header *header;
9256 + unsigned long flags;
9257 + u_int32_t offset;
9258 + DECLARE_WAITQUEUE(wait, current);
9259 + wait_queue_head_t wait_q;
9260 + struct erase_info erase;
9261 + u_int32_t magic_offset = 0; /* Offset for writing MAGIC # */
9262 +
9263 + if (!nvram_mtd) {
9264 + printk("nvram_commit: NVRAM not found\n");
9265 + return -ENODEV;
9266 + }
9267 +
9268 + if (in_interrupt()) {
9269 + printk("nvram_commit: not committing in interrupt\n");
9270 + return -EINVAL;
9271 + }
9272 +
9273 + /* Backup sector blocks to be erased */
9274 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9275 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9276 + printk("nvram_commit: out of memory\n");
9277 + return -ENOMEM;
9278 + }
9279 +
9280 + down(&nvram_sem);
9281 +
9282 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9283 + offset = nvram_mtd->size - erasesize;
9284 + len = 0;
9285 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9286 + if (ret || len != i) {
9287 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9288 + ret = -EIO;
9289 + goto done;
9290 + }
9291 + header = (struct nvram_header *)(buf + i);
9292 + magic_offset = i + ((void *)&header->magic - (void *)header);
9293 + } else {
9294 + offset = nvram_mtd->size - NVRAM_SPACE;
9295 + magic_offset = ((void *)&header->magic - (void *)header);
9296 + header = (struct nvram_header *)buf;
9297 + }
9298 +
9299 + /* clear the existing magic # to mark the NVRAM as unusable
9300 + we can pull MAGIC bits low without erase */
9301 + header->magic = NVRAM_CLEAR_MAGIC; /* All zeros magic */
9302 +
9303 + /* Unlock sector blocks (for Intel 28F320C3B flash) , 20060309 */
9304 + if(nvram_mtd->unlock)
9305 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9306 +
9307 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9308 + &magic_len, (char *)&header->magic);
9309 + if (ret || magic_len != sizeof(header->magic)) {
9310 + printk("nvram_commit: clear MAGIC error\n");
9311 + ret = -EIO;
9312 + goto done;
9313 + }
9314 +
9315 + header->magic = NVRAM_MAGIC; /* reset MAGIC before we regenerate the NVRAM,
9316 + otherwise we'll have an incorrect CRC */
9317 + /* Regenerate NVRAM */
9318 + spin_lock_irqsave(&nvram_lock, flags);
9319 + ret = _nvram_commit(header);
9320 + spin_unlock_irqrestore(&nvram_lock, flags);
9321 + if (ret)
9322 + goto done;
9323 +
9324 + /* Erase sector blocks */
9325 + init_waitqueue_head(&wait_q);
9326 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9327 + erase.mtd = nvram_mtd;
9328 + erase.addr = offset;
9329 + erase.len = nvram_mtd->erasesize;
9330 + erase.callback = erase_callback;
9331 + erase.priv = (u_long) &wait_q;
9332 +
9333 + set_current_state(TASK_INTERRUPTIBLE);
9334 + add_wait_queue(&wait_q, &wait);
9335 +
9336 + /* Unlock sector blocks */
9337 + if (nvram_mtd->unlock)
9338 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9339 +
9340 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9341 + set_current_state(TASK_RUNNING);
9342 + remove_wait_queue(&wait_q, &wait);
9343 + printk("nvram_commit: erase error\n");
9344 + goto done;
9345 + }
9346 +
9347 + /* Wait for erase to finish */
9348 + schedule();
9349 + remove_wait_queue(&wait_q, &wait);
9350 + }
9351 +
9352 + /* Write partition up to end of data area */
9353 + header->magic = NVRAM_INVALID_MAGIC; /* All ones magic */
9354 + offset = nvram_mtd->size - erasesize;
9355 + i = erasesize - NVRAM_SPACE + header->len;
9356 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9357 + if (ret || len != i) {
9358 + printk("nvram_commit: write error\n");
9359 + ret = -EIO;
9360 + goto done;
9361 + }
9362 +
9363 + /* Now mark the NVRAM in flash as "valid" by setting the correct
9364 + MAGIC # */
9365 + header->magic = NVRAM_MAGIC;
9366 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9367 + &magic_len, (char *)&header->magic);
9368 + if (ret || magic_len != sizeof(header->magic)) {
9369 + printk("nvram_commit: write MAGIC error\n");
9370 + ret = -EIO;
9371 + goto done;
9372 + }
9373 +
9374 + /*
9375 + * Reading a few bytes back here will put the device
9376 + * back to the correct mode on certain flashes */
9377 + offset = nvram_mtd->size - erasesize;
9378 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9379 +
9380 + done:
9381 + up(&nvram_sem);
9382 + kfree(buf);
9383 +
9384 + return ret;
9385 +}
9386 +
9387 +int
9388 +nvram_getall(char *buf, int count)
9389 +{
9390 + unsigned long flags;
9391 + int ret;
9392 +
9393 + spin_lock_irqsave(&nvram_lock, flags);
9394 + if (nvram_major >= 0)
9395 + ret = _nvram_getall(buf, count);
9396 + else
9397 + ret = early_nvram_getall(buf, count);
9398 + spin_unlock_irqrestore(&nvram_lock, flags);
9399 +
9400 + return ret;
9401 +}
9402 +
9403 +
9404 +
9405 +
9406 +
9407 +
9408 +
9409 +/* User mode interface below */
9410 +
9411 +static ssize_t
9412 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9413 +{
9414 + char tmp[100], *name = tmp, *value;
9415 + ssize_t ret;
9416 + unsigned long off;
9417 +
9418 + if (count > sizeof(tmp)) {
9419 + if (!(name = kmalloc(count, GFP_KERNEL)))
9420 + return -ENOMEM;
9421 + }
9422 +
9423 + if (copy_from_user(name, buf, count)) {
9424 + ret = -EFAULT;
9425 + goto done;
9426 + }
9427 +
9428 + if (*name == '\0') {
9429 + /* Get all variables */
9430 + ret = nvram_getall(name, count);
9431 + if (ret == 0) {
9432 + if (copy_to_user(buf, name, count)) {
9433 + ret = -EFAULT;
9434 + goto done;
9435 + }
9436 + ret = count;
9437 + }
9438 + } else {
9439 + if (!(value = nvram_get(name))) {
9440 + ret = 0;
9441 + goto done;
9442 + }
9443 +
9444 + /* Provide the offset into mmap() space */
9445 + off = (unsigned long) value - (unsigned long) nvram_buf;
9446 +
9447 + if (put_user(off, (unsigned long *) buf)) {
9448 + ret = -EFAULT;
9449 + goto done;
9450 + }
9451 +
9452 + ret = sizeof(unsigned long);
9453 + }
9454 +
9455 + flush_cache_all();
9456 +
9457 +done:
9458 + if (name != tmp)
9459 + kfree(name);
9460 +
9461 + return ret;
9462 +}
9463 +
9464 +static ssize_t
9465 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9466 +{
9467 + char tmp[100], *name = tmp, *value;
9468 + ssize_t ret;
9469 +
9470 + if (count > sizeof(tmp)) {
9471 + if (!(name = kmalloc(count, GFP_KERNEL)))
9472 + return -ENOMEM;
9473 + }
9474 +
9475 + if (copy_from_user(name, buf, count)) {
9476 + ret = -EFAULT;
9477 + goto done;
9478 + }
9479 +
9480 + value = name;
9481 + name = strsep(&value, "=");
9482 + if (value)
9483 + ret = nvram_set(name, value) ? : count;
9484 + else
9485 + ret = nvram_unset(name) ? : count;
9486 +
9487 + done:
9488 + if (name != tmp)
9489 + kfree(name);
9490 +
9491 + return ret;
9492 +}
9493 +
9494 +static int
9495 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9496 +{
9497 + if (cmd != NVRAM_MAGIC)
9498 + return -EINVAL;
9499 +
9500 + return nvram_commit();
9501 +}
9502 +
9503 +static int
9504 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9505 +{
9506 + unsigned long offset = virt_to_phys(nvram_buf);
9507 +
9508 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9509 + vma->vm_page_prot))
9510 + return -EAGAIN;
9511 +
9512 + return 0;
9513 +}
9514 +
9515 +static int
9516 +dev_nvram_open(struct inode *inode, struct file * file)
9517 +{
9518 + MOD_INC_USE_COUNT;
9519 + return 0;
9520 +}
9521 +
9522 +static int
9523 +dev_nvram_release(struct inode *inode, struct file * file)
9524 +{
9525 + MOD_DEC_USE_COUNT;
9526 + return 0;
9527 +}
9528 +
9529 +static struct file_operations dev_nvram_fops = {
9530 + owner: THIS_MODULE,
9531 + open: dev_nvram_open,
9532 + release: dev_nvram_release,
9533 + read: dev_nvram_read,
9534 + write: dev_nvram_write,
9535 + ioctl: dev_nvram_ioctl,
9536 + mmap: dev_nvram_mmap,
9537 +};
9538 +
9539 +static void
9540 +dev_nvram_exit(void)
9541 +{
9542 + int order = 0;
9543 + struct page *page, *end;
9544 +
9545 + if (nvram_handle)
9546 + devfs_unregister(nvram_handle);
9547 +
9548 + if (nvram_major >= 0)
9549 + devfs_unregister_chrdev(nvram_major, "nvram");
9550 +
9551 + if (nvram_mtd)
9552 + put_mtd_device(nvram_mtd);
9553 +
9554 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9555 + order++;
9556 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9557 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9558 + mem_map_unreserve(page);
9559 +
9560 + _nvram_exit();
9561 +}
9562 +
9563 +static int __init
9564 +dev_nvram_init(void)
9565 +{
9566 + int order = 0, ret = 0;
9567 + struct page *page, *end;
9568 + unsigned int i;
9569 +
9570 + /* Allocate and reserve memory to mmap() */
9571 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9572 + order++;
9573 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9574 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9575 + mem_map_reserve(page);
9576 +
9577 +#ifdef CONFIG_MTD
9578 + /* Find associated MTD device */
9579 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9580 + nvram_mtd = get_mtd_device(NULL, i);
9581 + if (nvram_mtd) {
9582 + if (!strcmp(nvram_mtd->name, "nvram") &&
9583 + nvram_mtd->size >= NVRAM_SPACE)
9584 + break;
9585 + put_mtd_device(nvram_mtd);
9586 + }
9587 + }
9588 + if (i >= MAX_MTD_DEVICES)
9589 + nvram_mtd = NULL;
9590 +#endif
9591 +
9592 + /* Initialize hash table lock */
9593 + spin_lock_init(&nvram_lock);
9594 +
9595 + /* Initialize commit semaphore */
9596 + init_MUTEX(&nvram_sem);
9597 +
9598 + /* Register char device */
9599 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9600 + ret = nvram_major;
9601 + goto err;
9602 + }
9603 +
9604 + /* Initialize hash table */
9605 + _nvram_init(sbh);
9606 +
9607 + /* Create /dev/nvram handle */
9608 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
9609 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
9610 +
9611 + /* Set the SDRAM NCDL value into NVRAM if not already done */
9612 + if (getintvar(NULL, "sdram_ncdl") == 0) {
9613 + unsigned int ncdl;
9614 + char buf[] = "0x00000000";
9615 +
9616 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
9617 + sprintf(buf, "0x%08x", ncdl);
9618 + nvram_set("sdram_ncdl", buf);
9619 + nvram_commit();
9620 + }
9621 + }
9622 +
9623 + return 0;
9624 +
9625 + err:
9626 + dev_nvram_exit();
9627 + return ret;
9628 +}
9629 +
9630 +module_init(dev_nvram_init);
9631 +module_exit(dev_nvram_exit);
9632 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
9633 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
9634 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-10-02 21:22:56.000000000 +0200
9635 @@ -0,0 +1,380 @@
9636 +/*
9637 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
9638 + *
9639 + * Copyright 2006, Broadcom Corporation
9640 + * All Rights Reserved.
9641 + *
9642 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9643 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9644 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9645 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9646 + *
9647 + * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
9648 + */
9649 +
9650 +#include <linux/config.h>
9651 +#include <linux/types.h>
9652 +#include <linux/kernel.h>
9653 +#include <linux/sched.h>
9654 +#include <linux/pci.h>
9655 +#include <linux/init.h>
9656 +#include <linux/delay.h>
9657 +#include <asm/io.h>
9658 +#include <asm/irq.h>
9659 +#include <asm/paccess.h>
9660 +
9661 +#include <typedefs.h>
9662 +#include <osl.h>
9663 +#include <bcmutils.h>
9664 +#include <sbconfig.h>
9665 +#include <sbutils.h>
9666 +#include <hndpci.h>
9667 +#include <pcicfg.h>
9668 +#include <bcmdevs.h>
9669 +#include <bcmnvram.h>
9670 +
9671 +/* Global SB handle */
9672 +extern sb_t *bcm947xx_sbh;
9673 +extern spinlock_t bcm947xx_sbh_lock;
9674 +
9675 +/* Convenience */
9676 +#define sbh bcm947xx_sbh
9677 +#define sbh_lock bcm947xx_sbh_lock
9678 +
9679 +static int
9680 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
9681 +{
9682 + unsigned long flags;
9683 + int ret;
9684 +
9685 + spin_lock_irqsave(&sbh_lock, flags);
9686 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9687 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9688 + spin_unlock_irqrestore(&sbh_lock, flags);
9689 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9690 +}
9691 +
9692 +static int
9693 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
9694 +{
9695 + unsigned long flags;
9696 + int ret;
9697 +
9698 + spin_lock_irqsave(&sbh_lock, flags);
9699 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9700 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9701 + spin_unlock_irqrestore(&sbh_lock, flags);
9702 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9703 +}
9704 +
9705 +static int
9706 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
9707 +{
9708 + unsigned long flags;
9709 + int ret;
9710 +
9711 + spin_lock_irqsave(&sbh_lock, flags);
9712 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9713 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9714 + spin_unlock_irqrestore(&sbh_lock, flags);
9715 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9716 +}
9717 +
9718 +static int
9719 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
9720 +{
9721 + unsigned long flags;
9722 + int ret;
9723 +
9724 + spin_lock_irqsave(&sbh_lock, flags);
9725 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9726 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9727 + spin_unlock_irqrestore(&sbh_lock, flags);
9728 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9729 +}
9730 +
9731 +static int
9732 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
9733 +{
9734 + unsigned long flags;
9735 + int ret;
9736 +
9737 + spin_lock_irqsave(&sbh_lock, flags);
9738 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9739 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9740 + spin_unlock_irqrestore(&sbh_lock, flags);
9741 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9742 +}
9743 +
9744 +static int
9745 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
9746 +{
9747 + unsigned long flags;
9748 + int ret;
9749 +
9750 + spin_lock_irqsave(&sbh_lock, flags);
9751 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9752 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9753 + spin_unlock_irqrestore(&sbh_lock, flags);
9754 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9755 +}
9756 +
9757 +static struct pci_ops pcibios_ops = {
9758 + sbpci_read_config_byte,
9759 + sbpci_read_config_word,
9760 + sbpci_read_config_dword,
9761 + sbpci_write_config_byte,
9762 + sbpci_write_config_word,
9763 + sbpci_write_config_dword
9764 +};
9765 +
9766 +
9767 +void __init
9768 +pcibios_init(void)
9769 +{
9770 + ulong flags;
9771 +
9772 + if (!(sbh = sb_kattach()))
9773 + panic("sb_kattach failed");
9774 + spin_lock_init(&sbh_lock);
9775 +
9776 + spin_lock_irqsave(&sbh_lock, flags);
9777 + sbpci_init(sbh);
9778 + spin_unlock_irqrestore(&sbh_lock, flags);
9779 +
9780 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
9781 +
9782 + /* Scan the SB bus */
9783 + pci_scan_bus(0, &pcibios_ops, NULL);
9784 +
9785 +}
9786 +
9787 +char * __init
9788 +pcibios_setup(char *str)
9789 +{
9790 + if (!strncmp(str, "ban=", 4)) {
9791 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
9792 + return NULL;
9793 + }
9794 +
9795 + return (str);
9796 +}
9797 +
9798 +static u32 pci_iobase = 0x100;
9799 +static u32 pci_membase = SB_PCI_DMA;
9800 +
9801 +void __init
9802 +pcibios_fixup_bus(struct pci_bus *b)
9803 +{
9804 + struct list_head *ln;
9805 + struct pci_dev *d;
9806 + struct resource *res;
9807 + int pos, size;
9808 + u32 *base;
9809 + u8 irq;
9810 +
9811 + printk("PCI: Fixing up bus %d\n", b->number);
9812 +
9813 + /* Fix up SB */
9814 + if (b->number == 0) {
9815 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9816 + d = pci_dev_b(ln);
9817 + /* Fix up interrupt lines */
9818 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
9819 + d->irq = irq + 2;
9820 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9821 + }
9822 + }
9823 +
9824 + /* Fix up external PCI */
9825 + else {
9826 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9827 + d = pci_dev_b(ln);
9828 + /* Fix up resource bases */
9829 + for (pos = 0; pos < 6; pos++) {
9830 + res = &d->resource[pos];
9831 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
9832 + if (res->end) {
9833 + size = res->end - res->start + 1;
9834 + if (*base & (size - 1))
9835 + *base = (*base + size) & ~(size - 1);
9836 + res->start = *base;
9837 + res->end = res->start + size - 1;
9838 + *base += size;
9839 + pci_write_config_dword(d,
9840 + PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
9841 + }
9842 + /* Fix up PCI bridge BAR0 only */
9843 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
9844 + break;
9845 + }
9846 + /* Fix up interrupt lines */
9847 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
9848 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
9849 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9850 + }
9851 + }
9852 +}
9853 +
9854 +unsigned int
9855 +pcibios_assign_all_busses(void)
9856 +{
9857 + return 1;
9858 +}
9859 +
9860 +void
9861 +pcibios_align_resource(void *data, struct resource *res,
9862 + unsigned long size, unsigned long align)
9863 +{
9864 +}
9865 +
9866 +int
9867 +pcibios_enable_resources(struct pci_dev *dev)
9868 +{
9869 + u16 cmd, old_cmd;
9870 + int idx;
9871 + struct resource *r;
9872 +
9873 + /* External PCI only */
9874 + if (dev->bus->number == 0)
9875 + return 0;
9876 +
9877 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
9878 + old_cmd = cmd;
9879 + for (idx = 0; idx < 6; idx++) {
9880 + r = &dev->resource[idx];
9881 + if (r->flags & IORESOURCE_IO)
9882 + cmd |= PCI_COMMAND_IO;
9883 + if (r->flags & IORESOURCE_MEM)
9884 + cmd |= PCI_COMMAND_MEMORY;
9885 + }
9886 + if (dev->resource[PCI_ROM_RESOURCE].start)
9887 + cmd |= PCI_COMMAND_MEMORY;
9888 + if (cmd != old_cmd) {
9889 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
9890 + pci_write_config_word(dev, PCI_COMMAND, cmd);
9891 + }
9892 + return 0;
9893 +}
9894 +
9895 +int
9896 +pcibios_enable_device(struct pci_dev *dev, int mask)
9897 +{
9898 + ulong flags;
9899 + uint coreidx;
9900 + void *regs;
9901 +
9902 + /* External PCI device enable */
9903 + if (dev->bus->number != 0)
9904 + return pcibios_enable_resources(dev);
9905 +
9906 + /* These cores come out of reset enabled */
9907 + if (dev->device == SB_MIPS ||
9908 + dev->device == SB_MIPS33 ||
9909 + dev->device == SB_EXTIF ||
9910 + dev->device == SB_CC)
9911 + return 0;
9912 +
9913 + spin_lock_irqsave(&sbh_lock, flags);
9914 + coreidx = sb_coreidx(sbh);
9915 + regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
9916 + if (!regs)
9917 + return PCIBIOS_DEVICE_NOT_FOUND;
9918 +
9919 + /*
9920 + * The USB core requires a special bit to be set during core
9921 + * reset to enable host (OHCI) mode. Resetting the SB core in
9922 + * pcibios_enable_device() is a hack for compatibility with
9923 + * vanilla usb-ohci so that it does not have to know about
9924 + * SB. A driver that wants to use the USB core in device mode
9925 + * should know about SB and should reset the bit back to 0
9926 + * after calling pcibios_enable_device().
9927 + */
9928 + if (sb_coreid(sbh) == SB_USB) {
9929 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
9930 + sb_core_reset(sbh, 1 << 29, 0);
9931 + }
9932 + /*
9933 + * USB 2.0 special considerations:
9934 + *
9935 + * 1. Since the core supports both OHCI and EHCI functions, it must
9936 + * only be reset once.
9937 + *
9938 + * 2. In addition to the standard SB reset sequence, the Host Control
9939 + * Register must be programmed to bring the USB core and various
9940 + * phy components out of reset.
9941 + */
9942 + else if (sb_coreid(sbh) == SB_USB20H) {
9943 + if (!sb_iscoreup(sbh)) {
9944 + sb_core_reset(sbh, 0, 0);
9945 + writel(0x7FF, (ulong)regs + 0x200);
9946 + udelay(1);
9947 + }
9948 + } else
9949 + sb_core_reset(sbh, 0, 0);
9950 +
9951 + sb_setcoreidx(sbh, coreidx);
9952 + spin_unlock_irqrestore(&sbh_lock, flags);
9953 +
9954 + return 0;
9955 +}
9956 +
9957 +void
9958 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
9959 + struct resource *res, int resource)
9960 +{
9961 + unsigned long where, size;
9962 + u32 reg;
9963 +
9964 + /* External PCI only */
9965 + if (dev->bus->number == 0)
9966 + return;
9967 +
9968 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
9969 + size = res->end - res->start;
9970 + pci_read_config_dword(dev, where, &reg);
9971 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
9972 + pci_write_config_dword(dev, where, reg);
9973 +}
9974 +
9975 +static void __init
9976 +quirk_sbpci_bridge(struct pci_dev *dev)
9977 +{
9978 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
9979 + return;
9980 +
9981 + printk("PCI: Fixing up bridge\n");
9982 +
9983 + /* Enable PCI bridge bus mastering and memory space */
9984 + pci_set_master(dev);
9985 + pcibios_enable_resources(dev);
9986 +
9987 + /* Enable PCI bridge BAR1 prefetch and burst */
9988 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
9989 +}
9990 +
9991 +struct pci_fixup pcibios_fixups[] = {
9992 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
9993 + { 0 }
9994 +};
9995 +
9996 +/*
9997 + * If we set up a device for bus mastering, we need to check the latency
9998 + * timer as certain crappy BIOSes forget to set it properly.
9999 + */
10000 +unsigned int pcibios_max_latency = 255;
10001 +
10002 +void pcibios_set_master(struct pci_dev *dev)
10003 +{
10004 + u8 lat;
10005 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10006 + if (lat < 16)
10007 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10008 + else if (lat > pcibios_max_latency)
10009 + lat = pcibios_max_latency;
10010 + else
10011 + return;
10012 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10013 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10014 +}
10015 +
10016 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10017 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10018 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-10-02 21:19:59.000000000 +0200
10019 @@ -0,0 +1,41 @@
10020 +/*
10021 + * Early initialization code for BCM94710 boards
10022 + *
10023 + * Copyright 2004, Broadcom Corporation
10024 + * All Rights Reserved.
10025 + *
10026 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10027 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10028 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10029 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10030 + *
10031 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10032 + */
10033 +
10034 +#include <linux/config.h>
10035 +#include <linux/init.h>
10036 +#include <linux/kernel.h>
10037 +#include <linux/types.h>
10038 +#include <asm/bootinfo.h>
10039 +
10040 +void __init
10041 +prom_init(int argc, const char **argv)
10042 +{
10043 + unsigned long mem;
10044 +
10045 + mips_machgroup = MACH_GROUP_BRCM;
10046 + mips_machtype = MACH_BCM947XX;
10047 +
10048 + /* Figure out memory size by finding aliases */
10049 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10050 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10051 + *(unsigned long *)(prom_init))
10052 + break;
10053 + }
10054 + add_memory_region(0, mem, BOOT_MEM_RAM);
10055 +}
10056 +
10057 +void __init
10058 +prom_free_prom_memory(void)
10059 +{
10060 +}
10061 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10062 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10063 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-10-02 21:19:59.000000000 +0200
10064 @@ -0,0 +1,1132 @@
10065 +/*
10066 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10067 + *
10068 + * Copyright 2006, Broadcom Corporation
10069 + * All Rights Reserved.
10070 + *
10071 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10072 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10073 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10074 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10075 + *
10076 + * $Id: hndmips.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
10077 + */
10078 +
10079 +#include <typedefs.h>
10080 +#include <bcmdefs.h>
10081 +#include <osl.h>
10082 +#include <bcmutils.h>
10083 +#include <sbutils.h>
10084 +#include <bcmdevs.h>
10085 +#include <bcmnvram.h>
10086 +#include <sbconfig.h>
10087 +#include <sbextif.h>
10088 +#include <sbchipc.h>
10089 +#include <sbmemc.h>
10090 +#include <mipsinc.h>
10091 +#include <sbhndmips.h>
10092 +#include <hndcpu.h>
10093 +
10094 +/* sbipsflag register format, indexed by irq. */
10095 +static const uint32 sbips_int_mask[] = {
10096 + 0, /* placeholder */
10097 + SBIPS_INT1_MASK,
10098 + SBIPS_INT2_MASK,
10099 + SBIPS_INT3_MASK,
10100 + SBIPS_INT4_MASK
10101 +};
10102 +
10103 +static const uint32 sbips_int_shift[] = {
10104 + 0, /* placeholder */
10105 + SBIPS_INT1_SHIFT,
10106 + SBIPS_INT2_SHIFT,
10107 + SBIPS_INT3_SHIFT,
10108 + SBIPS_INT4_SHIFT
10109 +};
10110 +
10111 +/*
10112 + * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs.
10113 + * Per-port BSP code is required to provide necessary translations between
10114 + * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag.
10115 + *
10116 + * See sb_irq() for the mapping.
10117 + */
10118 +static uint shirq_map_base = 0;
10119 +
10120 +/* Returns the SB interrupt flag of the current core. */
10121 +static uint32
10122 +sb_getflag(sb_t *sbh)
10123 +{
10124 + osl_t *osh;
10125 + void *regs;
10126 + sbconfig_t *sb;
10127 +
10128 + osh = sb_osh(sbh);
10129 + regs = sb_coreregs(sbh);
10130 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10131 +
10132 + return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK);
10133 +}
10134 +
10135 +/*
10136 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10137 + * 0 is returned.
10138 + */
10139 +uint
10140 +sb_irq(sb_t *sbh)
10141 +{
10142 + osl_t *osh;
10143 + uint idx;
10144 + void *regs;
10145 + sbconfig_t *sb;
10146 + uint32 flag, sbipsflag;
10147 + uint irq = 0;
10148 +
10149 + osh = sb_osh(sbh);
10150 + flag = sb_getflag(sbh);
10151 +
10152 + idx = sb_coreidx(sbh);
10153 +
10154 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10155 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10156 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10157 +
10158 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10159 + sbipsflag = R_REG(osh, &sb->sbipsflag);
10160 + for (irq = 1; irq <= 4; irq++) {
10161 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10162 + break;
10163 + }
10164 + if (irq == 5)
10165 + irq = 0;
10166 + }
10167 +
10168 + sb_setcoreidx(sbh, idx);
10169 +
10170 + return irq;
10171 +}
10172 +
10173 +/* Clears the specified MIPS IRQ. */
10174 +static void
10175 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
10176 +{
10177 + osl_t *osh;
10178 + void *regs;
10179 + sbconfig_t *sb;
10180 +
10181 + osh = sb_osh(sbh);
10182 +
10183 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10184 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10185 + ASSERT(regs);
10186 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10187 +
10188 + if (irq == 0)
10189 + W_REG(osh, &sb->sbintvec, 0);
10190 + else
10191 + OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
10192 +}
10193 +
10194 +/*
10195 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10196 + * IRQ 0 may be assigned more than once.
10197 + *
10198 + * The old assignment to the specified core is removed first.
10199 + */
10200 +static void
10201 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
10202 +{
10203 + osl_t *osh;
10204 + void *regs;
10205 + sbconfig_t *sb;
10206 + uint32 flag;
10207 + uint oldirq;
10208 +
10209 + osh = sb_osh(sbh);
10210 +
10211 + regs = sb_setcore(sbh, coreid, coreunit);
10212 + ASSERT(regs);
10213 + flag = sb_getflag(sbh);
10214 + oldirq = sb_irq(sbh);
10215 + if (oldirq)
10216 + sb_clearirq(sbh, oldirq);
10217 +
10218 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10219 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10220 + ASSERT(regs);
10221 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10222 +
10223 + if (!oldirq)
10224 + AND_REG(osh, &sb->sbintvec, ~(1 << flag));
10225 +
10226 + if (irq == 0)
10227 + OR_REG(osh, &sb->sbintvec, 1 << flag);
10228 + else {
10229 + flag <<= sbips_int_shift[irq];
10230 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10231 + flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
10232 + W_REG(osh, &sb->sbipsflag, flag);
10233 + }
10234 +}
10235 +
10236 +/*
10237 + * Initializes clocks and interrupts. SB and NVRAM access must be
10238 + * initialized prior to calling.
10239 + *
10240 + * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero.
10241 + */
10242 +void
10243 +BCMINITFN(sb_mips_init)(sb_t *sbh, uint shirqmap)
10244 +{
10245 + osl_t *osh;
10246 + ulong hz, ns, tmp;
10247 + extifregs_t *eir;
10248 + chipcregs_t *cc;
10249 + char *value;
10250 + uint irq;
10251 +
10252 + osh = sb_osh(sbh);
10253 +
10254 + /* Figure out current SB clock speed */
10255 + if ((hz = sb_clock(sbh)) == 0)
10256 + hz = 100000000;
10257 + ns = 1000000000 / hz;
10258 +
10259 + /* Setup external interface timing */
10260 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10261 + /* Initialize extif so we can get to the LEDs and external UART */
10262 + W_REG(osh, &eir->prog_config, CF_EN);
10263 +
10264 + /* Set timing for the flash */
10265 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10266 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10267 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10268 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10269 +
10270 + /* Set programmable interface timing for external uart */
10271 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10272 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10273 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10274 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10275 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10276 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10277 + /* Set timing for the flash */
10278 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10279 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10280 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10281 + if ((sb_corerev(sbh) < 9) ||
10282 + (BCMINIT(sb_chip)(sbh) == 0x5365))
10283 + W_REG(osh, &cc->flash_waitcount, tmp);
10284 +
10285 + if ((sb_corerev(sbh) < 9) ||
10286 + ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) ||
10287 + (BCMINIT(sb_chip)(sbh) == 0x5365)) {
10288 + W_REG(osh, &cc->pcmcia_memwait, tmp);
10289 + }
10290 +
10291 + /* Save shared IRQ mapping base */
10292 + shirq_map_base = shirqmap;
10293 + }
10294 +
10295 + /* Chip specific initialization */
10296 + switch (sb_chip(sbh)) {
10297 + case BCM4710_CHIP_ID:
10298 + /* Clear interrupt map */
10299 + for (irq = 0; irq <= 4; irq++)
10300 + sb_clearirq(sbh, irq);
10301 + sb_setirq(sbh, 0, SB_CODEC, 0);
10302 + sb_setirq(sbh, 0, SB_EXTIF, 0);
10303 + sb_setirq(sbh, 2, SB_ENET, 1);
10304 + sb_setirq(sbh, 3, SB_ILINE20, 0);
10305 + sb_setirq(sbh, 4, SB_PCI, 0);
10306 + ASSERT(eir);
10307 + value = nvram_get("et0phyaddr");
10308 + if (value && !strcmp(value, "31")) {
10309 + /* Enable internal UART */
10310 + W_REG(osh, &eir->corecontrol, CC_UE);
10311 + /* Give USB its own interrupt */
10312 + sb_setirq(sbh, 1, SB_USB, 0);
10313 + } else {
10314 + /* Disable internal UART */
10315 + W_REG(osh, &eir->corecontrol, 0);
10316 + /* Give Ethernet its own interrupt */
10317 + sb_setirq(sbh, 1, SB_ENET, 0);
10318 + sb_setirq(sbh, 0, SB_USB, 0);
10319 + }
10320 + break;
10321 + case BCM5350_CHIP_ID:
10322 + /* Clear interrupt map */
10323 + for (irq = 0; irq <= 4; irq++)
10324 + sb_clearirq(sbh, irq);
10325 + sb_setirq(sbh, 0, SB_CC, 0);
10326 + sb_setirq(sbh, 0, SB_MIPS33, 0);
10327 + sb_setirq(sbh, 1, SB_D11, 0);
10328 + sb_setirq(sbh, 2, SB_ENET, 0);
10329 + sb_setirq(sbh, 3, SB_PCI, 0);
10330 + sb_setirq(sbh, 4, SB_USB, 0);
10331 + break;
10332 + case BCM4785_CHIP_ID:
10333 + /* Reassign PCI to irq 4 */
10334 + sb_setirq(sbh, 4, SB_PCI, 0);
10335 + break;
10336 + }
10337 +}
10338 +
10339 +uint32
10340 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
10341 +{
10342 + extifregs_t *eir;
10343 + chipcregs_t *cc;
10344 + uint32 n, m;
10345 + uint idx;
10346 + uint32 pll_type, rate = 0;
10347 +
10348 + /* get index of the current core */
10349 + idx = sb_coreidx(sbh);
10350 + pll_type = PLL_TYPE1;
10351 +
10352 + /* switch to extif or chipc core */
10353 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10354 + n = R_REG(osh, &eir->clockcontrol_n);
10355 + m = R_REG(osh, &eir->clockcontrol_sb);
10356 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10357 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10358 + n = R_REG(osh, &cc->clockcontrol_n);
10359 + if ((pll_type == PLL_TYPE2) ||
10360 + (pll_type == PLL_TYPE4) ||
10361 + (pll_type == PLL_TYPE6) ||
10362 + (pll_type == PLL_TYPE7))
10363 + m = R_REG(osh, &cc->clockcontrol_m3);
10364 + else if (pll_type == PLL_TYPE5) {
10365 + rate = 200000000;
10366 + goto out;
10367 + }
10368 + else if (pll_type == PLL_TYPE3) {
10369 + if (sb_chip(sbh) == BCM5365_CHIP_ID) {
10370 + rate = 200000000;
10371 + goto out;
10372 + }
10373 + /* 5350 uses m2 to control mips */
10374 + else
10375 + m = R_REG(osh, &cc->clockcontrol_m2);
10376 + } else
10377 + m = R_REG(osh, &cc->clockcontrol_sb);
10378 + } else
10379 + goto out;
10380 +
10381 +
10382 + /* calculate rate */
10383 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
10384 + rate = 100000000;
10385 + else
10386 + rate = sb_clock_rate(pll_type, n, m);
10387 +
10388 + if (pll_type == PLL_TYPE6)
10389 + rate = SB2MIPS_T6(rate);
10390 +
10391 +out:
10392 + /* switch back to previous core */
10393 + sb_setcoreidx(sbh, idx);
10394 +
10395 + return rate;
10396 +}
10397 +
10398 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10399 +
10400 +static void
10401 +BCMINITFN(handler)(void)
10402 +{
10403 + __asm__(
10404 + ".set\tmips32\n\t"
10405 + "ssnop\n\t"
10406 + "ssnop\n\t"
10407 + /* Disable interrupts */
10408 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10409 + "mfc0 $15, $12\n\t"
10410 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10411 + "li $14, -31746\n\t"
10412 + "and $15, $15, $14\n\t"
10413 + "mtc0 $15, $12\n\t"
10414 + "eret\n\t"
10415 + "nop\n\t"
10416 + "nop\n\t"
10417 + ".set\tmips0");
10418 +}
10419 +
10420 +/* The following MUST come right after handler() */
10421 +static void
10422 +BCMINITFN(afterhandler)(void)
10423 +{
10424 +}
10425 +
10426 +/*
10427 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10428 + *
10429 + * MIPS clocks synchronization function has been moved from PLL in chipcommon
10430 + * core rev. 15 to a DLL inside the MIPS core in 4785.
10431 + */
10432 +bool
10433 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10434 +{
10435 + extifregs_t *eir = NULL;
10436 + chipcregs_t *cc = NULL;
10437 + mipsregs_t *mipsr = NULL;
10438 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10439 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
10440 + uint32 pll_type, sync_mode;
10441 + uint ic_size, ic_lsize;
10442 + uint idx, i;
10443 +
10444 + /* PLL configuration: type 1 */
10445 + typedef struct {
10446 + uint32 mipsclock;
10447 + uint16 n;
10448 + uint32 sb;
10449 + uint32 pci33;
10450 + uint32 pci25;
10451 + } n3m_table_t;
10452 + static n3m_table_t BCMINITDATA(type1_table)[] = {
10453 + /* 96.000 32.000 24.000 */
10454 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 },
10455 + /* 100.000 33.333 25.000 */
10456 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 },
10457 + /* 104.000 31.200 24.960 */
10458 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 },
10459 + /* 108.000 32.400 24.923 */
10460 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 },
10461 + /* 112.000 32.000 24.889 */
10462 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 },
10463 + /* 115.200 32.000 24.000 */
10464 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 },
10465 + /* 120.000 30.000 24.000 */
10466 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 },
10467 + /* 124.800 31.200 24.960 */
10468 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 },
10469 + /* 128.000 32.000 24.000 */
10470 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 },
10471 + /* 132.000 33.000 24.750 */
10472 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 },
10473 + /* 136.000 32.640 24.727 */
10474 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 },
10475 + /* 140.000 30.000 24.706 */
10476 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 },
10477 + /* 144.000 30.857 24.686 */
10478 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 },
10479 + /* 150.857 33.000 24.000 */
10480 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 },
10481 + /* 152.000 32.571 24.000 */
10482 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 },
10483 + /* 156.000 31.200 24.960 */
10484 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 },
10485 + /* 160.000 32.000 24.000 */
10486 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 },
10487 + /* 163.200 32.640 24.727 */
10488 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 },
10489 + /* 168.000 32.000 24.889 */
10490 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 },
10491 + /* 176.000 33.000 24.000 */
10492 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 },
10493 + };
10494 +
10495 + /* PLL configuration: type 3 */
10496 + typedef struct {
10497 + uint32 mipsclock;
10498 + uint16 n;
10499 + uint32 m2; /* that is the clockcontrol_m2 */
10500 + } type3_table_t;
10501 + static type3_table_t type3_table[] = {
10502 + /* for 5350, mips clock is always double sb clock */
10503 + { 150000000, 0x311, 0x4020005 },
10504 + { 200000000, 0x311, 0x4020003 },
10505 + };
10506 +
10507 + /* PLL configuration: type 2, 4, 7 */
10508 + typedef struct {
10509 + uint32 mipsclock;
10510 + uint32 sbclock;
10511 + uint16 n;
10512 + uint32 sb;
10513 + uint32 pci33;
10514 + uint32 m2;
10515 + uint32 m3;
10516 + uint32 ratio_cfg;
10517 + uint32 ratio_parm;
10518 + uint32 d11_r1;
10519 + uint32 d11_r2;
10520 + } n4m_table_t;
10521 + static n4m_table_t BCMINITDATA(type2_table)[] = {
10522 + { 120000000, 60000000, 0x0303, 0x01000200, 0x01000600, 0x01000200, 0x05000200, 11,
10523 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10524 + { 150000000, 75000000, 0x0303, 0x01000100, 0x01000600, 0x01000100, 0x05000100, 11,
10525 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10526 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8,
10527 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10528 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11,
10529 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10530 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11,
10531 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10532 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10533 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10534 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10535 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10536 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10537 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10538 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8,
10539 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10540 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10541 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10542 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11,
10543 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10544 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11,
10545 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10546 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10547 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10548 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10549 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10550 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10551 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10552 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10553 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10554 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10555 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10556 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01010100, 0x05000100, 8,
10557 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10558 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01010100, 0x05000100, 11,
10559 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10560 + { 330000000, 132000000, 0x0903, 0x01000200, 0x00020200, 0x01010100, 0x05000100, 0,
10561 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10562 + { 330000000, 146666666, 0x0903, 0x01010000, 0x00020200, 0x01010100, 0x05000100, 0,
10563 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10564 + { 330000000, 165000000, 0x0903, 0x01000100, 0x00020200, 0x01010100, 0x05000100, 0,
10565 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10566 + { 360000000, 120000000, 0x0a03, 0x01000300, 0x00010201, 0x01010200, 0x05000100, 0,
10567 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10568 + { 360000000, 144000000, 0x0a03, 0x01000200, 0x00010201, 0x01010200, 0x05000100, 0,
10569 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10570 + { 360000000, 160000000, 0x0a03, 0x01010000, 0x00010201, 0x01010200, 0x05000100, 0,
10571 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10572 + { 360000000, 180000000, 0x0a03, 0x01000100, 0x00010201, 0x01010200, 0x05000100, 0,
10573 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10574 + { 390000000, 130000000, 0x0b03, 0x01010100, 0x00020101, 0x01020100, 0x05000100, 0,
10575 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10576 + { 390000000, 156000000, 0x0b03, 0x01000200, 0x00020101, 0x01020100, 0x05000100, 0,
10577 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10578 + { 390000000, 173000000, 0x0b03, 0x01010000, 0x00020101, 0x01020100, 0x05000100, 0,
10579 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10580 + { 390000000, 195000000, 0x0b03, 0x01000100, 0x00020101, 0x01020100, 0x05000100, 0,
10581 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10582 + };
10583 + static n4m_table_t BCMINITDATA(type4_table)[] = {
10584 + { 120000000, 60000000, 0x0009, 0x11020009, 0x01030203, 0x11020009, 0x04000009, 11,
10585 + 0x0aaa0555 },
10586 + { 150000000, 75000000, 0x0009, 0x11050002, 0x01030203, 0x11050002, 0x04000005, 11,
10587 + 0x0aaa0555 },
10588 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10589 + 0x0aaa0555 },
10590 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11,
10591 + 0x0aaa0555 },
10592 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10593 + 0x0aaa0555 },
10594 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10595 + 0x0aaa0555 },
10596 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11,
10597 + 0x0aaa0555 },
10598 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10599 + 0x0aaa0555 },
10600 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10601 + 0x0aaa0555 },
10602 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11,
10603 + 0x0aaa0555 },
10604 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8,
10605 + 0x012a00a9 },
10606 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10607 + 0x0aaa0555 },
10608 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13,
10609 + 0x254a14a9 },
10610 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11,
10611 + 0x0aaa0555 },
10612 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9,
10613 + 0x02520129 },
10614 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10615 + 0x0aaa0555 },
10616 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10617 + 0x0aaa0555 },
10618 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13,
10619 + 0x254a14a9 },
10620 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10621 + 0x254a14a9 },
10622 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10623 + 0x254a14a9 },
10624 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9,
10625 + 0x02520129 },
10626 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11,
10627 + 0x0aaa0555 }
10628 + };
10629 + static n4m_table_t BCMINITDATA(type7_table)[] = {
10630 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10631 + 0x0aaa0555 },
10632 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10633 + 0x0aaa0555 },
10634 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10635 + 0x0aaa0555 },
10636 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11,
10637 + 0x0aaa0555 },
10638 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10639 + 0x0aaa0555 },
10640 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10641 + 0x0aaa0555 },
10642 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10643 + 0x0aaa0555 },
10644 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11,
10645 + 0x0aaa0555 },
10646 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10647 + 0x0aaa0555 },
10648 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10649 + 0x0aaa0555 },
10650 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10651 + 0x0aaa0555 },
10652 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10653 + 0x0aaa0555 },
10654 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11,
10655 + 0x0aaa0555 },
10656 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11,
10657 + 0x0aaa0555 }
10658 + };
10659 +
10660 + ulong start, end, dst;
10661 + bool ret = FALSE;
10662 +
10663 + volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008;
10664 + volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010;
10665 + volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018;
10666 +
10667 + /* get index of the current core */
10668 + idx = sb_coreidx(sbh);
10669 + clockcontrol_m2 = NULL;
10670 +
10671 + /* switch to extif or chipc core */
10672 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10673 + pll_type = PLL_TYPE1;
10674 + clockcontrol_n = &eir->clockcontrol_n;
10675 + clockcontrol_sb = &eir->clockcontrol_sb;
10676 + clockcontrol_pci = &eir->clockcontrol_pci;
10677 + clockcontrol_m2 = &cc->clockcontrol_m2;
10678 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10679 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10680 + if (pll_type == PLL_TYPE6) {
10681 + clockcontrol_n = NULL;
10682 + clockcontrol_sb = NULL;
10683 + clockcontrol_pci = NULL;
10684 + } else {
10685 + clockcontrol_n = &cc->clockcontrol_n;
10686 + clockcontrol_sb = &cc->clockcontrol_sb;
10687 + clockcontrol_pci = &cc->clockcontrol_pci;
10688 + clockcontrol_m2 = &cc->clockcontrol_m2;
10689 + }
10690 + } else
10691 + goto done;
10692 +
10693 + if (pll_type == PLL_TYPE6) {
10694 + /* Silence compilers */
10695 + orig_n = orig_sb = orig_pci = 0;
10696 + } else {
10697 + /* Store the current clock register values */
10698 + orig_n = R_REG(osh, clockcontrol_n);
10699 + orig_sb = R_REG(osh, clockcontrol_sb);
10700 + orig_pci = R_REG(osh, clockcontrol_pci);
10701 + }
10702 +
10703 + if (pll_type == PLL_TYPE1) {
10704 + /* Keep the current PCI clock if not specified */
10705 + if (pciclock == 0) {
10706 + pciclock = sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n),
10707 + R_REG(osh, clockcontrol_pci));
10708 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
10709 + }
10710 +
10711 + /* Search for the closest MIPS clock less than or equal to a preferred value */
10712 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
10713 + ASSERT(type1_table[i].mipsclock ==
10714 + sb_clock_rate(pll_type, type1_table[i].n,
10715 + type1_table[i].sb));
10716 + if (type1_table[i].mipsclock > mipsclock)
10717 + break;
10718 + }
10719 + if (i == 0) {
10720 + ret = FALSE;
10721 + goto done;
10722 + } else {
10723 + ret = TRUE;
10724 + i--;
10725 + }
10726 + ASSERT(type1_table[i].mipsclock <= mipsclock);
10727 +
10728 + /* No PLL change */
10729 + if ((orig_n == type1_table[i].n) &&
10730 + (orig_sb == type1_table[i].sb) &&
10731 + (orig_pci == type1_table[i].pci33))
10732 + goto done;
10733 +
10734 + /* Set the PLL controls */
10735 + W_REG(osh, clockcontrol_n, type1_table[i].n);
10736 + W_REG(osh, clockcontrol_sb, type1_table[i].sb);
10737 + if (pciclock == 25000000)
10738 + W_REG(osh, clockcontrol_pci, type1_table[i].pci25);
10739 + else
10740 + W_REG(osh, clockcontrol_pci, type1_table[i].pci33);
10741 +
10742 + /* Reset */
10743 + sb_watchdog(sbh, 1);
10744 + while (1);
10745 + } else if (pll_type == PLL_TYPE3) {
10746 + /* 5350 */
10747 + if (sb_chip(sbh) != BCM5365_CHIP_ID) {
10748 + /*
10749 + * Search for the closest MIPS clock less than or equal to
10750 + * a preferred value.
10751 + */
10752 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
10753 + if (type3_table[i].mipsclock > mipsclock)
10754 + break;
10755 + }
10756 + if (i == 0) {
10757 + ret = FALSE;
10758 + goto done;
10759 + } else {
10760 + ret = TRUE;
10761 + i--;
10762 + }
10763 + ASSERT(type3_table[i].mipsclock <= mipsclock);
10764 +
10765 + /* No PLL change */
10766 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10767 + if ((orig_n == type3_table[i].n) &&
10768 + (orig_m2 == type3_table[i].m2)) {
10769 + goto done;
10770 + }
10771 +
10772 + /* Set the PLL controls */
10773 + W_REG(osh, clockcontrol_n, type3_table[i].n);
10774 + W_REG(osh, clockcontrol_m2, type3_table[i].m2);
10775 +
10776 + /* Reset */
10777 + sb_watchdog(sbh, 1);
10778 + while (1);
10779 + }
10780 + } else if ((pll_type == PLL_TYPE2) ||
10781 + (pll_type == PLL_TYPE4) ||
10782 + (pll_type == PLL_TYPE6) ||
10783 + (pll_type == PLL_TYPE7)) {
10784 + n4m_table_t *table = NULL, *te;
10785 + uint tabsz = 0;
10786 +
10787 + ASSERT(cc);
10788 +
10789 + orig_mips = R_REG(osh, &cc->clockcontrol_m3);
10790 +
10791 + switch (pll_type) {
10792 + case PLL_TYPE6: {
10793 + uint32 new_mips = 0;
10794 +
10795 + ret = TRUE;
10796 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
10797 + new_mips = CC_T6_MMASK;
10798 +
10799 + if (orig_mips == new_mips)
10800 + goto done;
10801 +
10802 + W_REG(osh, &cc->clockcontrol_m3, new_mips);
10803 + goto end_fill;
10804 + }
10805 + case PLL_TYPE2:
10806 + table = type2_table;
10807 + tabsz = ARRAYSIZE(type2_table);
10808 + break;
10809 + case PLL_TYPE4:
10810 + table = type4_table;
10811 + tabsz = ARRAYSIZE(type4_table);
10812 + break;
10813 + case PLL_TYPE7:
10814 + table = type7_table;
10815 + tabsz = ARRAYSIZE(type7_table);
10816 + break;
10817 + default:
10818 + ASSERT("No table for plltype" == NULL);
10819 + break;
10820 + }
10821 +
10822 + /* Store the current clock register values */
10823 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10824 + orig_ratio_parm = 0;
10825 + orig_ratio_cfg = 0;
10826 +
10827 + /* Look up current ratio */
10828 + for (i = 0; i < tabsz; i++) {
10829 + if ((orig_n == table[i].n) &&
10830 + (orig_sb == table[i].sb) &&
10831 + (orig_pci == table[i].pci33) &&
10832 + (orig_m2 == table[i].m2) &&
10833 + (orig_mips == table[i].m3)) {
10834 + orig_ratio_parm = table[i].ratio_parm;
10835 + orig_ratio_cfg = table[i].ratio_cfg;
10836 + break;
10837 + }
10838 + }
10839 +
10840 + /* Search for the closest MIPS clock greater or equal to a preferred value */
10841 + for (i = 0; i < tabsz; i++) {
10842 + ASSERT(table[i].mipsclock ==
10843 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
10844 + if ((mipsclock <= table[i].mipsclock) &&
10845 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
10846 + break;
10847 + }
10848 + if (i == tabsz) {
10849 + ret = FALSE;
10850 + goto done;
10851 + } else {
10852 + te = &table[i];
10853 + ret = TRUE;
10854 + }
10855 +
10856 + /* No PLL change */
10857 + if ((orig_n == te->n) &&
10858 + (orig_sb == te->sb) &&
10859 + (orig_pci == te->pci33) &&
10860 + (orig_m2 == te->m2) &&
10861 + (orig_mips == te->m3))
10862 + goto done;
10863 +
10864 + /* Set the PLL controls */
10865 + W_REG(osh, clockcontrol_n, te->n);
10866 + W_REG(osh, clockcontrol_sb, te->sb);
10867 + W_REG(osh, clockcontrol_pci, te->pci33);
10868 + W_REG(osh, &cc->clockcontrol_m2, te->m2);
10869 + W_REG(osh, &cc->clockcontrol_m3, te->m3);
10870 +
10871 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
10872 + if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) &&
10873 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
10874 + W_REG(osh, &cc->chipcontrol,
10875 + R_REG(osh, &cc->chipcontrol) | 0x100);
10876 +
10877 + /* No ratio change */
10878 + if (sb_chip(sbh) != BCM4785_CHIP_ID) {
10879 + if (orig_ratio_parm == te->ratio_parm)
10880 + goto end_fill;
10881 + }
10882 +
10883 + /* Preload the code into the cache */
10884 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
10885 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10886 + start = ((ulong) &&start_fill_4785) & ~(ic_lsize - 1);
10887 + end = ((ulong) &&end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - 1);
10888 + }
10889 + else {
10890 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
10891 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
10892 + }
10893 + while (start < end) {
10894 + cache_op(start, Fill_I);
10895 + start += ic_lsize;
10896 + }
10897 +
10898 + /* Copy the handler */
10899 + start = (ulong) &handler;
10900 + end = (ulong) &afterhandler;
10901 + dst = KSEG1ADDR(0x180);
10902 + for (i = 0; i < (end - start); i += 4)
10903 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
10904 +
10905 + /* Preload the handler into the cache one line at a time */
10906 + for (i = 0; i < (end - start); i += ic_lsize)
10907 + cache_op(dst + i, Fill_I);
10908 +
10909 + /* Clear BEV bit */
10910 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
10911 +
10912 + /* Enable interrupts */
10913 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
10914 +
10915 + /* 4785 clock freq change procedures */
10916 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10917 + start_fill_4785:
10918 + /* Switch to async */
10919 + MTC0(C0_BROADCOM, 4, (1 << 22));
10920 +
10921 + /* Set clock ratio in MIPS */
10922 + *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1);
10923 + *dll_r2 = te->d11_r2;
10924 +
10925 + /* Enable new settings in MIPS */
10926 + *dll_r1 = *dll_r1 | 0xc0000000;
10927 +
10928 + /* Set active cfg */
10929 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) | (1 << 3) | 1);
10930 +
10931 + /* Fake soft reset (clock cfg registers not reset) */
10932 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10933 +
10934 + /* Clear active cfg */
10935 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3));
10936 +
10937 + /* set watchdog timer */
10938 + W_REG(osh, &cc->watchdog, 20);
10939 + (void) R_REG(osh, &cc->chipid);
10940 +
10941 + /* wait for timer interrupt */
10942 + __asm__ __volatile__(
10943 + ".set\tmips3\n\t"
10944 + "sync\n\t"
10945 + "wait\n\t"
10946 + ".set\tmips0");
10947 + end_fill_4785:
10948 + while (1);
10949 + }
10950 + /* Generic clock freq change procedures */
10951 + else {
10952 + /* Enable MIPS timer interrupt */
10953 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
10954 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
10955 + ASSERT(mipsr);
10956 + W_REG(osh, &mipsr->intmask, 1);
10957 +
10958 + start_fill:
10959 + /* step 1, set clock ratios */
10960 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
10961 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
10962 +
10963 + /* step 2: program timer intr */
10964 + W_REG(osh, &mipsr->timer, 100);
10965 + (void) R_REG(osh, &mipsr->timer);
10966 +
10967 + /* step 3, switch to async */
10968 + sync_mode = MFC0(C0_BROADCOM, 4);
10969 + MTC0(C0_BROADCOM, 4, 1 << 22);
10970 +
10971 + /* step 4, set cfg active */
10972 + MTC0(C0_BROADCOM, 2, (1 << 3) | 1);
10973 +
10974 + /* steps 5 & 6 */
10975 + __asm__ __volatile__(
10976 + ".set\tmips3\n\t"
10977 + "wait\n\t"
10978 + ".set\tmips0");
10979 +
10980 + /* step 7, clear cfg active */
10981 + MTC0(C0_BROADCOM, 2, 0);
10982 +
10983 + /* Additional Step: set back to orig sync mode */
10984 + MTC0(C0_BROADCOM, 4, sync_mode);
10985 +
10986 + /* step 8, fake soft reset */
10987 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10988 +
10989 + end_fill:
10990 + /* set watchdog timer */
10991 + W_REG(osh, &cc->watchdog, 20);
10992 + (void) R_REG(osh, &cc->chipid);
10993 +
10994 + /* wait for timer interrupt */
10995 + __asm__ __volatile__(
10996 + ".set\tmips3\n\t"
10997 + "sync\n\t"
10998 + "wait\n\t"
10999 + ".set\tmips0");
11000 + while (1);
11001 + }
11002 + }
11003 +
11004 +done:
11005 + /* Enable 4785 DLL */
11006 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
11007 + uint32 tmp;
11008 +
11009 + /* set mask to 1e, enable DLL (bit 0) */
11010 + *dll_ctrl |= 0x0041e021;
11011 +
11012 + /* enable aggressive hardware mode */
11013 + *dll_ctrl |= 0x00000080;
11014 +
11015 + /* wait for lock flag to clear */
11016 + while ((*dll_ctrl & 0x2) == 0);
11017 +
11018 + /* clear sticky flags (clear on write 1) */
11019 + tmp = *dll_ctrl;
11020 + *dll_ctrl = tmp;
11021 +
11022 + /* set mask to 5b'10001 */
11023 + *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000;
11024 +
11025 + /* enable sync mode */
11026 + MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff);
11027 + (void)MFC0(C0_BROADCOM, 4);
11028 + }
11029 +
11030 + /* switch back to previous core */
11031 + sb_setcoreidx(sbh, idx);
11032 +
11033 + return ret;
11034 +}
11035 +
11036 +void
11037 +BCMINITFN(enable_pfc)(uint32 mode)
11038 +{
11039 + ulong start, end;
11040 + uint ic_size, ic_lsize;
11041 +
11042 + /* If auto then choose the correct mode for this
11043 + * platform, currently we only ever select one mode
11044 + */
11045 + if (mode == PFC_AUTO)
11046 + mode = PFC_INST;
11047 +
11048 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11049 +
11050 + /* enable prefetch cache if available */
11051 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
11052 + start = ((ulong) &&setpfc_start) & ~(ic_lsize - 1);
11053 + end = ((ulong) &&setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1);
11054 +
11055 + /* Preload setpfc code into the cache one line at a time */
11056 + while (start < end) {
11057 + cache_op(start, Fill_I);
11058 + start += ic_lsize;
11059 + }
11060 +
11061 + /* Now set the pfc */
11062 + setpfc_start:
11063 + /* write range */
11064 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
11065 +
11066 + /* enable */
11067 + *(volatile uint32 *)PFC_CR0 = mode;
11068 + setpfc_end:
11069 + /* Compiler foder */
11070 + ic_size = 0;
11071 + }
11072 +}
11073 +
11074 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11075 +uint32
11076 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
11077 +{
11078 + osl_t *osh;
11079 + sbmemcregs_t *memc;
11080 + uint32 ret = 0;
11081 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11082 + uint idx, rev;
11083 +
11084 + osh = sb_osh(sbh);
11085 +
11086 + idx = sb_coreidx(sbh);
11087 +
11088 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11089 + if (memc == 0)
11090 + goto out;
11091 +
11092 + rev = sb_corerev(sbh);
11093 +
11094 + config = R_REG(osh, &memc->config);
11095 + wr = R_REG(osh, &memc->wrncdlcor);
11096 + rd = R_REG(osh, &memc->rdncdlcor);
11097 + misc = R_REG(osh, &memc->miscdlyctl);
11098 + dqsg = R_REG(osh, &memc->dqsgatencdl);
11099 +
11100 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11101 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11102 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11103 +
11104 + if (config & MEMC_CONFIG_DDR) {
11105 + ret = (wr << 16) | (rd << 8) | dqsg;
11106 + } else {
11107 + if (rev > 0)
11108 + cd = rd;
11109 + else
11110 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11111 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11112 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11113 + ret = (sm << 16) | (sd << 8) | cd;
11114 + }
11115 +
11116 +out:
11117 + /* switch back to previous core */
11118 + sb_setcoreidx(sbh, idx);
11119 +
11120 + return ret;
11121 +}
11122 +
11123 +#if defined(BCMPERFSTATS)
11124 +/*
11125 + * CP0 Register 25 supports 4 semi-independent 32bit performance counters.
11126 + * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?)
11127 + * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters
11128 + * $25 select 6 is the global perf control register.
11129 + */
11130 +/* enable and start instruction counting */
11131 +
11132 +void
11133 +hndmips_perf_instrcount_enable()
11134 +{
11135 + MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */
11136 + MTC0(C0_PERFORMANCE, 4,
11137 + 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instruction counting for counter 0 */
11138 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */
11139 +}
11140 +
11141 +/* enable and start I$ hit and I$ miss counting */
11142 +void
11143 +hndmips_perf_icachecount_enable(void)
11144 +{
11145 + MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */
11146 + MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */
11147 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */
11148 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */
11149 +}
11150 +
11151 +/* enable and start D$ hit and I$ miss counting */
11152 +void
11153 +hndmips_perf_dcachecount_enable(void)
11154 +{
11155 + MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */
11156 + MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */
11157 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */
11158 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */
11159 +}
11160 +
11161 +void
11162 +hndmips_perf_icache_miss_enable()
11163 +{
11164 + MTC0(C0_PERFORMANCE, 4,
11165 + 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */
11166 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */
11167 +}
11168 +
11169 +
11170 +void
11171 +hndmips_perf_icache_hit_enable()
11172 +{
11173 + MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5));
11174 + /* enable cache hits counting for counter 2 */
11175 + MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */
11176 +}
11177 +
11178 +uint32
11179 +hndmips_perf_read_instrcount()
11180 +{
11181 + return -(long)(MFC0(C0_PERFORMANCE, 0));
11182 +}
11183 +
11184 +uint32
11185 +hndmips_perf_read_cache_miss()
11186 +{
11187 + return -(long)(MFC0(C0_PERFORMANCE, 1));
11188 +}
11189 +
11190 +uint32
11191 +hndmips_perf_read_cache_hit()
11192 +{
11193 + return -(long)(MFC0(C0_PERFORMANCE, 2));
11194 +}
11195 +
11196 +#endif /* BCMINTERNAL | BCMPERFSTATS */
11197 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11198 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11199 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-10-02 21:19:59.000000000 +0200
11200 @@ -0,0 +1,768 @@
11201 +/*
11202 + * Low-Level PCI and SB support for BCM47xx
11203 + *
11204 + * Copyright 2006, Broadcom Corporation
11205 + * All Rights Reserved.
11206 + *
11207 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11208 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11209 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11210 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11211 + *
11212 + * $Id: hndpci.c,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
11213 + */
11214 +
11215 +#include <typedefs.h>
11216 +#include <osl.h>
11217 +#include <pcicfg.h>
11218 +#include <bcmdevs.h>
11219 +#include <sbconfig.h>
11220 +#include <bcmutils.h>
11221 +#include <sbutils.h>
11222 +#include <sbpci.h>
11223 +#include <bcmendian.h>
11224 +#include <bcmnvram.h>
11225 +#include <hndcpu.h>
11226 +#include <hndmips.h>
11227 +#include <hndpci.h>
11228 +
11229 +/* debug/trace */
11230 +#ifdef BCMDBG_PCI
11231 +#define PCI_MSG(args) printf args
11232 +#else
11233 +#define PCI_MSG(args)
11234 +#endif /* BCMDBG_PCI */
11235 +
11236 +/* Can free sbpci_init() memory after boot */
11237 +#ifndef linux
11238 +#define __init
11239 +#endif /* linux */
11240 +
11241 +/* Emulated configuration space */
11242 +typedef struct {
11243 + int n;
11244 + uint size0;
11245 + uint size1;
11246 + uint size2;
11247 + uint size3;
11248 +} sb_bar_cfg_t;
11249 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11250 +static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
11251 +
11252 +/* Links to emulated and real PCI configuration spaces */
11253 +#define MAXFUNCS 2
11254 +typedef struct {
11255 + pci_config_regs *emu; /* emulated PCI config */
11256 + pci_config_regs *pci; /* real PCI config */
11257 + sb_bar_cfg_t *bar; /* region sizes */
11258 +} sb_pci_cfg_t;
11259 +static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
11260 +
11261 +/* Special emulated config space for non-existing device */
11262 +static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
11263 +
11264 +/* Banned cores */
11265 +static uint16 pci_ban[SB_MAXCORES] = { 0 };
11266 +static uint pci_banned = 0;
11267 +
11268 +/* CardBus mode */
11269 +static bool cardbus = FALSE;
11270 +
11271 +/* Disable PCI host core */
11272 +static bool pci_disabled = FALSE;
11273 +
11274 +/* Host bridge slot #, default to 0 */
11275 +static uint8 pci_hbslot = 0;
11276 +
11277 +/* Internal macros */
11278 +#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
11279 +#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
11280 + * access host bridge PCI cfg space
11281 + * from SB
11282 + */
11283 +
11284 +/*
11285 + * Functions for accessing external PCI configuration space
11286 + */
11287 +
11288 +/* Assume one-hot slot wiring */
11289 +#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
11290 +
11291 +static uint32
11292 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
11293 +{
11294 + uint coreidx;
11295 + sbpciregs_t *regs;
11296 + uint32 addr = 0;
11297 + osl_t *osh;
11298 +
11299 + /* CardBusMode supports only one device */
11300 + if (cardbus && dev > 1)
11301 + return 0;
11302 +
11303 + osh = sb_osh(sbh);
11304 +
11305 + coreidx = sb_coreidx(sbh);
11306 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11307 +
11308 + /* Type 0 transaction */
11309 + if (bus == 1) {
11310 + /* Skip unwired slots */
11311 + if (dev < PCI_SLOT_MAX) {
11312 + uint32 win;
11313 +
11314 + /* Slide the PCI window to the appropriate slot */
11315 + win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
11316 + W_REG(osh, &regs->sbtopci1, win);
11317 + addr = SB_PCI_CFG |
11318 + ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
11319 + (func << PCICFG_FUN_SHIFT) |
11320 + (off & ~3);
11321 + }
11322 + } else {
11323 + /* Type 1 transaction */
11324 + W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
11325 + addr = SB_PCI_CFG |
11326 + (bus << PCICFG_BUS_SHIFT) |
11327 + (dev << PCICFG_SLOT_SHIFT) |
11328 + (func << PCICFG_FUN_SHIFT) |
11329 + (off & ~3);
11330 + }
11331 +
11332 + sb_setcoreidx(sbh, coreidx);
11333 +
11334 + return addr;
11335 +}
11336 +
11337 +/*
11338 + * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
11339 + *
11340 + * It returns TRUE to indicate that access to the host bridge's pci config
11341 + * from SB is ok, and values in 'addr' and 'val' are valid.
11342 + *
11343 + * It can only read registers at multiple of 4-bytes. Callers must pick up
11344 + * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
11345 + * the register address where value in 'val' is read.
11346 + */
11347 +static bool
11348 +sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
11349 + uint32 **addr, uint32 *val)
11350 +{
11351 + sbpciregs_t *regs;
11352 + osl_t *osh;
11353 + uint coreidx;
11354 + bool ret = FALSE;
11355 +
11356 + /* sanity check */
11357 + ASSERT(bus == 1);
11358 + ASSERT(dev == pci_hbslot);
11359 + ASSERT(func == 0);
11360 +
11361 + osh = sb_osh(sbh);
11362 +
11363 + /* read pci config when core rev >= 8 */
11364 + coreidx = sb_coreidx(sbh);
11365 + regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
11366 + if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
11367 + *addr = (uint32 *)&regs->pcicfg[func][off >> 2];
11368 + *val = R_REG(osh, *addr);
11369 + ret = TRUE;
11370 + }
11371 + sb_setcoreidx(sbh, coreidx);
11372 +
11373 + return ret;
11374 +}
11375 +
11376 +int
11377 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11378 +{
11379 + uint32 addr = 0, *reg = NULL, val;
11380 + int ret = 0;
11381 +
11382 + /*
11383 + * Set value to -1 when:
11384 + * flag 'pci_disabled' is true;
11385 + * value of 'addr' is zero;
11386 + * REG_MAP() fails;
11387 + * BUSPROBE() fails;
11388 + */
11389 + if (pci_disabled)
11390 + val = 0xffffffff;
11391 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11392 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11393 + ;
11394 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11395 + ((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
11396 + (BUSPROBE(val, reg) != 0))
11397 + val = 0xffffffff;
11398 +
11399 + PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
11400 + __FUNCTION__, val, reg, addr, len, off, buf));
11401 +
11402 + val >>= 8 * (off & 3);
11403 + if (len == 4)
11404 + *((uint32 *) buf) = val;
11405 + else if (len == 2)
11406 + *((uint16 *) buf) = (uint16) val;
11407 + else if (len == 1)
11408 + *((uint8 *) buf) = (uint8) val;
11409 + else
11410 + ret = -1;
11411 +
11412 + if (reg && addr)
11413 + REG_UNMAP(reg);
11414 +
11415 + return ret;
11416 +}
11417 +
11418 +int
11419 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11420 +{
11421 + osl_t *osh;
11422 + uint32 addr = 0, *reg = NULL, val;
11423 + int ret = 0;
11424 +
11425 + osh = sb_osh(sbh);
11426 +
11427 + /*
11428 + * Ignore write attempt when:
11429 + * flag 'pci_disabled' is true;
11430 + * value of 'addr' is zero;
11431 + * REG_MAP() fails;
11432 + * BUSPROBE() fails;
11433 + */
11434 + if (pci_disabled)
11435 + return 0;
11436 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11437 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11438 + ;
11439 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11440 + ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
11441 + (BUSPROBE(val, reg) != 0))
11442 + goto done;
11443 +
11444 + if (len == 4)
11445 + val = *((uint32 *) buf);
11446 + else if (len == 2) {
11447 + val &= ~(0xffff << (8 * (off & 3)));
11448 + val |= *((uint16 *) buf) << (8 * (off & 3));
11449 + } else if (len == 1) {
11450 + val &= ~(0xff << (8 * (off & 3)));
11451 + val |= *((uint8 *) buf) << (8 * (off & 3));
11452 + } else {
11453 + ret = -1;
11454 + goto done;
11455 + }
11456 +
11457 + PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
11458 +
11459 + W_REG(osh, reg, val);
11460 +
11461 +done:
11462 + if (reg && addr)
11463 + REG_UNMAP(reg);
11464 +
11465 + return ret;
11466 +}
11467 +
11468 +/*
11469 + * Must access emulated PCI configuration at these locations even when
11470 + * the real PCI config space exists and is accessible.
11471 + *
11472 + * PCI_CFG_VID (0x00)
11473 + * PCI_CFG_DID (0x02)
11474 + * PCI_CFG_PROGIF (0x09)
11475 + * PCI_CFG_SUBCL (0x0a)
11476 + * PCI_CFG_BASECL (0x0b)
11477 + * PCI_CFG_HDR (0x0e)
11478 + * PCI_CFG_INT (0x3c)
11479 + * PCI_CFG_PIN (0x3d)
11480 + */
11481 +#define FORCE_EMUCFG(off, len) \
11482 + ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
11483 + (off == PCI_CFG_PROGIF) || \
11484 + (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
11485 + (off == PCI_CFG_HDR) || \
11486 + (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
11487 +
11488 +/* Sync the emulation registers and the real PCI config registers. */
11489 +static void
11490 +sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11491 + uint off, uint len)
11492 +{
11493 + osl_t *osh;
11494 + uint oldidx;
11495 +
11496 + ASSERT(cfg);
11497 + ASSERT(cfg->emu);
11498 + ASSERT(cfg->pci);
11499 +
11500 + /* decide if real PCI config register access is necessary */
11501 + if (FORCE_EMUCFG(off, len))
11502 + return;
11503 +
11504 + osh = sb_osh(sbh);
11505 +
11506 + /* access to the real pci config space only when the core is up */
11507 + oldidx = sb_coreidx(sbh);
11508 + sb_setcoreidx(sbh, coreidx);
11509 + if (sb_iscoreup(sbh)) {
11510 + if (len == 4)
11511 + *(uint32 *)((ulong)cfg->emu + off) =
11512 + htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
11513 + else if (len == 2)
11514 + *(uint16 *)((ulong)cfg->emu + off) =
11515 + htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
11516 + else if (len == 1)
11517 + *(uint8 *)((ulong)cfg->emu + off) =
11518 + R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
11519 + }
11520 + sb_setcoreidx(sbh, oldidx);
11521 +}
11522 +
11523 +static void
11524 +sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11525 + uint off, uint len)
11526 +{
11527 + osl_t *osh;
11528 + uint oldidx;
11529 +
11530 + ASSERT(cfg);
11531 + ASSERT(cfg->emu);
11532 + ASSERT(cfg->pci);
11533 +
11534 + osh = sb_osh(sbh);
11535 +
11536 + /* decide if real PCI config register access is necessary */
11537 + if (FORCE_EMUCFG(off, len))
11538 + return;
11539 +
11540 + /* access to the real pci config space only when the core is up */
11541 + oldidx = sb_coreidx(sbh);
11542 + sb_setcoreidx(sbh, coreidx);
11543 + if (sb_iscoreup(sbh)) {
11544 + if (len == 4)
11545 + W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
11546 + ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
11547 + else if (len == 2)
11548 + W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
11549 + ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
11550 + else if (len == 1)
11551 + W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
11552 + *(uint8 *)((ulong)cfg->emu + off));
11553 + }
11554 + sb_setcoreidx(sbh, oldidx);
11555 +}
11556 +
11557 +/*
11558 + * Functions for accessing translated SB configuration space
11559 + */
11560 +static int
11561 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11562 +{
11563 + pci_config_regs *cfg;
11564 +
11565 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11566 + return -1;
11567 + cfg = sb_pci_cfg[dev][func].emu;
11568 +
11569 + ASSERT(ISALIGNED(off, len));
11570 + ASSERT(ISALIGNED((uintptr)buf, len));
11571 +
11572 + /* use special config space if the device does not exist */
11573 + if (!cfg)
11574 + cfg = &sb_pci_null;
11575 + /* sync emulation with real PCI config if necessary */
11576 + else if (sb_pci_cfg[dev][func].pci)
11577 + sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11578 +
11579 + if (len == 4)
11580 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11581 + else if (len == 2)
11582 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11583 + else if (len == 1)
11584 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11585 + else
11586 + return -1;
11587 +
11588 + return 0;
11589 +}
11590 +
11591 +static int
11592 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11593 +{
11594 + uint coreidx;
11595 + void *regs;
11596 + pci_config_regs *cfg;
11597 + osl_t *osh;
11598 + sb_bar_cfg_t *bar;
11599 +
11600 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11601 + return -1;
11602 + cfg = sb_pci_cfg[dev][func].emu;
11603 + if (!cfg)
11604 + return -1;
11605 +
11606 + ASSERT(ISALIGNED(off, len));
11607 + ASSERT(ISALIGNED((uintptr)buf, len));
11608 +
11609 + osh = sb_osh(sbh);
11610 +
11611 + /* Emulate BAR sizing */
11612 + if (off >= OFFSETOF(pci_config_regs, base[0]) &&
11613 + off <= OFFSETOF(pci_config_regs, base[3]) &&
11614 + len == 4 && *((uint32 *) buf) == ~0) {
11615 + coreidx = sb_coreidx(sbh);
11616 + if ((regs = sb_setcoreidx(sbh, dev))) {
11617 + bar = sb_pci_cfg[dev][func].bar;
11618 + /* Highest numbered address match register */
11619 + if (off == OFFSETOF(pci_config_regs, base[0]))
11620 + cfg->base[0] = ~(bar->size0 - 1);
11621 + else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
11622 + cfg->base[1] = ~(bar->size1 - 1);
11623 + else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
11624 + cfg->base[2] = ~(bar->size2 - 1);
11625 + else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
11626 + cfg->base[3] = ~(bar->size3 - 1);
11627 + }
11628 + sb_setcoreidx(sbh, coreidx);
11629 + }
11630 + else if (len == 4)
11631 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11632 + else if (len == 2)
11633 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11634 + else if (len == 1)
11635 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11636 + else
11637 + return -1;
11638 +
11639 + /* sync emulation with real PCI config if necessary */
11640 + if (sb_pci_cfg[dev][func].pci)
11641 + sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11642 +
11643 + return 0;
11644 +}
11645 +
11646 +int
11647 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11648 +{
11649 + if (bus == 0)
11650 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11651 + else
11652 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11653 +}
11654 +
11655 +int
11656 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11657 +{
11658 + if (bus == 0)
11659 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11660 + else
11661 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11662 +}
11663 +
11664 +void
11665 +sbpci_ban(uint16 core)
11666 +{
11667 + if (pci_banned < ARRAYSIZE(pci_ban))
11668 + pci_ban[pci_banned++] = core;
11669 +}
11670 +
11671 +/*
11672 + * Initiliaze PCI core. Return 0 after a successful initialization.
11673 + * Otherwise return -1 to indicate there is no PCI core and return 1
11674 + * to indicate PCI core is disabled.
11675 + */
11676 +int __init
11677 +sbpci_init_pci(sb_t *sbh)
11678 +{
11679 + uint chip, chiprev, chippkg, host;
11680 + uint32 boardflags;
11681 + sbpciregs_t *pci;
11682 + sbconfig_t *sb;
11683 + uint32 val;
11684 + int ret = 0;
11685 + char *hbslot;
11686 + osl_t *osh;
11687 +
11688 + chip = sb_chip(sbh);
11689 + chiprev = sb_chiprev(sbh);
11690 + chippkg = sb_chippkg(sbh);
11691 +
11692 + osh = sb_osh(sbh);
11693 +
11694 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11695 + printk("PCI: no core\n");
11696 + pci_disabled = TRUE;
11697 + return -1;
11698 + }
11699 +
11700 + if ((chip == 0x4310) && (chiprev == 0))
11701 + pci_disabled = TRUE;
11702 +
11703 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11704 +
11705 + boardflags = (uint32) getintvar(NULL, "boardflags");
11706 +
11707 + /*
11708 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11709 + * PCI is bonded out, some boards may leave the pins
11710 + * floating.
11711 + */
11712 + if (((chip == BCM4712_CHIP_ID) &&
11713 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11714 + (chippkg == BCM4712MID_PKG_ID))) ||
11715 + (boardflags & BFL_NOPCI))
11716 + pci_disabled = TRUE;
11717 +
11718 + /* Enable the core */
11719 + sb_core_reset(sbh, 0, 0);
11720 +
11721 + /*
11722 + * If the PCI core should not be touched (disabled, not bonded
11723 + * out, or pins floating), do not even attempt to access core
11724 + * registers. Otherwise, try to determine if it is in host
11725 + * mode.
11726 + */
11727 + if (pci_disabled)
11728 + host = 0;
11729 + else
11730 + host = !BUSPROBE(val, &pci->control);
11731 +
11732 + if (!host) {
11733 + ret = 1;
11734 +
11735 + /* Disable PCI interrupts in client mode */
11736 + W_REG(osh, &sb->sbintvec, 0);
11737 +
11738 + /* Disable the PCI bridge in client mode */
11739 + sbpci_ban(SB_PCI);
11740 + sb_core_disable(sbh, 0);
11741 +
11742 + printk("PCI: Disabled\n");
11743 + } else {
11744 + printk("PCI: Initializing host\n");
11745 +
11746 + /* Disable PCI SBReqeustTimeout for BCM4785 */
11747 + if (chip == BCM4785_CHIP_ID) {
11748 + AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
11749 + sb_commit(sbh);
11750 + }
11751 +
11752 + /* Reset the external PCI bus and enable the clock */
11753 + W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
11754 + W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
11755 + OSL_DELAY(150); /* delay > 100 us */
11756 + W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
11757 + /* Use internal arbiter and park REQ/GRNT at external master 0 */
11758 + W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
11759 + OSL_DELAY(1); /* delay 1 us */
11760 + if (sb_corerev(sbh) >= 8) {
11761 + val = getintvar(NULL, "parkid");
11762 + ASSERT(val <= PCI_PARKID_LAST);
11763 + OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
11764 + OSL_DELAY(1);
11765 + }
11766 +
11767 + /* Enable CardBusMode */
11768 + cardbus = getintvar(NULL, "cardbus") == 1;
11769 + if (cardbus) {
11770 + printk("PCI: Enabling CardBus\n");
11771 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11772 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
11773 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
11774 + W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
11775 + }
11776 +
11777 + /* 64 MB I/O access window */
11778 + W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
11779 + /* 64 MB configuration access window */
11780 + W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
11781 + /* 1 GB memory access window */
11782 + W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11783 +
11784 + /* Host bridge slot # nvram overwrite */
11785 + if ((hbslot = nvram_get("pcihbslot"))) {
11786 + pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
11787 + ASSERT(pci_hbslot < PCI_MAX_DEVICES);
11788 + }
11789 +
11790 + /* Enable PCI bridge BAR0 prefetch and burst */
11791 + val = 6;
11792 + sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
11793 +
11794 + /* Enable PCI interrupts */
11795 + W_REG(osh, &pci->intmask, PCI_INTA);
11796 + }
11797 +
11798 + return ret;
11799 +}
11800 +
11801 +/*
11802 + * Get the PCI region address and size information.
11803 + */
11804 +static void __init
11805 +sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
11806 +{
11807 + osl_t *osh;
11808 + uint16 coreid;
11809 + void *regs;
11810 + sbconfig_t *sb;
11811 + uint32 base;
11812 +
11813 + osh = sb_osh(sbh);
11814 + coreid = sb_coreid(sbh);
11815 + regs = sb_coreregs(sbh);
11816 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11817 +
11818 + switch (coreid) {
11819 + case SB_USB20H:
11820 + base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11821 +
11822 + cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
11823 + cfg->base[1] = 0;
11824 + cfg->base[2] = 0;
11825 + cfg->base[3] = 0;
11826 + cfg->base[4] = 0;
11827 + cfg->base[5] = 0;
11828 + bar->n = 1;
11829 + bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
11830 + bar->size1 = 0;
11831 + bar->size2 = 0;
11832 + bar->size3 = 0;
11833 + break;
11834 + default:
11835 + cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11836 + cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
11837 + cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
11838 + cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
11839 + cfg->base[4] = 0;
11840 + cfg->base[5] = 0;
11841 + bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11842 + bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
11843 + bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
11844 + bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
11845 + bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
11846 + break;
11847 + }
11848 +}
11849 +
11850 +/*
11851 + * Construct PCI config spaces for SB cores so that they
11852 + * can be accessed as if they were PCI devices.
11853 + */
11854 +static void __init
11855 +sbpci_init_cores(sb_t *sbh)
11856 +{
11857 + uint chiprev, coreidx, i;
11858 + sbconfig_t *sb;
11859 + pci_config_regs *cfg, *pci;
11860 + sb_bar_cfg_t *bar;
11861 + void *regs;
11862 + osl_t *osh;
11863 + uint16 vendor, device;
11864 + uint16 coreid;
11865 + uint8 class, subclass, progif;
11866 + uint dev;
11867 + uint8 header;
11868 + uint func;
11869 +
11870 + chiprev = sb_chiprev(sbh);
11871 + coreidx = sb_coreidx(sbh);
11872 +
11873 + osh = sb_osh(sbh);
11874 +
11875 + /* Scan the SB bus */
11876 + bzero(sb_config_regs, sizeof(sb_config_regs));
11877 + bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
11878 + bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
11879 + memset(&sb_pci_null, -1, sizeof(sb_pci_null));
11880 + cfg = sb_config_regs;
11881 + bar = sb_bar_cfg;
11882 + for (dev = 0; dev < SB_MAXCORES; dev ++) {
11883 + /* Check if the core exists */
11884 + if (!(regs = sb_setcoreidx(sbh, dev)))
11885 + continue;
11886 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11887 +
11888 + /* Check if this core is banned */
11889 + coreid = sb_coreid(sbh);
11890 + for (i = 0; i < pci_banned; i++)
11891 + if (coreid == pci_ban[i])
11892 + break;
11893 + if (i < pci_banned)
11894 + continue;
11895 +
11896 + for (func = 0; func < MAXFUNCS; ++func) {
11897 + /* Make sure we won't go beyond the limit */
11898 + if (cfg >= &sb_config_regs[SB_MAXCORES]) {
11899 + printk("PCI: too many emulated devices\n");
11900 + goto done;
11901 + }
11902 +
11903 + /* Convert core id to pci id */
11904 + if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
11905 + &progif, &header))
11906 + continue;
11907 +
11908 + /*
11909 + * Differentiate real PCI config from emulated.
11910 + * non zero 'pci' indicate there is a real PCI config space
11911 + * for this device.
11912 + */
11913 + switch (device) {
11914 + case BCM47XX_GIGETH_ID:
11915 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11916 + break;
11917 + case BCM47XX_SATAXOR_ID:
11918 + pci = (pci_config_regs *)((uint32)regs + 0x400);
11919 + break;
11920 + case BCM47XX_ATA100_ID:
11921 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11922 + break;
11923 + default:
11924 + pci = NULL;
11925 + break;
11926 + }
11927 + /* Supported translations */
11928 + cfg->vendor = htol16(vendor);
11929 + cfg->device = htol16(device);
11930 + cfg->rev_id = chiprev;
11931 + cfg->prog_if = progif;
11932 + cfg->sub_class = subclass;
11933 + cfg->base_class = class;
11934 + cfg->header_type = header;
11935 + sbpci_init_regions(sbh, func, cfg, bar);
11936 + /* Save core interrupt flag */
11937 + cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
11938 + /* Save core interrupt assignment */
11939 + cfg->int_line = sb_irq(sbh);
11940 + /* Indicate there is no SROM */
11941 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11942 +
11943 + /* Point to the PCI config spaces */
11944 + sb_pci_cfg[dev][func].emu = cfg;
11945 + sb_pci_cfg[dev][func].pci = pci;
11946 + sb_pci_cfg[dev][func].bar = bar;
11947 + cfg ++;
11948 + bar ++;
11949 + }
11950 + }
11951 +
11952 +done:
11953 + sb_setcoreidx(sbh, coreidx);
11954 +}
11955 +
11956 +/*
11957 + * Initialize PCI core and construct PCI config spaces for SB cores.
11958 + * Must propagate sbpci_init_pci() return value to the caller to let
11959 + * them know the PCI core initialization status.
11960 + */
11961 +int __init
11962 +sbpci_init(sb_t *sbh)
11963 +{
11964 + int status = sbpci_init_pci(sbh);
11965 + sbpci_init_cores(sbh);
11966 + return status;
11967 +}
11968 +
11969 diff -urN linux.old/arch/mips/bcm947xx/sbutils.c linux.dev/arch/mips/bcm947xx/sbutils.c
11970 --- linux.old/arch/mips/bcm947xx/sbutils.c 1970-01-01 01:00:00.000000000 +0100
11971 +++ linux.dev/arch/mips/bcm947xx/sbutils.c 2006-10-02 21:19:59.000000000 +0200
11972 @@ -0,0 +1,3081 @@
11973 +/*
11974 + * Misc utility routines for accessing chip-specific features
11975 + * of the SiliconBackplane-based Broadcom chips.
11976 + *
11977 + * Copyright 2006, Broadcom Corporation
11978 + * All Rights Reserved.
11979 + *
11980 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11981 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11982 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11983 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11984 + * $Id: sbutils.c,v 1.10 2006/04/08 07:12:42 honor Exp $
11985 + */
11986 +
11987 +#include <typedefs.h>
11988 +#include <bcmdefs.h>
11989 +#include <osl.h>
11990 +#include <bcmutils.h>
11991 +#include <sbutils.h>
11992 +#include <bcmdevs.h>
11993 +#include <sbconfig.h>
11994 +#include <sbchipc.h>
11995 +#include <sbpci.h>
11996 +#include <sbpcie.h>
11997 +#include <pcicfg.h>
11998 +#include <sbpcmcia.h>
11999 +#include <sbextif.h>
12000 +#include <sbsocram.h>
12001 +#include <bcmsrom.h>
12002 +#ifdef __mips__
12003 +#include <mipsinc.h>
12004 +#endif /* __mips__ */
12005 +
12006 +/* debug/trace */
12007 +#define SB_ERROR(args)
12008 +
12009 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12010 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12011 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12012 +
12013 +/* misc sb info needed by some of the routines */
12014 +typedef struct sb_info {
12015 +
12016 + struct sb_pub sb; /* back plane public state (must be first field) */
12017 +
12018 + void *osh; /* osl os handle */
12019 + void *sdh; /* bcmsdh handle */
12020 +
12021 + void *curmap; /* current regs va */
12022 + void *regs[SB_MAXCORES]; /* other regs va */
12023 +
12024 + uint curidx; /* current core index */
12025 + uint dev_coreid; /* the core provides driver functions */
12026 +
12027 + bool memseg; /* flag to toggle MEM_SEG register */
12028 +
12029 + uint gpioidx; /* gpio control core index */
12030 + uint gpioid; /* gpio control coretype */
12031 +
12032 + uint numcores; /* # discovered cores */
12033 + uint coreid[SB_MAXCORES]; /* id of each core */
12034 +
12035 + void *intr_arg; /* interrupt callback function arg */
12036 + sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
12037 + sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
12038 + sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
12039 +
12040 +} sb_info_t;
12041 +
12042 +/* local prototypes */
12043 +static sb_info_t * sb_doattach(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12044 + uint bustype, void *sdh, char **vars, uint *varsz);
12045 +static void sb_scan(sb_info_t *si);
12046 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12047 +static uint _sb_coreidx(sb_info_t *si);
12048 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12049 +static uint sb_pcidev2chip(uint pcidev);
12050 +static uint sb_chip2numcores(uint chip);
12051 +static bool sb_ispcie(sb_info_t *si);
12052 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12053 +static int sb_pci_fixcfg(sb_info_t *si);
12054 +
12055 +/* routines to access mdio slave device registers */
12056 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12057 +static void sb_war30841(sb_info_t *si);
12058 +
12059 +/* delay needed between the mdio control/ mdiodata register data access */
12060 +#define PR28829_DELAY() OSL_DELAY(10)
12061 +
12062 +/* size that can take bitfielddump */
12063 +#define BITFIELD_DUMP_SIZE 32
12064 +
12065 +/* global variable to indicate reservation/release of gpio's */
12066 +static uint32 sb_gpioreservation = 0;
12067 +
12068 +#define SB_INFO(sbh) (sb_info_t*)sbh
12069 +#define SET_SBREG(si, r, mask, val) \
12070 + W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val)))
12071 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \
12072 + ISALIGNED((x), SB_CORE_SIZE))
12073 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12074 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12075 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12076 +#define BADIDX (SB_MAXCORES+1)
12077 +#define NOREV -1 /* Invalid rev */
12078 +
12079 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12080 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12081 +
12082 +/* sonicsrev */
12083 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12084 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12085 +
12086 +#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr))
12087 +#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v))
12088 +#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v)))
12089 +#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v)))
12090 +
12091 +/*
12092 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12093 + * after core switching to avoid invalid register accesss inside ISR.
12094 + */
12095 +#define INTR_OFF(si, intr_val) \
12096 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12097 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12098 +#define INTR_RESTORE(si, intr_val) \
12099 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12100 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12101 +
12102 +/* dynamic clock control defines */
12103 +#define LPOMINFREQ 25000 /* low power oscillator min */
12104 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12105 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12106 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12107 +#define PCIMINFREQ 25000000 /* 25 MHz */
12108 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12109 +
12110 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12111 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12112 +
12113 +/* different register spaces to access thr'u pcie indirect access */
12114 +#define PCIE_CONFIGREGS 1 /* Access to config space */
12115 +#define PCIE_PCIEREGS 2 /* Access to pcie registers */
12116 +
12117 +/* GPIO Based LED powersave defines */
12118 +#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
12119 +#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
12120 +
12121 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12122 +
12123 +static uint32
12124 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12125 +{
12126 + uint8 tmp;
12127 + uint32 val, intr_val = 0;
12128 +
12129 +
12130 + /*
12131 + * compact flash only has 11 bits address, while we needs 12 bits address.
12132 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12133 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12134 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12135 + */
12136 + if (si->memseg) {
12137 + INTR_OFF(si, intr_val);
12138 + tmp = 1;
12139 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12140 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12141 + }
12142 +
12143 + val = R_REG(si->osh, sbr);
12144 +
12145 + if (si->memseg) {
12146 + tmp = 0;
12147 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12148 + INTR_RESTORE(si, intr_val);
12149 + }
12150 +
12151 + return (val);
12152 +}
12153 +
12154 +static void
12155 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12156 +{
12157 + uint8 tmp;
12158 + volatile uint32 dummy;
12159 + uint32 intr_val = 0;
12160 +
12161 +
12162 + /*
12163 + * compact flash only has 11 bits address, while we needs 12 bits address.
12164 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12165 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12166 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12167 + */
12168 + if (si->memseg) {
12169 + INTR_OFF(si, intr_val);
12170 + tmp = 1;
12171 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12172 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12173 + }
12174 +
12175 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12176 +#ifdef IL_BIGENDIAN
12177 + dummy = R_REG(si->osh, sbr);
12178 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12179 + dummy = R_REG(si->osh, sbr);
12180 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12181 +#else
12182 + dummy = R_REG(si->osh, sbr);
12183 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12184 + dummy = R_REG(si->osh, sbr);
12185 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12186 +#endif /* IL_BIGENDIAN */
12187 + } else
12188 + W_REG(si->osh, sbr, v);
12189 +
12190 + if (si->memseg) {
12191 + tmp = 0;
12192 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12193 + INTR_RESTORE(si, intr_val);
12194 + }
12195 +}
12196 +
12197 +/*
12198 + * Allocate a sb handle.
12199 + * devid - pci device id (used to determine chip#)
12200 + * osh - opaque OS handle
12201 + * regs - virtual address of initial core registers
12202 + * bustype - pci/pcmcia/sb/sdio/etc
12203 + * vars - pointer to a pointer area for "environment" variables
12204 + * varsz - pointer to int to return the size of the vars
12205 + */
12206 +sb_t *
12207 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
12208 + uint bustype, void *sdh, char **vars, uint *varsz)
12209 +{
12210 + sb_info_t *si;
12211 +
12212 + /* alloc sb_info_t */
12213 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
12214 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
12215 + return (NULL);
12216 + }
12217 +
12218 + if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, (uint*)varsz) == NULL) {
12219 + MFREE(osh, si, sizeof(sb_info_t));
12220 + return (NULL);
12221 + }
12222 +
12223 + return (sb_t *)si;
12224 +}
12225 +
12226 +/* Using sb_kattach depends on SB_BUS support, either implicit */
12227 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
12228 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12229 +
12230 +/* global kernel resource */
12231 +static sb_info_t ksi;
12232 +static bool ksi_attached = FALSE;
12233 +
12234 +/* generic kernel variant of sb_attach() */
12235 +sb_t *
12236 +BCMINITFN(sb_kattach)(void)
12237 +{
12238 + osl_t *osh = NULL;
12239 + uint32 *regs;
12240 +
12241 + if (!ksi_attached) {
12242 + uint32 cid;
12243 +
12244 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
12245 + cid = R_REG(osh, (uint32 *)regs);
12246 + if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) &&
12247 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
12248 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
12249 + uint32 *scc, val;
12250 +
12251 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
12252 + val = R_REG(osh, scc);
12253 + SB_ERROR((" initial scc = 0x%x\n", val));
12254 + val |= SCC_SS_XTAL;
12255 + W_REG(osh, scc, val);
12256 + }
12257 +
12258 + if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void*)regs,
12259 + SB_BUS, NULL, NULL, NULL) == NULL) {
12260 + return NULL;
12261 + }
12262 + else
12263 + ksi_attached = TRUE;
12264 + }
12265 +
12266 + return (sb_t *)&ksi;
12267 +}
12268 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12269 +
12270 +static sb_info_t *
12271 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12272 + uint bustype, void *sdh, char **vars, uint *varsz)
12273 +{
12274 + uint origidx;
12275 + chipcregs_t *cc;
12276 + sbconfig_t *sb;
12277 + uint32 w;
12278 +
12279 + ASSERT(GOODREGS(regs));
12280 +
12281 + bzero((uchar*)si, sizeof(sb_info_t));
12282 +
12283 + si->sb.buscoreidx = si->gpioidx = BADIDX;
12284 +
12285 + si->curmap = regs;
12286 + si->sdh = sdh;
12287 + si->osh = osh;
12288 +
12289 + /* check to see if we are a sb core mimic'ing a pci core */
12290 + if (bustype == PCI_BUS) {
12291 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff) {
12292 + SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB "
12293 + "devid:0x%x\n", __FUNCTION__, devid));
12294 + bustype = SB_BUS;
12295 + }
12296 + }
12297 +
12298 + si->sb.bustype = bustype;
12299 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
12300 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
12301 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
12302 + return NULL;
12303 + }
12304 +
12305 + /* need to set memseg flag for CF card first before any sb registers access */
12306 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
12307 + si->memseg = TRUE;
12308 +
12309 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
12310 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
12311 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
12312 +
12313 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12314 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12315 + if (!GOODCOREADDR(w))
12316 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
12317 + }
12318 +
12319 + /* initialize current core index value */
12320 + si->curidx = _sb_coreidx(si);
12321 +
12322 + if (si->curidx == BADIDX) {
12323 + SB_ERROR(("sb_doattach: bad core index\n"));
12324 + return NULL;
12325 + }
12326 +
12327 + /* get sonics backplane revision */
12328 + sb = REGS2SB(si->curmap);
12329 + si->sb.sonicsrev = (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
12330 +
12331 + /* keep and reuse the initial register mapping */
12332 + origidx = si->curidx;
12333 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12334 + si->regs[origidx] = regs;
12335 +
12336 + /* is core-0 a chipcommon core? */
12337 + si->numcores = 1;
12338 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
12339 + if (sb_coreid(&si->sb) != SB_CC)
12340 + cc = NULL;
12341 +
12342 + /* determine chip id and rev */
12343 + if (cc) {
12344 + /* chip common core found! */
12345 + si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK;
12346 + si->sb.chiprev = (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
12347 + si->sb.chippkg = (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
12348 + } else {
12349 + /* no chip common core -- must convert device id to chip id */
12350 + if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) {
12351 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
12352 + sb_setcoreidx(&si->sb, origidx);
12353 + return NULL;
12354 + }
12355 + }
12356 +
12357 + /* get chipcommon rev */
12358 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
12359 +
12360 + /* determine numcores */
12361 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
12362 + si->numcores = (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
12363 + else
12364 + si->numcores = sb_chip2numcores(si->sb.chip);
12365 +
12366 + /* return to original core */
12367 + sb_setcoreidx(&si->sb, origidx);
12368 +
12369 + /* sanity checks */
12370 + ASSERT(si->sb.chip);
12371 +
12372 + /* scan for cores */
12373 + sb_scan(si);
12374 +
12375 + /* fixup necessary chip/core configurations */
12376 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12377 + if (sb_pci_fixcfg(si)) {
12378 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
12379 + return NULL;
12380 + }
12381 + }
12382 +
12383 + /* srom_var_init() depends on sb_scan() info */
12384 + if (srom_var_init(si, si->sb.bustype, si->curmap, si->osh, vars, varsz)) {
12385 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
12386 + return (NULL);
12387 + }
12388 +
12389 + if (cc == NULL) {
12390 + /*
12391 + * The chip revision number is hardwired into all
12392 + * of the pci function config rev fields and is
12393 + * independent from the individual core revision numbers.
12394 + * For example, the "A0" silicon of each chip is chip rev 0.
12395 + * For PCMCIA we get it from the CIS instead.
12396 + */
12397 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12398 + ASSERT(vars);
12399 + si->sb.chiprev = getintvar(*vars, "chiprev");
12400 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12401 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, sizeof(uint32));
12402 + si->sb.chiprev = w & 0xff;
12403 + } else
12404 + si->sb.chiprev = 0;
12405 + }
12406 +
12407 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12408 + w = getintvar(*vars, "regwindowsz");
12409 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
12410 + }
12411 +
12412 + /* gpio control core is required */
12413 + if (!GOODIDX(si->gpioidx)) {
12414 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
12415 + return NULL;
12416 + }
12417 +
12418 + /* get boardtype and boardrev */
12419 + switch (BUSTYPE(si->sb.bustype)) {
12420 + case PCI_BUS:
12421 + /* do a pci config read to get subsystem id and subvendor id */
12422 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32));
12423 + si->sb.boardvendor = w & 0xffff;
12424 + si->sb.boardtype = (w >> 16) & 0xffff;
12425 + break;
12426 +
12427 + case PCMCIA_BUS:
12428 + case SDIO_BUS:
12429 + si->sb.boardvendor = getintvar(*vars, "manfid");
12430 + si->sb.boardtype = getintvar(*vars, "prodid");
12431 + break;
12432 +
12433 + case SB_BUS:
12434 + case JTAG_BUS:
12435 + si->sb.boardvendor = VENDOR_BROADCOM;
12436 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
12437 + si->sb.boardtype = 0xffff;
12438 + break;
12439 + }
12440 +
12441 + if (si->sb.boardtype == 0) {
12442 + SB_ERROR(("sb_doattach: unknown board type\n"));
12443 + ASSERT(si->sb.boardtype);
12444 + }
12445 +
12446 + /* setup the GPIO based LED powersave register */
12447 + if (si->sb.ccrev >= 16) {
12448 + if ((vars == NULL) || ((w = getintvar(*vars, "leddc")) == 0))
12449 + w = DEFAULT_GPIOTIMERVAL;
12450 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
12451 + }
12452 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1)) {
12453 + /* set proper clk setup delays before forcing HT */
12454 + sb_clkctl_init((void *)si);
12455 + sb_corereg((void*)si, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
12456 + SYCC_HR, SYCC_HR);
12457 + }
12458 +
12459 +
12460 + return (si);
12461 +}
12462 +
12463 +uint
12464 +sb_coreid(sb_t *sbh)
12465 +{
12466 + sb_info_t *si;
12467 + sbconfig_t *sb;
12468 +
12469 + si = SB_INFO(sbh);
12470 + sb = REGS2SB(si->curmap);
12471 +
12472 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
12473 +}
12474 +
12475 +uint
12476 +sb_coreidx(sb_t *sbh)
12477 +{
12478 + sb_info_t *si;
12479 +
12480 + si = SB_INFO(sbh);
12481 + return (si->curidx);
12482 +}
12483 +
12484 +/* return current index of core */
12485 +static uint
12486 +_sb_coreidx(sb_info_t *si)
12487 +{
12488 + sbconfig_t *sb;
12489 + uint32 sbaddr = 0;
12490 +
12491 + ASSERT(si);
12492 +
12493 + switch (BUSTYPE(si->sb.bustype)) {
12494 + case SB_BUS:
12495 + sb = REGS2SB(si->curmap);
12496 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
12497 + break;
12498 +
12499 + case PCI_BUS:
12500 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12501 + break;
12502 +
12503 + case PCMCIA_BUS: {
12504 + uint8 tmp = 0;
12505 +
12506 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
12507 + sbaddr = (uint)tmp << 12;
12508 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
12509 + sbaddr |= (uint)tmp << 16;
12510 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
12511 + sbaddr |= (uint)tmp << 24;
12512 + break;
12513 + }
12514 +
12515 +#ifdef BCMJTAG
12516 + case JTAG_BUS:
12517 + sbaddr = (uint32)si->curmap;
12518 + break;
12519 +#endif /* BCMJTAG */
12520 +
12521 + default:
12522 + ASSERT(0);
12523 + }
12524 +
12525 + if (!GOODCOREADDR(sbaddr))
12526 + return BADIDX;
12527 +
12528 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
12529 +}
12530 +
12531 +uint
12532 +sb_corevendor(sb_t *sbh)
12533 +{
12534 + sb_info_t *si;
12535 + sbconfig_t *sb;
12536 +
12537 + si = SB_INFO(sbh);
12538 + sb = REGS2SB(si->curmap);
12539 +
12540 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
12541 +}
12542 +
12543 +uint
12544 +sb_corerev(sb_t *sbh)
12545 +{
12546 + sb_info_t *si;
12547 + sbconfig_t *sb;
12548 + uint sbidh;
12549 +
12550 + si = SB_INFO(sbh);
12551 + sb = REGS2SB(si->curmap);
12552 + sbidh = R_SBREG(si, &sb->sbidhigh);
12553 +
12554 + return (SBCOREREV(sbidh));
12555 +}
12556 +
12557 +void *
12558 +sb_osh(sb_t *sbh)
12559 +{
12560 + sb_info_t *si;
12561 +
12562 + si = SB_INFO(sbh);
12563 + return si->osh;
12564 +}
12565 +
12566 +void
12567 +sb_setosh(sb_t *sbh, osl_t *osh)
12568 +{
12569 + sb_info_t *si;
12570 +
12571 + si = SB_INFO(sbh);
12572 + if (si->osh != NULL) {
12573 + SB_ERROR(("osh is already set....\n"));
12574 + ASSERT(!si->osh);
12575 + }
12576 + si->osh = osh;
12577 +}
12578 +
12579 +/* set/clear sbtmstatelow core-specific flags */
12580 +uint32
12581 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
12582 +{
12583 + sb_info_t *si;
12584 + sbconfig_t *sb;
12585 + uint32 w;
12586 +
12587 + si = SB_INFO(sbh);
12588 + sb = REGS2SB(si->curmap);
12589 +
12590 + ASSERT((val & ~mask) == 0);
12591 +
12592 + /* mask and set */
12593 + if (mask || val) {
12594 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
12595 + W_SBREG(si, &sb->sbtmstatelow, w);
12596 + }
12597 +
12598 + /* return the new value */
12599 + return (R_SBREG(si, &sb->sbtmstatelow));
12600 +}
12601 +
12602 +/* set/clear sbtmstatehigh core-specific flags */
12603 +uint32
12604 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
12605 +{
12606 + sb_info_t *si;
12607 + sbconfig_t *sb;
12608 + uint32 w;
12609 +
12610 + si = SB_INFO(sbh);
12611 + sb = REGS2SB(si->curmap);
12612 +
12613 + ASSERT((val & ~mask) == 0);
12614 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
12615 +
12616 + /* mask and set */
12617 + if (mask || val) {
12618 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
12619 + W_SBREG(si, &sb->sbtmstatehigh, w);
12620 + }
12621 +
12622 + /* return the new value */
12623 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
12624 +}
12625 +
12626 +/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
12627 +int
12628 +sb_corebist(sb_t *sbh)
12629 +{
12630 + uint32 sblo;
12631 + sb_info_t *si;
12632 + sbconfig_t *sb;
12633 + int result = 0;
12634 +
12635 + si = SB_INFO(sbh);
12636 + sb = REGS2SB(si->curmap);
12637 +
12638 + sblo = R_SBREG(si, &sb->sbtmstatelow);
12639 + W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE));
12640 +
12641 + SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), 100000);
12642 +
12643 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF)
12644 + result = BCME_ERROR;
12645 +
12646 + W_SBREG(si, &sb->sbtmstatelow, sblo);
12647 +
12648 + return result;
12649 +}
12650 +
12651 +bool
12652 +sb_iscoreup(sb_t *sbh)
12653 +{
12654 + sb_info_t *si;
12655 + sbconfig_t *sb;
12656 +
12657 + si = SB_INFO(sbh);
12658 + sb = REGS2SB(si->curmap);
12659 +
12660 + return ((R_SBREG(si, &sb->sbtmstatelow) &
12661 + (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
12662 +}
12663 +
12664 +/*
12665 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
12666 + * switch back to the original core, and return the new value.
12667 + *
12668 + * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
12669 + *
12670 + * Also, when using pci/pcie, we can optimize away the core switching for pci registers
12671 + * and (on newer pci cores) chipcommon registers.
12672 + */
12673 +static uint
12674 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
12675 +{
12676 + uint origidx = 0;
12677 + uint32 *r = NULL;
12678 + uint w;
12679 + uint intr_val = 0;
12680 + bool fast = FALSE;
12681 +
12682 + ASSERT(GOODIDX(coreidx));
12683 + ASSERT(regoff < SB_CORE_SIZE);
12684 + ASSERT((val & ~mask) == 0);
12685 +
12686 +#ifdef notyet
12687 + if (si->sb.bustype == SB_BUS) {
12688 + /* If internal bus, we can always get at everything */
12689 + fast = TRUE;
12690 + r = (uint32 *)((uchar *)si->regs[coreidx] + regoff);
12691 + } else if (si->sb.bustype == PCI_BUS) {
12692 + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
12693 +
12694 + if ((si->coreid[coreidx] == SB_CC) &&
12695 + ((si->sb.buscoretype == SB_PCIE) ||
12696 + (si->sb.buscorerev >= 13))) {
12697 + /* Chipc registers are mapped at 12KB */
12698 +
12699 + fast = TRUE;
12700 + r = (uint32 *)((char *)si->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
12701 + } else if (si->sb.buscoreidx == coreidx) {
12702 + /* pci registers are at either in the last 2KB of an 8KB window
12703 + * or, in pcie and pci rev 13 at 8KB
12704 + */
12705 + fast = TRUE;
12706 + if ((si->sb.buscoretype == SB_PCIE) ||
12707 + (si->sb.buscorerev >= 13))
12708 + r = (uint32 *)((char *)si->curmap +
12709 + PCI_16KB0_PCIREGS_OFFSET + regoff);
12710 + else
12711 + r = (uint32 *)((char *)si->curmap +
12712 + ((regoff >= SBCONFIGOFF) ?
12713 + PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
12714 + regoff);
12715 + }
12716 + }
12717 +#endif /* notyet */
12718 +
12719 + if (!fast) {
12720 + INTR_OFF(si, intr_val);
12721 +
12722 + /* save current core index */
12723 + origidx = sb_coreidx(&si->sb);
12724 +
12725 + /* switch core */
12726 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
12727 + }
12728 + ASSERT(r);
12729 +
12730 + /* mask and set */
12731 + if (mask || val) {
12732 + if (regoff >= SBCONFIGOFF) {
12733 + w = (R_SBREG(si, r) & ~mask) | val;
12734 + W_SBREG(si, r, w);
12735 + } else {
12736 + w = (R_REG(si->osh, r) & ~mask) | val;
12737 + W_REG(si->osh, r, w);
12738 + }
12739 + }
12740 +
12741 + /* readback */
12742 + if (regoff >= SBCONFIGOFF)
12743 + w = R_SBREG(si, r);
12744 + else
12745 + w = R_REG(si->osh, r);
12746 +
12747 + if (!fast) {
12748 + /* restore core index */
12749 + if (origidx != coreidx)
12750 + sb_setcoreidx(&si->sb, origidx);
12751 +
12752 + INTR_RESTORE(si, intr_val);
12753 + }
12754 +
12755 + return (w);
12756 +}
12757 +
12758 +#define DWORD_ALIGN(x) (x & ~(0x03))
12759 +#define BYTE_POS(x) (x & 0x3)
12760 +#define WORD_POS(x) (x & 0x1)
12761 +
12762 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
12763 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
12764 +
12765 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
12766 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
12767 +
12768 +#define read_pci_cfg_byte(a) \
12769 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
12770 +
12771 +#define read_pci_cfg_write(a) \
12772 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
12773 +
12774 +
12775 +/* return TRUE if requested capability exists in the PCI config space */
12776 +static bool
12777 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
12778 +{
12779 + uint8 cap_id;
12780 + uint8 cap_ptr;
12781 + uint32 bufsize;
12782 + uint8 byte_val;
12783 +
12784 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
12785 + return FALSE;
12786 +
12787 + /* check for Header type 0 */
12788 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
12789 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
12790 + return FALSE;
12791 +
12792 + /* check if the capability pointer field exists */
12793 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
12794 + if (!(byte_val & PCI_CAPPTR_PRESENT))
12795 + return FALSE;
12796 +
12797 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
12798 + /* check if the capability pointer is 0x00 */
12799 + if (cap_ptr == 0x00)
12800 + return FALSE;
12801 +
12802 +
12803 + /* loop thr'u the capability list and see if the pcie capabilty exists */
12804 +
12805 + cap_id = read_pci_cfg_byte(cap_ptr);
12806 +
12807 + while (cap_id != req_cap_id) {
12808 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
12809 + if (cap_ptr == 0x00) break;
12810 + cap_id = read_pci_cfg_byte(cap_ptr);
12811 + }
12812 + if (cap_id != req_cap_id) {
12813 + return FALSE;
12814 + }
12815 + /* found the caller requested capability */
12816 + if ((buf != NULL) && (buflen != NULL)) {
12817 + bufsize = *buflen;
12818 + if (!bufsize) goto end;
12819 + *buflen = 0;
12820 + /* copy the cpability data excluding cap ID and next ptr */
12821 + cap_ptr += 2;
12822 + if ((bufsize + cap_ptr) > SZPCR)
12823 + bufsize = SZPCR - cap_ptr;
12824 + *buflen = bufsize;
12825 + while (bufsize--) {
12826 + *buf = read_pci_cfg_byte(cap_ptr);
12827 + cap_ptr++;
12828 + buf++;
12829 + }
12830 + }
12831 +end:
12832 + return TRUE;
12833 +}
12834 +
12835 +/* return TRUE if PCIE capability exists the pci config space */
12836 +static inline bool
12837 +sb_ispcie(sb_info_t *si)
12838 +{
12839 + return (sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
12840 +}
12841 +
12842 +/* scan the sb enumerated space to identify all cores */
12843 +static void
12844 +BCMINITFN(sb_scan)(sb_info_t *si)
12845 +{
12846 + uint origidx;
12847 + uint i;
12848 + bool pci;
12849 + bool pcie;
12850 + uint pciidx;
12851 + uint pcieidx;
12852 + uint pcirev;
12853 + uint pcierev;
12854 +
12855 +
12856 + /* numcores should already be set */
12857 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
12858 +
12859 + /* save current core index */
12860 + origidx = sb_coreidx(&si->sb);
12861 +
12862 + si->sb.buscorerev = NOREV;
12863 + si->sb.buscoreidx = BADIDX;
12864 +
12865 + si->gpioidx = BADIDX;
12866 +
12867 + pci = pcie = FALSE;
12868 + pcirev = pcierev = NOREV;
12869 + pciidx = pcieidx = BADIDX;
12870 +
12871 + for (i = 0; i < si->numcores; i++) {
12872 + sb_setcoreidx(&si->sb, i);
12873 + si->coreid[i] = sb_coreid(&si->sb);
12874 +
12875 + if (si->coreid[i] == SB_PCI) {
12876 + pciidx = i;
12877 + pcirev = sb_corerev(&si->sb);
12878 + pci = TRUE;
12879 + } else if (si->coreid[i] == SB_PCIE) {
12880 + pcieidx = i;
12881 + pcierev = sb_corerev(&si->sb);
12882 + pcie = TRUE;
12883 + } else if (si->coreid[i] == SB_PCMCIA) {
12884 + si->sb.buscorerev = sb_corerev(&si->sb);
12885 + si->sb.buscoretype = si->coreid[i];
12886 + si->sb.buscoreidx = i;
12887 + }
12888 + }
12889 + if (pci && pcie) {
12890 + if (sb_ispcie(si))
12891 + pci = FALSE;
12892 + else
12893 + pcie = FALSE;
12894 + }
12895 + if (pci) {
12896 + si->sb.buscoretype = SB_PCI;
12897 + si->sb.buscorerev = pcirev;
12898 + si->sb.buscoreidx = pciidx;
12899 + } else if (pcie) {
12900 + si->sb.buscoretype = SB_PCIE;
12901 + si->sb.buscorerev = pcierev;
12902 + si->sb.buscoreidx = pcieidx;
12903 + }
12904 +
12905 + /*
12906 + * Find the gpio "controlling core" type and index.
12907 + * Precedence:
12908 + * - if there's a chip common core - use that
12909 + * - else if there's a pci core (rev >= 2) - use that
12910 + * - else there had better be an extif core (4710 only)
12911 + */
12912 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
12913 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
12914 + si->gpioid = SB_CC;
12915 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
12916 + si->gpioidx = si->sb.buscoreidx;
12917 + si->gpioid = SB_PCI;
12918 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
12919 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
12920 + si->gpioid = SB_EXTIF;
12921 + } else
12922 + ASSERT(si->gpioidx != BADIDX);
12923 +
12924 + /* return to original core index */
12925 + sb_setcoreidx(&si->sb, origidx);
12926 +}
12927 +
12928 +/* may be called with core in reset */
12929 +void
12930 +sb_detach(sb_t *sbh)
12931 +{
12932 + sb_info_t *si;
12933 + uint idx;
12934 +
12935 + si = SB_INFO(sbh);
12936 +
12937 + if (si == NULL)
12938 + return;
12939 +
12940 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12941 + for (idx = 0; idx < SB_MAXCORES; idx++)
12942 + if (si->regs[idx]) {
12943 + REG_UNMAP(si->regs[idx]);
12944 + si->regs[idx] = NULL;
12945 + }
12946 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12947 + if (si != &ksi)
12948 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12949 + MFREE(si->osh, si, sizeof(sb_info_t));
12950 +
12951 +}
12952 +
12953 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
12954 +static uint
12955 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
12956 +{
12957 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
12958 + return (BCM4710_CHIP_ID);
12959 + if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID))
12960 + return (BCM4402_CHIP_ID);
12961 + if (pcidev == BCM4401_ENET_ID)
12962 + return (BCM4402_CHIP_ID);
12963 +
12964 + return (0);
12965 +}
12966 +
12967 +/* convert chip number to number of i/o cores */
12968 +static uint
12969 +BCMINITFN(sb_chip2numcores)(uint chip)
12970 +{
12971 + if (chip == BCM4710_CHIP_ID)
12972 + return (9);
12973 + if (chip == BCM4402_CHIP_ID)
12974 + return (3);
12975 + if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
12976 + return (6);
12977 + if (chip == BCM4704_CHIP_ID)
12978 + return (9);
12979 + if (chip == BCM5365_CHIP_ID)
12980 + return (7);
12981 +
12982 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
12983 + ASSERT(0);
12984 + return (1);
12985 +}
12986 +
12987 +/* return index of coreid or BADIDX if not found */
12988 +static uint
12989 +sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit)
12990 +{
12991 + uint found;
12992 + uint i;
12993 +
12994 + found = 0;
12995 +
12996 + for (i = 0; i < si->numcores; i++)
12997 + if (si->coreid[i] == coreid) {
12998 + if (found == coreunit)
12999 + return (i);
13000 + found++;
13001 + }
13002 +
13003 + return (BADIDX);
13004 +}
13005 +
13006 +/*
13007 + * this function changes logical "focus" to the indiciated core,
13008 + * must be called with interrupt off.
13009 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13010 + */
13011 +void*
13012 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13013 +{
13014 + sb_info_t *si;
13015 + uint32 sbaddr;
13016 + uint8 tmp;
13017 +
13018 + si = SB_INFO(sbh);
13019 +
13020 + if (coreidx >= si->numcores)
13021 + return (NULL);
13022 +
13023 + /*
13024 + * If the user has provided an interrupt mask enabled function,
13025 + * then assert interrupts are disabled before switching the core.
13026 + */
13027 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13028 +
13029 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13030 +
13031 + switch (BUSTYPE(si->sb.bustype)) {
13032 + case SB_BUS:
13033 + /* map new one */
13034 + if (!si->regs[coreidx]) {
13035 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13036 + ASSERT(GOODREGS(si->regs[coreidx]));
13037 + }
13038 + si->curmap = si->regs[coreidx];
13039 + break;
13040 +
13041 + case PCI_BUS:
13042 + /* point bar0 window */
13043 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13044 + break;
13045 +
13046 + case PCMCIA_BUS:
13047 + tmp = (sbaddr >> 12) & 0x0f;
13048 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13049 + tmp = (sbaddr >> 16) & 0xff;
13050 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13051 + tmp = (sbaddr >> 24) & 0xff;
13052 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13053 + break;
13054 +#ifdef BCMJTAG
13055 + case JTAG_BUS:
13056 + /* map new one */
13057 + if (!si->regs[coreidx]) {
13058 + si->regs[coreidx] = (void *)sbaddr;
13059 + ASSERT(GOODREGS(si->regs[coreidx]));
13060 + }
13061 + si->curmap = si->regs[coreidx];
13062 + break;
13063 +#endif /* BCMJTAG */
13064 + }
13065 +
13066 + si->curidx = coreidx;
13067 +
13068 + return (si->curmap);
13069 +}
13070 +
13071 +/*
13072 + * this function changes logical "focus" to the indiciated core,
13073 + * must be called with interrupt off.
13074 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13075 + */
13076 +void*
13077 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13078 +{
13079 + sb_info_t *si;
13080 + uint idx;
13081 +
13082 + si = SB_INFO(sbh);
13083 + idx = sb_findcoreidx(si, coreid, coreunit);
13084 + if (!GOODIDX(idx))
13085 + return (NULL);
13086 +
13087 + return (sb_setcoreidx(sbh, idx));
13088 +}
13089 +
13090 +/* return chip number */
13091 +uint
13092 +sb_chip(sb_t *sbh)
13093 +{
13094 + sb_info_t *si;
13095 +
13096 + si = SB_INFO(sbh);
13097 + return (si->sb.chip);
13098 +}
13099 +
13100 +/* return chip revision number */
13101 +uint
13102 +sb_chiprev(sb_t *sbh)
13103 +{
13104 + sb_info_t *si;
13105 +
13106 + si = SB_INFO(sbh);
13107 + return (si->sb.chiprev);
13108 +}
13109 +
13110 +/* return chip common revision number */
13111 +uint
13112 +sb_chipcrev(sb_t *sbh)
13113 +{
13114 + sb_info_t *si;
13115 +
13116 + si = SB_INFO(sbh);
13117 + return (si->sb.ccrev);
13118 +}
13119 +
13120 +/* return chip package option */
13121 +uint
13122 +sb_chippkg(sb_t *sbh)
13123 +{
13124 + sb_info_t *si;
13125 +
13126 + si = SB_INFO(sbh);
13127 + return (si->sb.chippkg);
13128 +}
13129 +
13130 +/* return PCI core rev. */
13131 +uint
13132 +sb_pcirev(sb_t *sbh)
13133 +{
13134 + sb_info_t *si;
13135 +
13136 + si = SB_INFO(sbh);
13137 + return (si->sb.buscorerev);
13138 +}
13139 +
13140 +bool
13141 +BCMINITFN(sb_war16165)(sb_t *sbh)
13142 +{
13143 + sb_info_t *si;
13144 +
13145 + si = SB_INFO(sbh);
13146 +
13147 + return (PCI(si) && (si->sb.buscorerev <= 10));
13148 +}
13149 +
13150 +static void
13151 +BCMINITFN(sb_war30841)(sb_info_t *si)
13152 +{
13153 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13154 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13155 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13156 +}
13157 +
13158 +/* return PCMCIA core rev. */
13159 +uint
13160 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13161 +{
13162 + sb_info_t *si;
13163 +
13164 + si = SB_INFO(sbh);
13165 + return (si->sb.buscorerev);
13166 +}
13167 +
13168 +/* return board vendor id */
13169 +uint
13170 +sb_boardvendor(sb_t *sbh)
13171 +{
13172 + sb_info_t *si;
13173 +
13174 + si = SB_INFO(sbh);
13175 + return (si->sb.boardvendor);
13176 +}
13177 +
13178 +/* return boardtype */
13179 +uint
13180 +sb_boardtype(sb_t *sbh)
13181 +{
13182 + sb_info_t *si;
13183 + char *var;
13184 +
13185 + si = SB_INFO(sbh);
13186 +
13187 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13188 + /* boardtype format is a hex string */
13189 + si->sb.boardtype = getintvar(NULL, "boardtype");
13190 +
13191 + /* backward compatibility for older boardtype string format */
13192 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13193 + if (!strcmp(var, "bcm94710dev"))
13194 + si->sb.boardtype = BCM94710D_BOARD;
13195 + else if (!strcmp(var, "bcm94710ap"))
13196 + si->sb.boardtype = BCM94710AP_BOARD;
13197 + else if (!strcmp(var, "bu4710"))
13198 + si->sb.boardtype = BU4710_BOARD;
13199 + else if (!strcmp(var, "bcm94702mn"))
13200 + si->sb.boardtype = BCM94702MN_BOARD;
13201 + else if (!strcmp(var, "bcm94710r1"))
13202 + si->sb.boardtype = BCM94710R1_BOARD;
13203 + else if (!strcmp(var, "bcm94710r4"))
13204 + si->sb.boardtype = BCM94710R4_BOARD;
13205 + else if (!strcmp(var, "bcm94702cpci"))
13206 + si->sb.boardtype = BCM94702CPCI_BOARD;
13207 + else if (!strcmp(var, "bcm95380_rr"))
13208 + si->sb.boardtype = BCM95380RR_BOARD;
13209 + }
13210 + }
13211 +
13212 + return (si->sb.boardtype);
13213 +}
13214 +
13215 +/* return bus type of sbh device */
13216 +uint
13217 +sb_bus(sb_t *sbh)
13218 +{
13219 + sb_info_t *si;
13220 +
13221 + si = SB_INFO(sbh);
13222 + return (si->sb.bustype);
13223 +}
13224 +
13225 +/* return bus core type */
13226 +uint
13227 +sb_buscoretype(sb_t *sbh)
13228 +{
13229 + sb_info_t *si;
13230 +
13231 + si = SB_INFO(sbh);
13232 +
13233 + return (si->sb.buscoretype);
13234 +}
13235 +
13236 +/* return bus core revision */
13237 +uint
13238 +sb_buscorerev(sb_t *sbh)
13239 +{
13240 + sb_info_t *si;
13241 + si = SB_INFO(sbh);
13242 +
13243 + return (si->sb.buscorerev);
13244 +}
13245 +
13246 +/* return list of found cores */
13247 +uint
13248 +sb_corelist(sb_t *sbh, uint coreid[])
13249 +{
13250 + sb_info_t *si;
13251 +
13252 + si = SB_INFO(sbh);
13253 +
13254 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof(uint)));
13255 + return (si->numcores);
13256 +}
13257 +
13258 +/* return current register mapping */
13259 +void *
13260 +sb_coreregs(sb_t *sbh)
13261 +{
13262 + sb_info_t *si;
13263 +
13264 + si = SB_INFO(sbh);
13265 + ASSERT(GOODREGS(si->curmap));
13266 +
13267 + return (si->curmap);
13268 +}
13269 +
13270 +
13271 +/* do buffered registers update */
13272 +void
13273 +sb_commit(sb_t *sbh)
13274 +{
13275 + sb_info_t *si;
13276 + uint origidx;
13277 + uint intr_val = 0;
13278 +
13279 + si = SB_INFO(sbh);
13280 +
13281 + origidx = si->curidx;
13282 + ASSERT(GOODIDX(origidx));
13283 +
13284 + INTR_OFF(si, intr_val);
13285 +
13286 + /* switch over to chipcommon core if there is one, else use pci */
13287 + if (si->sb.ccrev != NOREV) {
13288 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
13289 +
13290 + /* do the buffer registers update */
13291 + W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT);
13292 + W_REG(si->osh, &ccregs->broadcastdata, 0x0);
13293 + } else if (PCI(si)) {
13294 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
13295 +
13296 + /* do the buffer registers update */
13297 + W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT);
13298 + W_REG(si->osh, &pciregs->bcastdata, 0x0);
13299 + } else
13300 + ASSERT(0);
13301 +
13302 + /* restore core index */
13303 + sb_setcoreidx(sbh, origidx);
13304 + INTR_RESTORE(si, intr_val);
13305 +}
13306 +
13307 +/* reset and re-enable a core
13308 + * inputs:
13309 + * bits - core specific bits that are set during and after reset sequence
13310 + * resetbits - core specific bits that are set only during reset sequence
13311 + */
13312 +void
13313 +sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
13314 +{
13315 + sb_info_t *si;
13316 + sbconfig_t *sb;
13317 + volatile uint32 dummy;
13318 +
13319 + si = SB_INFO(sbh);
13320 + ASSERT(GOODREGS(si->curmap));
13321 + sb = REGS2SB(si->curmap);
13322 +
13323 + /*
13324 + * Must do the disable sequence first to work for arbitrary current core state.
13325 + */
13326 + sb_core_disable(sbh, (bits | resetbits));
13327 +
13328 + /*
13329 + * Now do the initialization sequence.
13330 + */
13331 +
13332 + /* set reset while enabling the clock and forcing them on throughout the core */
13333 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits));
13334 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13335 + OSL_DELAY(1);
13336 +
13337 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
13338 + W_SBREG(si, &sb->sbtmstatehigh, 0);
13339 + }
13340 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
13341 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
13342 + }
13343 +
13344 + /* clear reset and allow it to propagate throughout the core */
13345 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
13346 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13347 + OSL_DELAY(1);
13348 +
13349 + /* leave clock enabled */
13350 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
13351 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13352 + OSL_DELAY(1);
13353 +}
13354 +
13355 +void
13356 +sb_core_tofixup(sb_t *sbh)
13357 +{
13358 + sb_info_t *si;
13359 + sbconfig_t *sb;
13360 +
13361 + si = SB_INFO(sbh);
13362 +
13363 + if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) ||
13364 + (PCI(si) && (si->sb.buscorerev >= 5)))
13365 + return;
13366 +
13367 + ASSERT(GOODREGS(si->curmap));
13368 + sb = REGS2SB(si->curmap);
13369 +
13370 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
13371 + SET_SBREG(si, &sb->sbimconfiglow,
13372 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13373 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
13374 + } else {
13375 + if (sb_coreid(sbh) == SB_PCI) {
13376 + SET_SBREG(si, &sb->sbimconfiglow,
13377 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13378 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13379 + } else {
13380 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
13381 + }
13382 + }
13383 +
13384 + sb_commit(sbh);
13385 +}
13386 +
13387 +/*
13388 + * Set the initiator timeout for the "master core".
13389 + * The master core is defined to be the core in control
13390 + * of the chip and so it issues accesses to non-memory
13391 + * locations (Because of dma *any* core can access memeory).
13392 + *
13393 + * The routine uses the bus to decide who is the master:
13394 + * SB_BUS => mips
13395 + * JTAG_BUS => chipc
13396 + * PCI_BUS => pci or pcie
13397 + * PCMCIA_BUS => pcmcia
13398 + * SDIO_BUS => pcmcia
13399 + *
13400 + * This routine exists so callers can disable initiator
13401 + * timeouts so accesses to very slow devices like otp
13402 + * won't cause an abort. The routine allows arbitrary
13403 + * settings of the service and request timeouts, though.
13404 + *
13405 + * Returns the timeout state before changing it or -1
13406 + * on error.
13407 + */
13408 +
13409 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
13410 +
13411 +uint32
13412 +sb_set_initiator_to(sb_t *sbh, uint32 to)
13413 +{
13414 + sb_info_t *si;
13415 + uint origidx, idx;
13416 + uint intr_val = 0;
13417 + uint32 tmp, ret = 0xffffffff;
13418 + sbconfig_t *sb;
13419 +
13420 + si = SB_INFO(sbh);
13421 +
13422 + if ((to & ~TO_MASK) != 0)
13423 + return ret;
13424 +
13425 + /* Figure out the master core */
13426 + idx = BADIDX;
13427 + switch (BUSTYPE(si->sb.bustype)) {
13428 + case PCI_BUS:
13429 + idx = si->sb.buscoreidx;
13430 + break;
13431 + case JTAG_BUS:
13432 + idx = SB_CC_IDX;
13433 + break;
13434 + case PCMCIA_BUS:
13435 + case SDIO_BUS:
13436 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
13437 + break;
13438 + case SB_BUS:
13439 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
13440 + idx = sb_findcoreidx(si, SB_MIPS, 0);
13441 + break;
13442 + default:
13443 + ASSERT(0);
13444 + }
13445 + if (idx == BADIDX)
13446 + return ret;
13447 +
13448 + INTR_OFF(si, intr_val);
13449 + origidx = sb_coreidx(sbh);
13450 +
13451 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
13452 +
13453 + tmp = R_SBREG(si, &sb->sbimconfiglow);
13454 + ret = tmp & TO_MASK;
13455 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
13456 +
13457 + sb_commit(sbh);
13458 + sb_setcoreidx(sbh, origidx);
13459 + INTR_RESTORE(si, intr_val);
13460 + return ret;
13461 +}
13462 +
13463 +void
13464 +sb_core_disable(sb_t *sbh, uint32 bits)
13465 +{
13466 + sb_info_t *si;
13467 + volatile uint32 dummy;
13468 + uint32 rej;
13469 + sbconfig_t *sb;
13470 +
13471 + si = SB_INFO(sbh);
13472 +
13473 + ASSERT(GOODREGS(si->curmap));
13474 + sb = REGS2SB(si->curmap);
13475 +
13476 + /* if core is already in reset, just return */
13477 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
13478 + return;
13479 +
13480 + /* reject value changed between sonics 2.2 and 2.3 */
13481 + if (si->sb.sonicsrev == SONICS_2_2)
13482 + rej = (1 << SBTML_REJ_SHIFT);
13483 + else
13484 + rej = (2 << SBTML_REJ_SHIFT);
13485 +
13486 + /* if clocks are not enabled, put into reset and return */
13487 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
13488 + goto disable;
13489 +
13490 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
13491 + OR_SBREG(si, &sb->sbtmstatelow, rej);
13492 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13493 + OSL_DELAY(1);
13494 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
13495 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY)
13496 + SB_ERROR(("%s: target state still busy\n", __FUNCTION__));
13497 +
13498 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
13499 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
13500 + dummy = R_SBREG(si, &sb->sbimstate);
13501 + OSL_DELAY(1);
13502 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
13503 + }
13504 +
13505 + /* set reset and reject while enabling the clocks */
13506 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
13507 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13508 + OSL_DELAY(10);
13509 +
13510 + /* don't forget to clear the initiator reject bit */
13511 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
13512 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
13513 +
13514 +disable:
13515 + /* leave reset and reject asserted */
13516 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
13517 + OSL_DELAY(1);
13518 +}
13519 +
13520 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
13521 +void
13522 +sb_watchdog(sb_t *sbh, uint ticks)
13523 +{
13524 + sb_info_t *si = SB_INFO(sbh);
13525 +
13526 + /* make sure we come up in fast clock mode */
13527 + sb_clkctl_clk(sbh, CLK_FAST);
13528 +
13529 + /* instant NMI */
13530 + switch (si->gpioid) {
13531 + case SB_CC:
13532 +#ifdef __mips__
13533 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1)
13534 + MTC0(C0_BROADCOM, 4, (1 << 22));
13535 +#endif /* __mips__ */
13536 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
13537 +#ifdef __mips__
13538 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1) {
13539 + __asm__ __volatile__ (
13540 + ".set\tmips3\n\t"
13541 + "sync\n\t"
13542 + "wait\n\t"
13543 + ".set\tmips0"
13544 + );
13545 + while (1);
13546 + }
13547 +#endif /* __mips__ */
13548 + break;
13549 + case SB_EXTIF:
13550 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
13551 + break;
13552 + }
13553 +}
13554 +
13555 +/* initialize the pcmcia core */
13556 +void
13557 +sb_pcmcia_init(sb_t *sbh)
13558 +{
13559 + sb_info_t *si;
13560 + uint8 cor = 0;
13561 +
13562 + si = SB_INFO(sbh);
13563 +
13564 + /* enable d11 mac interrupts */
13565 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13566 + cor |= COR_IRQEN | COR_FUNEN;
13567 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13568 +
13569 +}
13570 +
13571 +
13572 +/*
13573 + * Configure the pci core for pci client (NIC) action
13574 + * coremask is the bitvec of cores by index to be enabled.
13575 + */
13576 +void
13577 +BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
13578 +{
13579 + sb_info_t *si;
13580 + sbconfig_t *sb;
13581 + sbpciregs_t *pciregs;
13582 + uint32 sbflag;
13583 + uint32 w;
13584 + uint idx;
13585 + int reg_val;
13586 +
13587 + si = SB_INFO(sbh);
13588 +
13589 + /* if not pci bus, we're done */
13590 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13591 + return;
13592 +
13593 + ASSERT(PCI(si) || PCIE(si));
13594 + ASSERT(si->sb.buscoreidx != BADIDX);
13595 +
13596 + /* get current core index */
13597 + idx = si->curidx;
13598 +
13599 + /* we interrupt on this backplane flag number */
13600 + ASSERT(GOODREGS(si->curmap));
13601 + sb = REGS2SB(si->curmap);
13602 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
13603 +
13604 + /* switch over to pci core */
13605 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
13606 + sb = REGS2SB(pciregs);
13607 +
13608 + /*
13609 + * Enable sb->pci interrupts. Assume
13610 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
13611 + */
13612 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
13613 + /* pci config write to set this core bit in PCIIntMask */
13614 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
13615 + w |= (coremask << PCI_SBIM_SHIFT);
13616 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
13617 + } else {
13618 + /* set sbintvec bit for our flag number */
13619 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
13620 + }
13621 +
13622 + if (PCI(si)) {
13623 + OR_REG(si->osh, &pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
13624 + if (si->sb.buscorerev >= 11)
13625 + OR_REG(si->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
13626 + if (si->sb.buscorerev < 5) {
13627 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13628 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13629 + sb_commit(sbh);
13630 + }
13631 + }
13632 +
13633 +#ifdef PCIE_SUPPOER
13634 + /* PCIE workarounds */
13635 + if (PCIE(si)) {
13636 + if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) {
13637 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13638 + PCIE_TLP_WORKAROUNDSREG);
13639 + reg_val |= 0x8;
13640 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS,
13641 + PCIE_TLP_WORKAROUNDSREG, reg_val);
13642 + }
13643 +
13644 + if (si->sb.buscorerev == 1) {
13645 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13646 + PCIE_DLLP_LCREG);
13647 + reg_val |= (0x40);
13648 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
13649 + }
13650 +
13651 + if (si->sb.buscorerev == 0)
13652 + sb_war30841(si);
13653 + }
13654 +#endif
13655 +
13656 + /* switch back to previous core */
13657 + sb_setcoreidx(sbh, idx);
13658 +}
13659 +
13660 +uint32
13661 +sb_base(uint32 admatch)
13662 +{
13663 + uint32 base;
13664 + uint type;
13665 +
13666 + type = admatch & SBAM_TYPE_MASK;
13667 + ASSERT(type < 3);
13668 +
13669 + base = 0;
13670 +
13671 + if (type == 0) {
13672 + base = admatch & SBAM_BASE0_MASK;
13673 + } else if (type == 1) {
13674 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13675 + base = admatch & SBAM_BASE1_MASK;
13676 + } else if (type == 2) {
13677 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13678 + base = admatch & SBAM_BASE2_MASK;
13679 + }
13680 +
13681 + return (base);
13682 +}
13683 +
13684 +uint32
13685 +sb_size(uint32 admatch)
13686 +{
13687 + uint32 size;
13688 + uint type;
13689 +
13690 + type = admatch & SBAM_TYPE_MASK;
13691 + ASSERT(type < 3);
13692 +
13693 + size = 0;
13694 +
13695 + if (type == 0) {
13696 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
13697 + } else if (type == 1) {
13698 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13699 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
13700 + } else if (type == 2) {
13701 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13702 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
13703 + }
13704 +
13705 + return (size);
13706 +}
13707 +
13708 +/* return the core-type instantiation # of the current core */
13709 +uint
13710 +sb_coreunit(sb_t *sbh)
13711 +{
13712 + sb_info_t *si;
13713 + uint idx;
13714 + uint coreid;
13715 + uint coreunit;
13716 + uint i;
13717 +
13718 + si = SB_INFO(sbh);
13719 + coreunit = 0;
13720 +
13721 + idx = si->curidx;
13722 +
13723 + ASSERT(GOODREGS(si->curmap));
13724 + coreid = sb_coreid(sbh);
13725 +
13726 + /* count the cores of our type */
13727 + for (i = 0; i < idx; i++)
13728 + if (si->coreid[i] == coreid)
13729 + coreunit++;
13730 +
13731 + return (coreunit);
13732 +}
13733 +
13734 +static INLINE uint32
13735 +factor6(uint32 x)
13736 +{
13737 + switch (x) {
13738 + case CC_F6_2: return 2;
13739 + case CC_F6_3: return 3;
13740 + case CC_F6_4: return 4;
13741 + case CC_F6_5: return 5;
13742 + case CC_F6_6: return 6;
13743 + case CC_F6_7: return 7;
13744 + default: return 0;
13745 + }
13746 +}
13747 +
13748 +/* calculate the speed the SB would run at given a set of clockcontrol values */
13749 +uint32
13750 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
13751 +{
13752 + uint32 n1, n2, clock, m1, m2, m3, mc;
13753 +
13754 + n1 = n & CN_N1_MASK;
13755 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
13756 +
13757 + if (pll_type == PLL_TYPE6) {
13758 + if (m & CC_T6_MMASK)
13759 + return CC_T6_M1;
13760 + else
13761 + return CC_T6_M0;
13762 + } else if ((pll_type == PLL_TYPE1) ||
13763 + (pll_type == PLL_TYPE3) ||
13764 + (pll_type == PLL_TYPE4) ||
13765 + (pll_type == PLL_TYPE7)) {
13766 + n1 = factor6(n1);
13767 + n2 += CC_F5_BIAS;
13768 + } else if (pll_type == PLL_TYPE2) {
13769 + n1 += CC_T2_BIAS;
13770 + n2 += CC_T2_BIAS;
13771 + ASSERT((n1 >= 2) && (n1 <= 7));
13772 + ASSERT((n2 >= 5) && (n2 <= 23));
13773 + } else if (pll_type == PLL_TYPE5) {
13774 + return (100000000);
13775 + } else
13776 + ASSERT(0);
13777 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
13778 + if ((pll_type == PLL_TYPE3) ||
13779 + (pll_type == PLL_TYPE7)) {
13780 + clock = CC_CLOCK_BASE2 * n1 * n2;
13781 + } else
13782 + clock = CC_CLOCK_BASE1 * n1 * n2;
13783 +
13784 + if (clock == 0)
13785 + return 0;
13786 +
13787 + m1 = m & CC_M1_MASK;
13788 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
13789 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
13790 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
13791 +
13792 + if ((pll_type == PLL_TYPE1) ||
13793 + (pll_type == PLL_TYPE3) ||
13794 + (pll_type == PLL_TYPE4) ||
13795 + (pll_type == PLL_TYPE7)) {
13796 + m1 = factor6(m1);
13797 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
13798 + m2 += CC_F5_BIAS;
13799 + else
13800 + m2 = factor6(m2);
13801 + m3 = factor6(m3);
13802 +
13803 + switch (mc) {
13804 + case CC_MC_BYPASS: return (clock);
13805 + case CC_MC_M1: return (clock / m1);
13806 + case CC_MC_M1M2: return (clock / (m1 * m2));
13807 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
13808 + case CC_MC_M1M3: return (clock / (m1 * m3));
13809 + default: return (0);
13810 + }
13811 + } else {
13812 + ASSERT(pll_type == PLL_TYPE2);
13813 +
13814 + m1 += CC_T2_BIAS;
13815 + m2 += CC_T2M2_BIAS;
13816 + m3 += CC_T2_BIAS;
13817 + ASSERT((m1 >= 2) && (m1 <= 7));
13818 + ASSERT((m2 >= 3) && (m2 <= 10));
13819 + ASSERT((m3 >= 2) && (m3 <= 7));
13820 +
13821 + if ((mc & CC_T2MC_M1BYP) == 0)
13822 + clock /= m1;
13823 + if ((mc & CC_T2MC_M2BYP) == 0)
13824 + clock /= m2;
13825 + if ((mc & CC_T2MC_M3BYP) == 0)
13826 + clock /= m3;
13827 +
13828 + return (clock);
13829 + }
13830 +}
13831 +
13832 +/* returns the current speed the SB is running at */
13833 +uint32
13834 +sb_clock(sb_t *sbh)
13835 +{
13836 + sb_info_t *si;
13837 + extifregs_t *eir;
13838 + chipcregs_t *cc;
13839 + uint32 n, m;
13840 + uint idx;
13841 + uint32 pll_type, rate;
13842 + uint intr_val = 0;
13843 +
13844 + si = SB_INFO(sbh);
13845 + idx = si->curidx;
13846 + pll_type = PLL_TYPE1;
13847 +
13848 + INTR_OFF(si, intr_val);
13849 +
13850 + /* switch to extif or chipc core */
13851 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
13852 + n = R_REG(si->osh, &eir->clockcontrol_n);
13853 + m = R_REG(si->osh, &eir->clockcontrol_sb);
13854 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
13855 + pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
13856 + if (pll_type == PLL_NONE) {
13857 + INTR_RESTORE(si, intr_val);
13858 + return 80000000;
13859 + }
13860 + n = R_REG(si->osh, &cc->clockcontrol_n);
13861 + if (pll_type == PLL_TYPE6)
13862 + m = R_REG(si->osh, &cc->clockcontrol_m3);
13863 + else if ((pll_type == PLL_TYPE3) && !(BCMINIT(sb_chip)(sbh) == 0x5365))
13864 + m = R_REG(si->osh, &cc->clockcontrol_m2);
13865 + else
13866 + m = R_REG(si->osh, &cc->clockcontrol_sb);
13867 + } else {
13868 + INTR_RESTORE(si, intr_val);
13869 + return 0;
13870 + }
13871 +
13872 + /* calculate rate */
13873 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
13874 + rate = 100000000;
13875 + else {
13876 + rate = sb_clock_rate(pll_type, n, m);
13877 +
13878 + if (pll_type == PLL_TYPE3)
13879 + rate = rate / 2;
13880 + }
13881 +
13882 + /* switch back to previous core */
13883 + sb_setcoreidx(sbh, idx);
13884 +
13885 + INTR_RESTORE(si, intr_val);
13886 +
13887 + return rate;
13888 +}
13889 +
13890 +/* change logical "focus" to the gpio core for optimized access */
13891 +void*
13892 +sb_gpiosetcore(sb_t *sbh)
13893 +{
13894 + sb_info_t *si;
13895 +
13896 + si = SB_INFO(sbh);
13897 +
13898 + return (sb_setcoreidx(sbh, si->gpioidx));
13899 +}
13900 +
13901 +/* mask&set gpiocontrol bits */
13902 +uint32
13903 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13904 +{
13905 + sb_info_t *si;
13906 + uint regoff;
13907 +
13908 + si = SB_INFO(sbh);
13909 + regoff = 0;
13910 +
13911 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13912 +
13913 + /* gpios could be shared on router platforms */
13914 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13915 + mask = priority ? (sb_gpioreservation & mask) :
13916 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13917 + val &= mask;
13918 + }
13919 +
13920 + switch (si->gpioid) {
13921 + case SB_CC:
13922 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
13923 + break;
13924 +
13925 + case SB_PCI:
13926 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
13927 + break;
13928 +
13929 + case SB_EXTIF:
13930 + return (0);
13931 + }
13932 +
13933 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13934 +}
13935 +
13936 +/* mask&set gpio output enable bits */
13937 +uint32
13938 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13939 +{
13940 + sb_info_t *si;
13941 + uint regoff;
13942 +
13943 + si = SB_INFO(sbh);
13944 + regoff = 0;
13945 +
13946 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13947 +
13948 + /* gpios could be shared on router platforms */
13949 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13950 + mask = priority ? (sb_gpioreservation & mask) :
13951 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13952 + val &= mask;
13953 + }
13954 +
13955 + switch (si->gpioid) {
13956 + case SB_CC:
13957 + regoff = OFFSETOF(chipcregs_t, gpioouten);
13958 + break;
13959 +
13960 + case SB_PCI:
13961 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
13962 + break;
13963 +
13964 + case SB_EXTIF:
13965 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
13966 + break;
13967 + }
13968 +
13969 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13970 +}
13971 +
13972 +/* mask&set gpio output bits */
13973 +uint32
13974 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13975 +{
13976 + sb_info_t *si;
13977 + uint regoff;
13978 +
13979 + si = SB_INFO(sbh);
13980 + regoff = 0;
13981 +
13982 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13983 +
13984 + /* gpios could be shared on router platforms */
13985 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13986 + mask = priority ? (sb_gpioreservation & mask) :
13987 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13988 + val &= mask;
13989 + }
13990 +
13991 + switch (si->gpioid) {
13992 + case SB_CC:
13993 + regoff = OFFSETOF(chipcregs_t, gpioout);
13994 + break;
13995 +
13996 + case SB_PCI:
13997 + regoff = OFFSETOF(sbpciregs_t, gpioout);
13998 + break;
13999 +
14000 + case SB_EXTIF:
14001 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
14002 + break;
14003 + }
14004 +
14005 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14006 +}
14007 +
14008 +/* reserve one gpio */
14009 +uint32
14010 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14011 +{
14012 + sb_info_t *si;
14013 +
14014 + si = SB_INFO(sbh);
14015 +
14016 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14017 +
14018 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14019 + * reserve/release GPIO
14020 + */
14021 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14022 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14023 + return -1;
14024 + }
14025 + /* make sure only one bit is set */
14026 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14027 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14028 + return -1;
14029 + }
14030 +
14031 + /* already reserved */
14032 + if (sb_gpioreservation & gpio_bitmask)
14033 + return -1;
14034 + /* set reservation */
14035 + sb_gpioreservation |= gpio_bitmask;
14036 +
14037 + return sb_gpioreservation;
14038 +}
14039 +
14040 +/* release one gpio */
14041 +/*
14042 + * releasing the gpio doesn't change the current value on the GPIO last write value
14043 + * persists till some one overwrites it
14044 +*/
14045 +
14046 +uint32
14047 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14048 +{
14049 + sb_info_t *si;
14050 +
14051 + si = SB_INFO(sbh);
14052 +
14053 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14054 +
14055 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14056 + * reserve/release GPIO
14057 + */
14058 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14059 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14060 + return -1;
14061 + }
14062 + /* make sure only one bit is set */
14063 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14064 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14065 + return -1;
14066 + }
14067 +
14068 + /* already released */
14069 + if (!(sb_gpioreservation & gpio_bitmask))
14070 + return -1;
14071 +
14072 + /* clear reservation */
14073 + sb_gpioreservation &= ~gpio_bitmask;
14074 +
14075 + return sb_gpioreservation;
14076 +}
14077 +
14078 +/* return the current gpioin register value */
14079 +uint32
14080 +sb_gpioin(sb_t *sbh)
14081 +{
14082 + sb_info_t *si;
14083 + uint regoff;
14084 +
14085 + si = SB_INFO(sbh);
14086 + regoff = 0;
14087 +
14088 + switch (si->gpioid) {
14089 + case SB_CC:
14090 + regoff = OFFSETOF(chipcregs_t, gpioin);
14091 + break;
14092 +
14093 + case SB_PCI:
14094 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14095 + break;
14096 +
14097 + case SB_EXTIF:
14098 + regoff = OFFSETOF(extifregs_t, gpioin);
14099 + break;
14100 + }
14101 +
14102 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14103 +}
14104 +
14105 +/* mask&set gpio interrupt polarity bits */
14106 +uint32
14107 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14108 +{
14109 + sb_info_t *si;
14110 + uint regoff;
14111 +
14112 + si = SB_INFO(sbh);
14113 + regoff = 0;
14114 +
14115 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14116 +
14117 + /* gpios could be shared on router platforms */
14118 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14119 + mask = priority ? (sb_gpioreservation & mask) :
14120 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14121 + val &= mask;
14122 + }
14123 +
14124 + switch (si->gpioid) {
14125 + case SB_CC:
14126 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14127 + break;
14128 +
14129 + case SB_PCI:
14130 + /* pci gpio implementation does not support interrupt polarity */
14131 + ASSERT(0);
14132 + break;
14133 +
14134 + case SB_EXTIF:
14135 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14136 + break;
14137 + }
14138 +
14139 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14140 +}
14141 +
14142 +/* mask&set gpio interrupt mask bits */
14143 +uint32
14144 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14145 +{
14146 + sb_info_t *si;
14147 + uint regoff;
14148 +
14149 + si = SB_INFO(sbh);
14150 + regoff = 0;
14151 +
14152 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14153 +
14154 + /* gpios could be shared on router platforms */
14155 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14156 + mask = priority ? (sb_gpioreservation & mask) :
14157 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14158 + val &= mask;
14159 + }
14160 +
14161 + switch (si->gpioid) {
14162 + case SB_CC:
14163 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14164 + break;
14165 +
14166 + case SB_PCI:
14167 + /* pci gpio implementation does not support interrupt mask */
14168 + ASSERT(0);
14169 + break;
14170 +
14171 + case SB_EXTIF:
14172 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14173 + break;
14174 + }
14175 +
14176 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14177 +}
14178 +
14179 +/* assign the gpio to an led */
14180 +uint32
14181 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14182 +{
14183 + sb_info_t *si;
14184 +
14185 + si = SB_INFO(sbh);
14186 + if (si->sb.ccrev < 16)
14187 + return -1;
14188 +
14189 + /* gpio led powersave reg */
14190 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14191 +}
14192 +
14193 +/* mask & set gpio timer val */
14194 +uint32
14195 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14196 +{
14197 + sb_info_t *si;
14198 + si = SB_INFO(sbh);
14199 +
14200 + if (si->sb.ccrev < 16)
14201 + return -1;
14202 +
14203 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14204 +}
14205 +
14206 +
14207 +/* return the slow clock source - LPO, XTAL, or PCI */
14208 +static uint
14209 +sb_slowclk_src(sb_info_t *si)
14210 +{
14211 + chipcregs_t *cc;
14212 +
14213 +
14214 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14215 +
14216 + if (si->sb.ccrev < 6) {
14217 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS) &&
14218 + (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) &
14219 + PCI_CFG_GPIO_SCS))
14220 + return (SCC_SS_PCI);
14221 + else
14222 + return (SCC_SS_XTAL);
14223 + } else if (si->sb.ccrev < 10) {
14224 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14225 + return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
14226 + } else /* Insta-clock */
14227 + return (SCC_SS_XTAL);
14228 +}
14229 +
14230 +/* return the ILP (slowclock) min or max frequency */
14231 +static uint
14232 +sb_slowclk_freq(sb_info_t *si, bool max)
14233 +{
14234 + chipcregs_t *cc;
14235 + uint32 slowclk;
14236 + uint div;
14237 +
14238 +
14239 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14240 +
14241 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14242 +
14243 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14244 + ASSERT(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL);
14245 +
14246 + slowclk = sb_slowclk_src(si);
14247 + if (si->sb.ccrev < 6) {
14248 + if (slowclk == SCC_SS_PCI)
14249 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14250 + else
14251 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14252 + } else if (si->sb.ccrev < 10) {
14253 + div = 4 * (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14254 + if (slowclk == SCC_SS_LPO)
14255 + return (max? LPOMAXFREQ : LPOMINFREQ);
14256 + else if (slowclk == SCC_SS_XTAL)
14257 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14258 + else if (slowclk == SCC_SS_PCI)
14259 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14260 + else
14261 + ASSERT(0);
14262 + } else {
14263 + /* Chipc rev 10 is InstaClock */
14264 + div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
14265 + div = 4 * (div + 1);
14266 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
14267 + }
14268 + return (0);
14269 +}
14270 +
14271 +static void
14272 +BCMINITFN(sb_clkctl_setdelay)(sb_info_t *si, void *chipcregs)
14273 +{
14274 + chipcregs_t * cc;
14275 + uint slowmaxfreq, pll_delay, slowclk;
14276 + uint pll_on_delay, fref_sel_delay;
14277 +
14278 + pll_delay = PLL_DELAY;
14279 +
14280 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
14281 + * since the xtal will also be powered down by dynamic clk control logic.
14282 + */
14283 +
14284 + slowclk = sb_slowclk_src(si);
14285 + if (slowclk != SCC_SS_XTAL)
14286 + pll_delay += XTAL_ON_DELAY;
14287 +
14288 + /* Starting with 4318 it is ILP that is used for the delays */
14289 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
14290 +
14291 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
14292 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
14293 +
14294 + cc = (chipcregs_t *)chipcregs;
14295 + W_REG(si->osh, &cc->pll_on_delay, pll_on_delay);
14296 + W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay);
14297 +}
14298 +
14299 +/* initialize power control delay registers */
14300 +void
14301 +BCMINITFN(sb_clkctl_init)(sb_t *sbh)
14302 +{
14303 + sb_info_t *si;
14304 + uint origidx;
14305 + chipcregs_t *cc;
14306 +
14307 + si = SB_INFO(sbh);
14308 +
14309 + origidx = si->curidx;
14310 +
14311 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14312 + return;
14313 +
14314 + if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2))
14315 + W_REG(si->osh, &cc->chipcontrol,
14316 + (si->sb.chiprev == 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT);
14317 +
14318 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14319 + goto done;
14320 +
14321 + /* set all Instaclk chip ILP to 1 MHz */
14322 + else if (si->sb.ccrev >= 10)
14323 + SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
14324 + (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
14325 +
14326 + sb_clkctl_setdelay(si, (void *)cc);
14327 +
14328 +done:
14329 + sb_setcoreidx(sbh, origidx);
14330 +}
14331 +
14332 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
14333 +uint16
14334 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
14335 +{
14336 + sb_info_t *si;
14337 + uint origidx;
14338 + chipcregs_t *cc;
14339 + uint slowminfreq;
14340 + uint16 fpdelay;
14341 + uint intr_val = 0;
14342 +
14343 + si = SB_INFO(sbh);
14344 + fpdelay = 0;
14345 + origidx = si->curidx;
14346 +
14347 + INTR_OFF(si, intr_val);
14348 +
14349 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14350 + goto done;
14351 +
14352 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14353 + goto done;
14354 +
14355 + slowminfreq = sb_slowclk_freq(si, FALSE);
14356 + fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) +
14357 + (slowminfreq - 1)) / slowminfreq;
14358 +
14359 +done:
14360 + sb_setcoreidx(sbh, origidx);
14361 + INTR_RESTORE(si, intr_val);
14362 + return (fpdelay);
14363 +}
14364 +
14365 +/* turn primary xtal and/or pll off/on */
14366 +int
14367 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
14368 +{
14369 + sb_info_t *si;
14370 + uint32 in, out, outen;
14371 +
14372 + si = SB_INFO(sbh);
14373 +
14374 + switch (BUSTYPE(si->sb.bustype)) {
14375 +
14376 +
14377 + case PCMCIA_BUS:
14378 + return (0);
14379 +
14380 +
14381 + case PCI_BUS:
14382 +
14383 + /* pcie core doesn't have any mapping to control the xtal pu */
14384 + if (PCIE(si))
14385 + return -1;
14386 +
14387 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32));
14388 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32));
14389 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32));
14390 +
14391 + /*
14392 + * Avoid glitching the clock if GPRS is already using it.
14393 + * We can't actually read the state of the PLLPD so we infer it
14394 + * by the value of XTAL_PU which *is* readable via gpioin.
14395 + */
14396 + if (on && (in & PCI_CFG_GPIO_XTAL))
14397 + return (0);
14398 +
14399 + if (what & XTAL)
14400 + outen |= PCI_CFG_GPIO_XTAL;
14401 + if (what & PLL)
14402 + outen |= PCI_CFG_GPIO_PLL;
14403 +
14404 + if (on) {
14405 + /* turn primary xtal on */
14406 + if (what & XTAL) {
14407 + out |= PCI_CFG_GPIO_XTAL;
14408 + if (what & PLL)
14409 + out |= PCI_CFG_GPIO_PLL;
14410 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14411 + sizeof(uint32), out);
14412 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN,
14413 + sizeof(uint32), outen);
14414 + OSL_DELAY(XTAL_ON_DELAY);
14415 + }
14416 +
14417 + /* turn pll on */
14418 + if (what & PLL) {
14419 + out &= ~PCI_CFG_GPIO_PLL;
14420 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14421 + sizeof(uint32), out);
14422 + OSL_DELAY(2000);
14423 + }
14424 + } else {
14425 + if (what & XTAL)
14426 + out &= ~PCI_CFG_GPIO_XTAL;
14427 + if (what & PLL)
14428 + out |= PCI_CFG_GPIO_PLL;
14429 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32), out);
14430 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32),
14431 + outen);
14432 + }
14433 +
14434 + default:
14435 + return (-1);
14436 + }
14437 +
14438 + return (0);
14439 +}
14440 +
14441 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
14442 +/* returns true if we are forcing fast clock */
14443 +bool
14444 +sb_clkctl_clk(sb_t *sbh, uint mode)
14445 +{
14446 + sb_info_t *si;
14447 + uint origidx;
14448 + chipcregs_t *cc;
14449 + uint32 scc;
14450 + uint intr_val = 0;
14451 +
14452 + si = SB_INFO(sbh);
14453 +
14454 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
14455 + if (si->sb.ccrev < 6)
14456 + return (FALSE);
14457 +
14458 +
14459 + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
14460 + ASSERT(si->sb.ccrev != 10);
14461 +
14462 + INTR_OFF(si, intr_val);
14463 +
14464 + origidx = si->curidx;
14465 +
14466 + if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
14467 + (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10))
14468 + goto done;
14469 +
14470 + /* PR32414WAR "Force HT clock on" all the time, no dynamic clk ctl */
14471 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1))
14472 + goto done;
14473 +
14474 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
14475 + ASSERT(cc != NULL);
14476 +
14477 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14478 + goto done;
14479 +
14480 + switch (mode) {
14481 + case CLK_FAST: /* force fast (pll) clock */
14482 + if (si->sb.ccrev < 10) {
14483 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
14484 + sb_clkctl_xtal(&si->sb, XTAL, ON);
14485 +
14486 + SET_REG(si->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
14487 + } else
14488 + OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR);
14489 + /* wait for the PLL */
14490 + OSL_DELAY(PLL_DELAY);
14491 + break;
14492 +
14493 + case CLK_DYNAMIC: /* enable dynamic clock control */
14494 +
14495 + if (si->sb.ccrev < 10) {
14496 + scc = R_REG(si->osh, &cc->slow_clk_ctl);
14497 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
14498 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
14499 + scc |= SCC_XC;
14500 + W_REG(si->osh, &cc->slow_clk_ctl, scc);
14501 +
14502 + /* for dynamic control, we have to release our xtal_pu "force on" */
14503 + if (scc & SCC_XC)
14504 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
14505 + } else {
14506 + /* Instaclock */
14507 + AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR);
14508 + }
14509 + break;
14510 +
14511 + default:
14512 + ASSERT(0);
14513 + }
14514 +
14515 +done:
14516 + sb_setcoreidx(sbh, origidx);
14517 + INTR_RESTORE(si, intr_val);
14518 + return (mode == CLK_FAST);
14519 +}
14520 +
14521 +/* register driver interrupt disabling and restoring callback functions */
14522 +void
14523 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
14524 + void *intrsenabled_fn, void *intr_arg)
14525 +{
14526 + sb_info_t *si;
14527 +
14528 + si = SB_INFO(sbh);
14529 + si->intr_arg = intr_arg;
14530 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
14531 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
14532 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
14533 + /* save current core id. when this function called, the current core
14534 + * must be the core which provides driver functions(il, et, wl, etc.)
14535 + */
14536 + si->dev_coreid = si->coreid[si->curidx];
14537 +}
14538 +
14539 +
14540 +int
14541 +sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
14542 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
14543 + uint8 *pciheader)
14544 +{
14545 + uint16 vendor = 0xffff, device = 0xffff;
14546 + uint core, unit;
14547 + uint chip, chippkg;
14548 + uint nfunc;
14549 + char varname[SB_DEVPATH_BUFSZ + 8];
14550 + uint8 class, subclass, progif;
14551 + char devpath[SB_DEVPATH_BUFSZ];
14552 + uint8 header;
14553 +
14554 + core = sb_coreid(sbh);
14555 + unit = sb_coreunit(sbh);
14556 +
14557 + chip = sb_chip(sbh);
14558 + chippkg = sb_chippkg(sbh);
14559 +
14560 + progif = 0;
14561 + header = PCI_HEADER_NORMAL;
14562 +
14563 + /* Verify whether the function exists for the core */
14564 + nfunc = (core == SB_USB20H) ? 2 : 1;
14565 + if (func >= nfunc)
14566 + return BCME_ERROR;
14567 +
14568 + /* Known vendor translations */
14569 + switch (sb_corevendor(sbh)) {
14570 + case SB_VEND_BCM:
14571 + vendor = VENDOR_BROADCOM;
14572 + break;
14573 + default:
14574 + return BCME_ERROR;
14575 + }
14576 +
14577 + /* Determine class based on known core codes */
14578 + switch (core) {
14579 + case SB_ILINE20:
14580 + class = PCI_CLASS_NET;
14581 + subclass = PCI_NET_ETHER;
14582 + device = BCM47XX_ILINE_ID;
14583 + break;
14584 + case SB_ENET:
14585 + class = PCI_CLASS_NET;
14586 + subclass = PCI_NET_ETHER;
14587 + device = BCM47XX_ENET_ID;
14588 + break;
14589 + case SB_GIGETH:
14590 + class = PCI_CLASS_NET;
14591 + subclass = PCI_NET_ETHER;
14592 + device = BCM47XX_GIGETH_ID;
14593 + break;
14594 + case SB_SDRAM:
14595 + case SB_MEMC:
14596 + class = PCI_CLASS_MEMORY;
14597 + subclass = PCI_MEMORY_RAM;
14598 + device = (uint16)core;
14599 + break;
14600 + case SB_PCI:
14601 + case SB_PCIE:
14602 + class = PCI_CLASS_BRIDGE;
14603 + subclass = PCI_BRIDGE_PCI;
14604 + device = (uint16)core;
14605 + header = PCI_HEADER_BRIDGE;
14606 + break;
14607 + case SB_MIPS:
14608 + case SB_MIPS33:
14609 + class = PCI_CLASS_CPU;
14610 + subclass = PCI_CPU_MIPS;
14611 + device = (uint16)core;
14612 + break;
14613 + case SB_CODEC:
14614 + class = PCI_CLASS_COMM;
14615 + subclass = PCI_COMM_MODEM;
14616 + device = BCM47XX_V90_ID;
14617 + break;
14618 + case SB_USB:
14619 + class = PCI_CLASS_SERIAL;
14620 + subclass = PCI_SERIAL_USB;
14621 + progif = 0x10; /* OHCI */
14622 + device = BCM47XX_USB_ID;
14623 + break;
14624 + case SB_USB11H:
14625 + class = PCI_CLASS_SERIAL;
14626 + subclass = PCI_SERIAL_USB;
14627 + progif = 0x10; /* OHCI */
14628 + device = BCM47XX_USBH_ID;
14629 + break;
14630 + case SB_USB20H:
14631 + class = PCI_CLASS_SERIAL;
14632 + subclass = PCI_SERIAL_USB;
14633 + progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */
14634 + device = BCM47XX_USB20H_ID;
14635 + header = 0x80; /* multifunction */
14636 + break;
14637 + case SB_USB11D:
14638 + class = PCI_CLASS_SERIAL;
14639 + subclass = PCI_SERIAL_USB;
14640 + device = BCM47XX_USBD_ID;
14641 + break;
14642 + case SB_USB20D:
14643 + class = PCI_CLASS_SERIAL;
14644 + subclass = PCI_SERIAL_USB;
14645 + device = BCM47XX_USB20D_ID;
14646 + break;
14647 + case SB_IPSEC:
14648 + class = PCI_CLASS_CRYPT;
14649 + subclass = PCI_CRYPT_NETWORK;
14650 + device = BCM47XX_IPSEC_ID;
14651 + break;
14652 + case SB_ROBO:
14653 + class = PCI_CLASS_NET;
14654 + subclass = PCI_NET_OTHER;
14655 + device = BCM47XX_ROBO_ID;
14656 + break;
14657 + case SB_EXTIF:
14658 + case SB_CC:
14659 + class = PCI_CLASS_MEMORY;
14660 + subclass = PCI_MEMORY_FLASH;
14661 + device = (uint16)core;
14662 + break;
14663 + case SB_D11:
14664 + class = PCI_CLASS_NET;
14665 + subclass = PCI_NET_OTHER;
14666 + /* Let nvram variable override core ID */
14667 + sb_devpath(sbh, devpath, sizeof(devpath));
14668 + sprintf(varname, "%sdevid", devpath);
14669 + if ((device = (uint16)getintvar(NULL, varname)))
14670 + break;
14671 + /*
14672 + * no longer support wl%did, but keep the code
14673 + * here for backward compatibility.
14674 + */
14675 + sprintf(varname, "wl%did", unit);
14676 + if ((device = (uint16)getintvar(NULL, varname)))
14677 + break;
14678 + /* Chip specific conversion */
14679 + if (chip == BCM4712_CHIP_ID) {
14680 + if (chippkg == BCM4712SMALL_PKG_ID)
14681 + device = BCM4306_D11G_ID;
14682 + else
14683 + device = BCM4306_D11DUAL_ID;
14684 + break;
14685 + }
14686 + /* ignore it */
14687 + device = 0xffff;
14688 + break;
14689 + case SB_SATAXOR:
14690 + class = PCI_CLASS_XOR;
14691 + subclass = PCI_XOR_QDMA;
14692 + device = BCM47XX_SATAXOR_ID;
14693 + break;
14694 + case SB_ATA100:
14695 + class = PCI_CLASS_DASDI;
14696 + subclass = PCI_DASDI_IDE;
14697 + device = BCM47XX_ATA100_ID;
14698 + break;
14699 +
14700 + default:
14701 + class = subclass = progif = 0xff;
14702 + device = (uint16)core;
14703 + break;
14704 + }
14705 +
14706 + *pcivendor = vendor;
14707 + *pcidevice = device;
14708 + *pciclass = class;
14709 + *pcisubclass = subclass;
14710 + *pciprogif = progif;
14711 + *pciheader = header;
14712 +
14713 + return 0;
14714 +}
14715 +
14716 +
14717 +
14718 +/* use the mdio interface to write to mdio slaves */
14719 +static int
14720 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
14721 +{
14722 + uint mdiodata;
14723 + uint i = 0;
14724 + sbpcieregs_t *pcieregs;
14725 +
14726 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
14727 + ASSERT(pcieregs);
14728 +
14729 + /* enable mdio access to SERDES */
14730 + W_REG(si->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
14731 +
14732 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
14733 + (physmedia << MDIODATA_DEVADDR_SHF) |
14734 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
14735 +
14736 + W_REG(si->osh, (&pcieregs->mdiodata), mdiodata);
14737 +
14738 + PR28829_DELAY();
14739 +
14740 + /* retry till the transaction is complete */
14741 + while (i < 10) {
14742 + if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
14743 + /* Disable mdio access to SERDES */
14744 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14745 + return 0;
14746 + }
14747 + OSL_DELAY(1000);
14748 + i++;
14749 + }
14750 +
14751 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
14752 + /* Disable mdio access to SERDES */
14753 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14754 + ASSERT(0);
14755 + return 1;
14756 +
14757 +}
14758 +
14759 +/* indirect way to read pcie config regs */
14760 +uint
14761 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
14762 +{
14763 + sb_info_t *si;
14764 + sb_t *sbh;
14765 + uint retval = 0xFFFFFFFF;
14766 + sbpcieregs_t *pcieregs;
14767 + uint addrtype;
14768 +
14769 + sbh = (sb_t *)sb;
14770 + si = SB_INFO(sbh);
14771 + ASSERT(PCIE(si));
14772 +
14773 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14774 + ASSERT(pcieregs);
14775 +
14776 + addrtype = (uint)((uintptr)arg1);
14777 + switch (addrtype) {
14778 + case PCIE_CONFIGREGS:
14779 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14780 + retval = R_REG(si->osh, &(pcieregs->configdata));
14781 + break;
14782 + case PCIE_PCIEREGS:
14783 + W_REG(si->osh, &(pcieregs->pcieaddr), offset);
14784 + retval = R_REG(si->osh, &(pcieregs->pciedata));
14785 + break;
14786 + default:
14787 + ASSERT(0);
14788 + break;
14789 + }
14790 + return retval;
14791 +}
14792 +
14793 +/* indirect way to write pcie config/mdio/pciecore regs */
14794 +uint
14795 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
14796 +{
14797 + sb_info_t *si;
14798 + sbpcieregs_t *pcieregs;
14799 + uint addrtype;
14800 +
14801 + si = SB_INFO(sbh);
14802 + ASSERT(PCIE(si));
14803 +
14804 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14805 + ASSERT(pcieregs);
14806 +
14807 + addrtype = (uint)((uintptr)arg1);
14808 +
14809 + switch (addrtype) {
14810 + case PCIE_CONFIGREGS:
14811 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14812 + W_REG(si->osh, (&pcieregs->configdata), val);
14813 + break;
14814 + case PCIE_PCIEREGS:
14815 + W_REG(si->osh, (&pcieregs->pcieaddr), offset);
14816 + W_REG(si->osh, (&pcieregs->pciedata), val);
14817 + break;
14818 + default:
14819 + ASSERT(0);
14820 + break;
14821 + }
14822 + return 0;
14823 +}
14824 +
14825 +/* Build device path. Support SB, PCI, and JTAG for now. */
14826 +int
14827 +sb_devpath(sb_t *sbh, char *path, int size)
14828 +{
14829 + ASSERT(path);
14830 + ASSERT(size >= SB_DEVPATH_BUFSZ);
14831 +
14832 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
14833 + case SB_BUS:
14834 + case JTAG_BUS:
14835 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
14836 + break;
14837 + case PCI_BUS:
14838 + ASSERT((SB_INFO(sbh))->osh);
14839 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
14840 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
14841 + break;
14842 + case PCMCIA_BUS:
14843 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
14844 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
14845 + sprintf(path, "pc/%u/%u/", 1, 1);
14846 + break;
14847 + case SDIO_BUS:
14848 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
14849 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
14850 + break;
14851 + default:
14852 + ASSERT(0);
14853 + break;
14854 + }
14855 +
14856 + return 0;
14857 +}
14858 +
14859 +/*
14860 + * Fixup SROMless PCI device's configuration.
14861 + * The current core may be changed upon return.
14862 + */
14863 +static int
14864 +sb_pci_fixcfg(sb_info_t *si)
14865 +{
14866 + uint origidx, pciidx;
14867 + sbpciregs_t *pciregs;
14868 + sbpcieregs_t *pcieregs;
14869 + uint16 val16, *reg16;
14870 + char name[SB_DEVPATH_BUFSZ+16], *value;
14871 + char devpath[SB_DEVPATH_BUFSZ];
14872 +
14873 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
14874 +
14875 + /* Fixup PI in SROM shadow area to enable the correct PCI core access */
14876 + /* save the current index */
14877 + origidx = sb_coreidx(&si->sb);
14878 +
14879 + /* check 'pi' is correct and fix it if not */
14880 + if (si->sb.buscoretype == SB_PCIE) {
14881 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
14882 + ASSERT(pcieregs);
14883 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
14884 + } else if (si->sb.buscoretype == SB_PCI) {
14885 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
14886 + ASSERT(pciregs);
14887 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
14888 + } else {
14889 + ASSERT(0);
14890 + return -1;
14891 + }
14892 + pciidx = sb_coreidx(&si->sb);
14893 + val16 = R_REG(si->osh, reg16);
14894 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
14895 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
14896 + W_REG(si->osh, reg16, val16);
14897 + }
14898 +
14899 + /* restore the original index */
14900 + sb_setcoreidx(&si->sb, origidx);
14901 +
14902 + /*
14903 + * Fixup bar0window in PCI config space to make the core indicated
14904 + * by the nvram variable the current core.
14905 + * !Do it last, it may change the current core!
14906 + */
14907 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
14908 + return -1;
14909 + sprintf(name, "%sb0w", devpath);
14910 + if ((value = getvar(NULL, name))) {
14911 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
14912 + bcm_strtoul(value, NULL, 16));
14913 + /* update curidx since the current core is changed */
14914 + si->curidx = _sb_coreidx(si);
14915 + if (si->curidx == BADIDX) {
14916 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
14917 + return -1;
14918 + }
14919 + }
14920 +
14921 + return 0;
14922 +}
14923 +
14924 +static uint
14925 +sb_chipc_capability(sb_t *sbh)
14926 +{
14927 + sb_info_t *si;
14928 +
14929 + si = SB_INFO(sbh);
14930 +
14931 + /* Make sure that there is ChipCommon core present */
14932 + if (si->coreid[SB_CC_IDX] == SB_CC)
14933 + return (sb_corereg(si, SB_CC_IDX, OFFSETOF(chipcregs_t, capabilities),
14934 + 0, 0));
14935 + return 0;
14936 +}
14937 +
14938 +/* Return ADDR64 capability of the backplane */
14939 +bool
14940 +sb_backplane64(sb_t *sbh)
14941 +{
14942 + return ((sb_chipc_capability(sbh) & CAP_BKPLN64) != 0);
14943 +}
14944 +
14945 +void
14946 +sb_btcgpiowar(sb_t *sbh)
14947 +{
14948 + sb_info_t *si;
14949 + uint origidx;
14950 + uint intr_val = 0;
14951 + chipcregs_t *cc;
14952 + si = SB_INFO(sbh);
14953 +
14954 + /* Make sure that there is ChipCommon core present &&
14955 + * UART_TX is strapped to 1
14956 + */
14957 + if (!(sb_chipc_capability(sbh) & CAP_UARTGPIO))
14958 + return;
14959 +
14960 + /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */
14961 + INTR_OFF(si, intr_val);
14962 +
14963 + origidx = sb_coreidx(sbh);
14964 +
14965 + cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
14966 + if (cc == NULL)
14967 + goto end;
14968 +
14969 + W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04);
14970 +
14971 +end:
14972 + /* restore the original index */
14973 + sb_setcoreidx(sbh, origidx);
14974 +
14975 + INTR_RESTORE(si, intr_val);
14976 +}
14977 +
14978 +/* check if the device is removed */
14979 +bool
14980 +sb_deviceremoved(sb_t *sbh)
14981 +{
14982 + uint32 w;
14983 + sb_info_t *si;
14984 +
14985 + si = SB_INFO(sbh);
14986 +
14987 + switch (BUSTYPE(si->sb.bustype)) {
14988 + case PCI_BUS:
14989 + ASSERT(si->osh);
14990 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32));
14991 + if ((w & 0xFFFF) != VENDOR_BROADCOM)
14992 + return TRUE;
14993 + else
14994 + return FALSE;
14995 + default:
14996 + return FALSE;
14997 + }
14998 + return FALSE;
14999 +}
15000 +
15001 +/* Return the RAM size of the SOCRAM core */
15002 +uint32
15003 +sb_socram_size(sb_t *sbh)
15004 +{
15005 + sb_info_t *si;
15006 + uint origidx;
15007 + uint intr_val = 0;
15008 +
15009 + sbsocramregs_t *regs;
15010 + bool wasup;
15011 + uint corerev;
15012 + uint32 coreinfo;
15013 + uint memsize = 0;
15014 +
15015 + si = SB_INFO(sbh);
15016 + ASSERT(si);
15017 +
15018 + /* Block ints and save current core */
15019 + INTR_OFF(si, intr_val);
15020 + origidx = sb_coreidx(sbh);
15021 +
15022 + /* Switch to SOCRAM core */
15023 + if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
15024 + goto done;
15025 +
15026 + /* Get info for determining size */
15027 + if (!(wasup = sb_iscoreup(sbh)))
15028 + sb_core_reset(sbh, 0, 0);
15029 + corerev = sb_corerev(sbh);
15030 + coreinfo = R_REG(si->osh, &regs->coreinfo);
15031 +
15032 + /* Calculate size from coreinfo based on rev */
15033 + switch (corerev) {
15034 + case 0:
15035 + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
15036 + break;
15037 + default: /* rev >= 1 */
15038 + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
15039 + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
15040 + break;
15041 + }
15042 +
15043 + /* Return to previous state and core */
15044 + if (!wasup)
15045 + sb_core_disable(sbh, 0);
15046 + sb_setcoreidx(sbh, origidx);
15047 +
15048 +done:
15049 + INTR_RESTORE(si, intr_val);
15050 + return memsize;
15051 +}
15052 +
15053 +
15054 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
15055 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
15056 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-10-02 21:19:59.000000000 +0200
15057 @@ -0,0 +1,241 @@
15058 +/*
15059 + * Generic setup routines for Broadcom MIPS boards
15060 + *
15061 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
15062 + *
15063 + * This program is free software; you can redistribute it and/or modify it
15064 + * under the terms of the GNU General Public License as published by the
15065 + * Free Software Foundation; either version 2 of the License, or (at your
15066 + * option) any later version.
15067 + *
15068 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15069 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15070 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15071 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15072 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15073 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15074 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
15075 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15076 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
15077 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15078 + *
15079 + * You should have received a copy of the GNU General Public License along
15080 + * with this program; if not, write to the Free Software Foundation, Inc.,
15081 + * 675 Mass Ave, Cambridge, MA 02139, USA.
15082 + *
15083 + *
15084 + * Copyright 2005, Broadcom Corporation
15085 + * All Rights Reserved.
15086 + *
15087 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15088 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15089 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15090 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15091 + *
15092 + */
15093 +
15094 +#include <linux/config.h>
15095 +#include <linux/init.h>
15096 +#include <linux/kernel.h>
15097 +#include <linux/module.h>
15098 +#include <linux/serialP.h>
15099 +#include <linux/ide.h>
15100 +#include <asm/bootinfo.h>
15101 +#include <asm/cpu.h>
15102 +#include <asm/time.h>
15103 +#include <asm/reboot.h>
15104 +
15105 +#include <typedefs.h>
15106 +#include <osl.h>
15107 +#include <sbutils.h>
15108 +#include <bcmutils.h>
15109 +#include <bcmnvram.h>
15110 +#include <sbhndmips.h>
15111 +#include <hndmips.h>
15112 +#include <trxhdr.h>
15113 +
15114 +/* Virtual IRQ base, after last hw IRQ */
15115 +#define SBMIPS_VIRTIRQ_BASE 6
15116 +
15117 +/* # IRQs, hw and sw IRQs */
15118 +#define SBMIPS_NUMIRQS 8
15119 +
15120 +/* Global SB handle */
15121 +sb_t *bcm947xx_sbh = NULL;
15122 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
15123 +
15124 +/* Convenience */
15125 +#define sbh bcm947xx_sbh
15126 +#define sbh_lock bcm947xx_sbh_lock
15127 +
15128 +extern void bcm947xx_time_init(void);
15129 +extern void bcm947xx_timer_setup(struct irqaction *irq);
15130 +
15131 +#ifdef CONFIG_REMOTE_DEBUG
15132 +extern void set_debug_traps(void);
15133 +extern void rs_kgdb_hook(struct serial_state *);
15134 +extern void breakpoint(void);
15135 +#endif
15136 +
15137 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15138 +extern struct ide_ops std_ide_ops;
15139 +#endif
15140 +
15141 +/* Kernel command line */
15142 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
15143 +extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
15144 +
15145 +void
15146 +bcm947xx_machine_restart(char *command)
15147 +{
15148 + printk("Please stand by while rebooting the system...\n");
15149 +
15150 + /* Set the watchdog timer to reset immediately */
15151 + __cli();
15152 + sb_watchdog(sbh, 1);
15153 + while (1);
15154 +}
15155 +
15156 +void
15157 +bcm947xx_machine_halt(void)
15158 +{
15159 + printk("System halted\n");
15160 +
15161 + /* Disable interrupts and watchdog and spin forever */
15162 + __cli();
15163 + sb_watchdog(sbh, 0);
15164 + while (1);
15165 +}
15166 +
15167 +#ifdef CONFIG_SERIAL
15168 +
15169 +static int ser_line = 0;
15170 +
15171 +typedef struct {
15172 + void *regs;
15173 + uint irq;
15174 + uint baud_base;
15175 + uint reg_shift;
15176 +} serial_port;
15177 +
15178 +static serial_port ports[4];
15179 +static int num_ports = 0;
15180 +
15181 +static void
15182 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
15183 +{
15184 + ports[num_ports].regs = regs;
15185 + ports[num_ports].irq = irq;
15186 + ports[num_ports].baud_base = baud_base;
15187 + ports[num_ports].reg_shift = reg_shift;
15188 + num_ports++;
15189 +}
15190 +
15191 +static void
15192 +do_serial_add(serial_port *port)
15193 +{
15194 + void *regs;
15195 + uint irq;
15196 + uint baud_base;
15197 + uint reg_shift;
15198 + struct serial_struct s;
15199 +
15200 + regs = port->regs;
15201 + irq = port->irq;
15202 + baud_base = port->baud_base;
15203 + reg_shift = port->reg_shift;
15204 +
15205 + memset(&s, 0, sizeof(s));
15206 +
15207 + s.line = ser_line++;
15208 + s.iomem_base = regs;
15209 + s.irq = irq + 2;
15210 + s.baud_base = baud_base / 16;
15211 + s.flags = ASYNC_BOOT_AUTOCONF;
15212 + s.io_type = SERIAL_IO_MEM;
15213 + s.iomem_reg_shift = reg_shift;
15214 +
15215 + if (early_serial_setup(&s) != 0) {
15216 + printk(KERN_ERR "Serial setup failed!\n");
15217 + }
15218 +}
15219 +
15220 +#endif /* CONFIG_SERIAL */
15221 +
15222 +void __init
15223 +brcm_setup(void)
15224 +{
15225 + char *s;
15226 + int i;
15227 + char *value;
15228 +
15229 + /* Get global SB handle */
15230 + sbh = sb_kattach();
15231 +
15232 + /* Initialize clocks and interrupts */
15233 + sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
15234 +
15235 + if (BCM330X(current_cpu_data.processor_id) &&
15236 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
15237 + /*
15238 + * Now that the sbh is inited set the proper PFC value
15239 + */
15240 + printk("Setting the PFC to its default value\n");
15241 + enable_pfc(PFC_AUTO);
15242 + }
15243 +
15244 +
15245 +#ifdef CONFIG_SERIAL
15246 + sb_serial_init(sbh, serial_add);
15247 +
15248 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
15249 + /* Initialize UARTs */
15250 + s = nvram_get("kernel_args");
15251 + if (!s) s = "";
15252 + if (!strncmp(s, "console=ttyS1", 13)) {
15253 + for (i = num_ports; i; i--)
15254 + do_serial_add(&ports[i - 1]);
15255 + } else {
15256 + for (i = 0; i < num_ports; i++)
15257 + do_serial_add(&ports[i]);
15258 + }
15259 +#endif
15260 +
15261 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15262 + ide_ops = &std_ide_ops;
15263 +#endif
15264 +
15265 + /* Override default command line arguments */
15266 + value = nvram_get("kernel_cmdline");
15267 + if (value && strlen(value) && strncmp(value, "empty", 5))
15268 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
15269 +
15270 +
15271 + /* Generic setup */
15272 + _machine_restart = bcm947xx_machine_restart;
15273 + _machine_halt = bcm947xx_machine_halt;
15274 + _machine_power_off = bcm947xx_machine_halt;
15275 +
15276 + board_time_init = bcm947xx_time_init;
15277 + board_timer_setup = bcm947xx_timer_setup;
15278 +}
15279 +
15280 +const char *
15281 +get_system_type(void)
15282 +{
15283 + static char s[32];
15284 +
15285 + if (bcm947xx_sbh) {
15286 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
15287 + sb_chiprev(bcm947xx_sbh));
15288 + return s;
15289 + }
15290 + else
15291 + return "Broadcom BCM947XX";
15292 +}
15293 +
15294 +void __init
15295 +bus_error_init(void)
15296 +{
15297 +}
15298 +
15299 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
15300 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
15301 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-10-02 21:19:59.000000000 +0200
15302 @@ -0,0 +1,422 @@
15303 +/*
15304 + * Broadcom SiliconBackplane chipcommon serial flash interface
15305 + *
15306 + * Copyright 2006, Broadcom Corporation
15307 + * All Rights Reserved.
15308 + *
15309 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15310 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15311 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15312 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15313 + *
15314 + * $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
15315 + */
15316 +
15317 +#include <osl.h>
15318 +#include <typedefs.h>
15319 +#include <sbconfig.h>
15320 +#include <sbchipc.h>
15321 +#include <mipsinc.h>
15322 +#include <bcmutils.h>
15323 +#include <bcmdevs.h>
15324 +#include <sflash.h>
15325 +
15326 +/* Private global state */
15327 +static struct sflash sflash;
15328 +
15329 +/* Issue a serial flash command */
15330 +static INLINE void
15331 +sflash_cmd(chipcregs_t *cc, uint opcode)
15332 +{
15333 + W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
15334 + while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
15335 +}
15336 +
15337 +/* Initialize serial flash access */
15338 +struct sflash *
15339 +sflash_init(chipcregs_t *cc)
15340 +{
15341 + uint32 id, id2;
15342 +
15343 + bzero(&sflash, sizeof(sflash));
15344 +
15345 + sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
15346 +
15347 + switch (sflash.type) {
15348 + case SFLASH_ST:
15349 + /* Probe for ST chips */
15350 + sflash_cmd(cc, SFLASH_ST_DP);
15351 + sflash_cmd(cc, SFLASH_ST_RES);
15352 + id = R_REG(NULL, &cc->flashdata);
15353 + switch (id) {
15354 + case 0x11:
15355 + /* ST M25P20 2 Mbit Serial Flash */
15356 + sflash.blocksize = 64 * 1024;
15357 + sflash.numblocks = 4;
15358 + break;
15359 + case 0x12:
15360 + /* ST M25P40 4 Mbit Serial Flash */
15361 + sflash.blocksize = 64 * 1024;
15362 + sflash.numblocks = 8;
15363 + break;
15364 + case 0x13:
15365 + /* ST M25P80 8 Mbit Serial Flash */
15366 + sflash.blocksize = 64 * 1024;
15367 + sflash.numblocks = 16;
15368 + break;
15369 + case 0x14:
15370 + /* ST M25P16 16 Mbit Serial Flash */
15371 + sflash.blocksize = 64 * 1024;
15372 + sflash.numblocks = 32;
15373 + break;
15374 + case 0x15:
15375 + /* ST M25P32 32 Mbit Serial Flash */
15376 + sflash.blocksize = 64 * 1024;
15377 + sflash.numblocks = 64;
15378 + break;
15379 + case 0x16:
15380 + /* ST M25P64 64 Mbit Serial Flash */
15381 + sflash.blocksize = 64 * 1024;
15382 + sflash.numblocks = 128;
15383 + break;
15384 + case 0xbf:
15385 + W_REG(NULL, &cc->flashaddress, 1);
15386 + sflash_cmd(cc, SFLASH_ST_RES);
15387 + id2 = R_REG(NULL, &cc->flashdata);
15388 + if (id2 == 0x44) {
15389 + /* SST M25VF80 4 Mbit Serial Flash */
15390 + sflash.blocksize = 64 * 1024;
15391 + sflash.numblocks = 8;
15392 + }
15393 + break;
15394 + }
15395 + break;
15396 +
15397 + case SFLASH_AT:
15398 + /* Probe for Atmel chips */
15399 + sflash_cmd(cc, SFLASH_AT_STATUS);
15400 + id = R_REG(NULL, &cc->flashdata) & 0x3c;
15401 + switch (id) {
15402 + case 0xc:
15403 + /* Atmel AT45DB011 1Mbit Serial Flash */
15404 + sflash.blocksize = 256;
15405 + sflash.numblocks = 512;
15406 + break;
15407 + case 0x14:
15408 + /* Atmel AT45DB021 2Mbit Serial Flash */
15409 + sflash.blocksize = 256;
15410 + sflash.numblocks = 1024;
15411 + break;
15412 + case 0x1c:
15413 + /* Atmel AT45DB041 4Mbit Serial Flash */
15414 + sflash.blocksize = 256;
15415 + sflash.numblocks = 2048;
15416 + break;
15417 + case 0x24:
15418 + /* Atmel AT45DB081 8Mbit Serial Flash */
15419 + sflash.blocksize = 256;
15420 + sflash.numblocks = 4096;
15421 + break;
15422 + case 0x2c:
15423 + /* Atmel AT45DB161 16Mbit Serial Flash */
15424 + sflash.blocksize = 512;
15425 + sflash.numblocks = 4096;
15426 + break;
15427 + case 0x34:
15428 + /* Atmel AT45DB321 32Mbit Serial Flash */
15429 + sflash.blocksize = 512;
15430 + sflash.numblocks = 8192;
15431 + break;
15432 + case 0x3c:
15433 + /* Atmel AT45DB642 64Mbit Serial Flash */
15434 + sflash.blocksize = 1024;
15435 + sflash.numblocks = 8192;
15436 + break;
15437 + }
15438 + break;
15439 + }
15440 +
15441 + sflash.size = sflash.blocksize * sflash.numblocks;
15442 + return sflash.size ? &sflash : NULL;
15443 +}
15444 +
15445 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
15446 +int
15447 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
15448 +{
15449 + int cnt;
15450 + uint32 *from, *to;
15451 +
15452 + if (!len)
15453 + return 0;
15454 +
15455 + if ((offset + len) > sflash.size)
15456 + return -22;
15457 +
15458 + if ((len >= 4) && (offset & 3))
15459 + cnt = 4 - (offset & 3);
15460 + else if ((len >= 4) && ((uint32)buf & 3))
15461 + cnt = 4 - ((uint32)buf & 3);
15462 + else
15463 + cnt = len;
15464 +
15465 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
15466 + to = (uint32 *)buf;
15467 +
15468 + if (cnt < 4) {
15469 + bcopy(from, to, cnt);
15470 + return cnt;
15471 + }
15472 +
15473 + while (cnt >= 4) {
15474 + *to++ = *from++;
15475 + cnt -= 4;
15476 + }
15477 +
15478 + return (len - cnt);
15479 +}
15480 +
15481 +/* Poll for command completion. Returns zero when complete. */
15482 +int
15483 +sflash_poll(chipcregs_t *cc, uint offset)
15484 +{
15485 + if (offset >= sflash.size)
15486 + return -22;
15487 +
15488 + switch (sflash.type) {
15489 + case SFLASH_ST:
15490 + /* Check for ST Write In Progress bit */
15491 + sflash_cmd(cc, SFLASH_ST_RDSR);
15492 + return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
15493 + case SFLASH_AT:
15494 + /* Check for Atmel Ready bit */
15495 + sflash_cmd(cc, SFLASH_AT_STATUS);
15496 + return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
15497 + }
15498 +
15499 + return 0;
15500 +}
15501 +
15502 +/* Write len bytes starting at offset into buf. Returns number of bytes
15503 + * written. Caller should poll for completion.
15504 + */
15505 +int
15506 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15507 +{
15508 + struct sflash *sfl;
15509 + int ret = 0;
15510 + bool is4712b0;
15511 + uint32 page, byte, mask;
15512 +
15513 + if (!len)
15514 + return 0;
15515 +
15516 + if ((offset + len) > sflash.size)
15517 + return -22;
15518 +
15519 + sfl = &sflash;
15520 + switch (sfl->type) {
15521 + case SFLASH_ST:
15522 + mask = R_REG(NULL, &cc->chipid);
15523 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
15524 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
15525 + /* Enable writes */
15526 + sflash_cmd(cc, SFLASH_ST_WREN);
15527 + if (is4712b0) {
15528 + mask = 1 << 14;
15529 + W_REG(NULL, &cc->flashaddress, offset);
15530 + W_REG(NULL, &cc->flashdata, *buf++);
15531 + /* Set chip select */
15532 + OR_REG(NULL, &cc->gpioout, mask);
15533 + /* Issue a page program with the first byte */
15534 + sflash_cmd(cc, SFLASH_ST_PP);
15535 + ret = 1;
15536 + offset++;
15537 + len--;
15538 + while (len > 0) {
15539 + if ((offset & 255) == 0) {
15540 + /* Page boundary, drop cs and return */
15541 + AND_REG(NULL, &cc->gpioout, ~mask);
15542 + if (!sflash_poll(cc, offset)) {
15543 + /* Flash rejected command */
15544 + return -11;
15545 + }
15546 + return ret;
15547 + } else {
15548 + /* Write single byte */
15549 + sflash_cmd(cc, *buf++);
15550 + }
15551 + ret++;
15552 + offset++;
15553 + len--;
15554 + }
15555 + /* All done, drop cs if needed */
15556 + if ((offset & 255) != 1) {
15557 + /* Drop cs */
15558 + AND_REG(NULL, &cc->gpioout, ~mask);
15559 + if (!sflash_poll(cc, offset)) {
15560 + /* Flash rejected command */
15561 + return -12;
15562 + }
15563 + }
15564 + } else {
15565 + ret = 1;
15566 + W_REG(NULL, &cc->flashaddress, offset);
15567 + W_REG(NULL, &cc->flashdata, *buf);
15568 + /* Page program */
15569 + sflash_cmd(cc, SFLASH_ST_PP);
15570 + }
15571 + break;
15572 + case SFLASH_AT:
15573 + mask = sfl->blocksize - 1;
15574 + page = (offset & ~mask) << 1;
15575 + byte = offset & mask;
15576 + /* Read main memory page into buffer 1 */
15577 + if (byte || (len < sfl->blocksize)) {
15578 + W_REG(NULL, &cc->flashaddress, page);
15579 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
15580 + /* 250 us for AT45DB321B */
15581 + SPINWAIT(sflash_poll(cc, offset), 1000);
15582 + ASSERT(!sflash_poll(cc, offset));
15583 + }
15584 + /* Write into buffer 1 */
15585 + for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
15586 + W_REG(NULL, &cc->flashaddress, byte++);
15587 + W_REG(NULL, &cc->flashdata, *buf++);
15588 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
15589 + }
15590 + /* Write buffer 1 into main memory page */
15591 + W_REG(NULL, &cc->flashaddress, page);
15592 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
15593 + break;
15594 + }
15595 +
15596 + return ret;
15597 +}
15598 +
15599 +/* Erase a region. Returns number of bytes scheduled for erasure.
15600 + * Caller should poll for completion.
15601 + */
15602 +int
15603 +sflash_erase(chipcregs_t *cc, uint offset)
15604 +{
15605 + struct sflash *sfl;
15606 +
15607 + if (offset >= sflash.size)
15608 + return -22;
15609 +
15610 + sfl = &sflash;
15611 + switch (sfl->type) {
15612 + case SFLASH_ST:
15613 + sflash_cmd(cc, SFLASH_ST_WREN);
15614 + W_REG(NULL, &cc->flashaddress, offset);
15615 + sflash_cmd(cc, SFLASH_ST_SE);
15616 + return sfl->blocksize;
15617 + case SFLASH_AT:
15618 + W_REG(NULL, &cc->flashaddress, offset << 1);
15619 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
15620 + return sfl->blocksize;
15621 + }
15622 +
15623 + return 0;
15624 +}
15625 +
15626 +/*
15627 + * writes the appropriate range of flash, a NULL buf simply erases
15628 + * the region of flash
15629 + */
15630 +int
15631 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15632 +{
15633 + struct sflash *sfl;
15634 + uchar *block = NULL, *cur_ptr, *blk_ptr;
15635 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
15636 + uint blk_offset, blk_len, copied;
15637 + int bytes, ret = 0;
15638 +
15639 + /* Check address range */
15640 + if (len <= 0)
15641 + return 0;
15642 +
15643 + sfl = &sflash;
15644 + if ((offset + len) > sfl->size)
15645 + return -1;
15646 +
15647 + blocksize = sfl->blocksize;
15648 + mask = blocksize - 1;
15649 +
15650 + /* Allocate a block of mem */
15651 + if (!(block = MALLOC(NULL, blocksize)))
15652 + return -1;
15653 +
15654 + while (len) {
15655 + /* Align offset */
15656 + cur_offset = offset & ~mask;
15657 + cur_length = blocksize;
15658 + cur_ptr = block;
15659 +
15660 + remainder = blocksize - (offset & mask);
15661 + if (len < remainder)
15662 + cur_retlen = len;
15663 + else
15664 + cur_retlen = remainder;
15665 +
15666 + /* buf == NULL means erase only */
15667 + if (buf) {
15668 + /* Copy existing data into holding block if necessary */
15669 + if ((offset & mask) || (len < blocksize)) {
15670 + blk_offset = cur_offset;
15671 + blk_len = cur_length;
15672 + blk_ptr = cur_ptr;
15673 +
15674 + /* Copy entire block */
15675 + while (blk_len) {
15676 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
15677 + blk_offset += copied;
15678 + blk_len -= copied;
15679 + blk_ptr += copied;
15680 + }
15681 + }
15682 +
15683 + /* Copy input data into holding block */
15684 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
15685 + }
15686 +
15687 + /* Erase block */
15688 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
15689 + goto done;
15690 + while (sflash_poll(cc, (uint) cur_offset));
15691 +
15692 + /* buf == NULL means erase only */
15693 + if (!buf) {
15694 + offset += cur_retlen;
15695 + len -= cur_retlen;
15696 + continue;
15697 + }
15698 +
15699 + /* Write holding block */
15700 + while (cur_length > 0) {
15701 + if ((bytes = sflash_write(cc,
15702 + (uint) cur_offset,
15703 + (uint) cur_length,
15704 + (uchar *) cur_ptr)) < 0) {
15705 + ret = bytes;
15706 + goto done;
15707 + }
15708 + while (sflash_poll(cc, (uint) cur_offset));
15709 + cur_offset += bytes;
15710 + cur_length -= bytes;
15711 + cur_ptr += bytes;
15712 + }
15713 +
15714 + offset += cur_retlen;
15715 + len -= cur_retlen;
15716 + buf += cur_retlen;
15717 + }
15718 +
15719 + ret = len;
15720 +done:
15721 + if (block)
15722 + MFREE(NULL, block, blocksize);
15723 + return ret;
15724 +}
15725 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
15726 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
15727 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-10-02 21:19:59.000000000 +0200
15728 @@ -0,0 +1,104 @@
15729 +/*
15730 + * Copyright 2006, Broadcom Corporation
15731 + * All Rights Reserved.
15732 + *
15733 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15734 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15735 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15736 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15737 + *
15738 + * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
15739 + */
15740 +#include <linux/config.h>
15741 +#include <linux/init.h>
15742 +#include <linux/kernel.h>
15743 +#include <linux/sched.h>
15744 +#include <linux/serial_reg.h>
15745 +#include <linux/interrupt.h>
15746 +#include <asm/addrspace.h>
15747 +#include <asm/io.h>
15748 +#include <asm/time.h>
15749 +
15750 +#include <typedefs.h>
15751 +#include <osl.h>
15752 +#include <bcmnvram.h>
15753 +#include <sbconfig.h>
15754 +#include <sbextif.h>
15755 +#include <sbutils.h>
15756 +#include <hndmips.h>
15757 +#include <mipsinc.h>
15758 +#include <hndcpu.h>
15759 +
15760 +/* Global SB handle */
15761 +extern void *bcm947xx_sbh;
15762 +extern spinlock_t bcm947xx_sbh_lock;
15763 +
15764 +/* Convenience */
15765 +#define sbh bcm947xx_sbh
15766 +#define sbh_lock bcm947xx_sbh_lock
15767 +
15768 +extern int panic_timeout;
15769 +static int watchdog = 0;
15770 +static u8 *mcr = NULL;
15771 +
15772 +void __init
15773 +bcm947xx_time_init(void)
15774 +{
15775 + unsigned int hz;
15776 + extifregs_t *eir;
15777 +
15778 + /*
15779 + * Use deterministic values for initial counter interrupt
15780 + * so that calibrate delay avoids encountering a counter wrap.
15781 + */
15782 + write_c0_count(0);
15783 + write_c0_compare(0xffff);
15784 +
15785 + if (!(hz = sb_cpu_clock(sbh)))
15786 + hz = 100000000;
15787 +
15788 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
15789 + (hz + 500000) / 1000000);
15790 +
15791 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
15792 + mips_hpt_frequency = hz / 2;
15793 +
15794 + /* Set watchdog interval in ms */
15795 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
15796 +
15797 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
15798 + if (watchdog > 0) {
15799 + if (watchdog < 3000)
15800 + watchdog = 3000;
15801 + }
15802 +
15803 + /* Set panic timeout in seconds */
15804 + panic_timeout = watchdog / 1000;
15805 +}
15806 +
15807 +static void
15808 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15809 +{
15810 + /* Generic MIPS timer code */
15811 + timer_interrupt(irq, dev_id, regs);
15812 +
15813 + /* Set the watchdog timer to reset after the specified number of ms */
15814 + if (watchdog > 0)
15815 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
15816 +}
15817 +
15818 +static struct irqaction bcm947xx_timer_irqaction = {
15819 + bcm947xx_timer_interrupt,
15820 + SA_INTERRUPT,
15821 + 0,
15822 + "timer",
15823 + NULL,
15824 + NULL
15825 +};
15826 +
15827 +void __init
15828 +bcm947xx_timer_setup(struct irqaction *irq)
15829 +{
15830 + /* Enable the timer interrupt */
15831 + setup_irq(7, &bcm947xx_timer_irqaction);
15832 +}
15833 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
15834 --- linux.old/arch/mips/config-shared.in 2006-10-02 21:23:10.000000000 +0200
15835 +++ linux.dev/arch/mips/config-shared.in 2006-10-02 21:19:59.000000000 +0200
15836 @@ -208,6 +208,14 @@
15837 fi
15838 define_bool CONFIG_MIPS_RTC y
15839 fi
15840 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
15841 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
15842 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15843 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
15844 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
15845 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
15846 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
15847 +fi
15848 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
15849 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
15850 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
15851 @@ -229,6 +237,11 @@
15852 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
15853
15854 #
15855 +# Provide an option for a default kernel command line
15856 +#
15857 +string 'Default kernel command string' CONFIG_CMDLINE ""
15858 +
15859 +#
15860 # Select some configuration options automatically based on user selections.
15861 #
15862 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
15863 @@ -554,6 +567,12 @@
15864 define_bool CONFIG_SWAP_IO_SPACE_L y
15865 define_bool CONFIG_BOOT_ELF32 y
15866 fi
15867 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15868 + define_bool CONFIG_PCI y
15869 + define_bool CONFIG_NONCOHERENT_IO y
15870 + define_bool CONFIG_NEW_TIME_C y
15871 + define_bool CONFIG_NEW_IRQ y
15872 +fi
15873 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
15874 define_bool CONFIG_ARC32 y
15875 define_bool CONFIG_ARC_MEMORY y
15876 @@ -1042,7 +1061,11 @@
15877
15878 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
15879 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
15880 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
15881 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15882 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
15883 +else
15884 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
15885 +fi
15886 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
15887 if [ "$CONFIG_KGDB" = "y" ]; then
15888 define_bool CONFIG_DEBUG_INFO y
15889 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
15890 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-10-02 21:23:10.000000000 +0200
15891 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-10-02 21:19:59.000000000 +0200
15892 @@ -162,7 +162,7 @@
15893
15894 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
15895 {
15896 - switch (c->processor_id & 0xff00) {
15897 + switch (c->processor_id & PRID_IMP_MASK) {
15898 case PRID_IMP_R2000:
15899 c->cputype = CPU_R2000;
15900 c->isa_level = MIPS_CPU_ISA_I;
15901 @@ -172,7 +172,7 @@
15902 c->tlbsize = 64;
15903 break;
15904 case PRID_IMP_R3000:
15905 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
15906 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
15907 if (cpu_has_confreg())
15908 c->cputype = CPU_R3081E;
15909 else
15910 @@ -187,12 +187,12 @@
15911 break;
15912 case PRID_IMP_R4000:
15913 if (read_c0_config() & CONF_SC) {
15914 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15915 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15916 c->cputype = CPU_R4400PC;
15917 else
15918 c->cputype = CPU_R4000PC;
15919 } else {
15920 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15921 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15922 c->cputype = CPU_R4400SC;
15923 else
15924 c->cputype = CPU_R4000SC;
15925 @@ -438,7 +438,7 @@
15926 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
15927 {
15928 decode_config1(c);
15929 - switch (c->processor_id & 0xff00) {
15930 + switch (c->processor_id & PRID_IMP_MASK) {
15931 case PRID_IMP_4KC:
15932 c->cputype = CPU_4KC;
15933 c->isa_level = MIPS_CPU_ISA_M32;
15934 @@ -479,10 +479,10 @@
15935 {
15936 decode_config1(c);
15937 c->options |= MIPS_CPU_PREFETCH;
15938 - switch (c->processor_id & 0xff00) {
15939 + switch (c->processor_id & PRID_IMP_MASK) {
15940 case PRID_IMP_AU1_REV1:
15941 case PRID_IMP_AU1_REV2:
15942 - switch ((c->processor_id >> 24) & 0xff) {
15943 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
15944 case 0:
15945 c->cputype = CPU_AU1000;
15946 break;
15947 @@ -510,10 +510,34 @@
15948 }
15949 }
15950
15951 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
15952 +{
15953 + decode_config1(c);
15954 + c->options |= MIPS_CPU_PREFETCH;
15955 + switch (c->processor_id & PRID_IMP_MASK) {
15956 + case PRID_IMP_BCM4710:
15957 + c->cputype = CPU_BCM4710;
15958 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15959 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15960 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15961 + break;
15962 + case PRID_IMP_4KC:
15963 + case PRID_IMP_BCM3302:
15964 + c->cputype = CPU_BCM3302;
15965 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15966 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15967 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15968 + break;
15969 + default:
15970 + c->cputype = CPU_UNKNOWN;
15971 + break;
15972 + }
15973 +}
15974 +
15975 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
15976 {
15977 decode_config1(c);
15978 - switch (c->processor_id & 0xff00) {
15979 + switch (c->processor_id & PRID_IMP_MASK) {
15980 case PRID_IMP_SB1:
15981 c->cputype = CPU_SB1;
15982 c->isa_level = MIPS_CPU_ISA_M64;
15983 @@ -535,7 +559,7 @@
15984 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
15985 {
15986 decode_config1(c);
15987 - switch (c->processor_id & 0xff00) {
15988 + switch (c->processor_id & PRID_IMP_MASK) {
15989 case PRID_IMP_SR71000:
15990 c->cputype = CPU_SR71000;
15991 c->isa_level = MIPS_CPU_ISA_M64;
15992 @@ -560,7 +584,7 @@
15993 c->cputype = CPU_UNKNOWN;
15994
15995 c->processor_id = read_c0_prid();
15996 - switch (c->processor_id & 0xff0000) {
15997 + switch (c->processor_id & PRID_COMP_MASK) {
15998
15999 case PRID_COMP_LEGACY:
16000 cpu_probe_legacy(c);
16001 @@ -571,6 +595,9 @@
16002 case PRID_COMP_ALCHEMY:
16003 cpu_probe_alchemy(c);
16004 break;
16005 + case PRID_COMP_BROADCOM:
16006 + cpu_probe_broadcom(c);
16007 + break;
16008 case PRID_COMP_SIBYTE:
16009 cpu_probe_sibyte(c);
16010 break;
16011 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
16012 --- linux.old/arch/mips/kernel/head.S 2006-10-02 21:23:10.000000000 +0200
16013 +++ linux.dev/arch/mips/kernel/head.S 2006-10-02 21:19:59.000000000 +0200
16014 @@ -28,12 +28,20 @@
16015 #include <asm/mipsregs.h>
16016 #include <asm/stackframe.h>
16017
16018 +#ifdef CONFIG_BCM4710
16019 +#undef eret
16020 +#define eret nop; nop; eret
16021 +#endif
16022 +
16023 .text
16024 + j kernel_entry
16025 + nop
16026 +
16027 /*
16028 * Reserved space for exception handlers.
16029 * Necessary for machines which link their kernels at KSEG0.
16030 */
16031 - .fill 0x400
16032 + .fill 0x3f4
16033
16034 /* The following two symbols are used for kernel profiling. */
16035 EXPORT(stext)
16036 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
16037 --- linux.old/arch/mips/kernel/proc.c 2006-10-02 21:23:10.000000000 +0200
16038 +++ linux.dev/arch/mips/kernel/proc.c 2006-10-02 21:19:59.000000000 +0200
16039 @@ -78,9 +78,10 @@
16040 [CPU_AU1550] "Au1550",
16041 [CPU_24K] "MIPS 24K",
16042 [CPU_AU1200] "Au1200",
16043 + [CPU_BCM4710] "BCM4710",
16044 + [CPU_BCM3302] "BCM3302",
16045 };
16046
16047 -
16048 static int show_cpuinfo(struct seq_file *m, void *v)
16049 {
16050 unsigned int version = current_cpu_data.processor_id;
16051 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
16052 --- linux.old/arch/mips/kernel/setup.c 2006-10-02 21:23:10.000000000 +0200
16053 +++ linux.dev/arch/mips/kernel/setup.c 2006-10-02 21:19:59.000000000 +0200
16054 @@ -493,6 +493,7 @@
16055 void swarm_setup(void);
16056 void hp_setup(void);
16057 void au1x00_setup(void);
16058 + void brcm_setup(void);
16059 void frame_info_init(void);
16060
16061 frame_info_init();
16062 @@ -691,6 +692,11 @@
16063 pmc_yosemite_setup();
16064 break;
16065 #endif
16066 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
16067 + case MACH_GROUP_BRCM:
16068 + brcm_setup();
16069 + break;
16070 +#endif
16071 default:
16072 panic("Unsupported architecture");
16073 }
16074 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
16075 --- linux.old/arch/mips/kernel/traps.c 2006-10-02 21:23:10.000000000 +0200
16076 +++ linux.dev/arch/mips/kernel/traps.c 2006-10-02 21:19:59.000000000 +0200
16077 @@ -920,6 +920,7 @@
16078 void __init trap_init(void)
16079 {
16080 extern char except_vec1_generic;
16081 + extern char except_vec2_generic;
16082 extern char except_vec3_generic, except_vec3_r4000;
16083 extern char except_vec_ejtag_debug;
16084 extern char except_vec4;
16085 @@ -927,6 +928,7 @@
16086
16087 /* Copy the generic exception handler code to it's final destination. */
16088 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
16089 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
16090
16091 /*
16092 * Setup default vectors
16093 @@ -985,6 +987,12 @@
16094 set_except_vector(13, handle_tr);
16095 set_except_vector(22, handle_mdmx);
16096
16097 + if (current_cpu_data.cputype == CPU_SB1) {
16098 + /* Enable timer interrupt and scd mapped interrupt */
16099 + clear_c0_status(0xf000);
16100 + set_c0_status(0xc00);
16101 + }
16102 +
16103 if (cpu_has_fpu && !cpu_has_nofpuex)
16104 set_except_vector(15, handle_fpe);
16105
16106 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
16107 --- linux.old/arch/mips/Makefile 2006-10-02 21:23:10.000000000 +0200
16108 +++ linux.dev/arch/mips/Makefile 2006-10-02 21:19:59.000000000 +0200
16109 @@ -726,6 +726,19 @@
16110 endif
16111
16112 #
16113 +# Broadcom BCM947XX variants
16114 +#
16115 +ifdef CONFIG_BCM947XX
16116 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
16117 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
16118 +LOADADDR := 0x80001000
16119 +
16120 +zImage: vmlinux
16121 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
16122 +export LOADADDR
16123 +endif
16124 +
16125 +#
16126 # Choosing incompatible machines durings configuration will result in
16127 # error messages during linking. Select a default linkscript if
16128 # none has been choosen above.
16129 @@ -778,6 +791,7 @@
16130 $(MAKE) -C arch/$(ARCH)/tools clean
16131 $(MAKE) -C arch/mips/baget clean
16132 $(MAKE) -C arch/mips/lasat clean
16133 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
16134
16135 archmrproper:
16136 @$(MAKEBOOT) mrproper
16137 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16138 --- linux.old/arch/mips/mm/c-r4k.c 2006-10-02 21:23:10.000000000 +0200
16139 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-10-02 21:19:59.000000000 +0200
16140 @@ -1166,3 +1166,47 @@
16141 build_clear_page();
16142 build_copy_page();
16143 }
16144 +
16145 +#ifdef CONFIG_BCM4704
16146 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
16147 +{
16148 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
16149 + int i;
16150 + for (i = 0; i < nbytes; i += ic_lsize)
16151 + fill_icache_line((addr + i));
16152 +}
16153 +
16154 +/*
16155 + * This must be run from the cache on 4704A0
16156 + * so there are no mips core BIU ops in progress
16157 + * when the PFC is enabled.
16158 + */
16159 +#define PFC_CR0 0xff400000 /* control reg 0 */
16160 +#define PFC_CR1 0xff400004 /* control reg 1 */
16161 +static void __init enable_pfc(u32 mode)
16162 +{
16163 + /* write range */
16164 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
16165 +
16166 + /* enable */
16167 + *(volatile u32 *)PFC_CR0 = mode;
16168 +}
16169 +#endif
16170 +
16171 +
16172 +void check_enable_mips_pfc(int val)
16173 +{
16174 +
16175 +#ifdef CONFIG_BCM4704
16176 + struct cpuinfo_mips *c = &current_cpu_data;
16177 +
16178 + /* enable prefetch cache */
16179 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
16180 + && (read_c0_diag() & (1 << 29))) {
16181 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
16182 + enable_pfc(val);
16183 + }
16184 +#endif
16185 +}
16186 +
16187 +
16188 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
16189 --- linux.old/arch/mips/pci/Makefile 2006-10-02 21:23:10.000000000 +0200
16190 +++ linux.dev/arch/mips/pci/Makefile 2006-10-02 21:19:59.000000000 +0200
16191 @@ -13,7 +13,9 @@
16192 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
16193 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
16194 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
16195 +ifndef CONFIG_BCM947XX
16196 obj-y += pci.o
16197 +endif
16198 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
16199
16200 include $(TOPDIR)/Rules.make
16201 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
16202 --- linux.old/drivers/char/serial.c 2006-10-02 21:23:10.000000000 +0200
16203 +++ linux.dev/drivers/char/serial.c 2006-10-02 21:19:59.000000000 +0200
16204 @@ -444,6 +444,10 @@
16205 return inb(info->port+1);
16206 #endif
16207 case SERIAL_IO_MEM:
16208 +#ifdef CONFIG_BCM4310
16209 + readb((unsigned long) info->iomem_base +
16210 + (UART_SCR<<info->iomem_reg_shift));
16211 +#endif
16212 return readb((unsigned long) info->iomem_base +
16213 (offset<<info->iomem_reg_shift));
16214 default:
16215 @@ -464,6 +468,9 @@
16216 case SERIAL_IO_MEM:
16217 writeb(value, (unsigned long) info->iomem_base +
16218 (offset<<info->iomem_reg_shift));
16219 +#ifdef CONFIG_BCM4704
16220 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
16221 +#endif
16222 break;
16223 default:
16224 outb(value, info->port+offset);
16225 @@ -1728,7 +1735,7 @@
16226 /* Special case since 134 is really 134.5 */
16227 quot = (2*baud_base / 269);
16228 else if (baud)
16229 - quot = baud_base / baud;
16230 + quot = (baud_base + (baud / 2)) / baud;
16231 }
16232 /* If the quotient is zero refuse the change */
16233 if (!quot && old_termios) {
16234 @@ -1745,12 +1752,12 @@
16235 /* Special case since 134 is really 134.5 */
16236 quot = (2*baud_base / 269);
16237 else if (baud)
16238 - quot = baud_base / baud;
16239 + quot = (baud_base + (baud / 2)) / baud;
16240 }
16241 }
16242 /* As a last resort, if the quotient is zero, default to 9600 bps */
16243 if (!quot)
16244 - quot = baud_base / 9600;
16245 + quot = (baud_base + 4800) / 9600;
16246 /*
16247 * Work around a bug in the Oxford Semiconductor 952 rev B
16248 * chip which causes it to seriously miscalculate baud rates
16249 @@ -5994,6 +6001,13 @@
16250 * Divisor, bytesize and parity
16251 */
16252 state = rs_table + co->index;
16253 + /*
16254 + * Safe guard: state structure must have been initialized
16255 + */
16256 + if (state->iomem_base == NULL) {
16257 + printk("!unable to setup serial console!\n");
16258 + return -1;
16259 + }
16260 if (doflow)
16261 state->flags |= ASYNC_CONS_FLOW;
16262 info = &async_sercons;
16263 @@ -6007,7 +6021,7 @@
16264 info->io_type = state->io_type;
16265 info->iomem_base = state->iomem_base;
16266 info->iomem_reg_shift = state->iomem_reg_shift;
16267 - quot = state->baud_base / baud;
16268 + quot = (state->baud_base + (baud / 2)) / baud;
16269 cval = cflag & (CSIZE | CSTOPB);
16270 #if defined(__powerpc__) || defined(__alpha__)
16271 cval >>= 8;
16272 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
16273 --- linux.old/drivers/net/Makefile 2006-10-02 21:23:10.000000000 +0200
16274 +++ linux.dev/drivers/net/Makefile 2006-10-02 21:19:59.000000000 +0200
16275 @@ -3,6 +3,8 @@
16276 # Makefile for the Linux network (ethercard) device drivers.
16277 #
16278
16279 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
16280 +
16281 obj-y :=
16282 obj-m :=
16283 obj-n :=
16284 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
16285 --- linux.old/drivers/parport/Config.in 2006-10-02 21:23:10.000000000 +0200
16286 +++ linux.dev/drivers/parport/Config.in 2006-10-02 21:19:59.000000000 +0200
16287 @@ -11,6 +11,7 @@
16288 tristate 'Parallel port support' CONFIG_PARPORT
16289 if [ "$CONFIG_PARPORT" != "n" ]; then
16290 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
16291 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
16292 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
16293 if [ "$CONFIG_SERIAL" = "m" ]; then
16294 define_tristate CONFIG_PARPORT_PC_CML1 m
16295 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
16296 --- linux.old/drivers/parport/Makefile 2006-10-02 21:23:10.000000000 +0200
16297 +++ linux.dev/drivers/parport/Makefile 2006-10-02 21:19:59.000000000 +0200
16298 @@ -22,6 +22,7 @@
16299
16300 obj-$(CONFIG_PARPORT) += parport.o
16301 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
16302 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
16303 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
16304 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
16305 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
16306 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
16307 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
16308 +++ linux.dev/drivers/parport/parport_splink.c 2006-10-02 21:19:59.000000000 +0200
16309 @@ -0,0 +1,345 @@
16310 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
16311 + *
16312 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
16313 + * Based on parport_pc source
16314 + */
16315 +
16316 +#include <linux/config.h>
16317 +#include <linux/module.h>
16318 +#include <linux/init.h>
16319 +#include <linux/ioport.h>
16320 +#include <linux/kernel.h>
16321 +#include <linux/slab.h>
16322 +#include <linux/parport.h>
16323 +#include <linux/parport_pc.h>
16324 +
16325 +#define SPLINK_ADDRESS 0xBF800010
16326 +
16327 +#undef DEBUG
16328 +
16329 +#ifdef DEBUG
16330 +#define DPRINTK printk
16331 +#else
16332 +#define DPRINTK(stuff...)
16333 +#endif
16334 +
16335 +
16336 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
16337 + * it doesn't do any extra masking. */
16338 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
16339 + unsigned char mask,
16340 + unsigned char val)
16341 +{
16342 + struct parport_pc_private *priv = p->physport->private_data;
16343 + unsigned char *io = (unsigned char *) p->base;
16344 + unsigned char ctr = priv->ctr;
16345 +#ifdef DEBUG_PARPORT
16346 + printk (KERN_DEBUG
16347 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
16348 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
16349 +#endif
16350 + ctr = (ctr & ~mask) ^ val;
16351 + ctr &= priv->ctr_writable; /* only write writable bits. */
16352 + *(io+2) = ctr;
16353 + priv->ctr = ctr; /* Update soft copy */
16354 + return ctr;
16355 +}
16356 +
16357 +
16358 +
16359 +static void parport_splink_data_forward (struct parport *p)
16360 +{
16361 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16362 + __parport_splink_frob_control (p, 0x20, 0);
16363 +}
16364 +
16365 +static void parport_splink_data_reverse (struct parport *p)
16366 +{
16367 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16368 + __parport_splink_frob_control (p, 0x20, 0x20);
16369 +}
16370 +
16371 +/*
16372 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
16373 +{
16374 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
16375 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
16376 +}
16377 +*/
16378 +
16379 +static void parport_splink_enable_irq(struct parport *p)
16380 +{
16381 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
16382 + __parport_splink_frob_control (p, 0x10, 0x10);
16383 +}
16384 +
16385 +static void parport_splink_disable_irq(struct parport *p)
16386 +{
16387 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
16388 + __parport_splink_frob_control (p, 0x10, 0);
16389 +}
16390 +
16391 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
16392 +{
16393 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
16394 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
16395 + if (dev->irq_func &&
16396 + dev->port->irq != PARPORT_IRQ_NONE)
16397 + /* Set ackIntEn */
16398 + s->u.pc.ctr |= 0x10;
16399 +}
16400 +
16401 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
16402 +{
16403 + const struct parport_pc_private *priv = p->physport->private_data;
16404 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
16405 + s->u.pc.ctr = priv->ctr;
16406 +}
16407 +
16408 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
16409 +{
16410 + struct parport_pc_private *priv = p->physport->private_data;
16411 + unsigned char *io = (unsigned char *) p->base;
16412 + unsigned char ctr = s->u.pc.ctr;
16413 +
16414 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
16415 + *(io+2) = ctr;
16416 + priv->ctr = ctr;
16417 +}
16418 +
16419 +static void parport_splink_setup_interrupt(void) {
16420 + return;
16421 +}
16422 +
16423 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
16424 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
16425 + unsigned char *io = (unsigned char *) p->base;
16426 + *io = d;
16427 +}
16428 +
16429 +static unsigned char parport_splink_read_data(struct parport *p) {
16430 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
16431 + unsigned char *io = (unsigned char *) p->base;
16432 + return *io;
16433 +}
16434 +
16435 +static void parport_splink_write_control(struct parport *p, unsigned char d)
16436 +{
16437 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16438 + PARPORT_CONTROL_AUTOFD |
16439 + PARPORT_CONTROL_INIT |
16440 + PARPORT_CONTROL_SELECT);
16441 +
16442 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
16443 + /* Take this out when drivers have adapted to the newer interface. */
16444 + if (d & 0x20) {
16445 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
16446 + p->name, p->cad->name);
16447 + parport_splink_data_reverse (p);
16448 + }
16449 +
16450 + __parport_splink_frob_control (p, wm, d & wm);
16451 +}
16452 +
16453 +static unsigned char parport_splink_read_control(struct parport *p)
16454 +{
16455 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16456 + PARPORT_CONTROL_AUTOFD |
16457 + PARPORT_CONTROL_INIT |
16458 + PARPORT_CONTROL_SELECT);
16459 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
16460 + const struct parport_pc_private *priv = p->physport->private_data;
16461 + return priv->ctr & wm; /* Use soft copy */
16462 +}
16463 +
16464 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
16465 + unsigned char val)
16466 +{
16467 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16468 + PARPORT_CONTROL_AUTOFD |
16469 + PARPORT_CONTROL_INIT |
16470 + PARPORT_CONTROL_SELECT);
16471 +
16472 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
16473 + /* Take this out when drivers have adapted to the newer interface. */
16474 + if (mask & 0x20) {
16475 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
16476 + p->name, p->cad->name,
16477 + (val & 0x20) ? "reverse" : "forward");
16478 + if (val & 0x20)
16479 + parport_splink_data_reverse (p);
16480 + else
16481 + parport_splink_data_forward (p);
16482 + }
16483 +
16484 + /* Restrict mask and val to control lines. */
16485 + mask &= wm;
16486 + val &= wm;
16487 +
16488 + return __parport_splink_frob_control (p, mask, val);
16489 +}
16490 +
16491 +static unsigned char parport_splink_read_status(struct parport *p)
16492 +{
16493 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
16494 + unsigned char *io = (unsigned char *) p->base;
16495 + return *(io+1);
16496 +}
16497 +
16498 +static void parport_splink_inc_use_count(void)
16499 +{
16500 +#ifdef MODULE
16501 + MOD_INC_USE_COUNT;
16502 +#endif
16503 +}
16504 +
16505 +static void parport_splink_dec_use_count(void)
16506 +{
16507 +#ifdef MODULE
16508 + MOD_DEC_USE_COUNT;
16509 +#endif
16510 +}
16511 +
16512 +static struct parport_operations parport_splink_ops =
16513 +{
16514 + parport_splink_write_data,
16515 + parport_splink_read_data,
16516 +
16517 + parport_splink_write_control,
16518 + parport_splink_read_control,
16519 + parport_splink_frob_control,
16520 +
16521 + parport_splink_read_status,
16522 +
16523 + parport_splink_enable_irq,
16524 + parport_splink_disable_irq,
16525 +
16526 + parport_splink_data_forward,
16527 + parport_splink_data_reverse,
16528 +
16529 + parport_splink_init_state,
16530 + parport_splink_save_state,
16531 + parport_splink_restore_state,
16532 +
16533 + parport_splink_inc_use_count,
16534 + parport_splink_dec_use_count,
16535 +
16536 + parport_ieee1284_epp_write_data,
16537 + parport_ieee1284_epp_read_data,
16538 + parport_ieee1284_epp_write_addr,
16539 + parport_ieee1284_epp_read_addr,
16540 +
16541 + parport_ieee1284_ecp_write_data,
16542 + parport_ieee1284_ecp_read_data,
16543 + parport_ieee1284_ecp_write_addr,
16544 +
16545 + parport_ieee1284_write_compat,
16546 + parport_ieee1284_read_nibble,
16547 + parport_ieee1284_read_byte,
16548 +};
16549 +
16550 +/* --- Initialisation code -------------------------------- */
16551 +
16552 +static struct parport *parport_splink_probe_port (unsigned long int base)
16553 +{
16554 + struct parport_pc_private *priv;
16555 + struct parport_operations *ops;
16556 + struct parport *p;
16557 +
16558 + if (check_mem_region(base, 3)) {
16559 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
16560 + return NULL;
16561 + }
16562 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
16563 + if (!priv) {
16564 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
16565 + return NULL;
16566 + }
16567 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
16568 + if (!ops) {
16569 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
16570 + base);
16571 + kfree (priv);
16572 + return NULL;
16573 + }
16574 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
16575 + priv->ctr = 0xc;
16576 + priv->ctr_writable = 0xff;
16577 +
16578 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
16579 + PARPORT_DMA_NONE, ops))) {
16580 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
16581 + base);
16582 + kfree (priv);
16583 + kfree (ops);
16584 + return NULL;
16585 + }
16586 +
16587 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
16588 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
16589 + p->private_data = priv;
16590 +
16591 + parport_proc_register(p);
16592 + request_mem_region (p->base, 3, p->name);
16593 +
16594 + /* Done probing. Now put the port into a sensible start-up state. */
16595 + parport_splink_write_data(p, 0);
16596 + parport_splink_data_forward (p);
16597 +
16598 + /* Now that we've told the sharing engine about the port, and
16599 + found out its characteristics, let the high-level drivers
16600 + know about it. */
16601 + parport_announce_port (p);
16602 +
16603 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
16604 + base);
16605 + return p;
16606 +}
16607 +
16608 +static void parport_splink_unregister_port(struct parport *p) {
16609 + struct parport_pc_private *priv = p->private_data;
16610 + struct parport_operations *ops = p->ops;
16611 +
16612 + if (p->irq != PARPORT_IRQ_NONE)
16613 + free_irq(p->irq, p);
16614 + release_mem_region(p->base, 3);
16615 + parport_proc_unregister(p);
16616 + kfree (priv);
16617 + parport_unregister_port(p);
16618 + kfree (ops);
16619 +}
16620 +
16621 +
16622 +int parport_splink_init(void)
16623 +{
16624 + int ret;
16625 +
16626 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
16627 + parport_splink_setup_interrupt();
16628 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
16629 +
16630 + return ret;
16631 +}
16632 +
16633 +void parport_splink_cleanup(void) {
16634 + struct parport *p = parport_enumerate(), *tmp;
16635 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
16636 + if (p->size) {
16637 + if (p->modes & PARPORT_MODE_PCSPP) {
16638 + while(p) {
16639 + tmp = p->next;
16640 + parport_splink_unregister_port(p);
16641 + p = tmp;
16642 + }
16643 + }
16644 + }
16645 +}
16646 +
16647 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
16648 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
16649 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
16650 +MODULE_LICENSE("GPL");
16651 +
16652 +module_init(parport_splink_init)
16653 +module_exit(parport_splink_cleanup)
16654 +
16655 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
16656 --- linux.old/include/asm-mips/bootinfo.h 2006-10-02 21:23:10.000000000 +0200
16657 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-02 21:19:59.000000000 +0200
16658 @@ -37,6 +37,7 @@
16659 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
16660 #define MACH_GROUP_LASAT 21
16661 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
16662 +#define MACH_GROUP_BRCM 23 /* Broadcom */
16663
16664 /*
16665 * Valid machtype values for group unknown (low order halfword of mips_machtype)
16666 @@ -197,6 +198,15 @@
16667 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
16668
16669 /*
16670 + * Valid machtypes for group Broadcom
16671 + */
16672 +#define MACH_BCM93725 0
16673 +#define MACH_BCM93725_VJ 1
16674 +#define MACH_BCM93730 2
16675 +#define MACH_BCM947XX 3
16676 +#define MACH_BCM933XX 4
16677 +
16678 +/*
16679 * Valid machtype for group TITAN
16680 */
16681 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
16682 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
16683 --- linux.old/include/asm-mips/cpu.h 2006-10-02 21:23:10.000000000 +0200
16684 +++ linux.dev/include/asm-mips/cpu.h 2006-10-02 21:19:59.000000000 +0200
16685 @@ -22,6 +22,11 @@
16686 spec.
16687 */
16688
16689 +#define PRID_COPT_MASK 0xff000000
16690 +#define PRID_COMP_MASK 0x00ff0000
16691 +#define PRID_IMP_MASK 0x0000ff00
16692 +#define PRID_REV_MASK 0x000000ff
16693 +
16694 #define PRID_COMP_LEGACY 0x000000
16695 #define PRID_COMP_MIPS 0x010000
16696 #define PRID_COMP_BROADCOM 0x020000
16697 @@ -58,6 +63,7 @@
16698 #define PRID_IMP_RM7000 0x2700
16699 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
16700 #define PRID_IMP_RM9000 0x3400
16701 +#define PRID_IMP_BCM4710 0x4000
16702 #define PRID_IMP_R5432 0x5400
16703 #define PRID_IMP_R5500 0x5500
16704 #define PRID_IMP_4KC 0x8000
16705 @@ -66,10 +72,16 @@
16706 #define PRID_IMP_4KEC 0x8400
16707 #define PRID_IMP_4KSC 0x8600
16708 #define PRID_IMP_25KF 0x8800
16709 +#define PRID_IMP_BCM3302 0x9000
16710 +#define PRID_IMP_BCM3303 0x9100
16711 #define PRID_IMP_24K 0x9300
16712
16713 #define PRID_IMP_UNKNOWN 0xff00
16714
16715 +#define BCM330X(id) \
16716 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
16717 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
16718 +
16719 /*
16720 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
16721 */
16722 @@ -174,7 +186,9 @@
16723 #define CPU_AU1550 57
16724 #define CPU_24K 58
16725 #define CPU_AU1200 59
16726 -#define CPU_LAST 59
16727 +#define CPU_BCM4710 60
16728 +#define CPU_BCM3302 61
16729 +#define CPU_LAST 61
16730
16731 /*
16732 * ISA Level encodings
16733 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
16734 --- linux.old/include/asm-mips/r4kcache.h 2006-10-02 21:23:10.000000000 +0200
16735 +++ linux.dev/include/asm-mips/r4kcache.h 2006-10-02 21:19:59.000000000 +0200
16736 @@ -658,4 +658,17 @@
16737 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
16738 }
16739
16740 +extern inline void fill_icache_line(unsigned long addr)
16741 +{
16742 + __asm__ __volatile__(
16743 + ".set noreorder\n\t"
16744 + ".set mips3\n\t"
16745 + "cache %1, (%0)\n\t"
16746 + ".set mips0\n\t"
16747 + ".set reorder"
16748 + :
16749 + : "r" (addr),
16750 + "i" (Fill));
16751 +}
16752 +
16753 #endif /* __ASM_R4KCACHE_H */
16754 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
16755 --- linux.old/include/asm-mips/serial.h 2006-10-02 21:23:10.000000000 +0200
16756 +++ linux.dev/include/asm-mips/serial.h 2006-10-02 21:19:59.000000000 +0200
16757 @@ -223,6 +223,13 @@
16758 #define TXX927_SERIAL_PORT_DEFNS
16759 #endif
16760
16761 +#ifdef CONFIG_BCM947XX
16762 +/* reserve 4 ports to be configured at runtime */
16763 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
16764 +#else
16765 +#define BCM947XX_SERIAL_PORT_DEFNS
16766 +#endif
16767 +
16768 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
16769 #define STD_SERIAL_PORT_DEFNS \
16770 /* UART CLK PORT IRQ FLAGS */ \
16771 @@ -470,6 +477,7 @@
16772 #define SERIAL_PORT_DFNS \
16773 ATLAS_SERIAL_PORT_DEFNS \
16774 AU1000_SERIAL_PORT_DEFNS \
16775 + BCM947XX_SERIAL_PORT_DEFNS \
16776 COBALT_SERIAL_PORT_DEFNS \
16777 DDB5477_SERIAL_PORT_DEFNS \
16778 EV96100_SERIAL_PORT_DEFNS \
16779 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
16780 --- linux.old/init/do_mounts.c 2006-10-02 21:23:10.000000000 +0200
16781 +++ linux.dev/init/do_mounts.c 2006-10-02 21:19:59.000000000 +0200
16782 @@ -254,7 +254,13 @@
16783 { "ftlb", 0x2c08 },
16784 { "ftlc", 0x2c10 },
16785 { "ftld", 0x2c18 },
16786 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
16787 { "mtdblock", 0x1f00 },
16788 + { "mtdblock0",0x1f00 },
16789 + { "mtdblock1",0x1f01 },
16790 + { "mtdblock2",0x1f02 },
16791 + { "mtdblock3",0x1f03 },
16792 +#endif
16793 { "nb", 0x2b00 },
16794 { NULL, 0 }
16795 };
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