target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x.h

   1 /*
   2  * Ralink RT305x SoC specific definitions
   3  *
   4  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published
  10  * by the Free Software Foundation.
  11  */
  12
  13 #ifndef _RT305X_H_
  14 #define _RT305X_H_
  15
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18
  19 enum rt305x_soc_type {
  20         RT305X_SOC_UNKNOWN = 0,
  21         RT305X_SOC_RT3050,
  22         RT305X_SOC_RT3052,
  23         RT305X_SOC_RT3352,
  24 };
  25
  26 extern enum rt305x_soc_type rt305x_soc;
  27
  28 static inline int soc_is_rt3050(void)
  29 {
  30         return rt305x_soc == RT305X_SOC_RT3050;
  31 }
  32
  33 static inline int soc_is_rt3052(void)
  34 {
  35         return rt305x_soc == RT305X_SOC_RT3052;
  36 }
  37
  38 static inline int soc_is_rt305x(void)
  39 {
  40         return soc_is_rt3050() || soc_is_rt3052();
  41 }
  42
  43 static inline int soc_is_rt3352(void)
  44 {
  45         return rt305x_soc == RT305X_SOC_RT3352;
  46 }
  47
  48 #define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024)
  49 #define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024)
  50
  51 #define RT305X_CPU_IRQ_BASE     0
  52 #define RT305X_INTC_IRQ_BASE    8
  53 #define RT305X_INTC_IRQ_COUNT   32
  54 #define RT305X_GPIO_IRQ_BASE    40
  55
  56 #define RT305X_CPU_IRQ_INTC     (RT305X_CPU_IRQ_BASE + 2)
  57 #define RT305X_CPU_IRQ_FE       (RT305X_CPU_IRQ_BASE + 5)
  58 #define RT305X_CPU_IRQ_WNIC     (RT305X_CPU_IRQ_BASE + 6)
  59 #define RT305X_CPU_IRQ_COUNTER  (RT305X_CPU_IRQ_BASE + 7)
  60
  61 #define RT305X_INTC_IRQ_SYSCTL  (RT305X_INTC_IRQ_BASE + 0)
  62 #define RT305X_INTC_IRQ_TIMER0  (RT305X_INTC_IRQ_BASE + 1)
  63 #define RT305X_INTC_IRQ_TIMER1  (RT305X_INTC_IRQ_BASE + 2)
  64 #define RT305X_INTC_IRQ_IA      (RT305X_INTC_IRQ_BASE + 3)
  65 #define RT305X_INTC_IRQ_PCM     (RT305X_INTC_IRQ_BASE + 4)
  66 #define RT305X_INTC_IRQ_UART0   (RT305X_INTC_IRQ_BASE + 5)
  67 #define RT305X_INTC_IRQ_PIO     (RT305X_INTC_IRQ_BASE + 6)
  68 #define RT305X_INTC_IRQ_DMA     (RT305X_INTC_IRQ_BASE + 7)
  69 #define RT305X_INTC_IRQ_NAND    (RT305X_INTC_IRQ_BASE + 8)
  70 #define RT305X_INTC_IRQ_PERFC   (RT305X_INTC_IRQ_BASE + 9)
  71 #define RT305X_INTC_IRQ_I2S     (RT305X_INTC_IRQ_BASE + 10)
  72 #define RT305X_INTC_IRQ_UART1   (RT305X_INTC_IRQ_BASE + 12)
  73 #define RT305X_INTC_IRQ_ESW     (RT305X_INTC_IRQ_BASE + 17)
  74 #define RT305X_INTC_IRQ_OTG     (RT305X_INTC_IRQ_BASE + 18)
  75
  76 extern void __iomem *rt305x_sysc_base;
  77 extern void __iomem *rt305x_memc_base;
  78
  79 static inline void rt305x_sysc_wr(u32 val, unsigned reg)
  80 {
  81         __raw_writel(val, rt305x_sysc_base + reg);
  82 }
  83
  84 static inline u32 rt305x_sysc_rr(unsigned reg)
  85 {
  86         return __raw_readl(rt305x_sysc_base + reg);
  87 }
  88
  89 static inline void rt305x_memc_wr(u32 val, unsigned reg)
  90 {
  91         __raw_writel(val, rt305x_memc_base + reg);
  92 }
  93
  94 static inline u32 rt305x_memc_rr(unsigned reg)
  95 {
  96         return __raw_readl(rt305x_memc_base + reg);
  97 }
  98
  99 #define RT305X_GPIO_I2C_SD      1
 100 #define RT305X_GPIO_I2C_SCLK    2
 101 #define RT305X_GPIO_SPI_EN      3
 102 #define RT305X_GPIO_SPI_CLK     4
 103 #define RT305X_GPIO_SPI_DOUT    5
 104 #define RT305X_GPIO_SPI_DIN     6
 105 /* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
 106 #define RT305X_GPIO_7           7
 107 #define RT305X_GPIO_8           8
 108 #define RT305X_GPIO_9           9
 109 #define RT305X_GPIO_10          10
 110 #define RT305X_GPIO_11          11
 111 #define RT305X_GPIO_12          12
 112 #define RT305X_GPIO_13          13
 113 #define RT305X_GPIO_14          14
 114 #define RT305X_GPIO_UART1_TXD   15
 115 #define RT305X_GPIO_UART1_RXD   16
 116 #define RT305X_GPIO_JTAG_TDO    17
 117 #define RT305X_GPIO_JTAG_TDI    18
 118 #define RT305X_GPIO_JTAG_TMS    19
 119 #define RT305X_GPIO_JTAG_TCLK   20
 120 #define RT305X_GPIO_JTAG_TRST_N 21
 121 #define RT305X_GPIO_MDIO_MDC    22
 122 #define RT305X_GPIO_MDIO_MDIO   23
 123 #define RT305X_GPIO_SDRAM_MD16  24
 124 #define RT305X_GPIO_SDRAM_MD17  25
 125 #define RT305X_GPIO_SDRAM_MD18  26
 126 #define RT305X_GPIO_SDRAM_MD19  27
 127 #define RT305X_GPIO_SDRAM_MD20  28
 128 #define RT305X_GPIO_SDRAM_MD21  29
 129 #define RT305X_GPIO_SDRAM_MD22  30
 130 #define RT305X_GPIO_SDRAM_MD23  31
 131 #define RT305X_GPIO_SDRAM_MD24  32
 132 #define RT305X_GPIO_SDRAM_MD25  33
 133 #define RT305X_GPIO_SDRAM_MD26  34
 134 #define RT305X_GPIO_SDRAM_MD27  35
 135 #define RT305X_GPIO_SDRAM_MD28  36
 136 #define RT305X_GPIO_SDRAM_MD29  37
 137 #define RT305X_GPIO_SDRAM_MD30  38
 138 #define RT305X_GPIO_SDRAM_MD31  39
 139 #define RT305X_GPIO_GE0_TXD0    40
 140 #define RT305X_GPIO_GE0_TXD1    41
 141 #define RT305X_GPIO_GE0_TXD2    42
 142 #define RT305X_GPIO_GE0_TXD3    43
 143 #define RT305X_GPIO_GE0_TXEN    44
 144 #define RT305X_GPIO_GE0_TXCLK   45
 145 #define RT305X_GPIO_GE0_RXD0    46
 146 #define RT305X_GPIO_GE0_RXD1    47
 147 #define RT305X_GPIO_GE0_RXD2    48
 148 #define RT305X_GPIO_GE0_RXD3    49
 149 #define RT305X_GPIO_GE0_RXDV    50
 150 #define RT305X_GPIO_GE0_RXCLK   51
 151
 152 void rt305x_gpio_init(u32 mode);
 153
 154 #endif /* _RT305X_H_ */