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fix bcm47xx patch (remove duplicate flash chip patch)
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
2 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-08-12 19:32:05.137225512 +0200
4 @@ -0,0 +1,64 @@
5 +/*
6 + * Carsten Langgaard, carstenl@mips.com
7 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
8 + *
9 + * This program is free software; you can distribute it and/or modify it
10 + * under the terms of the GNU General Public License (Version 2) as
11 + * published by the Free Software Foundation.
12 + *
13 + * This program is distributed in the hope it will be useful, but WITHOUT
14 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 + * for more details.
17 + *
18 + * You should have received a copy of the GNU General Public License along
19 + * with this program; if not, write to the Free Software Foundation, Inc.,
20 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 + *
22 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
23 + */
24 +#include <linux/init.h>
25 +#include <linux/string.h>
26 +
27 +#include <asm/bootinfo.h>
28 +
29 +extern int prom_argc;
30 +extern int *_prom_argv;
31 +
32 +/*
33 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
34 + * This macro take care of sign extension.
35 + */
36 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
37 +
38 +char arcs_cmdline[CL_SIZE];
39 +
40 +char * __init prom_getcmdline(void)
41 +{
42 + return &(arcs_cmdline[0]);
43 +}
44 +
45 +
46 +void __init prom_init_cmdline(void)
47 +{
48 + char *cp;
49 + int actr;
50 +
51 + actr = 1; /* Always ignore argv[0] */
52 +
53 + cp = &(arcs_cmdline[0]);
54 +#ifdef CONFIG_CMDLINE_BOOL
55 + strcpy(cp, CONFIG_CMDLINE);
56 + cp += strlen(CONFIG_CMDLINE);
57 + *cp++ = ' ';
58 +#endif
59 + while(actr < prom_argc) {
60 + strcpy(cp, prom_argv(actr));
61 + cp += strlen(prom_argv(actr));
62 + *cp++ = ' ';
63 + actr++;
64 + }
65 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
66 + --cp;
67 + *cp = '\0';
68 +}
69 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
70 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
71 +++ linux.dev/arch/mips/ar7/init.c 2005-08-12 19:34:07.215666768 +0200
72 @@ -0,0 +1,182 @@
73 +/*
74 + * Carsten Langgaard, carstenl@mips.com
75 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
76 + *
77 + * This program is free software; you can distribute it and/or modify it
78 + * under the terms of the GNU General Public License (Version 2) as
79 + * published by the Free Software Foundation.
80 + *
81 + * This program is distributed in the hope it will be useful, but WITHOUT
82 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
83 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
84 + * for more details.
85 + *
86 + * You should have received a copy of the GNU General Public License along
87 + * with this program; if not, write to the Free Software Foundation, Inc.,
88 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
89 + *
90 + * PROM library initialisation code.
91 + */
92 +#include <linux/config.h>
93 +#include <linux/init.h>
94 +#include <linux/string.h>
95 +#include <linux/kernel.h>
96 +#include <linux/module.h>
97 +
98 +#include <asm/io.h>
99 +#include <asm/mips-boards/prom.h>
100 +#include <asm/mips-boards/generic.h>
101 +
102 +/* Environment variable */
103 +typedef struct {
104 + char *name;
105 + char *val;
106 +} t_env_var;
107 +
108 +int prom_argc;
109 +int *_prom_argv, *_prom_envp;
110 +
111 +/* max # of Adam2 environment variables */
112 +#define MAX_ENV_ENTRY 80
113 +
114 +static t_env_var local_envp[MAX_ENV_ENTRY];
115 +static int env_type = 0;
116 +int init_debug = 0;
117 +
118 +unsigned int max_env_entry;
119 +
120 +extern char *prom_psp_getenv(char *envname);
121 +
122 +static inline char *prom_adam2_getenv(char *envname)
123 +{
124 + /*
125 + * Return a pointer to the given environment variable.
126 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
127 + * in the PROM structures are only 32-bit, so we need some
128 + * workarounds, if we are running in 64-bit mode.
129 + */
130 + int i;
131 + t_env_var *env = (t_env_var *) local_envp;
132 +
133 + if (strcmp("bootloader", envname) == 0)
134 + return "Adam2";
135 +
136 + i = strlen(envname);
137 + while (env->name) {
138 + if(strncmp(envname, env->name, i) == 0) {
139 + return(env->val);
140 + }
141 + env++;
142 + }
143 +
144 + return NULL;
145 +}
146 +
147 +char *prom_getenv(char *envname)
148 +{
149 + if (env_type == 1)
150 + return prom_psp_getenv(envname);
151 + else
152 + return prom_adam2_getenv(envname);
153 +}
154 +
155 +static inline unsigned char str2hexnum(unsigned char c)
156 +{
157 + if (c >= '0' && c <= '9')
158 + return c - '0';
159 + if (c >= 'a' && c <= 'f')
160 + return c - 'a' + 10;
161 + return 0; /* foo */
162 +}
163 +
164 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
165 +{
166 + int i;
167 +
168 + for (i = 0; i < 6; i++) {
169 + unsigned char num;
170 +
171 + if((*str == '.') || (*str == ':'))
172 + str++;
173 + num = str2hexnum(*str++) << 4;
174 + num |= (str2hexnum(*str++));
175 + ea[i] = num;
176 + }
177 +}
178 +
179 +int get_ethernet_addr(char *ethernet_addr)
180 +{
181 + char *ethaddr_str;
182 +
183 + ethaddr_str = prom_getenv("ethaddr");
184 + if (!ethaddr_str) {
185 + printk("ethaddr not set in boot prom\n");
186 + return -1;
187 + }
188 + str2eaddr(ethernet_addr, ethaddr_str);
189 +
190 + if (init_debug > 1) {
191 + int i;
192 + printk("get_ethernet_addr: ");
193 + for (i=0; i<5; i++)
194 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
195 + printk("%02x\n", *(ethernet_addr+i));
196 + }
197 +
198 + return 0;
199 +}
200 +
201 +struct psbl_rec {
202 + unsigned int psbl_size;
203 + unsigned int env_base;
204 + unsigned int env_size;
205 + unsigned int ffs_base;
206 + unsigned int ffs_size;
207 +};
208 +
209 +static const char psp_env_version[] = "TIENV0.8";
210 +
211 +int __init prom_init(int argc, char **argv, char **envp)
212 +{
213 + int i;
214 +
215 + t_env_var *env = (t_env_var *) envp;
216 + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x94000300));
217 + void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
218 +
219 + prom_argc = argc;
220 + _prom_argv = (int *)argv;
221 + _prom_envp = (int *)envp;
222 +
223 + if(strcmp(psp_env, psp_env_version) == 0) {
224 + /* PSPBOOT */
225 +
226 + env_type = 1;
227 + _prom_envp = psp_env;
228 + max_env_entry = (psbl->env_size / 16) - 1;
229 + } else {
230 + /* Copy what we need locally so we are not dependent on
231 + * bootloader RAM. In Adam2, the environment parameters
232 + * are in flash but the table that references them is in
233 + * RAM
234 + */
235 +
236 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
237 + if (env->name) {
238 + local_envp[i].name = env->name;
239 + local_envp[i].val = env->val;
240 + } else {
241 + local_envp[i].name = NULL;
242 + local_envp[i].val = NULL;
243 + }
244 + }
245 + }
246 +
247 + set_io_port_base(0);
248 +
249 + prom_printf("\nLINUX started...\n");
250 + prom_init_cmdline();
251 + prom_meminit();
252 +
253 + return 0;
254 +}
255 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
256 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
257 +++ linux.dev/arch/mips/ar7/irq.c 2005-08-12 23:42:18.679820112 +0200
258 @@ -0,0 +1,709 @@
259 +/*
260 + * Nitin Dhingra, iamnd@ti.com
261 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
262 + *
263 + * ########################################################################
264 + *
265 + * This program is free software; you can distribute it and/or modify it
266 + * under the terms of the GNU General Public License (Version 2) as
267 + * published by the Free Software Foundation.
268 + *
269 + * This program is distributed in the hope it will be useful, but WITHOUT
270 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
271 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
272 + * for more details.
273 + *
274 + * You should have received a copy of the GNU General Public License along
275 + * with this program; if not, write to the Free Software Foundation, Inc.,
276 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
277 + *
278 + * ########################################################################
279 + *
280 + * Routines for generic manipulation of the interrupts found on the Texas
281 + * Instruments avalanche board
282 + *
283 + */
284 +
285 +#include <linux/config.h>
286 +#include <linux/init.h>
287 +#include <linux/sched.h>
288 +#include <linux/slab.h>
289 +#include <linux/interrupt.h>
290 +#include <linux/kernel_stat.h>
291 +#include <linux/proc_fs.h>
292 +#include <asm/irq.h>
293 +#include <asm/mips-boards/prom.h>
294 +#include <asm/ar7/ar7.h>
295 +#include <asm/ar7/avalanche_intc.h>
296 +#include <asm/gdb-stub.h>
297 +
298 +
299 +#define shutdown_avalanche_irq disable_avalanche_irq
300 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
301 +
302 +static unsigned int startup_avalanche_irq(unsigned int irq);
303 +static void end_avalanche_irq(unsigned int irq);
304 +void enable_avalanche_irq(unsigned int irq_nr);
305 +void disable_avalanche_irq(unsigned int irq_nr);
306 +
307 +static struct hw_interrupt_type avalanche_irq_type = {
308 + "TI AVALANCHE",
309 + startup_avalanche_irq,
310 + shutdown_avalanche_irq,
311 + enable_avalanche_irq,
312 + disable_avalanche_irq,
313 + mask_and_ack_avalanche_irq,
314 + end_avalanche_irq,
315 + NULL
316 +};
317 +
318 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
319 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
320 +
321 +
322 +unsigned long spurious_count = 0;
323 +
324 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
325 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
326 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
327 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
328 +
329 +extern asmlinkage void mipsIRQ(void);
330 +
331 +
332 +/*
333 + * The avalanche/MIPS interrupt line numbers are used to represent the
334 + * interrupts within the irqaction arrays. The index notation is
335 + * is as follows:
336 + *
337 + * 0-7 MIPS CPU Exceptions (HW/SW)
338 + * 8-47 Primary Interrupts (Avalanche)
339 + * 48-79 Secondary Interrupts (Avalanche)
340 + *
341 + */
342 +
343 +
344 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
345 +{
346 + NULL, NULL, NULL, NULL,
347 + NULL, NULL, NULL, NULL,
348 + NULL, NULL, NULL, NULL,
349 + NULL, NULL, NULL, NULL,
350 + NULL, NULL, NULL, NULL,
351 + NULL, NULL, NULL, NULL,
352 + NULL, NULL, NULL, NULL,
353 + NULL, NULL, NULL, NULL,
354 + NULL, NULL, NULL, NULL,
355 + NULL, NULL, NULL, NULL
356 +};
357 +
358 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
359 +{
360 + NULL, NULL, NULL, NULL,
361 + NULL, NULL, NULL, NULL,
362 + NULL, NULL, NULL, NULL,
363 + NULL, NULL, NULL, NULL,
364 + NULL, NULL, NULL, NULL,
365 + NULL, NULL, NULL, NULL,
366 + NULL, NULL, NULL, NULL,
367 + NULL, NULL, NULL, NULL
368 +};
369 +
370 +/*
371 + This remaps interrupts to exist on other channels than the default
372 + channels. essentially we can use the line # as the index for this
373 + array
374 + */
375 +
376 +
377 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
378 +unsigned long uni_secondary_interrupt = 0;
379 +
380 +static struct irqaction r4ktimer_action = {
381 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
382 +};
383 +
384 +static struct irqaction *irq_action[8] = {
385 + NULL, /* SW int 0 */
386 + NULL, /* SW int 1 */
387 + NULL, /* HW int 0 */
388 + NULL,
389 + NULL,
390 + NULL, /* HW int 3 */
391 + NULL, /* HW int 4 */
392 + &r4ktimer_action /* HW int 5 */
393 +};
394 +
395 +static void end_avalanche_irq(unsigned int irq)
396 +{
397 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
398 + enable_avalanche_irq(irq);
399 +}
400 +
401 +void disable_avalanche_irq(unsigned int irq_nr)
402 +{
403 + unsigned long flags;
404 + unsigned long chan_nr=0;
405 + unsigned long int_bit=0;
406 +
407 + if(irq_nr >= AVALANCHE_INT_END)
408 + {
409 + printk("whee, invalid irq_nr %d\n", irq_nr);
410 + panic("IRQ, you lose...");
411 + }
412 +
413 + save_and_cli(flags);
414 +
415 +
416 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
417 + {
418 + /* disable mips exception */
419 +
420 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
421 + change_c0_status(ST0_IM,int_bit);
422 + restore_flags(flags);
423 + return;
424 + }
425 +
426 + /* irq_nr represents the line number for the interrupt. We must
427 + * disable the channel number associated with that line number.
428 + */
429 +
430 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
431 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
432 + else
433 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
434 +
435 + /* disable the interrupt channel bit */
436 +
437 + /* primary interrupt #'s 0-31 */
438 +
439 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
440 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
441 +
442 + /* primary interrupt #'s 32-39 */
443 +
444 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
445 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
446 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
447 +
448 + else /* secondary interrupt #'s 0-31 */
449 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
450 +
451 + restore_flags(flags);
452 +}
453 +
454 +void enable_avalanche_irq(unsigned int irq_nr)
455 +{
456 + unsigned long flags;
457 + unsigned long chan_nr=0;
458 + unsigned long int_bit=0;
459 +
460 + if(irq_nr > AVALANCHE_INT_END) {
461 + printk("whee, invalid irq_nr %d\n", irq_nr);
462 + panic("IRQ, you lose...");
463 + }
464 +
465 + save_and_cli(flags);
466 +
467 +
468 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
469 + {
470 + /* Enable MIPS exceptions */
471 + int_bit = read_c0_status();
472 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
473 + restore_flags(flags);
474 + return;
475 + }
476 +
477 + /* irq_nr represents the line number for the interrupt. We must
478 + * disable the channel number associated with that line number.
479 + */
480 +
481 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
482 + chan_nr = AVINTNUM(irq_nr);
483 + else
484 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
485 +
486 + /* enable the interrupt channel bit */
487 +
488 + /* primary interrupt #'s 0-31 */
489 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
490 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
491 +
492 + /* primary interrupt #'s 32 throuth 39 */
493 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
494 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
495 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
496 +
497 + else /* secondary interrupt #'s 0-31 */
498 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
499 +
500 + restore_flags(flags);
501 +}
502 +
503 +static unsigned int startup_avalanche_irq(unsigned int irq)
504 +{
505 + enable_avalanche_irq(irq);
506 + return 0; /* never anything pending */
507 +}
508 +
509 +
510 +int get_irq_list(char *buf)
511 +{
512 + int i, len = 0;
513 + int num = 0;
514 + struct irqaction *action;
515 +
516 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
517 + {
518 + action = irq_action[i];
519 + if (!action)
520 + continue;
521 + len += sprintf(buf+len, "%2d: %8d %c %s",
522 + num, kstat.irqs[0][num],
523 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
524 + action->name);
525 + for (action=action->next; action; action = action->next) {
526 + len += sprintf(buf+len, ",%s %s",
527 + (action->flags & SA_INTERRUPT) ? " +" : "",
528 + action->name);
529 + }
530 + len += sprintf(buf+len, " [MIPS interrupt]\n");
531 + }
532 +
533 +
534 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
535 + {
536 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
537 + action = hw0_irq_action_primary[i];
538 + else
539 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
540 + if (!action)
541 + continue;
542 + len += sprintf(buf+len, "%2d: %8d %c %s",
543 + num, kstat.irqs[0][ LNXINTNUM(i) ],
544 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
545 + action->name);
546 +
547 + for (action=action->next; action; action = action->next)
548 + {
549 + len += sprintf(buf+len, ",%s %s",
550 + (action->flags & SA_INTERRUPT) ? " +" : "",
551 + action->name);
552 + }
553 +
554 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
555 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
556 + else
557 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
558 +
559 + }
560 +
561 + return len;
562 +}
563 +
564 +int request_irq(unsigned int irq,
565 + void (*handler)(int, void *, struct pt_regs *),
566 + unsigned long irqflags,
567 + const char * devname,
568 + void *dev_id)
569 +{
570 + struct irqaction *action;
571 +
572 + if (irq > AVALANCHE_INT_END)
573 + return -EINVAL;
574 + if (!handler)
575 + return -EINVAL;
576 +
577 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
578 + if(!action)
579 + return -ENOMEM;
580 +
581 + action->handler = handler;
582 + action->flags = irqflags;
583 + action->mask = 0;
584 + action->name = devname;
585 + irq_desc_ti[irq].action = action;
586 + action->dev_id = dev_id;
587 +
588 + action->next = 0;
589 +
590 + if(irq < MIPS_EXCEPTION_OFFSET)
591 + {
592 + irq_action[irq] = action;
593 + enable_avalanche_irq(irq);
594 + return 0;
595 + }
596 +
597 + if(irq < AVALANCHE_INT_END_PRIMARY)
598 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
599 + else
600 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
601 +
602 + enable_avalanche_irq(irq);
603 +
604 + return 0;
605 +}
606 +
607 +void free_irq(unsigned int irq, void *dev_id)
608 +{
609 + struct irqaction *action;
610 +
611 + if (irq > AVALANCHE_INT_END) {
612 + printk("Trying to free IRQ%d\n",irq);
613 + return;
614 + }
615 +
616 + if(irq < MIPS_EXCEPTION_OFFSET)
617 + {
618 + action = irq_action[irq];
619 + irq_action[irq] = NULL;
620 + irq_desc_ti[irq].action = NULL;
621 + disable_avalanche_irq(irq);
622 + kfree(action);
623 + return;
624 + }
625 +
626 + if(irq < AVALANCHE_INT_END_PRIMARY) {
627 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
628 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
629 + irq_desc_ti[irq].action = NULL;
630 + }
631 + else {
632 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
633 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
634 + irq_desc_ti[irq].action = NULL;
635 + }
636 +
637 + disable_avalanche_irq(irq);
638 + kfree(action);
639 +}
640 +
641 +#ifdef CONFIG_KGDB
642 +extern void breakpoint(void);
643 +extern int remote_debug;
644 +#endif
645 +
646 +
647 +//void init_IRQ(void) __init;
648 +void __init init_IRQ(void)
649 +{
650 + int i;
651 +
652 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
653 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
654 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
655 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
656 +
657 + /* Disable interrupts and clear pending
658 + */
659 +
660 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
661 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
662 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
663 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
664 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
665 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
666 +
667 +
668 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
669 + /* hack for speeding up the pacing. */
670 + printk("the pacing pre-scalar has been set as 600.\n");
671 + avalanche_hw0_ipaceregs->ipacep = 600;
672 + /* Channel to line mapping, Line to Channel mapping */
673 +
674 + for(i = 0; i < 40; i++)
675 + avalanche_int_set(i,i);
676 +
677 + /* Now safe to set the exception vector. */
678 + set_except_vector(0, mipsIRQ);
679 +
680 + /* Setup the IRQ description array. These will be mapped
681 + * as flat interrupts numbers. The mapping is as follows
682 + *
683 + * 0-7 MIPS CPU Exceptions (HW/SW)
684 + * 8-46 Primary Interrupts (Avalanche)
685 + * 47-78 Secondary Interrupts (Avalanche)
686 + */
687 +
688 + for (i = 0; i <= AVALANCHE_INT_END; i++)
689 + {
690 + irq_desc_ti[i].status = IRQ_DISABLED;
691 + irq_desc_ti[i].action = 0;
692 + irq_desc_ti[i].depth = 1;
693 + irq_desc_ti[i].handler = &avalanche_irq_type;
694 + }
695 +
696 +#ifdef CONFIG_KGDB
697 + if (remote_debug)
698 + {
699 + set_debug_traps();
700 + breakpoint();
701 + }
702 +#endif
703 +}
704 +
705 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
706 +{
707 + struct irqaction *action;
708 + int irq, cpu = smp_processor_id();
709 + unsigned long int_line_number,status;
710 + int i,secondary = 0;
711 + int chan_nr=0;
712 +
713 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
714 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
715 +
716 +
717 + if(chan_nr < 32)
718 + {
719 + if( chan_nr != uni_secondary_interrupt)
720 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
721 +
722 + }
723 +
724 + if((chan_nr < 40) && (chan_nr > 31))
725 + {
726 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
727 + }
728 +
729 +
730 + /* If the Priority Interrupt Index Register returns 40 then no
731 + * interrupts are pending
732 + */
733 +
734 + if(chan_nr == 40)
735 + return;
736 +
737 + if(chan_nr == uni_secondary_interrupt)
738 + {
739 + status = avalanche_hw0_ecregs->exsr;
740 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
741 + {
742 + if (status & 1<<i)
743 + {
744 + /* clear secondary interrupt */
745 + avalanche_hw0_ecregs->excr = 1 << i;
746 + break;
747 + }
748 + }
749 + irq = i;
750 + secondary = 1;
751 +
752 + /* clear the universal secondary interrupt */
753 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
754 +
755 + }
756 + else
757 + irq = chan_nr;
758 +
759 + /* Suraj Add code to clear secondary interrupt */
760 +
761 + if(secondary)
762 + action = hw0_irq_action_secondary[irq];
763 + else
764 + action = hw0_irq_action_primary[irq];
765 +
766 + /* if action == NULL, then we don't have a handler for the irq */
767 +
768 + if ( action == NULL ) {
769 + printk("No handler for hw0 irq: %i\n", irq);
770 + return;
771 + }
772 +
773 + irq_enter(cpu,irq);
774 + if(secondary)
775 + {
776 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
777 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
778 + }
779 + else
780 + {
781 + kstat.irqs[0][irq + 8]++;
782 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
783 + }
784 +
785 + irq_exit(cpu,irq);
786 +
787 + if(softirq_pending(cpu))
788 + do_softirq();
789 +
790 + return;
791 +}
792 +
793 +void avalanche_int_set(int channel, int line)
794 +{
795 + switch(channel)
796 + {
797 + case(0):
798 + avalanche_hw0_chregs->cintnr0 = line;
799 + break;
800 + case(1):
801 + avalanche_hw0_chregs->cintnr1 = line;
802 + break;
803 + case(2):
804 + avalanche_hw0_chregs->cintnr2 = line;
805 + break;
806 + case(3):
807 + avalanche_hw0_chregs->cintnr3 = line;
808 + break;
809 + case(4):
810 + avalanche_hw0_chregs->cintnr4 = line;
811 + break;
812 + case(5):
813 + avalanche_hw0_chregs->cintnr5 = line;
814 + break;
815 + case(6):
816 + avalanche_hw0_chregs->cintnr6 = line;
817 + break;
818 + case(7):
819 + avalanche_hw0_chregs->cintnr7 = line;
820 + break;
821 + case(8):
822 + avalanche_hw0_chregs->cintnr8 = line;
823 + break;
824 + case(9):
825 + avalanche_hw0_chregs->cintnr9 = line;
826 + break;
827 + case(10):
828 + avalanche_hw0_chregs->cintnr10 = line;
829 + break;
830 + case(11):
831 + avalanche_hw0_chregs->cintnr11 = line;
832 + break;
833 + case(12):
834 + avalanche_hw0_chregs->cintnr12 = line;
835 + break;
836 + case(13):
837 + avalanche_hw0_chregs->cintnr13 = line;
838 + break;
839 + case(14):
840 + avalanche_hw0_chregs->cintnr14 = line;
841 + break;
842 + case(15):
843 + avalanche_hw0_chregs->cintnr15 = line;
844 + break;
845 + case(16):
846 + avalanche_hw0_chregs->cintnr16 = line;
847 + break;
848 + case(17):
849 + avalanche_hw0_chregs->cintnr17 = line;
850 + break;
851 + case(18):
852 + avalanche_hw0_chregs->cintnr18 = line;
853 + break;
854 + case(19):
855 + avalanche_hw0_chregs->cintnr19 = line;
856 + break;
857 + case(20):
858 + avalanche_hw0_chregs->cintnr20 = line;
859 + break;
860 + case(21):
861 + avalanche_hw0_chregs->cintnr21 = line;
862 + break;
863 + case(22):
864 + avalanche_hw0_chregs->cintnr22 = line;
865 + break;
866 + case(23):
867 + avalanche_hw0_chregs->cintnr23 = line;
868 + break;
869 + case(24):
870 + avalanche_hw0_chregs->cintnr24 = line;
871 + break;
872 + case(25):
873 + avalanche_hw0_chregs->cintnr25 = line;
874 + break;
875 + case(26):
876 + avalanche_hw0_chregs->cintnr26 = line;
877 + break;
878 + case(27):
879 + avalanche_hw0_chregs->cintnr27 = line;
880 + break;
881 + case(28):
882 + avalanche_hw0_chregs->cintnr28 = line;
883 + break;
884 + case(29):
885 + avalanche_hw0_chregs->cintnr29 = line;
886 + break;
887 + case(30):
888 + avalanche_hw0_chregs->cintnr30 = line;
889 + break;
890 + case(31):
891 + avalanche_hw0_chregs->cintnr31 = line;
892 + break;
893 + case(32):
894 + avalanche_hw0_chregs->cintnr32 = line;
895 + break;
896 + case(33):
897 + avalanche_hw0_chregs->cintnr33 = line;
898 + break;
899 + case(34):
900 + avalanche_hw0_chregs->cintnr34 = line;
901 + break;
902 + case(35):
903 + avalanche_hw0_chregs->cintnr35 = line;
904 + break;
905 + case(36):
906 + avalanche_hw0_chregs->cintnr36 = line;
907 + break;
908 + case(37):
909 + avalanche_hw0_chregs->cintnr37 = line;
910 + break;
911 + case(38):
912 + avalanche_hw0_chregs->cintnr38 = line;
913 + break;
914 + case(39):
915 + avalanche_hw0_chregs->cintnr39 = line;
916 + break;
917 + default:
918 + printk("Error: Unknown Avalanche interrupt channel\n");
919 + }
920 +
921 + line_to_channel[line] = channel; /* Suraj check */
922 +
923 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
924 + uni_secondary_interrupt = line;
925 +
926 +}
927 +
928 +
929 +#define AVALANCHE_MAX_PACING_BLK 3
930 +#define AVALANCHE_PACING_LOW_VAL 2
931 +#define AVALANCHE_PACING_HIGH_VAL 63
932 +
933 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num,
934 + unsigned int pace_value)
935 +{
936 + unsigned int blk_offset;
937 + unsigned long flags;
938 +
939 + if(irq_nr < MIPS_EXCEPTION_OFFSET &&
940 + irq_nr >= AVALANCHE_INT_END_PRIMARY)
941 + return (0);
942 +
943 + if(blk_num > AVALANCHE_MAX_PACING_BLK)
944 + return(-1);
945 +
946 + if(pace_value > AVALANCHE_PACING_HIGH_VAL &&
947 + pace_value < AVALANCHE_PACING_LOW_VAL)
948 + return(-1);
949 +
950 + blk_offset = blk_num*8;
951 +
952 + save_and_cli(flags);
953 +
954 + /* disable the interrupt pacing, if enabled previously */
955 + avalanche_hw0_ipaceregs->ipacemax &= ~(0xff << blk_offset);
956 +
957 + /* clear the pacing map */
958 + avalanche_hw0_ipaceregs->ipacemap &= ~(0xff << blk_offset);
959 +
960 + /* setup the new values */
961 + avalanche_hw0_ipaceregs->ipacemap |= ((AVINTNUM(irq_nr)) << blk_offset);
962 + avalanche_hw0_ipaceregs->ipacemax |= ((0x80 | pace_value) << blk_offset);
963 +
964 + restore_flags(flags);
965 +
966 + return(0);
967 +}
968 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
969 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
970 +++ linux.dev/arch/mips/ar7/Makefile 2005-08-12 21:21:30.425150040 +0200
971 @@ -0,0 +1,14 @@
972 +.S.s:
973 + $(CPP) $(AFLAGS) $< -o $*.s
974 +
975 +.S.o:
976 + $(CC) $(AFLAGS) -c $< -o $*.o
977 +
978 +EXTRA_CFLAGS := -I$(TOPDIR)/include/asm/ar7 -DLITTLE_ENDIAN -D_LINK_KSEG0_
979 +O_TARGET := ar7.o
980 +
981 +obj-y := tnetd73xx_misc.o misc.o
982 +export-objs := misc.o
983 +obj-y += setup.o irq.o mipsIRQ.o reset.o init.o psp_env.o memory.o printf.o cmdline.o time.o
984 +
985 +include $(TOPDIR)/Rules.make
986 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
987 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
988 +++ linux.dev/arch/mips/ar7/memory.c 2005-08-12 19:52:25.301732312 +0200
989 @@ -0,0 +1,131 @@
990 +/*
991 + * Carsten Langgaard, carstenl@mips.com
992 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
993 + *
994 + * ########################################################################
995 + *
996 + * This program is free software; you can distribute it and/or modify it
997 + * under the terms of the GNU General Public License (Version 2) as
998 + * published by the Free Software Foundation.
999 + *
1000 + * This program is distributed in the hope it will be useful, but WITHOUT
1001 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1002 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1003 + * for more details.
1004 + *
1005 + * You should have received a copy of the GNU General Public License along
1006 + * with this program; if not, write to the Free Software Foundation, Inc.,
1007 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1008 + *
1009 + * ########################################################################
1010 + *
1011 + * PROM library functions for acquiring/using memory descriptors given to
1012 + * us from the YAMON.
1013 + *
1014 + */
1015 +#include <linux/config.h>
1016 +#include <linux/init.h>
1017 +#include <linux/mm.h>
1018 +#include <linux/bootmem.h>
1019 +
1020 +#include <asm/bootinfo.h>
1021 +#include <asm/page.h>
1022 +#include <asm/mips-boards/prom.h>
1023 +
1024 +enum yamon_memtypes {
1025 + yamon_dontuse,
1026 + yamon_prom,
1027 + yamon_free,
1028 +};
1029 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1030 +
1031 +/* References to section boundaries */
1032 +extern char _end;
1033 +
1034 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1035 +
1036 +
1037 +struct prom_pmemblock * __init prom_getmdesc(void)
1038 +{
1039 + char *memsize_str;
1040 + unsigned int memsize;
1041 +
1042 + memsize_str = prom_getenv("memsize");
1043 + if (!memsize_str) {
1044 + memsize = 0x02000000;
1045 + } else {
1046 + memsize = simple_strtol(memsize_str, NULL, 0);
1047 + }
1048 +
1049 + memset(mdesc, 0, sizeof(mdesc));
1050 +
1051 + mdesc[0].type = yamon_dontuse;
1052 + mdesc[0].base = 0x00000000;
1053 + mdesc[0].size = CONFIG_AR7_MEMORY;
1054 +
1055 + mdesc[1].type = yamon_prom;
1056 + mdesc[1].base = CONFIG_AR7_MEMORY;
1057 + mdesc[1].size = 0x00020000;
1058 +
1059 + mdesc[2].type = yamon_free;
1060 + mdesc[2].base = CONFIG_AR7_MEMORY + 0x00020000;
1061 + mdesc[2].size = (memsize + CONFIG_AR7_MEMORY) - mdesc[2].base;
1062 +
1063 + return &mdesc[0];
1064 +}
1065 +
1066 +static int __init prom_memtype_classify (unsigned int type)
1067 +{
1068 + switch (type) {
1069 + case yamon_free:
1070 + return BOOT_MEM_RAM;
1071 + case yamon_prom:
1072 + return BOOT_MEM_ROM_DATA;
1073 + default:
1074 + return BOOT_MEM_RESERVED;
1075 + }
1076 +}
1077 +
1078 +void __init prom_meminit(void)
1079 +{
1080 + struct prom_pmemblock *p;
1081 +
1082 + p = prom_getmdesc();
1083 +
1084 + while (p->size) {
1085 + long type;
1086 + unsigned long base, size;
1087 +
1088 + type = prom_memtype_classify (p->type);
1089 + base = p->base;
1090 + size = p->size;
1091 +
1092 + add_memory_region(base, size, type);
1093 + p++;
1094 + }
1095 +}
1096 +
1097 +void __init prom_free_prom_memory (void)
1098 +{
1099 +#if 0
1100 + int i;
1101 + unsigned long freed = 0;
1102 + unsigned long addr;
1103 +
1104 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1105 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1106 + continue;
1107 +
1108 + addr = boot_mem_map.map[i].addr;
1109 + while (addr < boot_mem_map.map[i].addr
1110 + + boot_mem_map.map[i].size) {
1111 + ClearPageReserved(virt_to_page(__va(addr)));
1112 + set_page_count(virt_to_page(__va(addr)), 1);
1113 + free_page((unsigned long)__va(addr));
1114 + addr += PAGE_SIZE;
1115 + freed += PAGE_SIZE;
1116 + }
1117 + }
1118 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1119 +#endif
1120 +}
1121 diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
1122 --- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1123 +++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-08-12 19:32:05.138225360 +0200
1124 @@ -0,0 +1,120 @@
1125 +/*
1126 + * Carsten Langgaard, carstenl@mips.com
1127 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1128 + *
1129 + * ########################################################################
1130 + *
1131 + * This program is free software; you can distribute it and/or modify it
1132 + * under the terms of the GNU General Public License (Version 2) as
1133 + * published by the Free Software Foundation.
1134 + *
1135 + * This program is distributed in the hope it will be useful, but WITHOUT
1136 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1137 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1138 + * for more details.
1139 + *
1140 + * You should have received a copy of the GNU General Public License along
1141 + * with this program; if not, write to the Free Software Foundation, Inc.,
1142 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1143 + *
1144 + * ########################################################################
1145 + *
1146 + * Interrupt exception dispatch code.
1147 + *
1148 + */
1149 +#include <linux/config.h>
1150 +
1151 +#include <asm/asm.h>
1152 +#include <asm/mipsregs.h>
1153 +#include <asm/regdef.h>
1154 +#include <asm/stackframe.h>
1155 +
1156 +/* A lot of complication here is taken away because:
1157 + *
1158 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1159 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1160 + * common case is one pending IRQ so optimize in that direction.
1161 + *
1162 + * 2) We need not check against bits in the status register IRQ mask, that
1163 + * would make this routine slow as hell.
1164 + *
1165 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1166 + * between like BSD spl() brain-damage.
1167 + *
1168 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1169 + * IRQs which we don't use at all and all external interrupt sources are
1170 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1171 + *
1172 + * MIPS IRQ Source
1173 + * -------- ------
1174 + * 0 Software (ignored)
1175 + * 1 Software (ignored)
1176 + * 2 Combined hardware interrupt (hw0)
1177 + * 3 Hardware (ignored)
1178 + * 4 Hardware (ignored)
1179 + * 5 Hardware (ignored)
1180 + * 6 Hardware (ignored)
1181 + * 7 R4k timer (what we use)
1182 + *
1183 + * Note: On the SEAD board thing are a little bit different.
1184 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1185 + * wired to UART1.
1186 + *
1187 + * We handle the IRQ according to _our_ priority which is:
1188 + *
1189 + * Highest ---- R4k Timer
1190 + * Lowest ---- Combined hardware interrupt
1191 + *
1192 + * then we just return, if multiple IRQs are pending then we will just take
1193 + * another exception, big deal.
1194 + */
1195 +
1196 +.text
1197 +.set noreorder
1198 +.set noat
1199 + .align 5
1200 +NESTED(mipsIRQ, PT_SIZE, sp)
1201 + SAVE_ALL
1202 + CLI
1203 + .set at
1204 +
1205 + mfc0 s0, CP0_CAUSE # get irq bits
1206 +
1207 + /* First we check for r4k counter/timer IRQ. */
1208 + andi a0, s0, CAUSEF_IP7
1209 + beq a0, zero, 1f
1210 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1211 +
1212 + /* Wheee, a timer interrupt. */
1213 + move a0, sp
1214 + jal ar7_timer_interrupt
1215 + nop
1216 +
1217 + j ret_from_irq
1218 + nop
1219 +
1220 + 1:
1221 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1222 + nop
1223 +
1224 + /* Wheee, combined hardware level zero interrupt. */
1225 + jal avalanche_hw0_irqdispatch
1226 + move a0, sp # delay slot
1227 +
1228 + j ret_from_irq
1229 + nop # delay slot
1230 +
1231 + 1:
1232 + /*
1233 + * Here by mistake? This is possible, what can happen is that by the
1234 + * time we take the exception the IRQ pin goes low, so just leave if
1235 + * this is the case.
1236 + */
1237 + move a1,s0
1238 + PRINT("Got interrupt: c0_cause = %08x\n")
1239 + mfc0 a1, CP0_EPC
1240 + PRINT("c0_epc = %08x\n")
1241 +
1242 + j ret_from_irq
1243 + nop
1244 +END(mipsIRQ)
1245 diff -urN linux.old/arch/mips/ar7/misc.c linux.dev/arch/mips/ar7/misc.c
1246 --- linux.old/arch/mips/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
1247 +++ linux.dev/arch/mips/ar7/misc.c 2005-08-12 19:32:05.136225664 +0200
1248 @@ -0,0 +1,319 @@
1249 +#include <asm/ar7/sangam.h>
1250 +#include <asm/ar7/avalanche_misc.h>
1251 +#include <linux/module.h>
1252 +#include <linux/spinlock.h>
1253 +
1254 +#define TRUE 1
1255 +
1256 +static unsigned int avalanche_vbus_freq;
1257 +
1258 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
1259 +
1260 +/*****************************************************************************
1261 + * Reset Control Module.
1262 + *****************************************************************************/
1263 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
1264 + AVALANCHE_RESET_CTRL_T reset_ctrl)
1265 +{
1266 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1267 +
1268 + if(module_reset_bit >= 32 && module_reset_bit < 64)
1269 + return;
1270 +
1271 + if(module_reset_bit >= 64)
1272 + {
1273 + if(p_remote_vlynq_dev_reset_ctrl)
1274 + return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
1275 + else
1276 + return;
1277 + }
1278 +
1279 + if(reset_ctrl == OUT_OF_RESET)
1280 + *reset_reg |= 1 << module_reset_bit;
1281 + else
1282 + *reset_reg &= ~(1 << module_reset_bit);
1283 +}
1284 +
1285 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
1286 +{
1287 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1288 +
1289 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
1290 +}
1291 +
1292 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
1293 +{
1294 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
1295 + *sw_reset_reg = mode;
1296 +}
1297 +
1298 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
1299 +
1300 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
1301 +{
1302 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
1303 +
1304 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
1305 +}
1306 +
1307 +
1308 +/*****************************************************************************
1309 + * Power Control Module
1310 + *****************************************************************************/
1311 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
1312 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
1313 +
1314 +
1315 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
1316 +{
1317 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1318 +
1319 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
1320 + /* power down the module */
1321 + *power_reg |= (1 << module_power_bit);
1322 + else
1323 + /* power on the module */
1324 + *power_reg &= (~(1 << module_power_bit));
1325 +}
1326 +
1327 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
1328 +{
1329 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1330 +
1331 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
1332 +}
1333 +
1334 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
1335 +{
1336 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1337 +
1338 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
1339 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
1340 +}
1341 +
1342 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
1343 +{
1344 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
1345 +
1346 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
1347 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
1348 +}
1349 +
1350 +/*****************************************************************************
1351 + * GPIO Control
1352 + *****************************************************************************/
1353 +
1354 +/****************************************************************************
1355 + * FUNCTION: avalanche_gpio_init
1356 + ***************************************************************************/
1357 +void avalanche_gpio_init(void)
1358 +{
1359 + spinlock_t closeLock;
1360 + unsigned int closeFlag;
1361 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
1362 + spin_lock_irqsave(&closeLock, closeFlag);
1363 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
1364 + spin_unlock_irqrestore(&closeLock, closeFlag);
1365 +}
1366 +
1367 +/****************************************************************************
1368 + * FUNCTION: avalanche_gpio_ctrl
1369 + ***************************************************************************/
1370 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
1371 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
1372 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
1373 +{
1374 + spinlock_t closeLock;
1375 + unsigned int closeFlag;
1376 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
1377 +
1378 + if(gpio_pin >= 32)
1379 + return(-1);
1380 +
1381 + spin_lock_irqsave(&closeLock, closeFlag);
1382 +
1383 + if(pin_mode == GPIO_PIN)
1384 + {
1385 + *gpio_ctrl |= (1 << gpio_pin);
1386 +
1387 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
1388 +
1389 + if(pin_direction == GPIO_INPUT_PIN)
1390 + *gpio_ctrl |= (1 << gpio_pin);
1391 + else
1392 + *gpio_ctrl &= ~(1 << gpio_pin);
1393 + }
1394 + else /* FUNCTIONAL PIN */
1395 + {
1396 + *gpio_ctrl &= ~(1 << gpio_pin);
1397 + }
1398 +
1399 + spin_unlock_irqrestore(&closeLock, closeFlag);
1400 +
1401 + return (0);
1402 +}
1403 +
1404 +/****************************************************************************
1405 + * FUNCTION: avalanche_gpio_out
1406 + ***************************************************************************/
1407 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
1408 +{
1409 + spinlock_t closeLock;
1410 + unsigned int closeFlag;
1411 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1412 +
1413 + if(gpio_pin >= 32)
1414 + return(-1);
1415 +
1416 + spin_lock_irqsave(&closeLock, closeFlag);
1417 + if(value == TRUE)
1418 + *gpio_out |= 1 << gpio_pin;
1419 + else
1420 + *gpio_out &= ~(1 << gpio_pin);
1421 + spin_unlock_irqrestore(&closeLock, closeFlag);
1422 +
1423 + return(0);
1424 +}
1425 +
1426 +/****************************************************************************
1427 + * FUNCTION: avalanche_gpio_in
1428 + ***************************************************************************/
1429 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
1430 +{
1431 + spinlock_t closeLock;
1432 + unsigned int closeFlag;
1433 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1434 + int ret_val = 0;
1435 +
1436 + if(gpio_pin >= 32)
1437 + return(-1);
1438 +
1439 + spin_lock_irqsave(&closeLock, closeFlag);
1440 + ret_val = ((*gpio_in) & (1 << gpio_pin));
1441 + spin_unlock_irqrestore(&closeLock, closeFlag);
1442 +
1443 + return (ret_val);
1444 +}
1445 +
1446 +/****************************************************************************
1447 + * FUNCTION: avalanche_gpio_out_val
1448 + ***************************************************************************/
1449 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
1450 + unsigned int reg_index)
1451 +{
1452 + spinlock_t closeLock;
1453 + unsigned int closeFlag;
1454 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
1455 +
1456 + if(reg_index > 0)
1457 + return(-1);
1458 +
1459 + spin_lock_irqsave(&closeLock, closeFlag);
1460 + *gpio_out &= ~out_mask;
1461 + *gpio_out |= out_val;
1462 + spin_unlock_irqrestore(&closeLock, closeFlag);
1463 +
1464 + return(0);
1465 +}
1466 +
1467 +/****************************************************************************
1468 + * FUNCTION: avalanche_gpio_in_value
1469 + ***************************************************************************/
1470 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
1471 +{
1472 + spinlock_t closeLock;
1473 + unsigned int closeFlag;
1474 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
1475 +
1476 + if(reg_index > 0)
1477 + return(-1);
1478 +
1479 + spin_lock_irqsave(&closeLock, closeFlag);
1480 + *in_val = *gpio_in;
1481 + spin_unlock_irqrestore(&closeLock, closeFlag);
1482 +
1483 + return (0);
1484 +}
1485 +
1486 +/***********************************************************************
1487 + *
1488 + * Wakeup Control Module for TNETV1050 Communication Processor
1489 + *
1490 + ***********************************************************************/
1491 +
1492 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
1493 +
1494 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
1495 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
1496 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
1497 +{
1498 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
1499 +
1500 + /* enable/disable */
1501 + if (wakeup_ctrl == WAKEUP_ENABLED)
1502 + /* enable wakeup */
1503 + *wakeup_status_reg |= wakeup_int;
1504 + else
1505 + /* disable wakeup */
1506 + *wakeup_status_reg &= (~wakeup_int);
1507 +
1508 + /* set polarity */
1509 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
1510 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1511 + else
1512 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
1513 +}
1514 +
1515 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
1516 +{
1517 + avalanche_vbus_freq = new_vbus_freq;
1518 +}
1519 +
1520 +unsigned int avalanche_get_vbus_freq()
1521 +{
1522 + return(avalanche_vbus_freq);
1523 +}
1524 +
1525 +unsigned int avalanche_get_chip_version_info()
1526 +{
1527 + return(*(volatile unsigned int*)AVALANCHE_CVR);
1528 +}
1529 +
1530 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
1531 +
1532 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
1533 +{
1534 + if(p_set_mdix_on_chip_fn)
1535 + return (p_set_mdix_on_chip_fn(base_addr, operation));
1536 + else
1537 + return(-1);
1538 +}
1539 +
1540 +unsigned int avalanche_is_mdix_on_chip(void)
1541 +{
1542 + return(p_set_mdix_on_chip_fn ? 1:0);
1543 +}
1544 +
1545 +EXPORT_SYMBOL(avalanche_reset_ctrl);
1546 +EXPORT_SYMBOL(avalanche_get_reset_status);
1547 +EXPORT_SYMBOL(avalanche_sys_reset);
1548 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
1549 +EXPORT_SYMBOL(avalanche_power_ctrl);
1550 +EXPORT_SYMBOL(avalanche_get_power_status);
1551 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
1552 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
1553 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
1554 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
1555 +
1556 +EXPORT_SYMBOL(avalanche_gpio_init);
1557 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
1558 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
1559 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
1560 +EXPORT_SYMBOL(avalanche_gpio_out_value);
1561 +EXPORT_SYMBOL(avalanche_gpio_in_value);
1562 +
1563 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
1564 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
1565 +
1566 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
1567 +
1568 diff -urN linux.old/arch/mips/ar7/platform.h linux.dev/arch/mips/ar7/platform.h
1569 --- linux.old/arch/mips/ar7/platform.h 1970-01-01 01:00:00.000000000 +0100
1570 +++ linux.dev/arch/mips/ar7/platform.h 2005-08-12 19:34:07.216666616 +0200
1571 @@ -0,0 +1,65 @@
1572 +#ifndef _PLATFORM_H_
1573 +#define _PLATFORM_H_
1574 +
1575 +#include <linux/config.h>
1576 +
1577 +
1578 +/* Important: The definition of ENV_SPACE_SIZE should match with that in
1579 + * PSPBoot. (/psp_boot/inc/psbl/env.h)
1580 + */
1581 +#ifdef CONFIG_MIPS_AVALANCHE_TICFG
1582 +#define ENV_SPACE_SIZE (10 * 1024)
1583 +#endif
1584 +
1585 +#ifdef CONFIG_MIPS_TNETV1050SDB
1586 +#define TNETV1050SDB
1587 +#define DUAL_FLASH
1588 +#endif
1589 +
1590 +#ifdef CONFIG_MIPS_AR7DB
1591 +#define TNETD73XX_BOARD
1592 +#define AR7DB
1593 +#endif
1594 +
1595 +#ifdef CONFIG_MIPS_AR7RD
1596 +#define TNETD73XX_BOARD
1597 +#define AR7RD
1598 +#endif
1599 +
1600 +#ifdef CONFIG_AR7WRD
1601 +#define TNETD73XX_BOARD
1602 +#define AR7WRD
1603 +#endif
1604 +
1605 +#ifdef CONFIG_MIPS_AR7VWI
1606 +#define TNETD73XX_BOARD
1607 +#define AR7VWi
1608 +#endif
1609 +
1610 +/* Merging from the DEV_DSL-PSPL4.3.2.7_Patch release. */
1611 +#ifdef CONFIG_MIPS_AR7VW
1612 +#define TNETD73XX_BOARD
1613 +#define AR7WRD
1614 +#endif
1615 +
1616 +#ifdef CONFIG_MIPS_AR7WI
1617 +#define TNETD73XX_BOARD
1618 +#define AR7Wi
1619 +#endif
1620 +
1621 +#ifdef CONFIG_MIPS_AR7V
1622 +#define TNETD73XX_BOARD
1623 +#define AR7V
1624 +#endif
1625 +
1626 +#ifdef CONFIG_MIPS_AR7V
1627 +#define TNETD73XX_BOARD
1628 +#define AR7V
1629 +#endif
1630 +
1631 +#ifdef CONFIG_MIPS_WA1130
1632 +#define AVALANCHE
1633 +#define WLAN
1634 +#endif
1635 +
1636 +#endif
1637 diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
1638 --- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
1639 +++ linux.dev/arch/mips/ar7/printf.c 2005-08-12 19:32:05.139225208 +0200
1640 @@ -0,0 +1,53 @@
1641 +/*
1642 + * Carsten Langgaard, carstenl@mips.com
1643 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1644 + *
1645 + * This program is free software; you can distribute it and/or modify it
1646 + * under the terms of the GNU General Public License (Version 2) as
1647 + * published by the Free Software Foundation.
1648 + *
1649 + * This program is distributed in the hope it will be useful, but WITHOUT
1650 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1651 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1652 + * for more details.
1653 + *
1654 + * You should have received a copy of the GNU General Public License along
1655 + * with this program; if not, write to the Free Software Foundation, Inc.,
1656 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1657 + *
1658 + * Putting things on the screen/serial line using Adam2 facilities.
1659 + */
1660 +
1661 +#include <linux/config.h>
1662 +#include <linux/init.h>
1663 +#include <linux/kernel.h>
1664 +#include <linux/serial_reg.h>
1665 +#include <linux/spinlock.h>
1666 +#include <asm/io.h>
1667 +#include <asm/serial.h>
1668 +#include <asm/addrspace.h>
1669 +
1670 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
1671 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4)
1672 +
1673 +static char ppbuf[1024];
1674 +
1675 +void (*prom_print_str)(unsigned int out, char *s, int len);
1676 +
1677 +void prom_printf(char *fmt, ...) __init;
1678 +void prom_printf(char *fmt, ...)
1679 +{
1680 + va_list args;
1681 + int len;
1682 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
1683 +
1684 + va_start(args, fmt);
1685 + vsprintf(ppbuf, fmt, args);
1686 + len = strlen(ppbuf);
1687 +
1688 + prom_print_str(1, ppbuf, len);
1689 +
1690 + va_end(args);
1691 + return;
1692 +
1693 +}
1694 diff -urN linux.old/arch/mips/ar7/psp_env.c linux.dev/arch/mips/ar7/psp_env.c
1695 --- linux.old/arch/mips/ar7/psp_env.c 1970-01-01 01:00:00.000000000 +0100
1696 +++ linux.dev/arch/mips/ar7/psp_env.c 2005-08-12 19:34:07.216666616 +0200
1697 @@ -0,0 +1,350 @@
1698 +#include <linux/config.h>
1699 +#include <linux/init.h>
1700 +#include <linux/string.h>
1701 +#include <linux/kernel.h>
1702 +#include <linux/module.h>
1703 +#include <asm/io.h>
1704 +
1705 +#include "platform.h"
1706 +
1707 +#define ENV_CELL_SIZE 16
1708 +
1709 +/* control field decode */
1710 +#define ENV_GARBAGE_BIT 0x01 /* Env is garbage if this bit is off */
1711 +#define ENV_DYNAMIC_BIT 0x02 /* Env is dynamic if this bit is off */
1712 +
1713 +#define ENV_CTRL_MASK 0x03
1714 +#define ENV_PREFINED (ENV_GARBAGE_BIT | ENV_DYNAMIC_BIT)
1715 +#define ENV_DYNAMIC (ENV_GARBAGE_BIT)
1716 +
1717 +struct env_variable {
1718 + unsigned char varNum;
1719 + unsigned char ctrl;
1720 + unsigned short chksum;
1721 + unsigned char numCells;
1722 + unsigned char data[ENV_CELL_SIZE - 5]; /* The data section starts
1723 + * here, continues for
1724 + * numCells.
1725 + */
1726 +};
1727 +
1728 +extern unsigned int max_env_entry;
1729 +
1730 +/* Internal macros */
1731 +#define get_next_block(var) ((struct env_variable *)( (char*)(var) + (var)->numCells * ENV_CELL_SIZE))
1732 +
1733 +typedef enum ENV_VARS {
1734 + env_vars_start = 0,
1735 + CPUFREQ,
1736 + MEMSZ,
1737 + FLASHSZ,
1738 + MODETTY0,
1739 + MODETTY1,
1740 + PROMPT,
1741 + BOOTCFG,
1742 + HWA_0,
1743 +#if !defined (AVALANCHE) || defined(TNETC401B)
1744 + HWA_1,
1745 +#endif
1746 +#if !defined(TNETV1020_BOARD)
1747 + HWA_RNDIS,
1748 +#endif
1749 +#if defined (TNETD73XX_BOARD)
1750 + HWA_3,
1751 +#endif
1752 + IPA,
1753 + IPA_SVR,
1754 + BLINE_MAC0,
1755 +#if !defined (AVALANCHE) || defined(TNETC401B)
1756 + BLINE_MAC1,
1757 +#endif
1758 +#if !defined(TNETV1020_BOARD)
1759 + BLINE_RNDIS,
1760 +#endif
1761 +#if defined (TNETD73XX_BOARD)
1762 + BLINE_ATM,
1763 +#endif
1764 +#if !defined(TNETV1020_BOARD)
1765 + USB_PID,
1766 + USB_VID,
1767 + USB_EPPOLLI,
1768 +#endif
1769 + IPA_GATEWAY,
1770 + SUBNET_MASK,
1771 +#if defined (TNETV1050_BOARD)
1772 + BLINE_ESWITCH,
1773 +#endif
1774 +#if !defined(TNETV1020_BOARD)
1775 + USB_SERIAL,
1776 + HWA_HRNDIS, /* Host (PC) side RNDIS address */
1777 +#endif
1778 + REMOTE_USER,
1779 + REMOTE_PASS,
1780 + REMOTE_DIR,
1781 + SYSFREQ,
1782 + LINK_TIMEOUT,
1783 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1784 + MAC_PORT,
1785 +#endif
1786 + PATH,
1787 + HOSTNAME,
1788 +#ifdef WLAN
1789 + HW_REV_MAJOR,
1790 + HW_REV_MINOR,
1791 + HW_PATCH,
1792 + SW_PATCH,
1793 + SERIAL_NUMBER,
1794 +#endif
1795 + TFTPCFG,
1796 +#if defined (TNETV1050_BOARD)
1797 + HWA_ESWITCH,
1798 +#endif
1799 + /*
1800 + * Add new env variables here.
1801 + * NOTE: New environment variables should always be placed at the end, ie
1802 + * just before env_vars_end.
1803 + */
1804 +
1805 + env_vars_end
1806 +} ENV_VARS;
1807 +
1808 +
1809 +struct env_description {
1810 + ENV_VARS idx;
1811 + char *nm;
1812 + char *alias;
1813 +};
1814 +
1815 +#define ENVSTR(x) #x
1816 +#define _ENV_ENTRY(x) {.idx = x, .nm = ENVSTR(x), .alias = NULL}
1817 +
1818 +struct env_description env_ns[] = {
1819 + _ENV_ENTRY(env_vars_start), /* start. */
1820 + _ENV_ENTRY(CPUFREQ),
1821 + _ENV_ENTRY(MEMSZ),
1822 + _ENV_ENTRY(FLASHSZ),
1823 + _ENV_ENTRY(MODETTY0),
1824 + _ENV_ENTRY(MODETTY1),
1825 + _ENV_ENTRY(PROMPT),
1826 + _ENV_ENTRY(BOOTCFG),
1827 + _ENV_ENTRY(HWA_0),
1828 +#if !defined (AVALANCHE) || defined(TNETC401B)
1829 + _ENV_ENTRY(HWA_1),
1830 +#endif
1831 +#if !defined(TNETV1020_BOARD)
1832 + _ENV_ENTRY(HWA_RNDIS),
1833 +#endif
1834 +#if defined (TNETD73XX_BOARD)
1835 + _ENV_ENTRY(HWA_3),
1836 +#endif
1837 + _ENV_ENTRY(IPA),
1838 + _ENV_ENTRY(IPA_SVR),
1839 + _ENV_ENTRY(IPA_GATEWAY),
1840 + _ENV_ENTRY(SUBNET_MASK),
1841 + _ENV_ENTRY(BLINE_MAC0),
1842 +#if !defined (AVALANCHE) || defined(TNETC401B)
1843 + _ENV_ENTRY(BLINE_MAC1),
1844 +#endif
1845 +#if !defined(TNETV1020_BOARD)
1846 + _ENV_ENTRY(BLINE_RNDIS),
1847 +#endif
1848 +#if defined (TNETD73XX_BOARD)
1849 + _ENV_ENTRY(BLINE_ATM),
1850 +#endif
1851 +#if !defined(TNETV1020_BOARD)
1852 + _ENV_ENTRY(USB_PID),
1853 + _ENV_ENTRY(USB_VID),
1854 + _ENV_ENTRY(USB_EPPOLLI),
1855 +#endif
1856 +#if defined (TNETV1050_BOARD)
1857 + _ENV_ENTRY(BLINE_ESWITCH),
1858 +#endif
1859 +#if !defined(TNETV1020_BOARD)
1860 + _ENV_ENTRY(USB_SERIAL),
1861 + _ENV_ENTRY(HWA_HRNDIS),
1862 +#endif
1863 + _ENV_ENTRY(REMOTE_USER),
1864 + _ENV_ENTRY(REMOTE_PASS),
1865 + _ENV_ENTRY(REMOTE_DIR),
1866 + _ENV_ENTRY(SYSFREQ),
1867 + _ENV_ENTRY(LINK_TIMEOUT),
1868 +#ifndef AVALANCHE /* Avalanche boards use only one mac port */
1869 + _ENV_ENTRY(MAC_PORT),
1870 +#endif
1871 + _ENV_ENTRY(PATH),
1872 + _ENV_ENTRY(HOSTNAME),
1873 +#ifdef WLAN
1874 + _ENV_ENTRY(HW_REV_MAJOR),
1875 + _ENV_ENTRY(HW_REV_MINOR),
1876 + _ENV_ENTRY(HW_PATCH),
1877 + _ENV_ENTRY(SW_PATCH),
1878 + _ENV_ENTRY(SERIAL_NUMBER),
1879 +#endif
1880 + _ENV_ENTRY(TFTPCFG),
1881 +#if defined (TNETV1050_BOARD)
1882 + _ENV_ENTRY(HWA_ESWITCH),
1883 +#endif
1884 + /*
1885 + * Add new entries below this.
1886 + */
1887 + /* Adam2 environment name alias. */
1888 + { .idx = IPA, .nm = "my_ipaddress" },
1889 + { .idx = CPUFREQ, .nm = "cpufrequency" },
1890 + { .idx = SYSFREQ, .nm = "sysfrequency" },
1891 + { .idx = HWA_0, .nm = "maca" },
1892 +#ifndef AVALANCHE
1893 + { .idx = HWA_1, .nm = "macb" },
1894 +#endif
1895 + { .idx = MODETTY0, .nm = "modetty0" },
1896 + { .idx = MODETTY1, .nm = "modetty1" },
1897 + { .idx = MEMSZ, .nm = "memsize" },
1898 +
1899 + _ENV_ENTRY(env_vars_end) /* delimiter. */
1900 +};
1901 +
1902 +static inline int var_to_idx(const char* var)
1903 +{
1904 + int ii;
1905 +
1906 + /* go over the list of pre-defined environment variables */
1907 + for (ii = env_vars_start; env_ns[ii].idx != env_vars_end; ii++){
1908 + /* check if the env variable is listed */
1909 + if (strcmp(env_ns[ii].nm, var) == 0) {
1910 + return env_ns[ii].idx;
1911 + }
1912 +
1913 + /* if an alias is present, check if the alias matches
1914 + * the description
1915 + */
1916 + if (env_ns[ii].alias != NULL) {
1917 + if (strcmp(env_ns[ii].alias, var) == 0) {
1918 + return env_ns[ii].idx;
1919 + }
1920 + }
1921 + }
1922 + return 0;
1923 +}
1924 +
1925 +extern int *_prom_envp;
1926 +
1927 +/* FIXME: reading from the flash is extremly unstable. Sometime a read returns garbage,
1928 + * the next read some seconds later is ok. It looks like something is hidding or
1929 + * overlay the flash address at 0xb0000000. Is this possible?
1930 + *
1931 + * The readb() and while() usage below is a attempt of a workarround - with limited success.
1932 + */
1933 +
1934 +static inline struct env_variable* get_var_by_number(int index)
1935 +{
1936 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1937 + volatile unsigned char nr;
1938 + int i;
1939 +
1940 + env_var++; /* skip signature */
1941 +
1942 + i = 0;
1943 + nr = readb(&(env_var->varNum));
1944 +
1945 + while (i < max_env_entry && nr != 0xFF) {
1946 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_PREFINED) {
1947 + if (nr == index) {
1948 + return env_var;
1949 + }
1950 + }
1951 + i++;
1952 + env_var = get_next_block(env_var);
1953 + nr = readb(&(env_var->varNum));
1954 + }
1955 +
1956 + return NULL;
1957 +}
1958 +
1959 +static inline struct env_variable* get_var_by_name(char *var)
1960 +{
1961 + struct env_variable *env_var = (struct env_variable *)_prom_envp;
1962 + volatile unsigned char nr;
1963 + int i;
1964 +
1965 + env_var++; /* skip signature */
1966 +
1967 + nr = readb(&(env_var->varNum));
1968 + i = 0;
1969 +
1970 + while (i < max_env_entry && nr != 0xFF) {
1971 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
1972 + if (strcmp(var, env_var->data) == 0)
1973 + return env_var;
1974 + }
1975 + i++;
1976 + env_var = get_next_block(env_var);
1977 + nr = readb(&(env_var->varNum));
1978 + }
1979 + return NULL;
1980 +}
1981 +
1982 +static inline struct env_variable* get_var(char *var)
1983 +{
1984 + int index = var_to_idx(var);
1985 +
1986 + if (index)
1987 + return get_var_by_number(index);
1988 + else
1989 + return get_var_by_name(var);
1990 +
1991 + return NULL;
1992 +}
1993 +
1994 +static inline char *get_value(struct env_variable* env_var)
1995 +{
1996 + unsigned char *name;
1997 + unsigned char *value;
1998 + unsigned short chksum;
1999 + int i;
2000 +
2001 + chksum = env_var->varNum + env_var->ctrl + env_var->numCells;
2002 +
2003 + if ((env_var->ctrl & ENV_CTRL_MASK) == ENV_DYNAMIC) {
2004 + name = env_var->data;
2005 + value = env_var->data + strlen(name) + 1;
2006 +
2007 + for(i = 0; i < strlen(name); i++)
2008 + chksum += name[i];
2009 + } else
2010 + value = env_var->data;
2011 +
2012 + for (i = 0; i < strlen(value); i++)
2013 + chksum += value[i];
2014 +
2015 + chksum += env_var->chksum;
2016 + chksum = ~(chksum);
2017 +
2018 + if(chksum != 0) {
2019 + return NULL;
2020 + }
2021 +
2022 + return value;
2023 +}
2024 +
2025 +struct psbl_rec {
2026 + unsigned int psbl_size;
2027 + unsigned int env_base;
2028 + unsigned int env_size;
2029 + unsigned int ffs_base;
2030 + unsigned int ffs_size;
2031 +};
2032 +
2033 +char *prom_psp_getenv(char *envname)
2034 +{
2035 + struct env_variable* env_var;
2036 + char *value;
2037 +
2038 + if (strcmp("bootloader", envname) == 0)
2039 + return "PSPBoot";
2040 +
2041 + if (!(env_var = get_var(envname)))
2042 + return NULL;
2043 +
2044 + value = get_value(env_var);
2045 +
2046 + return value;
2047 +}
2048 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
2049 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
2050 +++ linux.dev/arch/mips/ar7/reset.c 2005-08-12 19:32:05.139225208 +0200
2051 @@ -0,0 +1,56 @@
2052 +/*
2053 + * Carsten Langgaard, carstenl@mips.com
2054 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2055 + *
2056 + * ########################################################################
2057 + *
2058 + * This program is free software; you can distribute it and/or modify it
2059 + * under the terms of the GNU General Public License (Version 2) as
2060 + * published by the Free Software Foundation.
2061 + *
2062 + * This program is distributed in the hope it will be useful, but WITHOUT
2063 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2064 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2065 + * for more details.
2066 + *
2067 + * You should have received a copy of the GNU General Public License along
2068 + * with this program; if not, write to the Free Software Foundation, Inc.,
2069 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2070 + *
2071 + * ########################################################################
2072 + *
2073 + * Reset the MIPS boards.
2074 + *
2075 + */
2076 +#include <linux/config.h>
2077 +
2078 +#include <asm/reboot.h>
2079 +#include <asm/mips-boards/generic.h>
2080 +
2081 +static void ar7_machine_restart(char *command);
2082 +static void ar7_machine_halt(void);
2083 +static void ar7_machine_power_off(void);
2084 +
2085 +static void ar7_machine_restart(char *command)
2086 +{
2087 + volatile unsigned int *softres_reg = (void *)(KSEG1ADDR(0x08611600 + 0x4));
2088 +
2089 + *softres_reg = 1;
2090 +}
2091 +
2092 +static void ar7_machine_halt(void)
2093 +{
2094 +
2095 +}
2096 +
2097 +static void ar7_machine_power_off(void)
2098 +{
2099 +
2100 +}
2101 +
2102 +void ar7_reboot_setup(void)
2103 +{
2104 + _machine_restart = ar7_machine_restart;
2105 + _machine_halt = ar7_machine_halt;
2106 + _machine_power_off = ar7_machine_power_off;
2107 +}
2108 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
2109 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
2110 +++ linux.dev/arch/mips/ar7/setup.c 2005-08-12 19:32:05.139225208 +0200
2111 @@ -0,0 +1,120 @@
2112 +/*
2113 + * Carsten Langgaard, carstenl@mips.com
2114 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
2115 + *
2116 + * This program is free software; you can distribute it and/or modify it
2117 + * under the terms of the GNU General Public License (Version 2) as
2118 + * published by the Free Software Foundation.
2119 + *
2120 + * This program is distributed in the hope it will be useful, but WITHOUT
2121 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2122 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2123 + * for more details.
2124 + *
2125 + * You should have received a copy of the GNU General Public License along
2126 + * with this program; if not, write to the Free Software Foundation, Inc.,
2127 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2128 + */
2129 +#include <linux/config.h>
2130 +#include <linux/init.h>
2131 +#include <linux/sched.h>
2132 +#include <linux/mc146818rtc.h>
2133 +#include <linux/ioport.h>
2134 +
2135 +#include <asm/cpu.h>
2136 +#include <asm/bootinfo.h>
2137 +#include <asm/irq.h>
2138 +#include <asm/mips-boards/generic.h>
2139 +#include <asm/mips-boards/prom.h>
2140 +
2141 +#include <asm/dma.h>
2142 +#include <asm/time.h>
2143 +#include <asm/traps.h>
2144 +
2145 +#ifdef CONFIG_KGDB
2146 +extern void rs_kgdb_hook(int);
2147 +int remote_debug = 0;
2148 +#endif
2149 +
2150 +extern struct rtc_ops no_rtc_ops;
2151 +
2152 +extern void ar7_reboot_setup(void);
2153 +
2154 +extern void ar7_time_init(void);
2155 +extern void ar7_timer_setup(struct irqaction *irq);
2156 +
2157 +const char *get_system_type(void)
2158 +{
2159 + return "Texas Instruments AR7";
2160 +}
2161 +
2162 +void __init ar7_setup(void)
2163 +{
2164 +#ifdef CONFIG_KGDB
2165 + int rs_putDebugChar(char);
2166 + char rs_getDebugChar(void);
2167 + extern int (*generic_putDebugChar)(char);
2168 + extern char (*generic_getDebugChar)(void);
2169 +#endif
2170 + char *argptr;
2171 +#ifdef CONFIG_SERIAL_CONSOLE
2172 + argptr = prom_getcmdline();
2173 + if ((argptr = strstr(argptr, "console=")) == NULL) {
2174 + char console[20];
2175 + char *s;
2176 + int i = 0;
2177 +
2178 + s = prom_getenv("modetty0");
2179 + strcpy(console, "38400");
2180 +
2181 + if (s != NULL) {
2182 + while (s[i] >= '0' && s[i] <= '9')
2183 + i++;
2184 +
2185 + if (i > 0) {
2186 + strncpy(console, s, i);
2187 + console[i] = 0;
2188 + }
2189 + }
2190 +
2191 + argptr = prom_getcmdline();
2192 + strcat(argptr, " console=ttyS0,");
2193 + strcat(argptr, console);
2194 + }
2195 +#endif
2196 +
2197 +#ifdef CONFIG_KGDB
2198 + argptr = prom_getcmdline();
2199 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
2200 + int line;
2201 + argptr += strlen("kgdb=ttyS");
2202 + if (*argptr != '0' && *argptr != '1')
2203 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
2204 + "falling back to /dev/ttyS1\n", *argptr);
2205 + line = *argptr == '0' ? 0 : 1;
2206 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
2207 + line ? 1 : 0);
2208 +
2209 + rs_kgdb_hook(line);
2210 + generic_putDebugChar = rs_putDebugChar;
2211 + generic_getDebugChar = rs_getDebugChar;
2212 +
2213 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
2214 + "please connect your debugger\n", line ? 1 : 0);
2215 +
2216 + remote_debug = 1;
2217 + /* Breakpoints are in init_IRQ() */
2218 + }
2219 +#endif
2220 +
2221 + argptr = prom_getcmdline();
2222 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
2223 + cpu_data[0].options &= ~MIPS_CPU_FPU;
2224 +
2225 + rtc_ops = &no_rtc_ops;
2226 +
2227 + ar7_reboot_setup();
2228 +
2229 + board_time_init = ar7_time_init;
2230 + board_timer_setup = ar7_timer_setup;
2231 +}
2232 diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
2233 --- linux.old/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
2234 +++ linux.dev/arch/mips/ar7/time.c 2005-08-12 23:34:00.272589528 +0200
2235 @@ -0,0 +1,124 @@
2236 +/*
2237 + * Carsten Langgaard, carstenl@mips.com
2238 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2239 + *
2240 + * ########################################################################
2241 + *
2242 + * This program is free software; you can distribute it and/or modify it
2243 + * under the terms of the GNU General Public License (Version 2) as
2244 + * published by the Free Software Foundation.
2245 + *
2246 + * This program is distributed in the hope it will be useful, but WITHOUT
2247 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2248 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2249 + * for more details.
2250 + *
2251 + * You should have received a copy of the GNU General Public License along
2252 + * with this program; if not, write to the Free Software Foundation, Inc.,
2253 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2254 + *
2255 + * ########################################################################
2256 + *
2257 + * Setting up the clock on the MIPS boards.
2258 + *
2259 + */
2260 +
2261 +#include <linux/types.h>
2262 +#include <linux/config.h>
2263 +#include <linux/init.h>
2264 +#include <linux/kernel_stat.h>
2265 +#include <linux/sched.h>
2266 +#include <linux/spinlock.h>
2267 +
2268 +#include <asm/mipsregs.h>
2269 +#include <asm/ptrace.h>
2270 +#include <asm/hardirq.h>
2271 +#include <asm/div64.h>
2272 +
2273 +#include <linux/interrupt.h>
2274 +#include <linux/mc146818rtc.h>
2275 +#include <linux/timex.h>
2276 +
2277 +#include <asm/mips-boards/generic.h>
2278 +#include <asm/mips-boards/prom.h>
2279 +
2280 +extern asmlinkage void mipsIRQ(void);
2281 +
2282 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
2283 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
2284 +
2285 +#define MIPS_CPU_TIMER_IRQ 7
2286 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
2287 +
2288 +static inline void ack_r4ktimer(unsigned long newval)
2289 +{
2290 + write_c0_compare(newval);
2291 +}
2292 +
2293 +void ar7_timer_interrupt(struct pt_regs *regs)
2294 +{
2295 + int cpu = smp_processor_id();
2296 +
2297 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
2298 +
2299 + if (r4k_offset == 0)
2300 + goto null;
2301 +
2302 + do {
2303 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
2304 + do_timer(regs);
2305 + r4k_cur += r4k_offset;
2306 + ack_r4ktimer(r4k_cur);
2307 +
2308 + } while (((unsigned long)read_c0_count()
2309 + - r4k_cur) < 0x7fffffff);
2310 +
2311 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
2312 +
2313 + if (softirq_pending(cpu))
2314 + do_softirq();
2315 +
2316 + return;
2317 +
2318 +null:
2319 + ack_r4ktimer(0);
2320 +}
2321 +
2322 +/*
2323 + * Figure out the r4k offset, the amount to increment the compare
2324 + * register for each time tick.
2325 + */
2326 +static unsigned long __init cal_r4koff(void)
2327 +{
2328 + return ((CONFIG_AR7_CPU*500000)/HZ);
2329 +}
2330 +
2331 +void __init ar7_time_init(void)
2332 +{
2333 + unsigned long flags;
2334 + unsigned int est_freq;
2335 +
2336 + set_except_vector(0, mipsIRQ);
2337 + write_c0_count(0);
2338 +
2339 + printk("calculating r4koff... ");
2340 + r4k_offset = cal_r4koff();
2341 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
2342 +
2343 + est_freq = 2*r4k_offset*HZ;
2344 + est_freq += 5000; /* round */
2345 + est_freq -= est_freq%10000;
2346 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
2347 + (est_freq%1000000)*100/1000000);
2348 +}
2349 +
2350 +void __init ar7_timer_setup(struct irqaction *irq)
2351 +{
2352 + /* we are using the cpu counter for timer interrupts */
2353 + irq->handler = no_action; /* we use our own handler */
2354 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
2355 +
2356 + r4k_cur = (read_c0_count() + r4k_offset);
2357 + write_c0_compare(r4k_cur);
2358 + set_c0_status(ALLINTS);
2359 +}
2360 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
2361 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
2362 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-08-12 19:32:05.140225056 +0200
2363 @@ -0,0 +1,924 @@
2364 +/******************************************************************************
2365 + * FILE PURPOSE: TNETD73xx Misc modules API Source
2366 + ******************************************************************************
2367 + * FILE NAME: tnetd73xx_misc.c
2368 + *
2369 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
2370 + * FSER Modules API
2371 + * As per TNETD73xx specifications
2372 + *
2373 + * REVISION HISTORY:
2374 + * 27 Nov 02 - Sharath Kumar PSP TII
2375 + * 14 Feb 03 - Anant Gole PSP TII
2376 + *
2377 + * (C) Copyright 2002, Texas Instruments, Inc
2378 + *******************************************************************************/
2379 +
2380 +#define LITTLE_ENDIAN
2381 +#define _LINK_KSEG0_
2382 +
2383 +#include <linux/types.h>
2384 +#include <asm/ar7/tnetd73xx.h>
2385 +#include <asm/ar7/tnetd73xx_misc.h>
2386 +
2387 +/* TNETD73XX Revision */
2388 +u32 tnetd73xx_get_revision(void)
2389 +{
2390 + /* Read Chip revision register - This register is from GPIO module */
2391 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2392 +}
2393 +
2394 +/*****************************************************************************
2395 + * Reset Control Module
2396 + *****************************************************************************/
2397 +
2398 +
2399 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2400 +{
2401 + u32 reset_status;
2402 +
2403 + /* read current reset register */
2404 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2405 +
2406 + if (reset_ctrl == OUT_OF_RESET)
2407 + {
2408 + /* bring module out of reset */
2409 + reset_status |= (1 << reset_module);
2410 + }
2411 + else
2412 + {
2413 + /* put module in reset */
2414 + reset_status &= (~(1 << reset_module));
2415 + }
2416 +
2417 + /* write to the reset register */
2418 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2419 +}
2420 +
2421 +
2422 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2423 +{
2424 + u32 reset_status;
2425 +
2426 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2427 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2428 +}
2429 +
2430 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2431 +{
2432 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2433 +}
2434 +
2435 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2436 +
2437 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2438 +{
2439 + u32 sys_reset_status;
2440 +
2441 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2442 +
2443 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2444 +}
2445 +
2446 +
2447 +/*****************************************************************************
2448 + * Power Control Module
2449 + *****************************************************************************/
2450 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2451 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2452 +
2453 +
2454 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2455 +{
2456 + u32 power_status;
2457 +
2458 + /* read current power down control register */
2459 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2460 +
2461 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2462 + {
2463 + /* power down the module */
2464 + power_status |= (1 << power_module);
2465 + }
2466 + else
2467 + {
2468 + /* power on the module */
2469 + power_status &= (~(1 << power_module));
2470 + }
2471 +
2472 + /* write to the reset register */
2473 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2474 +}
2475 +
2476 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2477 +{
2478 + u32 power_status;
2479 +
2480 + /* read current power down control register */
2481 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2482 +
2483 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2484 +}
2485 +
2486 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2487 +{
2488 + u32 power_status;
2489 +
2490 + /* read current power down control register */
2491 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2492 +
2493 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2494 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2495 +
2496 + /* write to power down control register */
2497 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2498 +}
2499 +
2500 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2501 +{
2502 + u32 power_status;
2503 +
2504 + /* read current power down control register */
2505 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2506 +
2507 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2508 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2509 +
2510 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2511 +}
2512 +
2513 +
2514 +/*****************************************************************************
2515 + * Wakeup Control
2516 + *****************************************************************************/
2517 +
2518 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2519 +
2520 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2521 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2522 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2523 +{
2524 + u32 wakeup_status;
2525 +
2526 + /* read the wakeup control register */
2527 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2528 +
2529 + /* enable/disable */
2530 + if (wakeup_ctrl == WAKEUP_ENABLED)
2531 + {
2532 + /* enable wakeup */
2533 + wakeup_status |= wakeup_int;
2534 + }
2535 + else
2536 + {
2537 + /* disable wakeup */
2538 + wakeup_status &= (~wakeup_int);
2539 + }
2540 +
2541 + /* set polarity */
2542 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2543 + {
2544 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2545 + }
2546 + else
2547 + {
2548 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2549 + }
2550 +
2551 + /* write the wakeup control register */
2552 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2553 +}
2554 +
2555 +
2556 +/*****************************************************************************
2557 + * FSER Control
2558 + *****************************************************************************/
2559 +
2560 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2561 +{
2562 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2563 +}
2564 +
2565 +/*****************************************************************************
2566 + * Clock Control
2567 + *****************************************************************************/
2568 +
2569 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2570 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2571 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2572 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2573 +
2574 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2575 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2576 +
2577 +#define CLKC_PRE_DIVIDER 0x0000001F
2578 +#define CLKC_POST_DIVIDER 0x001F0000
2579 +
2580 +#define CLKC_PLL_STATUS 0x1
2581 +#define CLKC_PLL_FACTOR 0x0000F000
2582 +
2583 +#define BOOTCR_PLL_BYPASS (1 << 5)
2584 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2585 +
2586 +#define MIPS_PLL_SELECT 0x00030000
2587 +#define SYSTEM_PLL_SELECT 0x0000C000
2588 +#define USB_PLL_SELECT 0x000C0000
2589 +#define ADSLSS_PLL_SELECT 0x00C00000
2590 +
2591 +#define MIPS_AFECLKI_SELECT 0x00000000
2592 +#define MIPS_REFCLKI_SELECT 0x00010000
2593 +#define MIPS_XTAL3IN_SELECT 0x00020000
2594 +
2595 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2596 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2597 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2598 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2599 +
2600 +#define USB_SYSPLL_SELECT 0x00000000
2601 +#define USB_REFCLKI_SELECT 0x00040000
2602 +#define USB_XTAL3IN_SELECT 0x00080000
2603 +#define USB_MIPSPLL_SELECT 0x000C0000
2604 +
2605 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2606 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2607 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2608 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2609 +
2610 +#define SYS_MAX CLK_MHZ(150)
2611 +#define SYS_MIN CLK_MHZ(1)
2612 +
2613 +#define MIPS_SYNC_MAX SYS_MAX
2614 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2615 +#define MIPS_MIN CLK_MHZ(1)
2616 +
2617 +#define USB_MAX CLK_MHZ(100)
2618 +#define USB_MIN CLK_MHZ(1)
2619 +
2620 +#define ADSL_MAX CLK_MHZ(180)
2621 +#define ADSL_MIN CLK_MHZ(1)
2622 +
2623 +#define PLL_MUL_MAXFACTOR 15
2624 +#define MAX_DIV_VALUE 32
2625 +#define MIN_DIV_VALUE 1
2626 +
2627 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2628 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2629 +
2630 +#define DIVIDER_LOCK_TIME 10100
2631 +#define PLL_LOCK_TIME 10100 * 75
2632 +
2633 +
2634 +
2635 + /****************************************************************************
2636 + * DATA PURPOSE: PRIVATE Variables
2637 + **************************************************************************/
2638 + static u32 *clk_src[4];
2639 + static u32 mips_pll_out;
2640 + static u32 sys_pll_out;
2641 + static u32 afeclk_inp;
2642 + static u32 refclk_inp;
2643 + static u32 xtal_inp;
2644 + static u32 present_min;
2645 + static u32 present_max;
2646 +
2647 + /* Forward References */
2648 + static u32 find_gcd(u32 min, u32 max);
2649 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2650 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2651 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2652 + static void find_approx(u32 *,u32 *,u32);
2653 +
2654 + /****************************************************************************
2655 + * FUNCTION: tnetd73xx_clkc_init
2656 + ****************************************************************************
2657 + * Description: The routine initializes the internal variables depending on
2658 + * on the sources selected for different clocks.
2659 + ***************************************************************************/
2660 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2661 +{
2662 +
2663 + u32 choice;
2664 +
2665 + afeclk_inp = afeclk;
2666 + refclk_inp = refclk;
2667 + xtal_inp = xtal3in;
2668 +
2669 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2670 + switch(choice)
2671 + {
2672 + case MIPS_AFECLKI_SELECT:
2673 + clk_src[CLKC_MIPS] = &afeclk_inp;
2674 + break;
2675 +
2676 + case MIPS_REFCLKI_SELECT:
2677 + clk_src[CLKC_MIPS] = &refclk_inp;
2678 + break;
2679 +
2680 + case MIPS_XTAL3IN_SELECT:
2681 + clk_src[CLKC_MIPS] = &xtal_inp;
2682 + break;
2683 +
2684 + default :
2685 + clk_src[CLKC_MIPS] = 0;
2686 +
2687 + }
2688 +
2689 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2690 + switch(choice)
2691 + {
2692 + case SYSTEM_AFECLKI_SELECT:
2693 + clk_src[CLKC_SYS] = &afeclk_inp;
2694 + break;
2695 +
2696 + case SYSTEM_REFCLKI_SELECT:
2697 + clk_src[CLKC_SYS] = &refclk_inp;
2698 + break;
2699 +
2700 + case SYSTEM_XTAL3IN_SELECT:
2701 + clk_src[CLKC_SYS] = &xtal_inp;
2702 + break;
2703 +
2704 + case SYSTEM_MIPSPLL_SELECT:
2705 + clk_src[CLKC_SYS] = &mips_pll_out;
2706 + break;
2707 +
2708 + default :
2709 + clk_src[CLKC_SYS] = 0;
2710 +
2711 + }
2712 +
2713 +
2714 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2715 + switch(choice)
2716 + {
2717 + case ADSLSS_AFECLKI_SELECT:
2718 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2719 + break;
2720 +
2721 + case ADSLSS_REFCLKI_SELECT:
2722 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2723 + break;
2724 +
2725 + case ADSLSS_XTAL3IN_SELECT:
2726 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2727 + break;
2728 +
2729 + case ADSLSS_MIPSPLL_SELECT:
2730 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2731 + break;
2732 +
2733 + default :
2734 + clk_src[CLKC_ADSLSS] = 0;
2735 +
2736 + }
2737 +
2738 +
2739 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2740 + switch(choice)
2741 + {
2742 + case USB_SYSPLL_SELECT:
2743 + clk_src[CLKC_USB] = &sys_pll_out ;
2744 + break;
2745 +
2746 + case USB_REFCLKI_SELECT:
2747 + clk_src[CLKC_USB] = &refclk_inp;
2748 + break;
2749 +
2750 + case USB_XTAL3IN_SELECT:
2751 + clk_src[CLKC_USB] = &xtal_inp;
2752 + break;
2753 +
2754 + case USB_MIPSPLL_SELECT:
2755 + clk_src[CLKC_USB] = &mips_pll_out;
2756 + break;
2757 +
2758 + default :
2759 + clk_src[CLKC_USB] = 0;
2760 +
2761 + }
2762 +}
2763 +
2764 +
2765 +
2766 +/****************************************************************************
2767 + * FUNCTION: tnetd73xx_clkc_set_freq
2768 + ****************************************************************************
2769 + * Description: The above routine is called to set the output_frequency of the
2770 + * selected clock(using clk_id) to the required value given
2771 + * by the variable output_freq.
2772 + ***************************************************************************/
2773 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2774 +(
2775 + TNETD73XX_CLKC_ID_T clk_id,
2776 + u32 output_freq
2777 + )
2778 +{
2779 + u32 base_freq;
2780 + u32 multiplier;
2781 + u32 divider;
2782 + u32 min_prediv;
2783 + u32 max_prediv;
2784 + u32 prediv;
2785 + u32 postdiv;
2786 + u32 temp;
2787 +
2788 + /* check if PLLs are bypassed*/
2789 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2790 + {
2791 + return TNETD73XX_ERR_ERROR;
2792 + }
2793 +
2794 + /*check if the requested output_frequency is in valid range*/
2795 + switch( clk_id )
2796 + {
2797 + case CLKC_SYS:
2798 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2799 + {
2800 + return TNETD73XX_ERR_ERROR;
2801 + }
2802 + present_min = SYS_MIN;
2803 + present_max = SYS_MAX;
2804 + break;
2805 +
2806 + case CLKC_MIPS:
2807 + if((output_freq < MIPS_MIN) ||
2808 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2809 + {
2810 + return TNETD73XX_ERR_ERROR;
2811 + }
2812 + present_min = MIPS_MIN;
2813 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2814 + break;
2815 +
2816 + case CLKC_USB:
2817 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2818 + {
2819 + return TNETD73XX_ERR_ERROR;
2820 + }
2821 + present_min = USB_MIN;
2822 + present_max = USB_MAX;
2823 + break;
2824 +
2825 + case CLKC_ADSLSS:
2826 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2827 + {
2828 + return TNETD73XX_ERR_ERROR;
2829 + }
2830 + present_min = ADSL_MIN;
2831 + present_max = ADSL_MAX;
2832 + break;
2833 + }
2834 +
2835 +
2836 + base_freq = get_base_frequency(clk_id);
2837 +
2838 +
2839 + /* check for minimum base frequency value */
2840 + if( base_freq < MIN_PLL_INP_FREQ)
2841 + {
2842 + return TNETD73XX_ERR_ERROR;
2843 + }
2844 +
2845 + get_val(output_freq, base_freq, &multiplier, &divider);
2846 +
2847 + /* check multiplier range */
2848 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2849 + {
2850 + return TNETD73XX_ERR_ERROR;
2851 + }
2852 +
2853 + /* check divider value */
2854 + if( divider == 0 )
2855 + {
2856 + return TNETD73XX_ERR_ERROR;
2857 + }
2858 +
2859 + /*compute minimum and maximum predivider values */
2860 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2861 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2862 +
2863 + /*adjust the value of divider so that it not less than minimum predivider value*/
2864 + if (divider < min_prediv)
2865 + {
2866 + temp = CEIL(min_prediv, divider);
2867 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2868 + {
2869 + return TNETD73XX_ERR_ERROR ;
2870 + }
2871 + else
2872 + {
2873 + multiplier = temp * multiplier;
2874 + divider = min_prediv;
2875 + }
2876 +
2877 + }
2878 +
2879 + /* compute predivider and postdivider values */
2880 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2881 + postdiv = CEIL(divider,prediv);
2882 +
2883 + /*return fail if postdivider value falls out of range */
2884 + if(postdiv > MAX_DIV_VALUE)
2885 + {
2886 + return TNETD73XX_ERR_ERROR;
2887 + }
2888 +
2889 +
2890 + /*write predivider and postdivider values*/
2891 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2892 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2893 +
2894 + /*wait for divider output to stabilise*/
2895 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2896 +
2897 + /*write to PLL clock register*/
2898 +
2899 + if(clk_id == CLKC_SYS)
2900 + {
2901 + /* but before writing put DRAM to hold mode */
2902 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2903 + }
2904 + /*Bring PLL into div mode */
2905 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2906 +
2907 + /*compute the word to be written to PLLCR
2908 + *corresponding to multiplier value
2909 + */
2910 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2911 +
2912 + /* wait till PLL enters div mode */
2913 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2914 + /*nothing*/;
2915 +
2916 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2917 +
2918 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2919 + /*nothing*/;
2920 +
2921 +
2922 + /*wait for External pll to lock*/
2923 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2924 +
2925 + if(clk_id == CLKC_SYS)
2926 + {
2927 + /* Bring DRAM out of hold */
2928 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2929 + }
2930 +
2931 + return TNETD73XX_ERR_OK ;
2932 +}
2933 +
2934 +/****************************************************************************
2935 + * FUNCTION: tnetd73xx_clkc_get_freq
2936 + ****************************************************************************
2937 + * Description: The above routine is called to get the output_frequency of the
2938 + * selected clock( clk_id)
2939 + ***************************************************************************/
2940 +u32 tnetd73xx_clkc_get_freq
2941 +(
2942 + TNETD73XX_CLKC_ID_T clk_id
2943 + )
2944 +{
2945 +
2946 + u32 clk_ctrl_register;
2947 + u32 clk_pll_setting;
2948 + u32 clk_predivider;
2949 + u32 clk_postdivider;
2950 + u16 pll_factor;
2951 + u32 base_freq;
2952 + u32 divider;
2953 +
2954 + base_freq = get_base_frequency(clk_id);
2955 +
2956 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2957 +
2958 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2959 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2960 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2961 +
2962 + divider = clk_predivider * clk_postdivider;
2963 +
2964 +
2965 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2966 + {
2967 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2968 + }
2969 +
2970 +
2971 + else
2972 + {
2973 + /* return the current clock speed based upon the PLL setting */
2974 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2975 +
2976 + /* Get the PLL multiplication factor */
2977 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2978 +
2979 + /* Check if we're in divide mode or multiply mode */
2980 + if((clk_pll_setting & 0x1) == 0)
2981 + {
2982 + /* We're in divide mode */
2983 + if(pll_factor < 0x10)
2984 + return (CEIL(base_freq >> 1, divider));
2985 + else
2986 + return (CEIL(base_freq >> 2, divider));
2987 + }
2988 +
2989 + else /* We're in PLL mode */
2990 + {
2991 + /* See if PLLNDIV & PLLDIV are set */
2992 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2993 + {
2994 + if(clk_pll_setting & 0x1000)
2995 + {
2996 + /* clk = base_freq * k/2 */
2997 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2998 + }
2999 + else
3000 + {
3001 + /* clk = base_freq * (k-1) / 4)*/
3002 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
3003 + }
3004 + }
3005 + else
3006 + {
3007 + if(pll_factor < 0x10)
3008 + {
3009 + /* clk = base_freq * k */
3010 + return(CEIL(base_freq * pll_factor, divider));
3011 + }
3012 +
3013 + else
3014 + {
3015 + /* clk = base_freq */
3016 + return(CEIL(base_freq, divider));
3017 + }
3018 + }
3019 + }
3020 + return(0); /* Should never reach here */
3021 +
3022 + }
3023 +
3024 +}
3025 +
3026 +
3027 +/* local helper functions */
3028 +
3029 +/****************************************************************************
3030 + * FUNCTION: get_base_frequency
3031 + ****************************************************************************
3032 + * Description: The above routine is called to get base frequency of the clocks.
3033 + ***************************************************************************/
3034 +
3035 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
3036 +{
3037 + /* update the current MIPs PLL output value, if the required
3038 + * source is MIPS PLL
3039 + */
3040 + if ( clk_src[clk_id] == &mips_pll_out)
3041 + {
3042 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
3043 + }
3044 +
3045 +
3046 + /* update the current System PLL output value, if the required
3047 + * source is system PLL
3048 + */
3049 + if ( clk_src[clk_id] == &sys_pll_out)
3050 + {
3051 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
3052 + }
3053 +
3054 + return (*clk_src[clk_id]);
3055 +
3056 +}
3057 +
3058 +
3059 +
3060 +/****************************************************************************
3061 + * FUNCTION: find_gcd
3062 + ****************************************************************************
3063 + * Description: The above routine is called to find gcd of 2 numbers.
3064 + ***************************************************************************/
3065 +static u32 find_gcd
3066 +(
3067 + u32 min,
3068 + u32 max
3069 + )
3070 +{
3071 + if (max % min == 0)
3072 + {
3073 + return min;
3074 + }
3075 + else
3076 + {
3077 + return find_gcd(max % min, min);
3078 + }
3079 +}
3080 +
3081 +/****************************************************************************
3082 + * FUNCTION: compute_prediv
3083 + ****************************************************************************
3084 + * Description: The above routine is called to compute predivider value
3085 + ***************************************************************************/
3086 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
3087 +{
3088 + u16 prediv;
3089 +
3090 + /* return the divider itself it it falls within the range of predivider*/
3091 + if (min <= divider && divider <= max)
3092 + {
3093 + return divider;
3094 + }
3095 +
3096 + /* find a value for prediv such that it is a factor of divider */
3097 + for (prediv = max; prediv >= min ; prediv--)
3098 + {
3099 + if ( (divider % prediv) == 0 )
3100 + {
3101 + return prediv;
3102 + }
3103 + }
3104 +
3105 + /* No such factor exists, return min as prediv */
3106 + return min;
3107 +}
3108 +
3109 +/****************************************************************************
3110 + * FUNCTION: get_val
3111 + ****************************************************************************
3112 + * Description: This routine is called to get values of divider and multiplier.
3113 + ***************************************************************************/
3114 +
3115 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
3116 +{
3117 + u32 temp_mul;
3118 + u32 temp_div;
3119 + u32 gcd;
3120 + u32 min_freq;
3121 + u32 max_freq;
3122 +
3123 + /* find gcd of base_freq, output_freq */
3124 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
3125 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
3126 + gcd = find_gcd(min_freq , max_freq);
3127 +
3128 + if(gcd == 0)
3129 + return; /* ERROR */
3130 +
3131 + /* compute values of multiplier and divider */
3132 + temp_mul = output_freq / gcd;
3133 + temp_div = base_freq / gcd;
3134 +
3135 +
3136 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
3137 + if( temp_mul > PLL_MUL_MAXFACTOR )
3138 + {
3139 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
3140 + return;
3141 +
3142 + find_approx(&temp_mul,&temp_div,base_freq);
3143 + }
3144 +
3145 + *multiplier = temp_mul;
3146 + *divider = temp_div;
3147 +}
3148 +
3149 +/****************************************************************************
3150 + * FUNCTION: find_approx
3151 + ****************************************************************************
3152 + * Description: This function gets the approx value of num/denom.
3153 + ***************************************************************************/
3154 +
3155 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
3156 +{
3157 + u32 num1;
3158 + u32 denom1;
3159 + u32 num2;
3160 + u32 denom2;
3161 + int32_t closest;
3162 + int32_t prev_closest;
3163 + u32 temp_num;
3164 + u32 temp_denom;
3165 + u32 normalize;
3166 + u32 gcd;
3167 + u32 output_freq;
3168 +
3169 + num1 = *num;
3170 + denom1 = *denom;
3171 +
3172 + prev_closest = 0x7fffffff; /* maximum possible value */
3173 + num2 = num1;
3174 + denom2 = denom1;
3175 +
3176 + /* start with max */
3177 + for(temp_num = 15; temp_num >=1; temp_num--)
3178 + {
3179 +
3180 + temp_denom = CEIL(temp_num * denom1, num1);
3181 + output_freq = (temp_num * base_freq) / temp_denom;
3182 +
3183 + if(temp_denom < 1)
3184 + {
3185 + break;
3186 + }
3187 + else
3188 + {
3189 + normalize = CEIL(num1,temp_num);
3190 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
3191 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
3192 + {
3193 + prev_closest = closest;
3194 + num2 = temp_num;
3195 + denom2 = temp_denom;
3196 + }
3197 +
3198 + }
3199 +
3200 + }
3201 +
3202 + gcd = find_gcd(num2,denom2);
3203 + num2 = num2 / gcd;
3204 + denom2 = denom2 /gcd;
3205 +
3206 + *num = num2;
3207 + *denom = denom2;
3208 +}
3209 +
3210 +
3211 +/*****************************************************************************
3212 + * GPIO Control
3213 + *****************************************************************************/
3214 +
3215 +/****************************************************************************
3216 + * FUNCTION: tnetd73xx_gpio_init
3217 + ***************************************************************************/
3218 +void tnetd73xx_gpio_init()
3219 +{
3220 + /* Bring module out of reset */
3221 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
3222 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
3223 +}
3224 +
3225 +/****************************************************************************
3226 + * FUNCTION: tnetd73xx_gpio_ctrl
3227 + ***************************************************************************/
3228 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
3229 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
3230 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
3231 +{
3232 + u32 pin_status;
3233 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
3234 + if (pin_mode == GPIO_PIN)
3235 + {
3236 + pin_status |= (1 << gpio_pin);
3237 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3238 +
3239 + /* Set pin direction */
3240 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
3241 + if (pin_direction == GPIO_INPUT_PIN)
3242 + {
3243 + pin_status |= (1 << gpio_pin);
3244 + }
3245 + else /* GPIO_OUTPUT_PIN */
3246 + {
3247 + pin_status &= (~(1 << gpio_pin));
3248 + }
3249 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
3250 + }
3251 + else /* FUNCTIONAL PIN */
3252 + {
3253 + pin_status &= (~(1 << gpio_pin));
3254 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3255 + }
3256 +
3257 +}
3258 +
3259 +/****************************************************************************
3260 + * FUNCTION: tnetd73xx_gpio_out
3261 + ***************************************************************************/
3262 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
3263 +{
3264 + u32 pin_value;
3265 +
3266 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
3267 + if (value == 1)
3268 + {
3269 + pin_value |= (1 << gpio_pin);
3270 + }
3271 + else
3272 + {
3273 + pin_value &= (~(1 << gpio_pin));
3274 + }
3275 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
3276 +}
3277 +
3278 +/****************************************************************************
3279 + * FUNCTION: tnetd73xx_gpio_in
3280 + ***************************************************************************/
3281 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
3282 +{
3283 + u32 pin_value;
3284 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
3285 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
3286 +}
3287 +
3288 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
3289 --- linux.old/arch/mips/config-shared.in 2005-07-10 03:00:44.000000000 +0200
3290 +++ linux.dev/arch/mips/config-shared.in 2005-08-12 19:53:15.060167880 +0200
3291 @@ -20,6 +20,16 @@
3292 mainmenu_option next_comment
3293 comment 'Machine selection'
3294 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
3295 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
3296 +if [ "$CONFIG_AR7" = "y" ]; then
3297 + choice 'Texas Instruments Reference Platform' \
3298 + "AR7DB CONFIG_AR7DB \
3299 + AR7RD CONFIG_AR7RD \
3300 + AR7WRD CONFIG_AR7WRD" AR7DB
3301 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_CPU 150
3302 + int 'Texas Instruments AR7 System Frequency' CONFIG_AR7_SYS 125
3303 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
3304 +fi
3305 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
3306 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
3307 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
3308 @@ -239,6 +249,10 @@
3309 define_bool CONFIG_NONCOHERENT_IO y
3310 define_bool CONFIG_PC_KEYB y
3311 fi
3312 +if [ "$CONFIG_AR7" = "y" ]; then
3313 + define_bool CONFIG_NONCOHERENT_IO y
3314 + define_bool CONFIG_SWAP_IO_SPACE y
3315 +fi
3316 if [ "$CONFIG_CASIO_E55" = "y" ]; then
3317 define_bool CONFIG_IRQ_CPU y
3318 define_bool CONFIG_NONCOHERENT_IO y
3319 @@ -736,6 +750,7 @@
3320 mainmenu_option next_comment
3321 comment 'General setup'
3322 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3323 + "$CONFIG_AR7" = "y" -o \
3324 "$CONFIG_CASIO_E55" = "y" -o \
3325 "$CONFIG_DDB5074" = "y" -o \
3326 "$CONFIG_DDB5476" = "y" -o \
3327 @@ -797,6 +812,7 @@
3328 bool 'Networking support' CONFIG_NET
3329
3330 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3331 + "$CONFIG_AR7" = "y" -o \
3332 "$CONFIG_CASIO_E55" = "y" -o \
3333 "$CONFIG_DECSTATION" = "y" -o \
3334 "$CONFIG_IBM_WORKPAD" = "y" -o \
3335 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
3336 --- linux.old/arch/mips/kernel/head.S 2005-07-10 02:55:18.000000000 +0200
3337 +++ linux.dev/arch/mips/kernel/head.S 2005-08-12 23:05:36.954533232 +0200
3338 @@ -75,11 +75,11 @@
3339 * size!
3340 */
3341 NESTED(except_vec4, 0, sp)
3342 - .set push
3343 - .set noreorder
3344 -1: j 1b /* Dummy, will be replaced */
3345 - nop
3346 - .set pop
3347 + .set mips2
3348 + lui k0, 0x9400
3349 + ori k0, 0x200
3350 + jr k0
3351 + nop
3352 END(except_vec4)
3353
3354 /*
3355 diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
3356 --- linux.old/arch/mips/kernel/irq.c 2005-07-10 03:00:44.000000000 +0200
3357 +++ linux.dev/arch/mips/kernel/irq.c 2005-08-12 19:32:05.142224752 +0200
3358 @@ -76,6 +76,7 @@
3359 * Generic, controller-independent functions:
3360 */
3361
3362 +#ifndef CONFIG_AR7
3363 int get_irq_list(char *buf)
3364 {
3365 int i, j;
3366 @@ -110,6 +111,7 @@
3367 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
3368 return p - buf;
3369 }
3370 +#endif
3371
3372 #ifdef CONFIG_SMP
3373 int global_irq_holder = NO_PROC_ID;
3374 @@ -525,6 +527,7 @@
3375 *
3376 */
3377
3378 +#ifndef CONFIG_AR7
3379 int request_irq(unsigned int irq,
3380 void (*handler)(int, void *, struct pt_regs *),
3381 unsigned long irqflags,
3382 @@ -569,6 +572,7 @@
3383 kfree(action);
3384 return retval;
3385 }
3386 +#endif
3387
3388 /**
3389 * free_irq - free an interrupt
3390 @@ -588,6 +592,7 @@
3391 * the machine.
3392 */
3393
3394 +#ifndef CONFIG_AR7
3395 void free_irq(unsigned int irq, void *dev_id)
3396 {
3397 irq_desc_t *desc;
3398 @@ -629,6 +634,7 @@
3399 return;
3400 }
3401 }
3402 +#endif
3403
3404 /*
3405 * IRQ autodetection code..
3406 diff -urN linux.old/arch/mips/kernel/mips_ksyms.c linux.dev/arch/mips/kernel/mips_ksyms.c
3407 --- linux.old/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
3408 +++ linux.dev/arch/mips/kernel/mips_ksyms.c 2005-08-12 19:32:05.142224752 +0200
3409 @@ -40,6 +40,12 @@
3410 extern long __strnlen_user_nocheck_asm(const char *s);
3411 extern long __strnlen_user_asm(const char *s);
3412
3413 +#ifdef CONFIG_AR7
3414 +int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
3415 +char *prom_getenv(char *envname);
3416 +#endif
3417 +
3418 +
3419 EXPORT_SYMBOL(mips_machtype);
3420 #ifdef CONFIG_EISA
3421 EXPORT_SYMBOL(EISA_bus);
3422 @@ -103,3 +109,9 @@
3423 #endif
3424
3425 EXPORT_SYMBOL(get_wchan);
3426 +
3427 +#ifdef CONFIG_AR7
3428 +EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
3429 +EXPORT_SYMBOL_NOVERS(prom_getenv);
3430 +#endif
3431 +
3432 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3433 --- linux.old/arch/mips/kernel/setup.c 2005-07-10 03:00:44.000000000 +0200
3434 +++ linux.dev/arch/mips/kernel/setup.c 2005-08-12 19:56:27.917849056 +0200
3435 @@ -235,7 +235,11 @@
3436 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
3437 #define PFN_PHYS(x) ((x) << PAGE_SHIFT)
3438
3439 +#ifdef CONFIG_AR7
3440 +#define MAXMEM HIGHMEM_START + CONFIG_AR7_MEMORY
3441 +#else
3442 #define MAXMEM HIGHMEM_START
3443 +#endif
3444 #define MAXMEM_PFN PFN_DOWN(MAXMEM)
3445
3446 static inline void bootmem_init(void)
3447 @@ -320,7 +324,12 @@
3448 #endif
3449
3450 /* Initialize the boot-time allocator with low memory only. */
3451 +#ifdef CONFIG_AR7
3452 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
3453 + CONFIG_AR7_MEMORY >> PAGE_SHIFT, max_low_pfn);
3454 +#else
3455 bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
3456 +#endif
3457
3458 /*
3459 * Register fully available low RAM pages with the bootmem allocator.
3460 @@ -494,6 +503,7 @@
3461 void hp_setup(void);
3462 void au1x00_setup(void);
3463 void frame_info_init(void);
3464 + void ar7_setup(void);
3465
3466 frame_info_init();
3467 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3468 @@ -691,6 +701,11 @@
3469 pmc_yosemite_setup();
3470 break;
3471 #endif
3472 +#ifdef CONFIG_AR7
3473 + case MACH_GROUP_UNKNOWN:
3474 + ar7_setup();
3475 + break;
3476 +#endif
3477 default:
3478 panic("Unsupported architecture");
3479 }
3480 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3481 --- linux.old/arch/mips/kernel/traps.c 2005-07-10 03:00:44.000000000 +0200
3482 +++ linux.dev/arch/mips/kernel/traps.c 2005-08-12 23:38:46.505075576 +0200
3483 @@ -869,9 +869,15 @@
3484
3485 exception_handlers[n] = handler;
3486 if (n == 0 && cpu_has_divec) {
3487 +#ifdef CONFIG_AR7
3488 + *(volatile u32 *)(KSEG0+0x200+CONFIG_AR7_MEMORY) = 0x08000000 |
3489 + (0x03ffffff & (handler >> 2));
3490 + flush_icache_range(KSEG0+0x200+CONFIG_AR7_MEMORY, KSEG0 + 0x204 + CONFIG_AR7_MEMORY);
3491 +#else
3492 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3493 (0x03ffffff & (handler >> 2));
3494 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3495 +#endif
3496 }
3497 return (void *)old_handler;
3498 }
3499 @@ -1022,6 +1028,12 @@
3500
3501 if (board_nmi_handler_setup)
3502 board_nmi_handler_setup();
3503 +#ifdef CONFIG_AR7
3504 + memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x80), &except_vec1_generic, 0x80);
3505 + memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x180), &except_vec3_generic, 0x80);
3506 + memcpy((void *)(KSEG0 + CONFIG_AR7_MEMORY + 0x200), &except_vec4, 8);
3507 + flush_icache_range(KSEG0 + CONFIG_AR7_MEMORY, KSEG0 + CONFIG_AR7_MEMORY + 0x208);
3508 +#endif
3509
3510 flush_icache_range(KSEG0, KSEG0 + 0x400);
3511
3512 diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
3513 --- linux.old/arch/mips/lib/promlib.c 2005-07-10 03:00:44.000000000 +0200
3514 +++ linux.dev/arch/mips/lib/promlib.c 2005-08-12 20:39:57.087195024 +0200
3515 @@ -1,6 +1,8 @@
3516 #include <stdarg.h>
3517 #include <linux/kernel.h>
3518 +#include <linux/config.h>
3519
3520 +#ifndef CONFIG_AR7
3521 extern void prom_putchar(char);
3522
3523 void prom_printf(char *fmt, ...)
3524 @@ -22,3 +24,4 @@
3525 }
3526 va_end(args);
3527 }
3528 +#endif
3529 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
3530 --- linux.old/arch/mips/Makefile 2005-07-10 03:00:44.000000000 +0200
3531 +++ linux.dev/arch/mips/Makefile 2005-08-12 20:38:28.398677728 +0200
3532 @@ -369,6 +369,16 @@
3533 endif
3534
3535 #
3536 +# Texas Instruments AR7
3537 +#
3538 +
3539 +ifdef CONFIG_AR7
3540 +LIBS += arch/mips/ar7/ar7.o
3541 +SUBDIRS += arch/mips/ar7
3542 +LOADADDR += 0x94020000
3543 +endif
3544 +
3545 +#
3546 # DECstation family
3547 #
3548 ifdef CONFIG_DECSTATION
3549 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3550 --- linux.old/arch/mips/mm/init.c 2005-07-10 03:00:44.000000000 +0200
3551 +++ linux.dev/arch/mips/mm/init.c 2005-08-12 21:08:04.420681344 +0200
3552 @@ -248,6 +248,9 @@
3553
3554 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
3555 low = max_low_pfn;
3556 +#ifdef CONFIG_AR7
3557 + low = NODE_DATA(0)->bdata->node_low_pfn - (CONFIG_AR7_MEMORY >> PAGE_SHIFT);
3558 +#endif
3559 high = highend_pfn;
3560
3561 #ifdef CONFIG_ISA
3562 @@ -270,7 +273,11 @@
3563 zones_size[ZONE_HIGHMEM] = high - low;
3564 #endif
3565
3566 +#ifdef CONFIG_AR7
3567 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, CONFIG_AR7_MEMORY, 0);
3568 +#else
3569 free_area_init(zones_size);
3570 +#endif
3571 }
3572
3573 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3574 @@ -298,6 +305,10 @@
3575 return 0;
3576 }
3577
3578 +#ifdef CONFIG_AR7
3579 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
3580 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
3581 +#endif
3582 void __init mem_init(void)
3583 {
3584 unsigned long codesize, reservedpages, datasize, initsize;
3585 @@ -315,9 +326,21 @@
3586 #else
3587 max_mapnr = num_mappedpages = num_physpages = max_low_pfn;
3588 #endif
3589 +
3590 +#ifdef CONFIG_AR7
3591 + max_mapnr = num_mappedpages = num_physpages = MAX_LOW_PFN - START_PFN;
3592 + high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
3593 +
3594 +#if 0
3595 + /* WTF? */
3596 + free_bootmem_node(NODE_DATA(0), (CONFIG_AR7_MEMORY+PAGE_SIZE), (__pa(&_ftext))-(CONFIG_AR7_MEMORY+PAGE_SIZE));
3597 +#endif
3598 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
3599 +#else
3600 high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
3601 -
3602 totalram_pages += free_all_bootmem();
3603 +#endif
3604 +
3605 totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
3606
3607 reservedpages = ram = 0;
3608 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
3609 --- linux.old/drivers/char/serial.c 2005-07-10 03:00:44.000000000 +0200
3610 +++ linux.dev/drivers/char/serial.c 2005-08-12 19:32:05.147223992 +0200
3611 @@ -419,7 +419,40 @@
3612 return 0;
3613 }
3614
3615 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3616 +#if defined(CONFIG_AR7)
3617 +
3618 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
3619 +{
3620 + return (inb(info->port + (offset * 4)) & 0xff);
3621 +}
3622 +
3623 +
3624 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
3625 +{
3626 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3627 + return (inb(info->port + (offset * 4)) & 0xff);
3628 +#else
3629 + return (inb_p(info->port + (offset * 4)) & 0xff);
3630 +#endif
3631 +}
3632 +
3633 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
3634 +{
3635 + outb(value, info->port + (offset * 4));
3636 +}
3637 +
3638 +
3639 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
3640 + int value)
3641 +{
3642 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3643 + outb(value, info->port + (offset * 4));
3644 +#else
3645 + outb_p(value, info->port + (offset * 4));
3646 +#endif
3647 +}
3648 +
3649 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3650
3651 #include <asm/mips-boards/atlas.h>
3652
3653 @@ -478,8 +511,10 @@
3654 * needed for certain old 386 machines, I've left these #define's
3655 * in....
3656 */
3657 +#ifndef CONFIG_AR7
3658 #define serial_inp(info, offset) serial_in(info, offset)
3659 #define serial_outp(info, offset, value) serial_out(info, offset, value)
3660 +#endif
3661
3662
3663 /*
3664 @@ -1728,7 +1763,15 @@
3665 /* Special case since 134 is really 134.5 */
3666 quot = (2*baud_base / 269);
3667 else if (baud)
3668 +#ifdef CONFIG_AR7
3669 + quot = (CONFIG_AR7_SYS*500000) / baud;
3670 +
3671 + if ((quot%16)>7)
3672 + quot += 8;
3673 + quot /=16;
3674 +#else
3675 quot = baud_base / baud;
3676 +#endif
3677 }
3678 /* If the quotient is zero refuse the change */
3679 if (!quot && old_termios) {
3680 @@ -5552,8 +5595,10 @@
3681 state->irq = irq_cannonicalize(state->irq);
3682 if (state->hub6)
3683 state->io_type = SERIAL_IO_HUB6;
3684 +#ifndef CONFIG_AR7
3685 if (state->port && check_region(state->port,8))
3686 continue;
3687 +#endif
3688 #ifdef CONFIG_MCA
3689 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
3690 continue;
3691 @@ -6009,7 +6054,15 @@
3692 info->io_type = state->io_type;
3693 info->iomem_base = state->iomem_base;
3694 info->iomem_reg_shift = state->iomem_reg_shift;
3695 +#ifdef CONFIG_AR7
3696 + quot = (CONFIG_AR7_SYS*500000) / baud;
3697 +
3698 + if ((quot%16)>7)
3699 + quot += 8;
3700 + quot /=16;
3701 +#else
3702 quot = state->baud_base / baud;
3703 +#endif
3704 cval = cflag & (CSIZE | CSTOPB);
3705 #if defined(__powerpc__) || defined(__alpha__)
3706 cval >>= 8;
3707 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
3708 --- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
3709 +++ linux.dev/include/asm-mips/ar7/ar7.h 2005-08-12 19:32:05.147223992 +0200
3710 @@ -0,0 +1,33 @@
3711 +/*
3712 + * $Id$
3713 + * Copyright (C) $Date$ $Author$
3714 + *
3715 + * This program is free software; you can redistribute it and/or modify
3716 + * it under the terms of the GNU General Public License as published by
3717 + * the Free Software Foundation; either version 2 of the License, or
3718 + * (at your option) any later version.
3719 + *
3720 + * This program is distributed in the hope that it will be useful,
3721 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3722 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3723 + * GNU General Public License for more details.
3724 + *
3725 + * You should have received a copy of the GNU General Public License
3726 + * along with this program; if not, write to the Free Software
3727 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
3728 + *
3729 + */
3730 +
3731 +#ifndef _AR7_H
3732 +#define _AR7_H
3733 +
3734 +#include <asm/addrspace.h>
3735 +#include <linux/config.h>
3736 +
3737 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(CONFIG_AR7_MEMORY))
3738 +
3739 +#define AR7_UART0_REGS_BASE (KSEG1ADDR(0x08610E00))
3740 +#define AR7_UART1_REGS_BASE (KSEG1ADDR(0x08610F00))
3741 +#define AR7_BASE_BAUD ( 3686400 / 16 )
3742 +
3743 +#endif
3744 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
3745 --- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
3746 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-08-12 19:32:05.148223840 +0200
3747 @@ -0,0 +1,283 @@
3748 + /*
3749 + * Nitin Dhingra, iamnd@ti.com
3750 + * Copyright (C) 2000 Texas Instruments Inc.
3751 + *
3752 + *
3753 + * ########################################################################
3754 + *
3755 + * This program is free software; you can distribute it and/or modify it
3756 + * under the terms of the GNU General Public License (Version 2) as
3757 + * published by the Free Software Foundation.
3758 + *
3759 + * This program is distributed in the hope it will be useful, but WITHOUT
3760 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3761 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3762 + * for more details.
3763 + *
3764 + * You should have received a copy of the GNU General Public License along
3765 + * with this program; if not, write to the Free Software Foundation, Inc.,
3766 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3767 + *
3768 + * ########################################################################
3769 + *
3770 + * Defines of the Sead board specific address-MAP, registers, etc.
3771 + *
3772 + */
3773 +#ifndef _AVALANCHE_INTC_H
3774 +#define _AVALANCHE_INTC_H
3775 +
3776 +/* ----- */
3777 +
3778 +#define KSEG1_BASE 0xA0000000
3779 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
3780 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
3781 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
3782 +#define AVALANCHE_INTC_BASE PHYS_TO_K1(0x08612400)
3783 +
3784 +/* ----- */
3785 +
3786 +#define MIPS_EXCEPTION_OFFSET 8
3787 +
3788 +/******************************************************************************
3789 + Avalanche Interrupt number
3790 +******************************************************************************/
3791 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
3792 +
3793 +/*******************************************************************************
3794 +*Linux Interrupt number
3795 +*******************************************************************************/
3796 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3797 +
3798 +
3799 +
3800 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
3801 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
3802 +
3803 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
3804 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
3805 +
3806 +
3807 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
3808 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
3809 + + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
3810 +
3811 +
3812 +/*
3813 + * Avalanche interrupt controller register base (primary)
3814 + */
3815 +#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
3816 +
3817 +/******************************************************************************
3818 + * Avalanche exception controller register base (secondary)
3819 + ******************************************************************************/
3820 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
3821 +
3822 +
3823 +/******************************************************************************
3824 + * Avalanche Interrupt pacing register base (secondary)
3825 + ******************************************************************************/
3826 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
3827 +
3828 +
3829 +
3830 +/******************************************************************************
3831 + * Avalanche Interrupt Channel Control register base
3832 + *****************************************************************************/
3833 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3834 +
3835 +
3836 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
3837 +{
3838 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
3839 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
3840 + volatile unsigned long unused1; /*0x08 */
3841 + volatile unsigned long unused2; /*0x0C */
3842 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
3843 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
3844 + volatile unsigned long unused3; /*0x18 */
3845 + volatile unsigned long unused4; /*0x1C */
3846 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
3847 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
3848 + volatile unsigned long unused5; /*0x28 */
3849 + volatile unsigned long unused6; /*0x2C */
3850 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
3851 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
3852 + volatile unsigned long unused7; /* 0x38 */
3853 + volatile unsigned long unused8; /* 0x3c */
3854 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
3855 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
3856 + volatile unsigned long unused9; /* 0x48 */
3857 + volatile unsigned long unused10; /* 0x4C */
3858 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
3859 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
3860 + volatile unsigned long unused11; /* 0x58 */
3861 + volatile unsigned long unused12; /*0x5C */
3862 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
3863 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
3864 +};
3865 +
3866 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
3867 +{
3868 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
3869 + volatile unsigned long reserved; /*0x84 */
3870 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
3871 + volatile unsigned long reserved1; /*0x8c */
3872 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
3873 + volatile unsigned long reserved2; /*0x94 */
3874 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
3875 +};
3876 +struct avalanche_ipace_regs
3877 +{
3878 +
3879 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
3880 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
3881 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
3882 +};
3883 +struct avalanche_channel_int_number
3884 +{
3885 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
3886 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
3887 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
3888 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
3889 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
3890 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
3891 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
3892 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
3893 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
3894 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
3895 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
3896 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
3897 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
3898 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
3899 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
3900 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
3901 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
3902 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
3903 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
3904 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
3905 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
3906 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
3907 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
3908 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
3909 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
3910 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
3911 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
3912 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
3913 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
3914 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
3915 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
3916 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
3917 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
3918 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
3919 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
3920 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
3921 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
3922 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
3923 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
3924 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
3925 +};
3926 +
3927 +struct avalanche_interrupt_line_to_channel
3928 +{
3929 + unsigned long int_line0; /* Start of primary interrupts */
3930 + unsigned long int_line1;
3931 + unsigned long int_line2;
3932 + unsigned long int_line3;
3933 + unsigned long int_line4;
3934 + unsigned long int_line5;
3935 + unsigned long int_line6;
3936 + unsigned long int_line7;
3937 + unsigned long int_line8;
3938 + unsigned long int_line9;
3939 + unsigned long int_line10;
3940 + unsigned long int_line11;
3941 + unsigned long int_line12;
3942 + unsigned long int_line13;
3943 + unsigned long int_line14;
3944 + unsigned long int_line15;
3945 + unsigned long int_line16;
3946 + unsigned long int_line17;
3947 + unsigned long int_line18;
3948 + unsigned long int_line19;
3949 + unsigned long int_line20;
3950 + unsigned long int_line21;
3951 + unsigned long int_line22;
3952 + unsigned long int_line23;
3953 + unsigned long int_line24;
3954 + unsigned long int_line25;
3955 + unsigned long int_line26;
3956 + unsigned long int_line27;
3957 + unsigned long int_line28;
3958 + unsigned long int_line29;
3959 + unsigned long int_line30;
3960 + unsigned long int_line31;
3961 + unsigned long int_line32;
3962 + unsigned long int_line33;
3963 + unsigned long int_line34;
3964 + unsigned long int_line35;
3965 + unsigned long int_line36;
3966 + unsigned long int_line37;
3967 + unsigned long int_line38;
3968 + unsigned long int_line39;
3969 +};
3970 +
3971 +
3972 +/* Interrupt Line #'s (Sangam peripherals) */
3973 +
3974 +/*------------------------------*/
3975 +/* Sangam primary interrupts */
3976 +/*------------------------------*/
3977 +
3978 +#define UNIFIED_SECONDARY_INTERRUPT 0
3979 +#define AVALANCHE_EXT_INT_0 1
3980 +#define AVALANCHE_EXT_INT_1 2
3981 +/* Line #3 Reserved */
3982 +/* Line #4 Reserved */
3983 +#define AVALANCHE_TIMER_0_INT 5
3984 +#define AVALANCHE_TIMER_1_INT 6
3985 +#define AVALANCHE_UART0_INT 7
3986 +#define AVALANCHE_UART1_INT 8
3987 +#define AVALANCHE_PDMA_INT0 9
3988 +#define AVALANCHE_PDMA_INT1 10
3989 +/* Line #11 Reserved */
3990 +/* Line #12 Reserved */
3991 +/* Line #13 Reserved */
3992 +/* Line #14 Reserved */
3993 +#define AVALANCHE_ATM_SAR_INT 15
3994 +/* Line #16 Reserved */
3995 +/* Line #17 Reserved */
3996 +/* Line #18 Reserved */
3997 +#define AVALANCHE_MAC0_INT 19
3998 +/* Line #20 Reserved */
3999 +#define AVALANCHE_VLYNQ0_INT 21
4000 +#define AVALANCHE_CODEC_WAKE_INT 22
4001 +/* Line #23 Reserved */
4002 +#define AVALANCHE_USB_INT 24
4003 +#define AVALANCHE_VLYNQ1_INT 25
4004 +/* Line #26 Reserved */
4005 +/* Line #27 Reserved */
4006 +#define AVALANCHE_MAC1_INT 28
4007 +#define AVALANCHE_I2CM_INT 29
4008 +#define AVALANCHE_PDMA_INT2 30
4009 +#define AVALANCHE_PDMA_INT3 31
4010 +/* Line #32 Reserved */
4011 +/* Line #33 Reserved */
4012 +/* Line #34 Reserved */
4013 +/* Line #35 Reserved */
4014 +/* Line #36 Reserved */
4015 +#define AVALANCHE_VDMA_VT_RX_INT 37
4016 +#define AVALANCHE_VDMA_VT_TX_INT 38
4017 +#define AVALANCHE_ADSLSS_INT 39
4018 +
4019 +/*-----------------------------------*/
4020 +/* Sangam Secondary Interrupts */
4021 +/*-----------------------------------*/
4022 +#define PRIMARY_INTS 40
4023 +
4024 +#define EMIF_INT (7 + PRIMARY_INTS)
4025 +
4026 +
4027 +extern void avalanche_int_set(int channel, int line);
4028 +
4029 +
4030 +#endif /* _AVALANCHE_INTC_H */
4031 diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
4032 --- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
4033 +++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-08-12 19:32:05.148223840 +0200
4034 @@ -0,0 +1,174 @@
4035 +#ifndef _AVALANCHE_MISC_H_
4036 +#define _AVALANCHE_MISC_H_
4037 +
4038 +typedef enum AVALANCHE_ERR_t
4039 +{
4040 + AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
4041 + AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
4042 +
4043 + /* Pointers and args */
4044 + AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
4045 + AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
4046 + AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
4047 +
4048 + /* Memory issues */
4049 + AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
4050 + AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
4051 + AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
4052 + AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
4053 +
4054 + /* Device issues */
4055 + AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
4056 + AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
4057 +
4058 + AVALANCHE_ERR_INVID = -30 /* Invalid ID */
4059 +
4060 +} AVALANCHE_ERR;
4061 +
4062 +/*****************************************************************************
4063 + * Reset Control Module
4064 + *****************************************************************************/
4065 +
4066 +typedef enum AVALANCHE_RESET_MODULE_tag
4067 +{
4068 + RESET_MODULE_UART0 = 0,
4069 + RESET_MODULE_UART1 = 1,
4070 + RESET_MODULE_I2C = 2,
4071 + RESET_MODULE_TIMER0 = 3,
4072 + RESET_MODULE_TIMER1 = 4,
4073 + RESET_MODULE_GPIO = 6,
4074 + RESET_MODULE_ADSLSS = 7,
4075 + RESET_MODULE_USBS = 8,
4076 + RESET_MODULE_SAR = 9,
4077 + RESET_MODULE_VDMA_VT = 11,
4078 + RESET_MODULE_FSER = 12,
4079 + RESET_MODULE_VLYNQ1 = 16,
4080 + RESET_MODULE_EMAC0 = 17,
4081 + RESET_MODULE_DMA = 18,
4082 + RESET_MODULE_BIST = 19,
4083 + RESET_MODULE_VLYNQ0 = 20,
4084 + RESET_MODULE_EMAC1 = 21,
4085 + RESET_MODULE_MDIO = 22,
4086 + RESET_MODULE_ADSLSS_DSP = 23,
4087 + RESET_MODULE_EPHY = 26
4088 +} AVALANCHE_RESET_MODULE_T;
4089 +
4090 +typedef enum AVALANCHE_RESET_CTRL_tag
4091 +{
4092 + IN_RESET = 0,
4093 + OUT_OF_RESET
4094 +} AVALANCHE_RESET_CTRL_T;
4095 +
4096 +typedef enum AVALANCHE_SYS_RST_MODE_tag
4097 +{
4098 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
4099 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
4100 +} AVALANCHE_SYS_RST_MODE_T;
4101 +
4102 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
4103 +{
4104 + HARDWARE_RESET = 0,
4105 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
4106 + WATCHDOG_RESET,
4107 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
4108 +} AVALANCHE_SYS_RESET_STATUS_T;
4109 +
4110 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
4111 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
4112 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
4113 +
4114 +typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
4115 +
4116 +/*****************************************************************************
4117 + * Power Control Module
4118 + *****************************************************************************/
4119 +
4120 +typedef enum AVALANCHE_POWER_CTRL_tag
4121 +{
4122 + POWER_CTRL_POWER_UP = 0,
4123 + POWER_CTRL_POWER_DOWN
4124 +} AVALANCHE_POWER_CTRL_T;
4125 +
4126 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
4127 +{
4128 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
4129 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
4130 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
4131 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
4132 +} AVALANCHE_SYS_POWER_MODE_T;
4133 +
4134 +void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
4135 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
4136 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
4137 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
4138 +
4139 +/*****************************************************************************
4140 + * Wakeup Control
4141 + *****************************************************************************/
4142 +
4143 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
4144 +{
4145 + WAKEUP_INT0 = 1,
4146 + WAKEUP_INT1 = 2,
4147 + WAKEUP_INT2 = 4,
4148 + WAKEUP_INT3 = 8
4149 +} AVALANCHE_WAKEUP_INTERRUPT_T;
4150 +
4151 +typedef enum TNETV1050_WAKEUP_CTRL_tag
4152 +{
4153 + WAKEUP_DISABLED = 0,
4154 + WAKEUP_ENABLED
4155 +} AVALANCHE_WAKEUP_CTRL_T;
4156 +
4157 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
4158 +{
4159 + WAKEUP_ACTIVE_HIGH = 0,
4160 + WAKEUP_ACTIVE_LOW
4161 +} AVALANCHE_WAKEUP_POLARITY_T;
4162 +
4163 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
4164 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
4165 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
4166 +
4167 +/*****************************************************************************
4168 + * GPIO Control
4169 + *****************************************************************************/
4170 +
4171 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
4172 +{
4173 + FUNCTIONAL_PIN = 0,
4174 + GPIO_PIN = 1
4175 +} AVALANCHE_GPIO_PIN_MODE_T;
4176 +
4177 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
4178 +{
4179 + GPIO_OUTPUT_PIN = 0,
4180 + GPIO_INPUT_PIN = 1
4181 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
4182 +
4183 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
4184 +
4185 +void avalanche_gpio_init(void);
4186 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
4187 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
4188 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
4189 +int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
4190 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
4191 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
4192 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
4193 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
4194 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
4195 +int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
4196 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
4197 +
4198 +unsigned int avalanche_get_chip_version_info(void);
4199 +
4200 +unsigned int avalanche_get_vbus_freq(void);
4201 +void avalanche_set_vbus_freq(unsigned int);
4202 +
4203 +
4204 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
4205 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
4206 +unsigned int avalanche_is_mdix_on_chip(void);
4207 +
4208 +#endif
4209 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
4210 --- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
4211 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-08-12 19:32:05.149223688 +0200
4212 @@ -0,0 +1,567 @@
4213 +/*
4214 + * $Id$
4215 + * Avalanche Register Descriptions
4216 + *
4217 + * Jeff Harrell, jharrell@ti.com
4218 + * 2000 (c) Texas Instruments Inc.
4219 + */
4220 +
4221 +#ifndef __AVALANCHE_REGS_H
4222 +#define __AVALANCHE_REGS_H
4223 +
4224 +#include <asm/addrspace.h>
4225 +#include <linux/config.h>
4226 +
4227 +/*----------------------------------------*/
4228 +/* Base offsets within the Avalanche ASIC */
4229 +/*----------------------------------------*/
4230 +
4231 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
4232 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
4233 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
4234 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
4235 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
4236 +#define DES_BASE (KSEG1ADDR(0x08600000))
4237 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
4238 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
4239 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
4240 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
4241 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
4242 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
4243 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
4244 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
4245 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
4246 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
4247 +#define I2C_BASE (KSEG1ADDR(0x08611000))
4248 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
4249 +#define USB_BASE (KSEG1ADDR(0x08611200))
4250 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
4251 +#define DMA_BASE (KSEG1ADDR(0x08611400))
4252 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
4253 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
4254 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
4255 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
4256 +
4257 +/*---------------------------------*/
4258 +/* Device ID, chip version number */
4259 +/*---------------------------------*/
4260 +
4261 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
4262 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
4263 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
4264 +
4265 +/*----------------------------------*/
4266 +/* Reset Control VW changed to ptrs */
4267 +/*----------------------------------*/
4268 +
4269 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
4270 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
4271 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
4272 +
4273 +/* reset control bits */
4274 +
4275 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
4276 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
4277 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
4278 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
4279 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
4280 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
4281 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
4282 +/*
4283 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4284 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4285 + interface pins are inputs and must be reconfigured so as not to lose the
4286 + serial console interface
4287 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4288 +*/
4289 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
4290 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
4291 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
4292 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
4293 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
4294 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
4295 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
4296 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
4297 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
4298 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
4299 +
4300 +/*----------------------*/
4301 +/* Physical interfaces */
4302 +/*----------------------*/
4303 +
4304 +/* Phy loopback */
4305 +#define PHY_LOOPBACK 1
4306 +
4307 +
4308 +/* Phy 0 */
4309 +#define PHY0BASE (PHY_BASE)
4310 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
4311 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
4312 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
4313 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
4314 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
4315 +
4316 +
4317 +/* Phy 1 */
4318 +
4319 +#define PHY1BASE (PHY_BASE + 0x100000)
4320 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
4321 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
4322 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
4323 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
4324 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
4325 +
4326 +/* Phy 2 */
4327 +
4328 +#define PHY2BASE (PHY_BASE + 0x200000)
4329 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
4330 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
4331 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
4332 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
4333 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
4334 +
4335 +/*-------------------*/
4336 +/* Avalanche ATM SAR */
4337 +/*-------------------*/
4338 +
4339 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
4340 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
4341 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
4342 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
4343 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
4344 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
4345 +
4346 +/* Transmit completion ring registers */
4347 +
4348 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
4349 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
4350 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
4351 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
4352 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
4353 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
4354 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
4355 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
4356 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
4357 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
4358 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
4359 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
4360 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
4361 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
4362 +
4363 +/* Transmit Queue Packet registers */
4364 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
4365 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
4366 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
4367 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
4368 +/* Receive completion ring registers */
4369 +
4370 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
4371 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
4372 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
4373 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
4374 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
4375 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
4376 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
4377 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
4378 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
4379 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
4380 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
4381 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
4382 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
4383 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
4384 +
4385 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
4386 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
4387 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
4388 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
4389 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
4390 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
4391 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
4392 +
4393 +
4394 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
4395 +
4396 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
4397 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
4398 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
4399 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
4400 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
4401 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
4402 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
4403 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
4404 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
4405 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
4406 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
4407 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
4408 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
4409 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
4410 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
4411 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
4412 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
4413 +
4414 +
4415 +/*
4416 +
4417 +#define OAM_CPID_ADD 0xa30104e0
4418 +
4419 +#define OAM_LLID_ADD 0xa30104f0
4420 +
4421 +#define OAM_LLID_VAL 0xffffffff
4422 +
4423 +#define OAM_CORR_TAG 0xa3010500
4424 +
4425 +#define OAM_FAR_COUNT_ADD 0xa3010520
4426 +
4427 +#define OAM_NEAR_COUNT_ADD 0xa3010540
4428 +
4429 +#define OAM_CONFIG_REG_ADD 0xa3000018
4430 +*/
4431 +
4432 +
4433 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
4434 +
4435 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
4436 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
4437 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
4438 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
4439 +
4440 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
4441 +
4442 +
4443 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
4444 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
4445 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
4446 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
4447 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
4448 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
4449 +
4450 +/*------------------------------------------*/
4451 +/* DSL Interface */
4452 +/*------------------------------------------*/
4453 +
4454 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
4455 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
4456 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
4457 +
4458 +/* Fast */
4459 +
4460 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
4461 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
4462 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
4463 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
4464 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
4465 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
4466 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
4467 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
4468 +
4469 +/* Interleaved */
4470 +
4471 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
4472 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
4473 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
4474 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
4475 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
4476 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
4477 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
4478 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
4479 +
4480 +/*------------------------------------------*/
4481 +/* Broadband I/F */
4482 +/*------------------------------------------*/
4483 +
4484 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
4485 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
4486 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
4487 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
4488 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
4489 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
4490 +
4491 +#define AVBBIF_DISABLED 0x0
4492 +#define AVBBIF_LBT4040_INT 0x1
4493 +#define AVBBIF_XBUS 0x2
4494 +#define AVBBIF_LBT4040_EXT 0x4
4495 +
4496 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
4497 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
4498 +#define AVBBIF_TRANS_MASK 0xff000000
4499 +/*------------------------------------------*/
4500 +/* GPIO I/F */
4501 +/*------------------------------------------*/
4502 +
4503 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
4504 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
4505 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
4506 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
4507 +
4508 +#define GPIO_0 (1<<21)
4509 +#define GPIO_1 (1<<22)
4510 +#define GPIO_2 (1<<23)
4511 +#define GPIO_3 (1<<24)
4512 +#define EINT_1 (1<<18)
4513 +
4514 +/*
4515 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4516 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4517 + interface pins are inputs and must be reconfigured so as not to lose the
4518 + serial console interface
4519 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4520 +*/
4521 +
4522 +/*------------------------------------------*/
4523 +/* CLK_CTRL */
4524 +/*------------------------------------------*/
4525 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
4526 +
4527 +#define PCLK_0_HALF_VBUS (0<<16)
4528 +#define PCLK_EQ_INPUT (1<<16)
4529 +#define BBIF_CLK_HALF_VBUS (0<<17)
4530 +#define BBIF_CLK_EQ_VBUS (1<<17)
4531 +#define BBIF_CLK_EQ_BBCLK (3<<17)
4532 +#define DSP_MODCLK_DSPCLKI (0<<20)
4533 +#define DSP_MODCLK_REFCLKI (1<<20)
4534 +#define USB_CLK_EQ_USBCLKI (0<<21)
4535 +#define USB_CLK_EQ_REFCLKI (1<<21)
4536 +
4537 +/*------------------------------------------*/
4538 +/* PCI Control Registers */
4539 +/*------------------------------------------*/
4540 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
4541 +#define PCIC_CONTROL_CFG_DONE (1<<0)
4542 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
4543 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
4544 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
4545 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
4546 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
4547 +#define PCIC_CONTROL_MEM_MASK (1<<6)
4548 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
4549 +#define PCIC_CONTROL_IO_MASK (1<<8)
4550 +/* PCIC_CONTROL_RESERVED (1<<9) */
4551 +#define PCIC_CONTROL_BASE0_EN (1<<10)
4552 +#define PCIC_CONTROL_BASE1_EN (1<<11)
4553 +#define PCIC_CONTROL_BASE2_EN (1<<12)
4554 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
4555 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
4556 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
4557 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
4558 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
4559 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
4560 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
4561 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
4562 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
4563 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
4564 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
4565 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
4566 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
4567 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
4568 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
4569 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
4570 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
4571 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
4572 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
4573 +#define PCIC_INT_CLEAR_PM (1<<0)
4574 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
4575 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
4576 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
4577 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
4578 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
4579 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
4580 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
4581 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
4582 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
4583 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
4584 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
4585 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
4586 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
4587 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
4588 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
4589 +#define PCIC_INT_EN_AVAL_PM (1<<0)
4590 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
4591 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
4592 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
4593 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
4594 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
4595 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
4596 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
4597 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
4598 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
4599 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
4600 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
4601 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
4602 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
4603 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
4604 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
4605 +#define PCIC_INT_EN_PCI_PM (1<<0)
4606 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
4607 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
4608 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
4609 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
4610 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
4611 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
4612 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
4613 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
4614 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
4615 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
4616 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
4617 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
4618 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
4619 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
4620 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
4621 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
4622 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
4623 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
4624 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
4625 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
4626 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
4627 +/* PCIC_PM_CTL_RESERVED (1<<2) */
4628 +/* PCIC_PM_CTL_RESERVED (1<<3) */
4629 +/* PCIC_PM_CTL_RESERVED (1<<4) */
4630 +/* PCIC_PM_CTL_RESERVED (1<<5) */
4631 +/* PCIC_PM_CTL_RESERVED (1<<6) */
4632 +/* PCIC_PM_CTL_RESERVED (1<<7) */
4633 +/* PCIC_PM_CTL_RESERVED (1<<8) */
4634 +/* PCIC_PM_CTL_RESERVED (1<<9) */
4635 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
4636 +#define PCIC_PM_CTL_PMEIN (1<<11)
4637 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
4638 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
4639 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
4640 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
4641 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
4642 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
4643 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
4644 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
4645 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
4646 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
4647 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
4648 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
4649 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
4650 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
4651 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
4652 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
4653 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
4654 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
4655 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
4656 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
4657 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
4658 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
4659 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
4660 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
4661 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
4662 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
4663 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
4664 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
4665 +
4666 +/*------------------------------------------*/
4667 +/* IIC_INTERFACE */
4668 +/*------------------------------------------*/
4669 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
4670 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
4671 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
4672 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
4673 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
4674 +
4675 +#define I2CWRITE 0x200
4676 +#define I2CREAD 0x300
4677 +#define I2C_END_BURST 0x400
4678 +
4679 +/* read bits */
4680 +#define I2C_READ_ERROR 0x8000
4681 +#define I2C_READ_COMPLETE 0x4000
4682 +#define I2C_READ_BUSY 0x2000
4683 +
4684 +/* device types */
4685 +#define I2C_IO_EXPANDER 0x2
4686 +#define I2C_RTC 0xd
4687 +
4688 +/* device Addresses on I2C bus (EVM3) */
4689 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
4690 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
4691 +#define EVM3_RTC_I2C_ADDR 0x0
4692 +
4693 +/*------------------------------------------*/
4694 +/* Ethernet MAC register offset definitions */
4695 +/*------------------------------------------*/
4696 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
4697 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
4698 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
4699 +
4700 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4701 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
4702 +
4703 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
4704 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
4705 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
4706 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
4707 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
4708 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
4709 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
4710 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
4711 +
4712 +
4713 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
4714 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
4715 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
4716 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
4717 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
4718 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
4719 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
4720 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
4721 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
4722 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
4723 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
4724 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
4725 +
4726 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
4727 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
4728 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
4729 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
4730 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
4731 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
4732 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
4733 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
4734 +
4735 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
4736 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
4737 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
4738 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
4739 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
4740 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
4741 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
4742 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
4743 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
4744 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
4745 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
4746 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
4747 +
4748 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
4749 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
4750 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
4751 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
4752 +
4753 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
4754 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
4755 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
4756 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
4757 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
4758 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
4759 +
4760 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4761 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
4762 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
4763 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
4764 +
4765 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
4766 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
4767 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
4768 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
4769 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
4770 +
4771 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
4772 +
4773 +#endif __AVALANCHE_REGS_H
4774 +
4775 +
4776 +
4777 +
4778 +
4779 +
4780 diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
4781 --- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
4782 +++ linux.dev/include/asm-mips/ar7/if_port.h 2005-08-12 19:32:05.149223688 +0200
4783 @@ -0,0 +1,26 @@
4784 +/*******************************************************************************
4785 + * FILE PURPOSE: Interface port id Header file
4786 + *******************************************************************************
4787 + * FILE NAME: if_port.h
4788 + *
4789 + * DESCRIPTION: Header file carrying information about port ids of interfaces
4790 + *
4791 + *
4792 + * (C) Copyright 2003, Texas Instruments, Inc
4793 + ******************************************************************************/
4794 +#ifndef _IF_PORT_H_
4795 +#define _IF_PORT_H_
4796 +
4797 +#define AVALANCHE_CPMAC_LOW_PORT_ID 0
4798 +#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
4799 +#define AVALANCHE_USB_PORT_ID 2
4800 +#define AVALANCHE_WLAN_PORT_ID 3
4801 +
4802 +
4803 +#define AVALANCHE_MARVELL_BASE_PORT_ID 4
4804 +
4805 +/* The marvell ports occupy port ids from 4 to 8 */
4806 +/* so the next port id number should start at 9 */
4807 +
4808 +
4809 +#endif /* _IF_PORT_H_ */
4810 diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
4811 --- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
4812 +++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-08-12 19:32:05.150223536 +0200
4813 @@ -0,0 +1,77 @@
4814 +#ifndef _SANGAM_BOARDS_H
4815 +#define _SANGAM_BOARDS_H
4816 +
4817 +// Let us define board specific information here.
4818 +
4819 +
4820 +#if defined(CONFIG_AR7DB)
4821 +
4822 +#define AFECLK_FREQ 35328000
4823 +#define REFCLK_FREQ 25000000
4824 +#define OSC3_FREQ 24000000
4825 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4826 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
4827 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4828 +
4829 +#endif
4830 +
4831 +
4832 +#if defined(CONFIG_AR7RD)
4833 +#define AFECLK_FREQ 35328000
4834 +#define REFCLK_FREQ 25000000
4835 +#define OSC3_FREQ 24000000
4836 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4837 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4838 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4839 +#endif
4840 +
4841 +
4842 +#if defined(CONFIG_AR7WI)
4843 +#define AFECLK_FREQ 35328000
4844 +#define REFCLK_FREQ 25000000
4845 +#define OSC3_FREQ 24000000
4846 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4847 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4848 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4849 +#endif
4850 +
4851 +
4852 +#if defined(CONFIG_AR7V)
4853 +#define AFECLK_FREQ 35328000
4854 +#define REFCLK_FREQ 25000000
4855 +#define OSC3_FREQ 24000000
4856 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4857 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
4858 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4859 +#endif
4860 +
4861 +
4862 +#if defined(CONFIG_AR7WRD)
4863 +#define AFECLK_FREQ 35328000
4864 +#define REFCLK_FREQ 25000000
4865 +#define OSC3_FREQ 24000000
4866 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4867 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
4868 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4869 +#endif
4870 +
4871 +
4872 +#if defined(CONFIG_AR7VWI)
4873 +#define AFECLK_FREQ 35328000
4874 +#define REFCLK_FREQ 25000000
4875 +#define OSC3_FREQ 24000000
4876 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
4877 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
4878 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
4879 +#endif
4880 +
4881 +
4882 +#if defined CONFIG_SEAD2
4883 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
4884 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
4885 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
4886 +#include <asm/mips-boards/sead.h>
4887 +#endif
4888 +
4889 +
4890 +#endif
4891 diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
4892 --- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
4893 +++ linux.dev/include/asm-mips/ar7/sangam.h 2005-08-12 19:32:05.150223536 +0200
4894 @@ -0,0 +1,180 @@
4895 +#ifndef _SANGAM_H_
4896 +#define _SANGAM_H_
4897 +
4898 +#include <linux/config.h>
4899 +#include <asm/addrspace.h>
4900 +
4901 +/*----------------------------------------------------
4902 + * Sangam's Module Base Addresses
4903 + *--------------------------------------------------*/
4904 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
4905 +#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
4906 +#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
4907 +#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
4908 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
4909 +#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
4910 +#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
4911 +#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
4912 +#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
4913 +#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
4914 +#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
4915 +#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
4916 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
4917 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
4918 +#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
4919 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
4920 +#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
4921 +#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
4922 +#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
4923 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
4924 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
4925 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
4926 +#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
4927 +#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
4928 +#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
4929 +#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
4930 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
4931 +
4932 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
4933 +
4934 +
4935 +/*----------------------------------------------------
4936 + * Sangam Interrupt Map (Primary Interrupts)
4937 + *--------------------------------------------------*/
4938 +
4939 +#define AVALANCHE_UNIFIED_SECONDARY_INT 0
4940 +#define AVALANCHE_EXT_INT_0 1
4941 +#define AVALANCHE_EXT_INT_1 2
4942 +/* Line# 3 to 4 are reserved */
4943 +#define AVALANCHE_TIMER_0_INT 5
4944 +#define AVALANCHE_TIMER_1_INT 6
4945 +#define AVALANCHE_UART0_INT 7
4946 +#define AVALANCHE_UART1_INT 8
4947 +#define AVALANCHE_DMA_INT0 9
4948 +#define AVALANCHE_DMA_INT1 10
4949 +/* Line# 11 to 14 are reserved */
4950 +#define AVALANCHE_ATM_SAR_INT 15
4951 +/* Line# 16 to 18 are reserved */
4952 +#define AVALANCHE_LOW_CPMAC_INT 19
4953 +/* Line# 20 is reserved */
4954 +#define AVALANCHE_LOW_VLYNQ_INT 21
4955 +#define AVALANCHE_CODEC_WAKEUP_INT 22
4956 +/* Line# 23 is reserved */
4957 +#define AVALANCHE_USB_SLAVE_INT 24
4958 +#define AVALANCHE_HIGH_VLYNQ_INT 25
4959 +/* Line# 26 to 27 are reserved */
4960 +#define AVALANCHE_UNIFIED_PHY_INT 28
4961 +#define AVALANCHE_I2C_INT 29
4962 +#define AVALANCHE_DMA_INT2 30
4963 +#define AVALANCHE_DMA_INT3 31
4964 +/* Line# 32 is reserved */
4965 +#define AVALANCHE_HIGH_CPMAC_INT 33
4966 +/* Line# 34 to 36 is reserved */
4967 +#define AVALANCHE_VDMA_VT_RX_INT 37
4968 +#define AVALANCHE_VDMA_VT_TX_INT 38
4969 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
4970 +
4971 +
4972 +#define AVALANCHE_EMIF_INT 47
4973 +
4974 +
4975 +
4976 +/*-----------------------------------------------------------
4977 + * Sangam's Reset Bits
4978 + *---------------------------------------------------------*/
4979 +
4980 +#define AVALANCHE_UART0_RESET_BIT 0
4981 +#define AVALANCHE_UART1_RESET_BIT 1
4982 +#define AVALANCHE_I2C_RESET_BIT 2
4983 +#define AVALANCHE_TIMER0_RESET_BIT 3
4984 +#define AVALANCHE_TIMER1_RESET_BIT 4
4985 +/* Reset bit 5 is reserved. */
4986 +#define AVALANCHE_GPIO_RESET_BIT 6
4987 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
4988 +#define AVALANCHE_USB_SLAVE_RESET_BIT 8
4989 +#define AVALANCHE_ATM_SAR_RESET_BIT 9
4990 +/* Reset bit 10 is reserved. */
4991 +#define AVALANCHE_VDMA_VT_RESET_BIT 11
4992 +#define AVALANCHE_FSER_RESET_BIT 12
4993 +/* Reset bit 13 to 15 are reserved */
4994 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
4995 +#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
4996 +#define AVALANCHE_MCDMA_RESET_BIT 18
4997 +#define AVALANCHE_BIST_RESET_BIT 19
4998 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
4999 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
5000 +#define AVALANCHE_MDIO_RESET_BIT 22
5001 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
5002 +/* Reset bit 24 to 25 are reserved */
5003 +#define AVALANCHE_LOW_EPHY_RESET_BIT 26
5004 +/* Reset bit 27 to 31 are reserved */
5005 +
5006 +
5007 +#define AVALANCHE_POWER_MODULE_USBSP 0
5008 +#define AVALANCHE_POWER_MODULE_WDTP 1
5009 +#define AVALANCHE_POWER_MODULE_UT0P 2
5010 +#define AVALANCHE_POWER_MODULE_UT1P 3
5011 +#define AVALANCHE_POWER_MODULE_IICP 4
5012 +#define AVALANCHE_POWER_MODULE_VDMAP 5
5013 +#define AVALANCHE_POWER_MODULE_GPIOP 6
5014 +#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
5015 +#define AVALANCHE_POWER_MODULE_SARP 8
5016 +#define AVALANCHE_POWER_MODULE_ADSLP 9
5017 +#define AVALANCHE_POWER_MODULE_EMIFP 10
5018 +#define AVALANCHE_POWER_MODULE_ADSPP 12
5019 +#define AVALANCHE_POWER_MODULE_RAMP 13
5020 +#define AVALANCHE_POWER_MODULE_ROMP 14
5021 +#define AVALANCHE_POWER_MODULE_DMAP 15
5022 +#define AVALANCHE_POWER_MODULE_BISTP 16
5023 +#define AVALANCHE_POWER_MODULE_TIMER0P 18
5024 +#define AVALANCHE_POWER_MODULE_TIMER1P 19
5025 +#define AVALANCHE_POWER_MODULE_EMAC0P 20
5026 +#define AVALANCHE_POWER_MODULE_EMAC1P 22
5027 +#define AVALANCHE_POWER_MODULE_EPHYP 24
5028 +#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
5029 +
5030 +
5031 +
5032 +
5033 +
5034 +/*
5035 + * Sangam board vectors
5036 + */
5037 +
5038 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
5039 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
5040 +
5041 +/*-----------------------------------------------------------------------------
5042 + * Sangam's system register.
5043 + *
5044 + *---------------------------------------------------------------------------*/
5045 +#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
5046 +#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
5047 +#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
5048 +#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
5049 +#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
5050 +
5051 +#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
5052 +#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
5053 +
5054 +#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
5055 +#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
5056 +#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
5057 +#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
5058 +#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
5059 +
5060 +/*
5061 + * Yamon Prom print address.
5062 + */
5063 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
5064 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
5065 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
5066 +
5067 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
5068 +
5069 +#define AVALANCHE_GPIO_PIN_COUNT 32
5070 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
5071 +
5072 +#include "sangam_boards.h"
5073 +
5074 +#endif /*_SANGAM_H_ */
5075 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
5076 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
5077 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-08-12 19:32:05.171220344 +0200
5078 @@ -0,0 +1,42 @@
5079 +/******************************************************************************
5080 + * FILE PURPOSE: TNETD73xx Error Definations Header File
5081 + ******************************************************************************
5082 + * FILE NAME: tnetd73xx_err.h
5083 + *
5084 + * DESCRIPTION: Error definations for TNETD73XX
5085 + *
5086 + * REVISION HISTORY:
5087 + * 27 Nov 02 - PSP TII
5088 + *
5089 + * (C) Copyright 2002, Texas Instruments, Inc
5090 + *******************************************************************************/
5091 +
5092 +
5093 +#ifndef __TNETD73XX_ERR_H__
5094 +#define __TNETD73XX_ERR_H__
5095 +
5096 +typedef enum TNETD73XX_ERR_t
5097 +{
5098 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
5099 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
5100 +
5101 + /* Pointers and args */
5102 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
5103 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
5104 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
5105 +
5106 + /* Memory issues */
5107 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
5108 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
5109 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
5110 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
5111 +
5112 + /* Device issues */
5113 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
5114 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
5115 +
5116 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
5117 +
5118 +} TNETD73XX_ERR;
5119 +
5120 +#endif /* __TNETD73XX_ERR_H__ */
5121 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
5122 --- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
5123 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-08-12 19:32:05.151223384 +0200
5124 @@ -0,0 +1,338 @@
5125 +/******************************************************************************
5126 + * FILE PURPOSE: TNETD73xx Common Header File
5127 + ******************************************************************************
5128 + * FILE NAME: tnetd73xx.h
5129 + *
5130 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
5131 + *
5132 + * REVISION HISTORY:
5133 + * 27 Nov 02 - PSP TII
5134 + *
5135 + * (C) Copyright 2002, Texas Instruments, Inc
5136 + *******************************************************************************/
5137 +
5138 +/*
5139 + *
5140 + *
5141 + * These are const, typedef, and api definitions for tnetd73xx.
5142 + *
5143 + * NOTES:
5144 + * 1. This file may be included into both C and Assembly files.
5145 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
5146 + * avoid C data types (typedefs) below;
5147 + * - for .c files, you don't have to do anything special.
5148 + *
5149 + * 2. This file has a number of sections for each SOC subsystem. When adding
5150 + * a new constant, find the subsystem you are working on and follow the
5151 + * name pattern. If you are adding another typedef for your interface, please,
5152 + * place it with other typedefs and function prototypes.
5153 + *
5154 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
5155 + * cluttering. Include such items directly into the module's .c file or have a
5156 + * local .h file to pass data between smaller modules. This file defines only
5157 + * shared items.
5158 + */
5159 +
5160 +#ifndef __TNETD73XX_H__
5161 +#define __TNETD73XX_H__
5162 +
5163 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
5164 +
5165 +extern unsigned int tnetd73xx_mips_freq;
5166 +extern unsigned int tnetd73xx_vbus_freq;
5167 +
5168 +#include "tnetd73xx_err.h"
5169 +
5170 +#endif /* _ASMLANGUAGE */
5171 +
5172 +
5173 +/*******************************************************************************************
5174 +* Emerald core specific
5175 +******************************************************************************************** */
5176 +
5177 +#ifdef BIG_ENDIAN
5178 +#elif defined(LITTLE_ENDIAN)
5179 +#else
5180 +#error Need to define endianism
5181 +#endif
5182 +
5183 +#ifndef KSEG_MSK
5184 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
5185 +#endif
5186 +
5187 +#ifndef KSEG_INV_MASK
5188 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
5189 +#endif
5190 +
5191 +#ifndef KSEG0_BASE
5192 +#define KSEG0_BASE 0x80000000
5193 +#endif
5194 +
5195 +#ifndef KSEG1_BASE
5196 +#define KSEG1_BASE 0xA0000000
5197 +#endif
5198 +
5199 +#ifndef KSEG0
5200 +#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
5201 +#endif
5202 +
5203 +#ifndef KSEG1
5204 +#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
5205 +#endif
5206 +
5207 +#ifndef KUSEG
5208 +#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
5209 +#endif
5210 +
5211 +#ifndef PHYS_ADDR
5212 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
5213 +#endif
5214 +
5215 +#ifndef PHYS_TO_K0
5216 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
5217 +#endif
5218 +
5219 +#ifndef PHYS_TO_K1
5220 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
5221 +#endif
5222 +
5223 +#ifndef REG8_ADDR
5224 +#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
5225 +#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
5226 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
5227 +#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
5228 +#endif
5229 +
5230 +#ifndef REG16_ADDR
5231 +#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
5232 +#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
5233 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
5234 +#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
5235 +#endif
5236 +
5237 +#ifndef REG32_ADDR
5238 +#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
5239 +#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
5240 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
5241 +#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
5242 +#endif
5243 +
5244 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
5245 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
5246 +#endif
5247 +
5248 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
5249 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
5250 +#endif
5251 +
5252 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
5253 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
5254 +#endif
5255 +
5256 +/* TNETD73XX chip definations */
5257 +
5258 +#define FREQ_1MHZ 1000000
5259 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
5260 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
5261 +
5262 +#ifdef AR7SEAD2
5263 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
5264 +#else
5265 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
5266 +#endif
5267 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
5268 +
5269 +
5270 +
5271 +/* Module base addresses */
5272 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
5273 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
5274 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
5275 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
5276 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
5277 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
5278 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
5279 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
5280 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
5281 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
5282 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
5283 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
5284 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
5285 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
5286 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
5287 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
5288 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
5289 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
5290 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
5291 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
5292 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
5293 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
5294 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
5295 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
5296 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
5297 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
5298 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
5299 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
5300 +
5301 +/* BBIF Registers */
5302 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
5303 +
5304 +/* Device Configuration Latch Registers */
5305 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
5306 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
5307 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
5308 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
5309 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
5310 +
5311 +/* GPIO Control */
5312 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
5313 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
5314 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
5315 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
5316 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
5317 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
5318 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
5319 +
5320 +/* Reset Control */
5321 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
5322 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
5323 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
5324 +
5325 +/* Power Control */
5326 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
5327 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
5328 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
5329 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
5330 +
5331 +/* Clock Control */
5332 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
5333 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
5334 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
5335 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
5336 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
5337 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
5338 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
5339 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
5340 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
5341 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
5342 +
5343 +/* EMIF control */
5344 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
5345 +
5346 +/* UART */
5347 +#ifdef AR7SEAD2
5348 +#define TNETD73XX_UART_FREQ 3686400
5349 +#else
5350 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
5351 +#endif
5352 +
5353 +/* Interrupt Controller */
5354 +
5355 +/* Primary interrupts */
5356 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
5357 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
5358 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
5359 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
5360 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
5361 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
5362 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
5363 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
5364 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
5365 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
5366 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
5367 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
5368 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
5369 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
5370 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
5371 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
5372 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
5373 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
5374 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
5375 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
5376 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
5377 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
5378 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
5379 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
5380 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
5381 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
5382 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
5383 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
5384 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
5385 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
5386 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
5387 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
5388 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
5389 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
5390 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
5391 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
5392 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
5393 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
5394 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
5395 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
5396 +
5397 +/* Secondary interrupts */
5398 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
5399 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
5400 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
5401 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
5402 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
5403 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
5404 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
5405 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
5406 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
5407 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
5408 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
5409 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
5410 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
5411 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
5412 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
5413 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
5414 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
5415 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
5416 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
5417 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
5418 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
5419 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
5420 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
5421 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
5422 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
5423 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
5424 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
5425 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
5426 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
5427 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
5428 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
5429 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
5430 +
5431 +/* These ugly macros are to access the -1 registers, like config1 */
5432 +#define MFC0_SEL1_OPCODE(dst, src)\
5433 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
5434 + nop; \
5435 + nop; \
5436 + nop
5437 +
5438 +#define MTC0_SEL1_OPCODE(dst, src)\
5439 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
5440 + nop; \
5441 + nop; \
5442 + nop
5443 +
5444 +
5445 +/* Below are Jade core specific */
5446 +#define CFG0_4K_IL_MASK 0x00380000
5447 +#define CFG0_4K_IL_SHIFT 19
5448 +#define CFG0_4K_IA_MASK 0x00070000
5449 +#define CFG0_4K_IA_SHIFT 16
5450 +#define CFG0_4K_IS_MASK 0x01c00000
5451 +#define CFG0_4K_IS_SHIFT 22
5452 +
5453 +#define CFG0_4K_DL_MASK 0x00001c00
5454 +#define CFG0_4K_DL_SHIFT 10
5455 +#define CFG0_4K_DA_MASK 0x00000380
5456 +#define CFG0_4K_DA_SHIFT 7
5457 +#define CFG0_4K_DS_MASK 0x0000E000
5458 +#define CFG0_4K_DS_SHIFT 13
5459 +
5460 +
5461 +
5462 +#endif /* __TNETD73XX_H_ */
5463 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
5464 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
5465 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-08-12 19:32:05.172220192 +0200
5466 @@ -0,0 +1,239 @@
5467 +/******************************************************************************
5468 + * FILE PURPOSE: TNETD73xx Misc modules API Header
5469 + ******************************************************************************
5470 + * FILE NAME: tnetd73xx_misc.h
5471 + *
5472 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
5473 + * FSER Modules API
5474 + * As per TNETD73xx specifications
5475 + *
5476 + * REVISION HISTORY:
5477 + * 27 Nov 02 - Sharath Kumar PSP TII
5478 + * 14 Feb 03 - Anant Gole PSP TII
5479 + *
5480 + * (C) Copyright 2002, Texas Instruments, Inc
5481 + *******************************************************************************/
5482 +
5483 +#ifndef __TNETD73XX_MISC_H__
5484 +#define __TNETD73XX_MISC_H__
5485 +
5486 +/*****************************************************************************
5487 + * Reset Control Module
5488 + *****************************************************************************/
5489 +
5490 +typedef enum TNETD73XX_RESET_MODULE_tag
5491 +{
5492 + RESET_MODULE_UART0 = 0,
5493 + RESET_MODULE_UART1 = 1,
5494 + RESET_MODULE_I2C = 2,
5495 + RESET_MODULE_TIMER0 = 3,
5496 + RESET_MODULE_TIMER1 = 4,
5497 + RESET_MODULE_GPIO = 6,
5498 + RESET_MODULE_ADSLSS = 7,
5499 + RESET_MODULE_USBS = 8,
5500 + RESET_MODULE_SAR = 9,
5501 + RESET_MODULE_VDMA_VT = 11,
5502 + RESET_MODULE_FSER = 12,
5503 + RESET_MODULE_VLYNQ1 = 16,
5504 + RESET_MODULE_EMAC0 = 17,
5505 + RESET_MODULE_DMA = 18,
5506 + RESET_MODULE_BIST = 19,
5507 + RESET_MODULE_VLYNQ0 = 20,
5508 + RESET_MODULE_EMAC1 = 21,
5509 + RESET_MODULE_MDIO = 22,
5510 + RESET_MODULE_ADSLSS_DSP = 23,
5511 + RESET_MODULE_EPHY = 26
5512 +} TNETD73XX_RESET_MODULE_T;
5513 +
5514 +typedef enum TNETD73XX_RESET_CTRL_tag
5515 +{
5516 + IN_RESET = 0,
5517 + OUT_OF_RESET
5518 +} TNETD73XX_RESET_CTRL_T;
5519 +
5520 +typedef enum TNETD73XX_SYS_RST_MODE_tag
5521 +{
5522 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
5523 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
5524 +} TNETD73XX_SYS_RST_MODE_T;
5525 +
5526 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
5527 +{
5528 + HARDWARE_RESET = 0,
5529 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
5530 + WATCHDOG_RESET,
5531 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
5532 +} TNETD73XX_SYS_RESET_STATUS_T;
5533 +
5534 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
5535 + TNETD73XX_RESET_CTRL_T reset_ctrl);
5536 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
5537 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
5538 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
5539 +
5540 +/*****************************************************************************
5541 + * Power Control Module
5542 + *****************************************************************************/
5543 +
5544 +typedef enum TNETD73XX_POWER_MODULE_tag
5545 +{
5546 + POWER_MODULE_USBSP = 0,
5547 + POWER_MODULE_WDTP = 1,
5548 + POWER_MODULE_UT0P = 2,
5549 + POWER_MODULE_UT1P = 3,
5550 + POWER_MODULE_IICP = 4,
5551 + POWER_MODULE_VDMAP = 5,
5552 + POWER_MODULE_GPIOP = 6,
5553 + POWER_MODULE_VLYNQ1P = 7,
5554 + POWER_MODULE_SARP = 8,
5555 + POWER_MODULE_ADSLP = 9,
5556 + POWER_MODULE_EMIFP = 10,
5557 + POWER_MODULE_ADSPP = 12,
5558 + POWER_MODULE_RAMP = 13,
5559 + POWER_MODULE_ROMP = 14,
5560 + POWER_MODULE_DMAP = 15,
5561 + POWER_MODULE_BISTP = 16,
5562 + POWER_MODULE_TIMER0P = 18,
5563 + POWER_MODULE_TIMER1P = 19,
5564 + POWER_MODULE_EMAC0P = 20,
5565 + POWER_MODULE_EMAC1P = 22,
5566 + POWER_MODULE_EPHYP = 24,
5567 + POWER_MODULE_VLYNQ0P = 27,
5568 +} TNETD73XX_POWER_MODULE_T;
5569 +
5570 +typedef enum TNETD73XX_POWER_CTRL_tag
5571 +{
5572 + POWER_CTRL_POWER_UP = 0,
5573 + POWER_CTRL_POWER_DOWN
5574 +} TNETD73XX_POWER_CTRL_T;
5575 +
5576 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
5577 +{
5578 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
5579 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
5580 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
5581 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
5582 +} TNETD73XX_SYS_POWER_MODE_T;
5583 +
5584 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
5585 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
5586 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
5587 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
5588 +
5589 +/*****************************************************************************
5590 + * Wakeup Control
5591 + *****************************************************************************/
5592 +
5593 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
5594 +{
5595 + WAKEUP_INT0 = 1,
5596 + WAKEUP_INT1 = 2,
5597 + WAKEUP_INT2 = 4,
5598 + WAKEUP_INT3 = 8
5599 +} TNETD73XX_WAKEUP_INTERRUPT_T;
5600 +
5601 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
5602 +{
5603 + WAKEUP_DISABLED = 0,
5604 + WAKEUP_ENABLED
5605 +} TNETD73XX_WAKEUP_CTRL_T;
5606 +
5607 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
5608 +{
5609 + WAKEUP_ACTIVE_HIGH = 0,
5610 + WAKEUP_ACTIVE_LOW
5611 +} TNETD73XX_WAKEUP_POLARITY_T;
5612 +
5613 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
5614 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
5615 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
5616 +
5617 +/*****************************************************************************
5618 + * FSER Control
5619 + *****************************************************************************/
5620 +
5621 +typedef enum TNETD73XX_FSER_MODE_tag
5622 +{
5623 + FSER_I2C = 0,
5624 + FSER_UART = 1
5625 +} TNETD73XX_FSER_MODE_T;
5626 +
5627 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
5628 +
5629 +/*****************************************************************************
5630 + * Clock Control
5631 + *****************************************************************************/
5632 +
5633 +#define CLK_MHZ(x) ( (x) * 1000000 )
5634 +
5635 +typedef enum TNETD73XX_CLKC_ID_tag
5636 +{
5637 + CLKC_SYS = 0,
5638 + CLKC_MIPS,
5639 + CLKC_USB,
5640 + CLKC_ADSLSS
5641 +} TNETD73XX_CLKC_ID_T;
5642 +
5643 +void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
5644 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
5645 +__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
5646 +
5647 +/*****************************************************************************
5648 + * GPIO Control
5649 + *****************************************************************************/
5650 +
5651 +typedef enum TNETD73XX_GPIO_PIN_tag
5652 +{
5653 + GPIO_UART0_RD = 0,
5654 + GPIO_UART0_TD = 1,
5655 + GPIO_UART0_RTS = 2,
5656 + GPIO_UART0_CTS = 3,
5657 + GPIO_FSER_CLK = 4,
5658 + GPIO_FSER_D = 5,
5659 + GPIO_EXT_AFE_SCLK = 6,
5660 + GPIO_EXT_AFE_TX_FS = 7,
5661 + GPIO_EXT_AFE_TXD = 8,
5662 + GPIO_EXT_AFE_RS_FS = 9,
5663 + GPIO_EXT_AFE_RXD1 = 10,
5664 + GPIO_EXT_AFE_RXD0 = 11,
5665 + GPIO_EXT_AFE_CDIN = 12,
5666 + GPIO_EXT_AFE_CDOUT = 13,
5667 + GPIO_EPHY_SPEED100 = 14,
5668 + GPIO_EPHY_LINKON = 15,
5669 + GPIO_EPHY_ACTIVITY = 16,
5670 + GPIO_EPHY_FDUPLEX = 17,
5671 + GPIO_EINT0 = 18,
5672 + GPIO_EINT1 = 19,
5673 + GPIO_MBSP0_TCLK = 20,
5674 + GPIO_MBSP0_RCLK = 21,
5675 + GPIO_MBSP0_RD = 22,
5676 + GPIO_MBSP0_TD = 23,
5677 + GPIO_MBSP0_RFS = 24,
5678 + GPIO_MBSP0_TFS = 25,
5679 + GPIO_MII_DIO = 26,
5680 + GPIO_MII_DCLK = 27,
5681 +} TNETD73XX_GPIO_PIN_T;
5682 +
5683 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
5684 +{
5685 + FUNCTIONAL_PIN = 0,
5686 + GPIO_PIN = 1
5687 +} TNETD73XX_GPIO_PIN_MODE_T;
5688 +
5689 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
5690 +{
5691 + GPIO_OUTPUT_PIN = 0,
5692 + GPIO_INPUT_PIN = 1
5693 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
5694 +
5695 +void tnetd73xx_gpio_init(void);
5696 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
5697 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
5698 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
5699 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
5700 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
5701 +
5702 +/* TNETD73XX Revision */
5703 +__u32 tnetd73xx_get_revision(void);
5704 +
5705 +#endif /* __TNETD73XX_MISC_H__ */
5706 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
5707 --- linux.old/include/asm-mips/io.h 2005-07-10 03:00:44.000000000 +0200
5708 +++ linux.dev/include/asm-mips/io.h 2005-08-12 21:13:28.133469520 +0200
5709 @@ -63,8 +63,12 @@
5710 #ifdef CONFIG_64BIT_PHYS_ADDR
5711 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
5712 #else
5713 +#ifdef CONFIG_AR7
5714 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
5715 +#else
5716 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
5717 #endif
5718 +#endif
5719
5720 #define IO_SPACE_LIMIT 0xffff
5721
5722 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
5723 --- linux.old/include/asm-mips/irq.h 2005-07-10 03:00:44.000000000 +0200
5724 +++ linux.dev/include/asm-mips/irq.h 2005-08-12 19:32:05.172220192 +0200
5725 @@ -14,7 +14,12 @@
5726 #include <linux/config.h>
5727 #include <linux/linkage.h>
5728
5729 +#ifdef CONFIG_AR7
5730 +#include <asm/ar7/avalanche_intc.h>
5731 +#define NR_IRQS AVALANCHE_INT_END + 1
5732 +#else
5733 #define NR_IRQS 128 /* Largest number of ints of all machines. */
5734 +#endif
5735
5736 #ifdef CONFIG_I8259
5737 static inline int irq_cannonicalize(int irq)
5738 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
5739 --- linux.old/include/asm-mips/page.h 2005-07-10 03:00:44.000000000 +0200
5740 +++ linux.dev/include/asm-mips/page.h 2005-08-12 21:13:38.481896320 +0200
5741 @@ -129,7 +129,11 @@
5742
5743 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
5744 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
5745 +#ifdef CONFIG_AR7
5746 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
5747 +#else
5748 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
5749 +#endif
5750 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
5751
5752 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
5753 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
5754 --- linux.old/include/asm-mips/pgtable-32.h 2005-07-10 03:00:44.000000000 +0200
5755 +++ linux.dev/include/asm-mips/pgtable-32.h 2005-08-12 21:13:46.898616784 +0200
5756 @@ -108,7 +108,18 @@
5757 * and a page entry and page directory to the page they refer to.
5758 */
5759
5760 -#ifdef CONFIG_CPU_VR41XX
5761 +#if defined(CONFIG_AR7)
5762 +#define mk_pte(page, pgprot) \
5763 +({ \
5764 + pte_t __pte; \
5765 + \
5766 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
5767 + CONFIG_AR7_MEMORY) | \
5768 + pgprot_val(pgprot); \
5769 + \
5770 + __pte; \
5771 +})
5772 +#elif defined(CONFIG_CPU_VR41XX)
5773 #define mk_pte(page, pgprot) \
5774 ({ \
5775 pte_t __pte; \
5776 @@ -130,6 +141,7 @@
5777 })
5778 #endif
5779
5780 +
5781 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
5782 {
5783 #ifdef CONFIG_CPU_VR41XX
5784 @@ -175,7 +187,10 @@
5785 set_pte(ptep, __pte(0));
5786 }
5787
5788 -#ifdef CONFIG_CPU_VR41XX
5789 +#if defined(CONFIG_AR7)
5790 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
5791 +#define pte_page(x) phys_to_page(pte_val(x))
5792 +#elif defined(CONFIG_CPU_VR41XX)
5793 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
5794 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
5795 #else
5796 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
5797 --- linux.old/include/asm-mips/serial.h 2005-07-10 03:00:44.000000000 +0200
5798 +++ linux.dev/include/asm-mips/serial.h 2005-08-12 19:32:05.174219888 +0200
5799 @@ -65,6 +65,15 @@
5800
5801 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
5802
5803 +#ifdef CONFIG_AR7
5804 +#include <asm/ar7/ar7.h>
5805 +#define AR7_SERIAL_PORT_DEFNS \
5806 + { 0, AR7_BASE_BAUD, AR7_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
5807 + { 0, AR7_BASE_BAUD, AR7_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
5808 +#else
5809 +#define AR7_SERIAL_PORT_DEFNS
5810 +#endif
5811 +
5812 #ifdef CONFIG_MIPS_JAZZ
5813 #define _JAZZ_SERIAL_INIT(int, base) \
5814 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
5815 @@ -468,6 +477,7 @@
5816 #endif
5817
5818 #define SERIAL_PORT_DFNS \
5819 + AR7_SERIAL_PORT_DEFNS \
5820 ATLAS_SERIAL_PORT_DEFNS \
5821 AU1000_SERIAL_PORT_DEFNS \
5822 COBALT_SERIAL_PORT_DEFNS \
5823 diff -urN linux.old/Makefile linux.dev/Makefile
5824 --- linux.old/Makefile 2005-07-10 03:00:44.000000000 +0200
5825 +++ linux.dev/Makefile 2005-08-12 19:32:05.122227792 +0200
5826 @@ -91,7 +91,7 @@
5827
5828 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
5829
5830 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
5831 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
5832 -fno-strict-aliasing -fno-common
5833 ifndef CONFIG_FRAME_POINTER
5834 CFLAGS += -fomit-frame-pointer
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