package/rt2x00/src/rt73usb.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: Data structures and registers for the rt73usb module.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #ifndef RT73USB_H
  28 #define RT73USB_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF5226                          0x0001
  34 #define RF2528                          0x0002
  35 #define RF5225                          0x0003
  36 #define RF2527                          0x0004
  37
  38 /*
  39  * Max RSSI value, required for RSSI <-> dBm conversion.
  40  */
  41 #define MAX_RX_SSI                      120
  42 #define MAX_RX_NOISE                    -110
  43
  44 /*
  45  * Register layout information.
  46  */
  47 #define CSR_REG_BASE                    0x3000
  48 #define CSR_REG_SIZE                    0x04b0
  49 #define EEPROM_BASE                     0x0000
  50 #define EEPROM_SIZE                     0x0100
  51 #define BBP_SIZE                        0x0080
  52
  53 /*
  54  * USB registers.
  55  */
  56
  57 /*
  58  * MCU_LEDCS: LED control for MCU Mailbox.
  59  */
  60 #define MCU_LEDCS_LED_MODE              FIELD16(0x001f)
  61 #define MCU_LEDCS_RADIO_STATUS          FIELD16(0x0020)
  62 #define MCU_LEDCS_LINK_BG_STATUS        FIELD16(0x0040)
  63 #define MCU_LEDCS_LINK_A_STATUS         FIELD16(0x0080)
  64 #define MCU_LEDCS_POLARITY_GPIO_0       FIELD16(0x0100)
  65 #define MCU_LEDCS_POLARITY_GPIO_1       FIELD16(0x0200)
  66 #define MCU_LEDCS_POLARITY_GPIO_2       FIELD16(0x0400)
  67 #define MCU_LEDCS_POLARITY_GPIO_3       FIELD16(0x0800)
  68 #define MCU_LEDCS_POLARITY_GPIO_4       FIELD16(0x1000)
  69 #define MCU_LEDCS_POLARITY_ACT          FIELD16(0x2000)
  70 #define MCU_LEDCS_POLARITY_READY_BG     FIELD16(0x4000)
  71 #define MCU_LEDCS_POLARITY_READY_A      FIELD16(0x8000)
  72
  73 /*
  74  * 8051 firmware image.
  75  */
  76 #define FIRMWARE_RT2571                 "rt73.bin"
  77 #define FIRMWARE_IMAGE_BASE             0x0800
  78
  79 /*
  80  * Security key table memory.
  81  * 16 entries 32-byte for shared key table
  82  * 64 entries 32-byte for pairwise key table
  83  * 64 entries 8-byte for pairwise ta key table
  84  */
  85 #define SHARED_KEY_TABLE_BASE           0x1000
  86 #define PAIRWISE_KEY_TABLE_BASE         0x1200
  87 #define PAIRWISE_TA_TABLE_BASE          0x1a00
  88
  89 struct hw_key_entry {
  90         u8 key[16];
  91         u8 tx_mic[8];
  92         u8 rx_mic[8];
  93 } __attribute__ ((packed));
  94
  95 struct hw_pairwise_ta_entry {
  96         u8 address[6];
  97         u8 reserved[2];
  98 } __attribute__ ((packed));
  99
 100 /*
 101  * Since NULL frame won't be that long (256 byte),
 102  * We steal 16 tail bytes to save debugging settings.
 103  */
 104 #define HW_DEBUG_SETTING_BASE           0x2bf0
 105
 106 /*
 107  * On-chip BEACON frame space.
 108  */
 109 #define HW_BEACON_BASE0                 0x2400
 110 #define HW_BEACON_BASE1                 0x2500
 111 #define HW_BEACON_BASE2                 0x2600
 112 #define HW_BEACON_BASE3                 0x2700
 113
 114 /*
 115  * MAC Control/Status Registers(CSR).
 116  * Some values are set in TU, whereas 1 TU == 1024 us.
 117  */
 118
 119 /*
 120  * MAC_CSR0: ASIC revision number.
 121  */
 122 #define MAC_CSR0                        0x3000
 123
 124 /*
 125  * MAC_CSR1: System control register.
 126  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
 127  * BBP_RESET: Hardware reset BBP.
 128  * HOST_READY: Host is ready after initialization, 1: ready.
 129  */
 130 #define MAC_CSR1                        0x3004
 131 #define MAC_CSR1_SOFT_RESET             FIELD32(0x00000001)
 132 #define MAC_CSR1_BBP_RESET              FIELD32(0x00000002)
 133 #define MAC_CSR1_HOST_READY             FIELD32(0x00000004)
 134
 135 /*
 136  * MAC_CSR2: STA MAC register 0.
 137  */
 138 #define MAC_CSR2                        0x3008
 139 #define MAC_CSR2_BYTE0                  FIELD32(0x000000ff)
 140 #define MAC_CSR2_BYTE1                  FIELD32(0x0000ff00)
 141 #define MAC_CSR2_BYTE2                  FIELD32(0x00ff0000)
 142 #define MAC_CSR2_BYTE3                  FIELD32(0xff000000)
 143
 144 /*
 145  * MAC_CSR3: STA MAC register 1.
 146  */
 147 #define MAC_CSR3                        0x300c
 148 #define MAC_CSR3_BYTE4                  FIELD32(0x000000ff)
 149 #define MAC_CSR3_BYTE5                  FIELD32(0x0000ff00)
 150 #define MAC_CSR3_UNICAST_TO_ME_MASK     FIELD32(0x00ff0000)
 151
 152 /*
 153  * MAC_CSR4: BSSID register 0.
 154  */
 155 #define MAC_CSR4                        0x3010
 156 #define MAC_CSR4_BYTE0                  FIELD32(0x000000ff)
 157 #define MAC_CSR4_BYTE1                  FIELD32(0x0000ff00)
 158 #define MAC_CSR4_BYTE2                  FIELD32(0x00ff0000)
 159 #define MAC_CSR4_BYTE3                  FIELD32(0xff000000)
 160
 161 /*
 162  * MAC_CSR5: BSSID register 1.
 163  * BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
 164  */
 165 #define MAC_CSR5                        0x3014
 166 #define MAC_CSR5_BYTE4                  FIELD32(0x000000ff)
 167 #define MAC_CSR5_BYTE5                  FIELD32(0x0000ff00)
 168 #define MAC_CSR5_BSS_ID_MASK            FIELD32(0x00ff0000)
 169
 170 /*
 171  * MAC_CSR6: Maximum frame length register.
 172  */
 173 #define MAC_CSR6                        0x3018
 174 #define MAC_CSR6_MAX_FRAME_UNIT         FIELD32(0x000007ff)
 175
 176 /*
 177  * MAC_CSR7: Reserved
 178  */
 179 #define MAC_CSR7                        0x301c
 180
 181 /*
 182  * MAC_CSR8: SIFS/EIFS register.
 183  * All units are in US.
 184  */
 185 #define MAC_CSR8                        0x3020
 186 #define MAC_CSR8_SIFS                   FIELD32(0x000000ff)
 187 #define MAC_CSR8_SIFS_AFTER_RX_OFDM     FIELD32(0x0000ff00)
 188 #define MAC_CSR8_EIFS                   FIELD32(0xffff0000)
 189
 190 /*
 191  * MAC_CSR9: Back-Off control register.
 192  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
 193  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
 194  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
 195  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
 196  */
 197 #define MAC_CSR9                        0x3024
 198 #define MAC_CSR9_SLOT_TIME              FIELD32(0x000000ff)
 199 #define MAC_CSR9_CWMIN                  FIELD32(0x00000f00)
 200 #define MAC_CSR9_CWMAX                  FIELD32(0x0000f000)
 201 #define MAC_CSR9_CW_SELECT              FIELD32(0x00010000)
 202
 203 /*
 204  * MAC_CSR10: Power state configuration.
 205  */
 206 #define MAC_CSR10                       0x3028
 207
 208 /*
 209  * MAC_CSR11: Power saving transition time register.
 210  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
 211  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 212  * WAKEUP_LATENCY: In unit of TU.
 213  */
 214 #define MAC_CSR11                       0x302c
 215 #define MAC_CSR11_DELAY_AFTER_TBCN      FIELD32(0x000000ff)
 216 #define MAC_CSR11_TBCN_BEFORE_WAKEUP    FIELD32(0x00007f00)
 217 #define MAC_CSR11_AUTOWAKE              FIELD32(0x00008000)
 218 #define MAC_CSR11_WAKEUP_LATENCY        FIELD32(0x000f0000)
 219
 220 /*
 221  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
 222  * CURRENT_STATE: 0:sleep, 1:awake.
 223  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
 224  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
 225  */
 226 #define MAC_CSR12                       0x3030
 227 #define MAC_CSR12_CURRENT_STATE         FIELD32(0x00000001)
 228 #define MAC_CSR12_PUT_TO_SLEEP          FIELD32(0x00000002)
 229 #define MAC_CSR12_FORCE_WAKEUP          FIELD32(0x00000004)
 230 #define MAC_CSR12_BBP_CURRENT_STATE     FIELD32(0x00000008)
 231
 232 /*
 233  * MAC_CSR13: GPIO.
 234  */
 235 #define MAC_CSR13                       0x3034
 236
 237 /*
 238  * MAC_CSR14: LED control register.
 239  * ON_PERIOD: On period, default 70ms.
 240  * OFF_PERIOD: Off period, default 30ms.
 241  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
 242  * SW_LED: s/w LED, 1: ON, 0: OFF.
 243  * HW_LED_POLARITY: 0: active low, 1: active high.
 244  */
 245 #define MAC_CSR14                       0x3038
 246 #define MAC_CSR14_ON_PERIOD             FIELD32(0x000000ff)
 247 #define MAC_CSR14_OFF_PERIOD            FIELD32(0x0000ff00)
 248 #define MAC_CSR14_HW_LED                FIELD32(0x00010000)
 249 #define MAC_CSR14_SW_LED                FIELD32(0x00020000)
 250 #define MAC_CSR14_HW_LED_POLARITY       FIELD32(0x00040000)
 251 #define MAC_CSR14_SW_LED2               FIELD32(0x00080000)
 252
 253 /*
 254  * MAC_CSR15: NAV control.
 255  */
 256 #define MAC_CSR15                       0x303c
 257
 258 /*
 259  * TXRX control registers.
 260  * Some values are set in TU, whereas 1 TU == 1024 us.
 261  */
 262
 263 /*
 264  * TXRX_CSR0: TX/RX configuration register.
 265  * TSF_OFFSET: Default is 24.
 266  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
 267  * DISABLE_RX: Disable Rx engine.
 268  * DROP_CRC: Drop CRC error.
 269  * DROP_PHYSICAL: Drop physical error.
 270  * DROP_CONTROL: Drop control frame.
 271  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 272  * DROP_TO_DS: Drop fram ToDs bit is true.
 273  * DROP_VERSION_ERROR: Drop version error frame.
 274  * DROP_MULTICAST: Drop multicast frames.
 275  * DROP_BORADCAST: Drop broadcast frames.
 276  * ROP_ACK_CTS: Drop received ACK and CTS.
 277  */
 278 #define TXRX_CSR0                       0x3040
 279 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
 280 #define TXRX_CSR0_TSF_OFFSET            FIELD32(0x00007e00)
 281 #define TXRX_CSR0_AUTO_TX_SEQ           FIELD32(0x00008000)
 282 #define TXRX_CSR0_DISABLE_RX            FIELD32(0x00010000)
 283 #define TXRX_CSR0_DROP_CRC              FIELD32(0x00020000)
 284 #define TXRX_CSR0_DROP_PHYSICAL         FIELD32(0x00040000)
 285 #define TXRX_CSR0_DROP_CONTROL          FIELD32(0x00080000)
 286 #define TXRX_CSR0_DROP_NOT_TO_ME        FIELD32(0x00100000)
 287 #define TXRX_CSR0_DROP_TO_DS            FIELD32(0x00200000)
 288 #define TXRX_CSR0_DROP_VERSION_ERROR    FIELD32(0x00400000)
 289 #define TXRX_CSR0_DROP_MULTICAST        FIELD32(0x00800000)
 290 #define TXRX_CSR0_DROP_BORADCAST        FIELD32(0x01000000)
 291 #define TXRX_CSR0_DROP_ACK_CTS          FIELD32(0x02000000)
 292 #define TXRX_CSR0_TX_WITHOUT_WAITING    FIELD32(0x04000000)
 293
 294 /*
 295  * TXRX_CSR1
 296  */
 297 #define TXRX_CSR1                       0x3044
 298
 299 /*
 300  * TXRX_CSR2
 301  */
 302 #define TXRX_CSR2                       0x3048
 303
 304 /*
 305  * TXRX_CSR3
 306  */
 307 #define TXRX_CSR3                       0x304c
 308
 309 /*
 310  * TXRX_CSR4: Auto-Responder/Tx-retry register.
 311  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
 312  * OFDM_TX_RATE_DOWN: 1:enable.
 313  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
 314  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
 315  */
 316 #define TXRX_CSR4                       0x3050
 317 #define TXRX_CSR4_TX_ACK_TIMEOUT        FIELD32(0x000000ff)
 318 #define TXRX_CSR4_CNTL_ACK_POLICY       FIELD32(0x00000700)
 319 #define TXRX_CSR4_ACK_CTS_PSM           FIELD32(0x00010000)
 320 #define TXRX_CSR4_AUTORESPOND_ENABLE    FIELD32(0x00020000)
 321 #define TXRX_CSR4_AUTORESPOND_PREAMBLE  FIELD32(0x00040000)
 322 #define TXRX_CSR4_OFDM_TX_RATE_DOWN     FIELD32(0x00080000)
 323 #define TXRX_CSR4_OFDM_TX_RATE_STEP     FIELD32(0x00300000)
 324 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK  FIELD32(0x00400000)
 325 #define TXRX_CSR4_LONG_RETRY_LIMIT      FIELD32(0x0f000000)
 326 #define TXRX_CSR4_SHORT_RETRY_LIMIT     FIELD32(0xf0000000)
 327
 328 /*
 329  * TXRX_CSR5
 330  */
 331 #define TXRX_CSR5                       0x3054
 332
 333 /*
 334  * ACK/CTS payload consumed time registers.
 335  */
 336 #define TXRX_CSR6                       0x3058
 337 #define TXRX_CSR7                       0x305c
 338 #define TXRX_CSR8                       0x3060
 339
 340 /*
 341  * TXRX_CSR9: Synchronization control register.
 342  * BEACON_INTERVAL: In unit of 1/16 TU.
 343  * TSF_TICKING: Enable TSF auto counting.
 344  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 345  * BEACON_GEN: Enable beacon generator.
 346  */
 347 #define TXRX_CSR9                       0x3064
 348 #define TXRX_CSR9_BEACON_INTERVAL       FIELD32(0x0000ffff)
 349 #define TXRX_CSR9_TSF_TICKING           FIELD32(0x00010000)
 350 #define TXRX_CSR9_TSF_SYNC              FIELD32(0x00060000)
 351 #define TXRX_CSR9_TBTT_ENABLE           FIELD32(0x00080000)
 352 #define TXRX_CSR9_BEACON_GEN            FIELD32(0x00100000)
 353 #define TXRX_CSR9_TIMESTAMP_COMPENSATE  FIELD32(0xff000000)
 354
 355 /*
 356  * TXRX_CSR10: BEACON alignment.
 357  */
 358 #define TXRX_CSR10                      0x3068
 359
 360 /*
 361  * TXRX_CSR11: AES mask.
 362  */
 363 #define TXRX_CSR11                      0x306c
 364
 365 /*
 366  * TXRX_CSR12: TSF low 32.
 367  */
 368 #define TXRX_CSR12                      0x3070
 369 #define TXRX_CSR12_LOW_TSFTIMER         FIELD32(0xffffffff)
 370
 371 /*
 372  * TXRX_CSR13: TSF high 32.
 373  */
 374 #define TXRX_CSR13                      0x3074
 375 #define TXRX_CSR13_HIGH_TSFTIMER        FIELD32(0xffffffff)
 376
 377 /*
 378  * TXRX_CSR14: TBTT timer.
 379  */
 380 #define TXRX_CSR14                      0x3078
 381
 382 /*
 383  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
 384  */
 385 #define TXRX_CSR15                      0x307c
 386
 387 /*
 388  * PHY control registers.
 389  * Some values are set in TU, whereas 1 TU == 1024 us.
 390  */
 391
 392 /*
 393  * PHY_CSR0: RF/PS control.
 394  */
 395 #define PHY_CSR0                        0x3080
 396 #define PHY_CSR0_PA_PE_BG               FIELD32(0x00010000)
 397 #define PHY_CSR0_PA_PE_A                FIELD32(0x00020000)
 398
 399 /*
 400  * PHY_CSR1
 401  */
 402 #define PHY_CSR1                        0x3084
 403 #define PHY_CSR1_RF_RPI                 FIELD32(0x00010000)
 404
 405
 406 /*
 407  * PHY_CSR2: Pre-TX BBP control.
 408  */
 409 #define PHY_CSR2                        0x3088
 410
 411 /*
 412  * PHY_CSR3: BBP serial control register.
 413  * VALUE: Register value to program into BBP.
 414  * REG_NUM: Selected BBP register.
 415  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
 416  * BUSY: 1: ASIC is busy execute BBP programming.
 417  */
 418 #define PHY_CSR3                        0x308c
 419 #define PHY_CSR3_VALUE                  FIELD32(0x000000ff)
 420 #define PHY_CSR3_REGNUM                 FIELD32(0x00007f00)
 421 #define PHY_CSR3_READ_CONTROL           FIELD32(0x00008000)
 422 #define PHY_CSR3_BUSY                   FIELD32(0x00010000)
 423
 424 /*
 425  * PHY_CSR4: RF serial control register
 426  * VALUE: Register value (include register id) serial out to RF/IF chip.
 427  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
 428  * IF_SELECT: 1: select IF to program, 0: select RF to program.
 429  * PLL_LD: RF PLL_LD status.
 430  * BUSY: 1: ASIC is busy execute RF programming.
 431  */
 432 #define PHY_CSR4                        0x3090
 433 #define PHY_CSR4_VALUE                  FIELD32(0x00ffffff)
 434 #define PHY_CSR4_NUMBER_OF_BITS         FIELD32(0x1f000000)
 435 #define PHY_CSR4_IF_SELECT              FIELD32(0x20000000)
 436 #define PHY_CSR4_PLL_LD                 FIELD32(0x40000000)
 437 #define PHY_CSR4_BUSY                   FIELD32(0x80000000)
 438
 439 /*
 440  * PHY_CSR5: RX to TX signal switch timing control.
 441  */
 442 #define PHY_CSR5                        0x3094
 443
 444 /*
 445  * PHY_CSR6: TX to RX signal timing control.
 446  */
 447 #define PHY_CSR6                        0x3098
 448
 449 /*
 450  * PHY_CSR7: TX DAC switching timing control.
 451  */
 452 #define PHY_CSR7                        0x309c
 453
 454 /*
 455  * Security control register.
 456  */
 457
 458 /*
 459  * SEC_CSR0: Shared key table control.
 460  */
 461 #define SEC_CSR0                        0x30a0
 462
 463 /*
 464  * SEC_CSR1: Shared key table security mode register.
 465  */
 466 #define SEC_CSR1                        0x30a4
 467 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 468 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 469 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 470 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 471 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 472 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 473 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 474 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 475
 476 /*
 477  * Pairwise key table valid bitmap registers.
 478  * SEC_CSR2: pairwise key table valid bitmap 0.
 479  * SEC_CSR3: pairwise key table valid bitmap 1.
 480  */
 481 #define SEC_CSR2                        0x30a8
 482 #define SEC_CSR3                        0x30ac
 483
 484 /*
 485  * SEC_CSR4: Pairwise key table lookup control.
 486  */
 487 #define SEC_CSR4                        0x30b0
 488
 489 /*
 490  * SEC_CSR5: shared key table security mode register.
 491  */
 492 #define SEC_CSR5                        0x30b4
 493 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 494 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 495 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 496 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 497 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 498 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 499 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 500 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 501
 502 /*
 503  * STA control registers.
 504  */
 505
 506 /*
 507  * STA_CSR0: RX PLCP error count & RX FCS error count.
 508  */
 509 #define STA_CSR0                        0x30c0
 510 #define STA_CSR0_FCS_ERROR              FIELD32(0x0000ffff)
 511 #define STA_CSR0_PLCP_ERROR             FIELD32(0xffff0000)
 512
 513 /*
 514  * STA_CSR1: RX False CCA count & RX LONG frame count.
 515  */
 516 #define STA_CSR1                        0x30c4
 517 #define STA_CSR1_PHYSICAL_ERROR         FIELD32(0x0000ffff)
 518 #define STA_CSR1_FALSE_CCA_ERROR        FIELD32(0xffff0000)
 519
 520 /*
 521  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
 522  */
 523 #define STA_CSR2                        0x30c8
 524 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
 525 #define STA_CSR2_RX_OVERFLOW_COUNT      FIELD32(0xffff0000)
 526
 527 /*
 528  * STA_CSR3: TX Beacon count.
 529  */
 530 #define STA_CSR3                        0x30cc
 531 #define STA_CSR3_TX_BEACON_COUNT        FIELD32(0x0000ffff)
 532
 533 /*
 534  * STA_CSR4: TX Retry count.
 535  */
 536 #define STA_CSR4                        0x30d0
 537 #define STA_CSR4_TX_NO_RETRY_COUNT      FIELD32(0x0000ffff)
 538 #define STA_CSR4_TX_ONE_RETRY_COUNT     FIELD32(0xffff0000)
 539
 540 /*
 541  * STA_CSR5: TX Retry count.
 542  */
 543 #define STA_CSR5                        0x30d4
 544 #define STA_CSR4_TX_MULTI_RETRY_COUNT   FIELD32(0x0000ffff)
 545 #define STA_CSR4_TX_RETRY_FAIL_COUNT    FIELD32(0xffff0000)
 546
 547 /*
 548  * QOS control registers.
 549  */
 550
 551 /*
 552  * QOS_CSR1: TXOP holder MAC address register.
 553  */
 554 #define QOS_CSR1                        0x30e4
 555 #define QOS_CSR1_BYTE4                  FIELD32(0x000000ff)
 556 #define QOS_CSR1_BYTE5                  FIELD32(0x0000ff00)
 557
 558 /*
 559  * QOS_CSR2: TXOP holder timeout register.
 560  */
 561 #define QOS_CSR2                        0x30e8
 562
 563 /*
 564  * RX QOS-CFPOLL MAC address register.
 565  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
 566  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
 567  */
 568 #define QOS_CSR3                        0x30ec
 569 #define QOS_CSR4                        0x30f0
 570
 571 /*
 572  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
 573  */
 574 #define QOS_CSR5                        0x30f4
 575
 576 /*
 577  * WMM Scheduler Register
 578  */
 579
 580 /*
 581  * AIFSN_CSR: AIFSN for each EDCA AC.
 582  * AIFSN0: For AC_BK.
 583  * AIFSN1: For AC_BE.
 584  * AIFSN2: For AC_VI.
 585  * AIFSN3: For AC_VO.
 586  */
 587 #define AIFSN_CSR                       0x0400
 588 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
 589 #define AIFSN_CSR_AIFSN1                FIELD32(0x000000f0)
 590 #define AIFSN_CSR_AIFSN2                FIELD32(0x00000f00)
 591 #define AIFSN_CSR_AIFSN3                FIELD32(0x0000f000)
 592
 593 /*
 594  * CWMIN_CSR: CWmin for each EDCA AC.
 595  * CWMIN0: For AC_BK.
 596  * CWMIN1: For AC_BE.
 597  * CWMIN2: For AC_VI.
 598  * CWMIN3: For AC_VO.
 599  */
 600 #define CWMIN_CSR                       0x0404
 601 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
 602 #define CWMIN_CSR_CWMIN1                FIELD32(0x000000f0)
 603 #define CWMIN_CSR_CWMIN2                FIELD32(0x00000f00)
 604 #define CWMIN_CSR_CWMIN3                FIELD32(0x0000f000)
 605
 606 /*
 607  * CWMAX_CSR: CWmax for each EDCA AC.
 608  * CWMAX0: For AC_BK.
 609  * CWMAX1: For AC_BE.
 610  * CWMAX2: For AC_VI.
 611  * CWMAX3: For AC_VO.
 612  */
 613 #define CWMAX_CSR                       0x0408
 614 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
 615 #define CWMAX_CSR_CWMAX1                FIELD32(0x000000f0)
 616 #define CWMAX_CSR_CWMAX2                FIELD32(0x00000f00)
 617 #define CWMAX_CSR_CWMAX3                FIELD32(0x0000f000)
 618
 619 /*
 620  * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
 621  * AC0_TX_OP: For AC_BK, in unit of 32us.
 622  * AC1_TX_OP: For AC_BE, in unit of 32us.
 623  */
 624 #define AC_TXOP_CSR0                    0x040c
 625 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
 626 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
 627
 628 /*
 629  * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
 630  * AC2_TX_OP: For AC_VI, in unit of 32us.
 631  * AC3_TX_OP: For AC_VO, in unit of 32us.
 632  */
 633 #define AC_TXOP_CSR1                    0x0410
 634 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
 635 #define AC_TXOP_CSR1_AC3_TX_OP          FIELD32(0xffff0000)
 636
 637 /*
 638  * RF registers
 639  */
 640 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 641 #define RF4_FREQ_OFFSET                 FIELD32(0x0003f000)
 642
 643 /*
 644  * EEPROM content.
 645  * The wordsize of the EEPROM is 16 bits.
 646  */
 647
 648 /*
 649  * HW MAC address.
 650  */
 651 #define EEPROM_MAC_ADDR_0               0x0002
 652 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 653 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
 654 #define EEPROM_MAC_ADDR1                0x0003
 655 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
 656 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
 657 #define EEPROM_MAC_ADDR_2               0x0004
 658 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
 659 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 660
 661 /*
 662  * EEPROM antenna.
 663  * ANTENNA_NUM: Number of antenna's.
 664  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 665  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 666  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
 667  * DYN_TXAGC: Dynamic TX AGC control.
 668  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 669  * RF_TYPE: Rf_type of this adapter.
 670  */
 671 #define EEPROM_ANTENNA                  0x0010
 672 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
 673 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
 674 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
 675 #define EEPROM_ANTENNA_FRAME_TYPE       FIELD16(0x0040)
 676 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
 677 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 678 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
 679
 680 /*
 681  * EEPROM NIC config.
 682  * EXTERNAL_LNA: External LNA.
 683  */
 684 #define EEPROM_NIC                      0x0011
 685 #define EEPROM_NIC_EXTERNAL_LNA         FIELD16(0x0010)
 686
 687 /*
 688  * EEPROM geography.
 689  * GEO_A: Default geographical setting for 5GHz band
 690  * GEO: Default geographical setting.
 691  */
 692 #define EEPROM_GEOGRAPHY                0x0012
 693 #define EEPROM_GEOGRAPHY_GEO_A          FIELD16(0x00ff)
 694 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0xff00)
 695
 696 /*
 697  * EEPROM BBP.
 698  */
 699 #define EEPROM_BBP_START                0x0013
 700 #define EEPROM_BBP_SIZE                 16
 701 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
 702 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
 703
 704 /*
 705  * EEPROM TXPOWER 802.11G
 706  */
 707 #define EEPROM_TXPOWER_G_START          0x0023
 708 #define EEPROM_TXPOWER_G_SIZE           7
 709 #define EEPROM_TXPOWER_G_1              FIELD16(0x00ff)
 710 #define EEPROM_TXPOWER_G_2              FIELD16(0xff00)
 711
 712 /*
 713  * EEPROM Frequency
 714  */
 715 #define EEPROM_FREQ                     0x002f
 716 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
 717 #define EEPROM_FREQ_SEQ_MASK            FIELD16(0xff00)
 718 #define EEPROM_FREQ_SEQ                 FIELD16(0x0300)
 719
 720 /*
 721  * EEPROM LED.
 722  * POLARITY_RDY_G: Polarity RDY_G setting.
 723  * POLARITY_RDY_A: Polarity RDY_A setting.
 724  * POLARITY_ACT: Polarity ACT setting.
 725  * POLARITY_GPIO_0: Polarity GPIO0 setting.
 726  * POLARITY_GPIO_1: Polarity GPIO1 setting.
 727  * POLARITY_GPIO_2: Polarity GPIO2 setting.
 728  * POLARITY_GPIO_3: Polarity GPIO3 setting.
 729  * POLARITY_GPIO_4: Polarity GPIO4 setting.
 730  * LED_MODE: Led mode.
 731  */
 732 #define EEPROM_LED                      0x0030
 733 #define EEPROM_LED_POLARITY_RDY_G       FIELD16(0x0001)
 734 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
 735 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
 736 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
 737 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
 738 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
 739 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
 740 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
 741 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
 742
 743 /*
 744  * EEPROM TXPOWER 802.11A
 745  */
 746 #define EEPROM_TXPOWER_A_START          0x0031
 747 #define EEPROM_TXPOWER_A_SIZE           12
 748 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
 749 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
 750
 751 /*
 752  * BBP content.
 753  * The wordsize of the BBP is 8 bits.
 754  */
 755
 756 /*
 757  * BBP_R2
 758  */
 759 #define BBP_R2_BG_MODE                  FIELD8(0x20)
 760
 761 /*
 762  * BBP_R3
 763  */
 764 #define BBP_R3_SMART_MODE               FIELD8(0x01)
 765
 766 /*
 767  * BBP_R4: RX antenna control
 768  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
 769  */
 770 #define BBP_R4_RX_ANTENNA               FIELD8(0x03)
 771 #define BBP_R4_RX_FRAME_END             FIELD8(0x10)
 772 #define BBP_R4_RX_BG_MODE               FIELD8(0x20)
 773
 774 /*
 775  * BBP_R77
 776  */
 777 #define BBP_R77_PAIR                    FIELD8(0x03)
 778
 779 /*
 780  * DMA descriptor defines.
 781  */
 782 #define TXD_DESC_SIZE                   ( 6 * sizeof(struct data_desc) )
 783 #define RXD_DESC_SIZE                   ( 6 * sizeof(struct data_desc) )
 784
 785 /*
 786  * TX descriptor format for TX, PRIO and Beacon Ring.
 787  */
 788
 789 /*
 790  * Word0
 791  * BURST: Next frame belongs to same "burst" event.
 792  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
 793  * KEY_TABLE: Use per-client pairwise KEY table.
 794  * KEY_INDEX:
 795  * Key index (0~31) to the pairwise KEY table.
 796  * 0~3 to shared KEY table 0 (BSS0).
 797  * 4~7 to shared KEY table 1 (BSS1).
 798  * 8~11 to shared KEY table 2 (BSS2).
 799  * 12~15 to shared KEY table 3 (BSS3).
 800  * BURST2: For backward compatibility, set to same value as BURST.
 801  */
 802 #define TXD_W0_BURST                    FIELD32(0x00000001)
 803 #define TXD_W0_VALID                    FIELD32(0x00000002)
 804 #define TXD_W0_MORE_FRAG                FIELD32(0x00000004)
 805 #define TXD_W0_ACK                      FIELD32(0x00000008)
 806 #define TXD_W0_TIMESTAMP                FIELD32(0x00000010)
 807 #define TXD_W0_OFDM                     FIELD32(0x00000020)
 808 #define TXD_W0_IFS                      FIELD32(0x00000040)
 809 #define TXD_W0_RETRY_MODE               FIELD32(0x00000080)
 810 #define TXD_W0_TKIP_MIC                 FIELD32(0x00000100)
 811 #define TXD_W0_KEY_TABLE                FIELD32(0x00000200)
 812 #define TXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
 813 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 814 #define TXD_W0_BURST2                   FIELD32(0x10000000)
 815 #define TXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
 816
 817 /*
 818  * Word1
 819  * HOST_Q_ID: EDCA/HCCA queue ID.
 820  * HW_SEQUENCE: MAC overwrites the frame sequence number.
 821  * BUFFER_COUNT: Number of buffers in this TXD.
 822  */
 823 #define TXD_W1_HOST_Q_ID                FIELD32(0x0000000f)
 824 #define TXD_W1_AIFSN                    FIELD32(0x000000f0)
 825 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
 826 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
 827 #define TXD_W1_IV_OFFSET                FIELD32(0x003f0000)
 828 #define TXD_W1_HW_SEQUENCE              FIELD32(0x10000000)
 829 #define TXD_W1_BUFFER_COUNT             FIELD32(0xe0000000)
 830
 831 /*
 832  * Word2: PLCP information
 833  */
 834 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
 835 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
 836 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
 837 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
 838
 839 /*
 840  * Word3
 841  */
 842 #define TXD_W3_IV                       FIELD32(0xffffffff)
 843
 844 /*
 845  * Word4
 846  */
 847 #define TXD_W4_EIV                      FIELD32(0xffffffff)
 848
 849 /*
 850  * Word5
 851  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
 852  * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
 853  * WAITING_DMA_DONE_INT: TXD been filled with data
 854  * and waiting for TxDoneISR housekeeping.
 855  */
 856 #define TXD_W5_FRAME_OFFSET             FIELD32(0x000000ff)
 857 #define TXD_W5_PACKET_ID                FIELD32(0x0000ff00)
 858 #define TXD_W5_TX_POWER                 FIELD32(0x00ff0000)
 859 #define TXD_W5_WAITING_DMA_DONE_INT     FIELD32(0x01000000)
 860
 861 /*
 862  * RX descriptor format for RX Ring.
 863  */
 864
 865 /*
 866  * Word0
 867  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
 868  * KEY_INDEX: Decryption key actually used.
 869  */
 870 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
 871 #define RXD_W0_DROP                     FIELD32(0x00000002)
 872 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000004)
 873 #define RXD_W0_MULTICAST                FIELD32(0x00000008)
 874 #define RXD_W0_BROADCAST                FIELD32(0x00000010)
 875 #define RXD_W0_MY_BSS                   FIELD32(0x00000020)
 876 #define RXD_W0_CRC                      FIELD32(0x00000040)
 877 #define RXD_W0_OFDM                     FIELD32(0x00000080)
 878 #define RXD_W0_CIPHER_ERROR             FIELD32(0x00000300)
 879 #define RXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
 880 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 881 #define RXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
 882
 883 /*
 884  * WORD1
 885  * SIGNAL: RX raw data rate reported by BBP.
 886  * RSSI: RSSI reported by BBP.
 887  */
 888 #define RXD_W1_SIGNAL                   FIELD32(0x000000ff)
 889 #define RXD_W1_RSSI                     FIELD32(0x0000ff00)
 890 #define RXD_W1_FRAME_OFFSET             FIELD32(0x7f000000)
 891
 892 /*
 893  * Word2
 894  * IV: Received IV of originally encrypted.
 895  */
 896 #define RXD_W2_IV                       FIELD32(0xffffffff)
 897
 898 /*
 899  * Word3
 900  * EIV: Received EIV of originally encrypted.
 901  */
 902 #define RXD_W3_EIV                      FIELD32(0xffffffff)
 903
 904 /*
 905  * Word4
 906  */
 907 #define RXD_W4_RESERVED                 FIELD32(0xffffffff)
 908
 909 /*
 910  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
 911  * and passed to the HOST driver.
 912  * The following fields are for DMA block and HOST usage only.
 913  * Can't be touched by ASIC MAC block.
 914  */
 915
 916 /*
 917  * Word5
 918  */
 919 #define RXD_W5_RESERVED                 FIELD32(0xffffffff)
 920
 921 /*
 922  * Macro's for converting txpower from EEPROM to dscape value
 923  * and from dscape value to register value.
 924  */
 925 #define MIN_TXPOWER     0
 926 #define MAX_TXPOWER     31
 927 #define DEFAULT_TXPOWER 24
 928
 929 #define TXPOWER_FROM_DEV(__txpower)             \
 930 ({                                              \
 931         ((__txpower) > MAX_TXPOWER) ?           \
 932                 DEFAULT_TXPOWER : (__txpower);  \
 933 })
 934
 935 #define TXPOWER_TO_DEV(__txpower)                       \
 936 ({                                                      \
 937         ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :    \
 938         (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :   \
 939         (__txpower));                                   \
 940 })
 941
 942 /*
 943  * Interrupt functions.
 944  */
 945 static void rt73usb_interrupt_rxdone(struct urb *urb);
 946
 947 #endif /* RT73USB_H */