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[openwrt.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/if.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/list.h>
21 #include <linux/if_ether.h>
22 #include <linux/skbuff.h>
23 #include <linux/netdevice.h>
24 #include <linux/netlink.h>
25 #include <linux/bitops.h>
26 #include <net/genetlink.h>
27 #include <linux/switch.h>
28 #include <linux/delay.h>
29 #include <linux/phy.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/lockdep.h>
33 #include "ar8216.h"
34
35 /* size of the vlan table */
36 #define AR8X16_MAX_VLANS 128
37 #define AR8X16_PROBE_RETRIES 10
38
39 struct ar8216_priv;
40
41 #define AR8XXX_CAP_GIGE BIT(0)
42
43 struct ar8xxx_chip {
44 unsigned long caps;
45
46 int (*hw_init)(struct ar8216_priv *priv);
47 void (*init_globals)(struct ar8216_priv *priv);
48 void (*init_port)(struct ar8216_priv *priv, int port);
49 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
50 u32 ingress, u32 members, u32 pvid);
51 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
52 int (*atu_flush)(struct ar8216_priv *priv);
53 void (*vtu_flush)(struct ar8216_priv *priv);
54 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
55 };
56
57 struct ar8216_priv {
58 struct switch_dev dev;
59 struct phy_device *phy;
60 u32 (*read)(struct ar8216_priv *priv, int reg);
61 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
62 const struct net_device_ops *ndo_old;
63 struct net_device_ops ndo;
64 struct mutex reg_mutex;
65 int chip_type;
66 const struct ar8xxx_chip *chip;
67 bool initialized;
68 bool port4_phy;
69 char buf[80];
70
71 bool init;
72
73 /* all fields below are cleared on reset */
74 bool vlan;
75 u16 vlan_id[AR8X16_MAX_VLANS];
76 u8 vlan_table[AR8X16_MAX_VLANS];
77 u8 vlan_tagged;
78 u16 pvid[AR8216_NUM_PORTS];
79 };
80
81 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
82
83 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
84 {
85 return priv->chip->caps & AR8XXX_CAP_GIGE;
86 }
87
88 static inline void
89 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
90 {
91 regaddr >>= 1;
92 *r1 = regaddr & 0x1e;
93
94 regaddr >>= 5;
95 *r2 = regaddr & 0x7;
96
97 regaddr >>= 3;
98 *page = regaddr & 0x1ff;
99 }
100
101 static u32
102 ar8216_mii_read(struct ar8216_priv *priv, int reg)
103 {
104 struct phy_device *phy = priv->phy;
105 struct mii_bus *bus = phy->bus;
106 u16 r1, r2, page;
107 u16 lo, hi;
108
109 split_addr((u32) reg, &r1, &r2, &page);
110
111 mutex_lock(&bus->mdio_lock);
112
113 bus->write(bus, 0x18, 0, page);
114 usleep_range(1000, 2000); /* wait for the page switch to propagate */
115 lo = bus->read(bus, 0x10 | r2, r1);
116 hi = bus->read(bus, 0x10 | r2, r1 + 1);
117
118 mutex_unlock(&bus->mdio_lock);
119
120 return (hi << 16) | lo;
121 }
122
123 static void
124 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
125 {
126 struct phy_device *phy = priv->phy;
127 struct mii_bus *bus = phy->bus;
128 u16 r1, r2, r3;
129 u16 lo, hi;
130
131 split_addr((u32) reg, &r1, &r2, &r3);
132 lo = val & 0xffff;
133 hi = (u16) (val >> 16);
134
135 mutex_lock(&bus->mdio_lock);
136
137 bus->write(bus, 0x18, 0, r3);
138 usleep_range(1000, 2000); /* wait for the page switch to propagate */
139 bus->write(bus, 0x10 | r2, r1 + 1, hi);
140 bus->write(bus, 0x10 | r2, r1, lo);
141
142 mutex_unlock(&bus->mdio_lock);
143 }
144
145 static void
146 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
147 u16 dbg_addr, u16 dbg_data)
148 {
149 struct mii_bus *bus = priv->phy->bus;
150
151 mutex_lock(&bus->mdio_lock);
152 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
153 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
154 mutex_unlock(&bus->mdio_lock);
155 }
156
157 static u32
158 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
159 {
160 u32 v;
161
162 lockdep_assert_held(&priv->reg_mutex);
163
164 v = priv->read(priv, reg);
165 v &= ~mask;
166 v |= val;
167 priv->write(priv, reg, v);
168
169 return v;
170 }
171
172 static void
173 ar8216_read_port_link(struct ar8216_priv *priv, int port,
174 struct switch_port_link *link)
175 {
176 u32 status;
177 u32 speed;
178
179 memset(link, '\0', sizeof(*link));
180
181 status = priv->chip->read_port_status(priv, port);
182
183 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
184 if (link->aneg) {
185 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
186 if (!link->link)
187 return;
188 } else {
189 link->link = true;
190 }
191
192 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
193 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
194 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
195
196 speed = (status & AR8216_PORT_STATUS_SPEED) >>
197 AR8216_PORT_STATUS_SPEED_S;
198
199 switch (speed) {
200 case AR8216_PORT_SPEED_10M:
201 link->speed = SWITCH_PORT_SPEED_10;
202 break;
203 case AR8216_PORT_SPEED_100M:
204 link->speed = SWITCH_PORT_SPEED_100;
205 break;
206 case AR8216_PORT_SPEED_1000M:
207 link->speed = SWITCH_PORT_SPEED_1000;
208 break;
209 default:
210 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
211 break;
212 }
213 }
214
215 static int
216 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
217 struct switch_val *val)
218 {
219 struct ar8216_priv *priv = to_ar8216(dev);
220 priv->vlan = !!val->value.i;
221 return 0;
222 }
223
224 static int
225 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
226 struct switch_val *val)
227 {
228 struct ar8216_priv *priv = to_ar8216(dev);
229 val->value.i = priv->vlan;
230 return 0;
231 }
232
233
234 static int
235 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
236 {
237 struct ar8216_priv *priv = to_ar8216(dev);
238
239 /* make sure no invalid PVIDs get set */
240
241 if (vlan >= dev->vlans)
242 return -EINVAL;
243
244 priv->pvid[port] = vlan;
245 return 0;
246 }
247
248 static int
249 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
250 {
251 struct ar8216_priv *priv = to_ar8216(dev);
252 *vlan = priv->pvid[port];
253 return 0;
254 }
255
256 static int
257 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
258 struct switch_val *val)
259 {
260 struct ar8216_priv *priv = to_ar8216(dev);
261 priv->vlan_id[val->port_vlan] = val->value.i;
262 return 0;
263 }
264
265 static int
266 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
267 struct switch_val *val)
268 {
269 struct ar8216_priv *priv = to_ar8216(dev);
270 val->value.i = priv->vlan_id[val->port_vlan];
271 return 0;
272 }
273
274 static int
275 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
276 struct switch_port_link *link)
277 {
278 struct ar8216_priv *priv = to_ar8216(dev);
279
280 ar8216_read_port_link(priv, port, link);
281 return 0;
282 }
283
284 static int
285 ar8216_mangle_tx(struct sk_buff *skb, struct net_device *dev)
286 {
287 struct ar8216_priv *priv = dev->phy_ptr;
288 unsigned char *buf;
289
290 if (unlikely(!priv))
291 goto error;
292
293 if (!priv->vlan)
294 goto send;
295
296 if (unlikely(skb_headroom(skb) < 2)) {
297 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
298 goto error;
299 }
300
301 buf = skb_push(skb, 2);
302 buf[0] = 0x10;
303 buf[1] = 0x80;
304
305 send:
306 return priv->ndo_old->ndo_start_xmit(skb, dev);
307
308 error:
309 dev_kfree_skb_any(skb);
310 return 0;
311 }
312
313 static int
314 ar8216_mangle_rx(struct sk_buff *skb, int napi)
315 {
316 struct ar8216_priv *priv;
317 struct net_device *dev;
318 unsigned char *buf;
319 int port, vlan;
320
321 dev = skb->dev;
322 if (!dev)
323 goto error;
324
325 priv = dev->phy_ptr;
326 if (!priv)
327 goto error;
328
329 /* don't strip the header if vlan mode is disabled */
330 if (!priv->vlan)
331 goto recv;
332
333 /* strip header, get vlan id */
334 buf = skb->data;
335 skb_pull(skb, 2);
336
337 /* check for vlan header presence */
338 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
339 goto recv;
340
341 port = buf[0] & 0xf;
342
343 /* no need to fix up packets coming from a tagged source */
344 if (priv->vlan_tagged & (1 << port))
345 goto recv;
346
347 /* lookup port vid from local table, the switch passes an invalid vlan id */
348 vlan = priv->vlan_id[priv->pvid[port]];
349
350 buf[14 + 2] &= 0xf0;
351 buf[14 + 2] |= vlan >> 8;
352 buf[15 + 2] = vlan & 0xff;
353
354 recv:
355 skb->protocol = eth_type_trans(skb, skb->dev);
356
357 if (napi)
358 return netif_receive_skb(skb);
359 else
360 return netif_rx(skb);
361
362 error:
363 /* no vlan? eat the packet! */
364 dev_kfree_skb_any(skb);
365 return NET_RX_DROP;
366 }
367
368 static int
369 ar8216_netif_rx(struct sk_buff *skb)
370 {
371 return ar8216_mangle_rx(skb, 0);
372 }
373
374 static int
375 ar8216_netif_receive_skb(struct sk_buff *skb)
376 {
377 return ar8216_mangle_rx(skb, 1);
378 }
379
380
381 static struct switch_attr ar8216_globals[] = {
382 {
383 .type = SWITCH_TYPE_INT,
384 .name = "enable_vlan",
385 .description = "Enable VLAN mode",
386 .set = ar8216_sw_set_vlan,
387 .get = ar8216_sw_get_vlan,
388 .max = 1
389 },
390 };
391
392 static struct switch_attr ar8216_port[] = {
393 };
394
395 static struct switch_attr ar8216_vlan[] = {
396 {
397 .type = SWITCH_TYPE_INT,
398 .name = "vid",
399 .description = "VLAN ID (0-4094)",
400 .set = ar8216_sw_set_vid,
401 .get = ar8216_sw_get_vid,
402 .max = 4094,
403 },
404 };
405
406
407 static int
408 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
409 {
410 struct ar8216_priv *priv = to_ar8216(dev);
411 u8 ports = priv->vlan_table[val->port_vlan];
412 int i;
413
414 val->len = 0;
415 for (i = 0; i < dev->ports; i++) {
416 struct switch_port *p;
417
418 if (!(ports & (1 << i)))
419 continue;
420
421 p = &val->value.ports[val->len++];
422 p->id = i;
423 if (priv->vlan_tagged & (1 << i))
424 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
425 else
426 p->flags = 0;
427 }
428 return 0;
429 }
430
431 static int
432 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
433 {
434 struct ar8216_priv *priv = to_ar8216(dev);
435 u8 *vt = &priv->vlan_table[val->port_vlan];
436 int i, j;
437
438 *vt = 0;
439 for (i = 0; i < val->len; i++) {
440 struct switch_port *p = &val->value.ports[i];
441
442 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
443 priv->vlan_tagged |= (1 << p->id);
444 } else {
445 priv->vlan_tagged &= ~(1 << p->id);
446 priv->pvid[p->id] = val->port_vlan;
447
448 /* make sure that an untagged port does not
449 * appear in other vlans */
450 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
451 if (j == val->port_vlan)
452 continue;
453 priv->vlan_table[j] &= ~(1 << p->id);
454 }
455 }
456
457 *vt |= 1 << p->id;
458 }
459 return 0;
460 }
461
462 static int
463 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
464 {
465 int timeout = 20;
466 u32 t = 0;
467
468 while (1) {
469 t = priv->read(priv, reg);
470 if ((t & mask) == val)
471 return 0;
472
473 if (timeout-- <= 0)
474 break;
475
476 udelay(10);
477 }
478
479 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
480 (unsigned int) reg, t, mask, val);
481 return -ETIMEDOUT;
482 }
483
484 static void
485 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
486 {
487 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
488 return;
489 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
490 val &= AR8216_VTUDATA_MEMBER;
491 val |= AR8216_VTUDATA_VALID;
492 priv->write(priv, AR8216_REG_VTU_DATA, val);
493 }
494 op |= AR8216_VTU_ACTIVE;
495 priv->write(priv, AR8216_REG_VTU, op);
496 }
497
498 static void
499 ar8216_vtu_flush(struct ar8216_priv *priv)
500 {
501 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
502 }
503
504 static void
505 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
506 {
507 u32 op;
508
509 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
510 ar8216_vtu_op(priv, op, port_mask);
511 }
512
513 static int
514 ar8216_atu_flush(struct ar8216_priv *priv)
515 {
516 int ret;
517
518 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
519 if (!ret)
520 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
521
522 return ret;
523 }
524
525 static u32
526 ar8216_read_port_status(struct ar8216_priv *priv, int port)
527 {
528 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
529 }
530
531 static void
532 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
533 u32 members, u32 pvid)
534 {
535 u32 header;
536
537 if (priv->vlan && port == AR8216_PORT_CPU && priv->chip_type == AR8216)
538 header = AR8216_PORT_CTRL_HEADER;
539 else
540 header = 0;
541
542 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
543 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
544 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
545 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
546 AR8216_PORT_CTRL_LEARN | header |
547 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
548 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
549
550 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
551 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
552 AR8216_PORT_VLAN_DEFAULT_ID,
553 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
554 (ingress << AR8216_PORT_VLAN_MODE_S) |
555 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
556 }
557
558 static void
559 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
560 u32 members, u32 pvid)
561 {
562 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
563 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
564 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
565 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
566 AR8216_PORT_CTRL_LEARN |
567 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
568 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
569
570 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
571 AR8236_PORT_VLAN_DEFAULT_ID,
572 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
573
574 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
575 AR8236_PORT_VLAN2_VLAN_MODE |
576 AR8236_PORT_VLAN2_MEMBER,
577 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
578 (members << AR8236_PORT_VLAN2_MEMBER_S));
579 }
580
581 static int
582 ar8216_sw_hw_apply(struct switch_dev *dev)
583 {
584 struct ar8216_priv *priv = to_ar8216(dev);
585 u8 portmask[AR8216_NUM_PORTS];
586 int i, j;
587
588 mutex_lock(&priv->reg_mutex);
589 /* flush all vlan translation unit entries */
590 priv->chip->vtu_flush(priv);
591
592 memset(portmask, 0, sizeof(portmask));
593 if (!priv->init) {
594 /* calculate the port destination masks and load vlans
595 * into the vlan translation unit */
596 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
597 u8 vp = priv->vlan_table[j];
598
599 if (!vp)
600 continue;
601
602 for (i = 0; i < dev->ports; i++) {
603 u8 mask = (1 << i);
604 if (vp & mask)
605 portmask[i] |= vp & ~mask;
606 }
607
608 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
609 priv->vlan_table[j]);
610 }
611 } else {
612 /* vlan disabled:
613 * isolate all ports, but connect them to the cpu port */
614 for (i = 0; i < dev->ports; i++) {
615 if (i == AR8216_PORT_CPU)
616 continue;
617
618 portmask[i] = 1 << AR8216_PORT_CPU;
619 portmask[AR8216_PORT_CPU] |= (1 << i);
620 }
621 }
622
623 /* update the port destination mask registers and tag settings */
624 for (i = 0; i < dev->ports; i++) {
625 int egress, ingress;
626 int pvid;
627
628 if (priv->vlan) {
629 pvid = priv->vlan_id[priv->pvid[i]];
630 if (priv->vlan_tagged & (1 << i))
631 egress = AR8216_OUT_ADD_VLAN;
632 else
633 egress = AR8216_OUT_STRIP_VLAN;
634 ingress = AR8216_IN_SECURE;
635 } else {
636 pvid = i;
637 egress = AR8216_OUT_KEEP;
638 ingress = AR8216_IN_PORT_ONLY;
639 }
640
641 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
642 pvid);
643 }
644 mutex_unlock(&priv->reg_mutex);
645 return 0;
646 }
647
648 static int
649 ar8216_hw_init(struct ar8216_priv *priv)
650 {
651 return 0;
652 }
653
654 static int
655 ar8236_hw_init(struct ar8216_priv *priv)
656 {
657 int i;
658 struct mii_bus *bus;
659
660 if (priv->initialized)
661 return 0;
662
663 /* Initialize the PHYs */
664 bus = priv->phy->bus;
665 for (i = 0; i < 5; i++) {
666 mdiobus_write(bus, i, MII_ADVERTISE,
667 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
668 ADVERTISE_PAUSE_ASYM);
669 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
670 }
671 msleep(1000);
672
673 priv->initialized = true;
674 return 0;
675 }
676
677 static int
678 ar8316_hw_init(struct ar8216_priv *priv)
679 {
680 int i;
681 u32 val, newval;
682 struct mii_bus *bus;
683
684 val = priv->read(priv, 0x8);
685
686 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
687 if (priv->port4_phy) {
688 /* value taken from Ubiquiti RouterStation Pro */
689 newval = 0x81461bea;
690 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
691 } else {
692 newval = 0x01261be2;
693 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
694 }
695 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
696 /* value taken from AVM Fritz!Box 7390 sources */
697 newval = 0x010e5b71;
698 } else {
699 /* no known value for phy interface */
700 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
701 priv->phy->interface);
702 return -EINVAL;
703 }
704
705 if (val == newval)
706 goto out;
707
708 priv->write(priv, 0x8, newval);
709
710 /* Initialize the ports */
711 bus = priv->phy->bus;
712 for (i = 0; i < 5; i++) {
713 if ((i == 4) && priv->port4_phy &&
714 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
715 /* work around for phy4 rgmii mode */
716 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
717 /* rx delay */
718 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
719 /* tx delay */
720 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
721 msleep(1000);
722 }
723
724 /* initialize the port itself */
725 mdiobus_write(bus, i, MII_ADVERTISE,
726 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
727 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
728 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
729 msleep(1000);
730 }
731
732 out:
733 priv->initialized = true;
734 return 0;
735 }
736
737 static void
738 ar8216_init_globals(struct ar8216_priv *priv)
739 {
740 /* standard atheros magic */
741 priv->write(priv, 0x38, 0xc000050e);
742
743 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
744 AR8216_GCTRL_MTU, 1518 + 8 + 2);
745 }
746
747 static void
748 ar8236_init_globals(struct ar8216_priv *priv)
749 {
750 /* enable jumbo frames */
751 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
752 AR8316_GCTRL_MTU, 9018 + 8 + 2);
753 }
754
755 static void
756 ar8316_init_globals(struct ar8216_priv *priv)
757 {
758 /* standard atheros magic */
759 priv->write(priv, 0x38, 0xc000050e);
760
761 /* enable cpu port to receive multicast and broadcast frames */
762 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
763
764 /* enable jumbo frames */
765 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
766 AR8316_GCTRL_MTU, 9018 + 8 + 2);
767 }
768
769 static void
770 ar8216_init_port(struct ar8216_priv *priv, int port)
771 {
772 /* Enable port learning and tx */
773 priv->write(priv, AR8216_REG_PORT_CTRL(port),
774 AR8216_PORT_CTRL_LEARN |
775 (4 << AR8216_PORT_CTRL_STATE_S));
776
777 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
778
779 if (port == AR8216_PORT_CPU) {
780 priv->write(priv, AR8216_REG_PORT_STATUS(port),
781 AR8216_PORT_STATUS_LINK_UP |
782 ar8xxx_has_gige(priv) ? AR8216_PORT_SPEED_1000M :
783 AR8216_PORT_SPEED_100M |
784 AR8216_PORT_STATUS_TXMAC |
785 AR8216_PORT_STATUS_RXMAC |
786 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
787 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
788 AR8216_PORT_STATUS_DUPLEX);
789 } else {
790 priv->write(priv, AR8216_REG_PORT_STATUS(port),
791 AR8216_PORT_STATUS_LINK_AUTO);
792 }
793 }
794
795 static const struct ar8xxx_chip ar8216_chip = {
796 .hw_init = ar8216_hw_init,
797 .init_globals = ar8216_init_globals,
798 .init_port = ar8216_init_port,
799 .setup_port = ar8216_setup_port,
800 .read_port_status = ar8216_read_port_status,
801 .atu_flush = ar8216_atu_flush,
802 .vtu_flush = ar8216_vtu_flush,
803 .vtu_load_vlan = ar8216_vtu_load_vlan,
804 };
805
806 static const struct ar8xxx_chip ar8236_chip = {
807 .hw_init = ar8236_hw_init,
808 .init_globals = ar8236_init_globals,
809 .init_port = ar8216_init_port,
810 .setup_port = ar8236_setup_port,
811 .read_port_status = ar8216_read_port_status,
812 .atu_flush = ar8216_atu_flush,
813 .vtu_flush = ar8216_vtu_flush,
814 .vtu_load_vlan = ar8216_vtu_load_vlan,
815 };
816
817 static const struct ar8xxx_chip ar8316_chip = {
818 .caps = AR8XXX_CAP_GIGE,
819 .hw_init = ar8316_hw_init,
820 .init_globals = ar8316_init_globals,
821 .init_port = ar8216_init_port,
822 .setup_port = ar8216_setup_port,
823 .read_port_status = ar8216_read_port_status,
824 .atu_flush = ar8216_atu_flush,
825 .vtu_flush = ar8216_vtu_flush,
826 .vtu_load_vlan = ar8216_vtu_load_vlan,
827 };
828
829 static int
830 ar8216_sw_reset_switch(struct switch_dev *dev)
831 {
832 struct ar8216_priv *priv = to_ar8216(dev);
833 int i;
834
835 mutex_lock(&priv->reg_mutex);
836 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
837 offsetof(struct ar8216_priv, vlan));
838
839 for (i = 0; i < AR8X16_MAX_VLANS; i++)
840 priv->vlan_id[i] = i;
841
842 /* Configure all ports */
843 for (i = 0; i < dev->ports; i++)
844 priv->chip->init_port(priv, i);
845
846 priv->chip->init_globals(priv);
847 mutex_unlock(&priv->reg_mutex);
848
849 return ar8216_sw_hw_apply(dev);
850 }
851
852 static const struct switch_dev_ops ar8216_sw_ops = {
853 .attr_global = {
854 .attr = ar8216_globals,
855 .n_attr = ARRAY_SIZE(ar8216_globals),
856 },
857 .attr_port = {
858 .attr = ar8216_port,
859 .n_attr = ARRAY_SIZE(ar8216_port),
860 },
861 .attr_vlan = {
862 .attr = ar8216_vlan,
863 .n_attr = ARRAY_SIZE(ar8216_vlan),
864 },
865 .get_port_pvid = ar8216_sw_get_pvid,
866 .set_port_pvid = ar8216_sw_set_pvid,
867 .get_vlan_ports = ar8216_sw_get_ports,
868 .set_vlan_ports = ar8216_sw_set_ports,
869 .apply_config = ar8216_sw_hw_apply,
870 .reset_switch = ar8216_sw_reset_switch,
871 .get_port_link = ar8216_sw_get_port_link,
872 };
873
874 static int
875 ar8216_id_chip(struct ar8216_priv *priv)
876 {
877 u32 val;
878 u16 id;
879 int i;
880
881 priv->chip_type = UNKNOWN;
882
883 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
884 if (val == ~0)
885 return -ENODEV;
886
887 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
888 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
889 u16 t;
890
891 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
892 if (val == ~0)
893 return -ENODEV;
894
895 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
896 if (t != id)
897 return -ENODEV;
898 }
899
900 switch (id) {
901 case 0x0101:
902 priv->chip_type = AR8216;
903 priv->chip = &ar8216_chip;
904 break;
905 case 0x0301:
906 priv->chip_type = AR8236;
907 priv->chip = &ar8236_chip;
908 break;
909 case 0x1000:
910 case 0x1001:
911 priv->chip_type = AR8316;
912 priv->chip = &ar8316_chip;
913 break;
914 default:
915 printk(KERN_DEBUG
916 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
917 (int)(id >> AR8216_CTRL_VERSION_S),
918 (int)(id & AR8216_CTRL_REVISION),
919 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
920 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
921
922 return -ENODEV;
923 }
924
925 return 0;
926 }
927
928 static int
929 ar8216_config_init(struct phy_device *pdev)
930 {
931 struct ar8216_priv *priv = pdev->priv;
932 struct net_device *dev = pdev->attached_dev;
933 struct switch_dev *swdev;
934 int ret;
935
936 if (!priv) {
937 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
938 if (priv == NULL)
939 return -ENOMEM;
940 }
941
942 priv->phy = pdev;
943
944 ret = ar8216_id_chip(priv);
945 if (ret)
946 goto err_free_priv;
947
948 if (pdev->addr != 0) {
949 if (ar8xxx_has_gige(priv)) {
950 pdev->supported |= SUPPORTED_1000baseT_Full;
951 pdev->advertising |= ADVERTISED_1000baseT_Full;
952 }
953
954 if (priv->chip_type == AR8316) {
955 /* check if we're attaching to the switch twice */
956 pdev = pdev->bus->phy_map[0];
957 if (!pdev) {
958 kfree(priv);
959 return 0;
960 }
961
962 /* switch device has not been initialized, reuse priv */
963 if (!pdev->priv) {
964 priv->port4_phy = true;
965 pdev->priv = priv;
966 return 0;
967 }
968
969 kfree(priv);
970
971 /* switch device has been initialized, reinit */
972 priv = pdev->priv;
973 priv->dev.ports = (AR8216_NUM_PORTS - 1);
974 priv->initialized = false;
975 priv->port4_phy = true;
976 ar8316_hw_init(priv);
977 return 0;
978 }
979
980 kfree(priv);
981 return 0;
982 }
983
984 printk(KERN_INFO "%s: AR%d switch driver attached.\n",
985 pdev->attached_dev->name, priv->chip_type);
986
987 if (ar8xxx_has_gige(priv))
988 pdev->supported = SUPPORTED_1000baseT_Full;
989 else
990 pdev->supported = SUPPORTED_100baseT_Full;
991 pdev->advertising = pdev->supported;
992
993 mutex_init(&priv->reg_mutex);
994 priv->read = ar8216_mii_read;
995 priv->write = ar8216_mii_write;
996
997 pdev->priv = priv;
998
999 swdev = &priv->dev;
1000 swdev->cpu_port = AR8216_PORT_CPU;
1001 swdev->ops = &ar8216_sw_ops;
1002 swdev->ports = AR8216_NUM_PORTS;
1003
1004 if (priv->chip_type == AR8316) {
1005 swdev->name = "Atheros AR8316";
1006 swdev->vlans = AR8X16_MAX_VLANS;
1007
1008 if (priv->port4_phy) {
1009 /* port 5 connected to the other mac, therefore unusable */
1010 swdev->ports = (AR8216_NUM_PORTS - 1);
1011 }
1012 } else if (priv->chip_type == AR8236) {
1013 swdev->name = "Atheros AR8236";
1014 swdev->vlans = AR8216_NUM_VLANS;
1015 swdev->ports = AR8216_NUM_PORTS;
1016 } else {
1017 swdev->name = "Atheros AR8216";
1018 swdev->vlans = AR8216_NUM_VLANS;
1019 }
1020
1021 ret = register_switch(&priv->dev, pdev->attached_dev);
1022 if (ret)
1023 goto err_free_priv;
1024
1025 priv->init = true;
1026
1027 ret = priv->chip->hw_init(priv);
1028 if (ret)
1029 goto err_free_priv;
1030
1031 ret = ar8216_sw_reset_switch(&priv->dev);
1032 if (ret)
1033 goto err_free_priv;
1034
1035 dev->phy_ptr = priv;
1036
1037 /* VID fixup only needed on ar8216 */
1038 if (pdev->addr == 0 && priv->chip_type == AR8216) {
1039 pdev->pkt_align = 2;
1040 pdev->netif_receive_skb = ar8216_netif_receive_skb;
1041 pdev->netif_rx = ar8216_netif_rx;
1042 priv->ndo_old = dev->netdev_ops;
1043 memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
1044 priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
1045 dev->netdev_ops = &priv->ndo;
1046 }
1047
1048 priv->init = false;
1049
1050 return 0;
1051
1052 err_free_priv:
1053 kfree(priv);
1054 return ret;
1055 }
1056
1057 static int
1058 ar8216_read_status(struct phy_device *phydev)
1059 {
1060 struct ar8216_priv *priv = phydev->priv;
1061 struct switch_port_link link;
1062 int ret;
1063
1064 if (phydev->addr != 0)
1065 return genphy_read_status(phydev);
1066
1067 ar8216_read_port_link(priv, phydev->addr, &link);
1068 phydev->link = !!link.link;
1069 if (!phydev->link)
1070 return 0;
1071
1072 switch (link.speed) {
1073 case SWITCH_PORT_SPEED_10:
1074 phydev->speed = SPEED_10;
1075 break;
1076 case SWITCH_PORT_SPEED_100:
1077 phydev->speed = SPEED_100;
1078 break;
1079 case SWITCH_PORT_SPEED_1000:
1080 phydev->speed = SPEED_1000;
1081 break;
1082 default:
1083 phydev->speed = 0;
1084 }
1085 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1086
1087 /* flush the address translation unit */
1088 mutex_lock(&priv->reg_mutex);
1089 ret = priv->chip->atu_flush(priv);
1090 mutex_unlock(&priv->reg_mutex);
1091
1092 phydev->state = PHY_RUNNING;
1093 netif_carrier_on(phydev->attached_dev);
1094 phydev->adjust_link(phydev->attached_dev);
1095
1096 return ret;
1097 }
1098
1099 static int
1100 ar8216_config_aneg(struct phy_device *phydev)
1101 {
1102 if (phydev->addr == 0)
1103 return 0;
1104
1105 return genphy_config_aneg(phydev);
1106 }
1107
1108 static int
1109 ar8216_probe(struct phy_device *pdev)
1110 {
1111 struct ar8216_priv priv;
1112
1113 priv.phy = pdev;
1114 return ar8216_id_chip(&priv);
1115 }
1116
1117 static void
1118 ar8216_remove(struct phy_device *pdev)
1119 {
1120 struct ar8216_priv *priv = pdev->priv;
1121 struct net_device *dev = pdev->attached_dev;
1122
1123 if (!priv)
1124 return;
1125
1126 if (priv->ndo_old && dev)
1127 dev->netdev_ops = priv->ndo_old;
1128 if (pdev->addr == 0)
1129 unregister_switch(&priv->dev);
1130 kfree(priv);
1131 }
1132
1133 static struct phy_driver ar8216_driver = {
1134 .phy_id = 0x004d0000,
1135 .name = "Atheros AR8216/AR8236/AR8316",
1136 .phy_id_mask = 0xffff0000,
1137 .features = PHY_BASIC_FEATURES,
1138 .probe = ar8216_probe,
1139 .remove = ar8216_remove,
1140 .config_init = &ar8216_config_init,
1141 .config_aneg = &ar8216_config_aneg,
1142 .read_status = &ar8216_read_status,
1143 .driver = { .owner = THIS_MODULE },
1144 };
1145
1146 int __init
1147 ar8216_init(void)
1148 {
1149 return phy_driver_register(&ar8216_driver);
1150 }
1151
1152 void __exit
1153 ar8216_exit(void)
1154 {
1155 phy_driver_unregister(&ar8216_driver);
1156 }
1157
1158 module_init(ar8216_init);
1159 module_exit(ar8216_exit);
1160 MODULE_LICENSE("GPL");
1161
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