package/uboot-lantiq/patches/020-mips-enhancements.patch

   1 --- a/cpu/mips/start.S
   2 +++ b/cpu/mips/start.S
   3 @@ -69,6 +69,9 @@ _start:
   4  #elif defined(CONFIG_PURPLE)
   5         .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
   6         .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
   7 +#elif defined(CONFIG_SYS_EBU_BOOT)
   8 +       .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
   9 +       .word 0x00000000           /* phase of the flash                    */
  10  #else
  11         RVECENT(romReserved,2)
  12  #endif
  13 @@ -202,7 +205,25 @@ _start:
  14          * 128 * 8 == 1024 == 0x400
  15          * so this is address R_VEC+0x400 == 0xbfc00400
  16          */
  17 -#ifdef CONFIG_PURPLE
  18 +#ifndef CONFIG_PURPLE
  19 +       XVECENT(romExcHandle,0x400);    /* bfc00400: Int, CauseIV=1 */
  20 +       RVECENT(romReserved,129);
  21 +       RVECENT(romReserved,130);
  22 +       RVECENT(romReserved,131);
  23 +       RVECENT(romReserved,132);
  24 +       RVECENT(romReserved,133);
  25 +       RVECENT(romReserved,134);
  26 +       RVECENT(romReserved,135);
  27 +       RVECENT(romReserved,136);
  28 +       RVECENT(romReserved,137);
  29 +       RVECENT(romReserved,138);
  30 +       RVECENT(romReserved,139);
  31 +       RVECENT(romReserved,140);
  32 +       RVECENT(romReserved,141);
  33 +       RVECENT(romReserved,142);
  34 +       RVECENT(romReserved,143);
  35 +       XVECENT(romExcHandle,0x480);    /* bfc00480: EJTAG debug exception */
  36 +#else /* CONFIG_PURPLE */
  37  /* 0xbfc00400 */
  38         .word   0xdc870000
  39         .word   0xfca70000
  40 @@ -228,6 +249,12 @@ _start:
  41  #endif /* CONFIG_PURPLE */
  42         .align 4
  43  reset:
  44 +#ifdef CONFIG_SYS_MIPS_MULTI_CPU
  45 +       mfc0    k0, CP0_EBASE
  46 +       and     k0, EBASEF_CPUNUM
  47 +       bne     k0, zero, ifx_mips_handler_cpux
  48 +       nop
  49 +#endif
  50
  51         /* Clear watch registers.
  52          */
  53 @@ -239,6 +266,16 @@ reset:
  54
  55         setup_c0_status_reset
  56
  57 +#if defined(CONFIG_MIPS24KEC) || defined(CONFIG_MIPS34KC)
  58 +       /* CONFIG7 register */
  59 +       /* Erratum "RPS May Cause Incorrect Instruction Execution"
  60 +        * for 24KEC and 34KC */
  61 +       mfc0    k0, CP0_CONFIG, 7
  62 +       li      k1, MIPS_CONF7_RPS
  63 +       or      k0, k1
  64 +       mtc0    k0, CP0_CONFIG, 7
  65 +#endif
  66 +
  67         /* Init Timer */
  68         mtc0    zero, CP0_COUNT
  69         mtc0    zero, CP0_COMPARE
  70 @@ -270,9 +307,12 @@ reset:
  71         jalr    t9
  72         nop
  73
  74 +#ifndef CONFIG_SYS_MIPS_CACHE_OPER_MODE
  75 +#define CONFIG_SYS_MIPS_CACHE_OPER_MODE CONF_CM_CACHABLE_NONCOHERENT
  76 +#endif
  77         /* ... and enable them.
  78          */
  79 -       li      t0, CONF_CM_CACHABLE_NONCOHERENT
  80 +       li      t0, CONFIG_SYS_MIPS_CACHE_OPER_MODE
  81         mtc0    t0, CP0_CONFIG
  82  #endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
  83
  84 @@ -419,3 +459,15 @@ romReserved:
  85
  86  romExcHandle:
  87         b       romExcHandle
  88 +
  89 +       /* Additional handlers.
  90 +        */
  91 +#ifdef CONFIG_SYS_MIPS_MULTI_CPU
  92 +/*
  93 + * Stop Slave CPUs
  94 + */
  95 +ifx_mips_handler_cpux:
  96 +       wait;
  97 +       b ifx_mips_handler_cpux;
  98 +       nop;
  99 +#endif
 100 --- a/include/asm-mips/mipsregs.h
 101 +++ b/include/asm-mips/mipsregs.h
 102 @@ -57,6 +57,7 @@
 103  #define CP0_CAUSE $13
 104  #define CP0_EPC $14
 105  #define CP0_PRID $15
 106 +#define CP0_EBASE $15,1
 107  #define CP0_CONFIG $16
 108  #define CP0_LLADDR $17
 109  #define CP0_WATCHLO $18
 110 @@ -395,6 +396,14 @@
 111  #define  CAUSEF_BD             (_ULCAST_(1)   << 31)
 112
 113  /*
 114 + * Bits in the coprocessor 0 EBase register
 115 + */
 116 +#define EBASEB_CPUNUM          0
 117 +#define EBASEF_CPUNUM          (0x3ff << EBASEB_CPUNUM)
 118 +#define EBASEB_EXPBASE         12
 119 +#define EBASEF_EXPBASE         (0x3ffff << EBASEB_EXPBASE)
 120 +
 121 +/*
 122   * Bits in the coprocessor 0 config register.
 123   */
 124  /* Generic bits.  */