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[uml] add support for 3.2
[openwrt.git] / target / linux / generic / patches-2.6.31 / 941-ssb_update.patch
1 --- a/drivers/ssb/Kconfig
2 +++ b/drivers/ssb/Kconfig
3 @@ -66,6 +66,20 @@ config SSB_PCMCIAHOST
4
5 If unsure, say N
6
7 +config SSB_SDIOHOST_POSSIBLE
8 + bool
9 + depends on SSB && (MMC = y || MMC = SSB)
10 + default y
11 +
12 +config SSB_SDIOHOST
13 + bool "Support for SSB on SDIO-bus host"
14 + depends on SSB_SDIOHOST_POSSIBLE
15 + help
16 + Support for a Sonics Silicon Backplane on top
17 + of a SDIO device.
18 +
19 + If unsure, say N
20 +
21 config SSB_SILENT
22 bool "No SSB kernel messages"
23 depends on SSB && EMBEDDED
24 --- a/drivers/ssb/Makefile
25 +++ b/drivers/ssb/Makefile
26 @@ -6,6 +6,7 @@ ssb-$(CONFIG_SSB_SPROM) += sprom.o
27 # host support
28 ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o
29 ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.o
30 +ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
31
32 # built-in drivers
33 ssb-y += driver_chipcommon.o
34 --- a/drivers/ssb/b43_pci_bridge.c
35 +++ b/drivers/ssb/b43_pci_bridge.c
36 @@ -5,12 +5,13 @@
37 * because of its small size we include it in the SSB core
38 * instead of creating a standalone module.
39 *
40 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
41 + * Copyright 2007 Michael Buesch <m@bues.ch>
42 *
43 * Licensed under the GNU/GPL. See COPYING for details.
44 */
45
46 #include <linux/pci.h>
47 +#include <linux/module.h>
48 #include <linux/ssb/ssb.h>
49
50 #include "ssb_private.h"
51 @@ -24,6 +25,7 @@ static const struct pci_device_id b43_pc
52 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
53 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
54 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
55 + { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC, 0x4318) },
56 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
57 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
58 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
59 --- a/drivers/ssb/driver_chipcommon.c
60 +++ b/drivers/ssb/driver_chipcommon.c
61 @@ -3,7 +3,7 @@
62 * Broadcom ChipCommon core driver
63 *
64 * Copyright 2005, Broadcom Corporation
65 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
66 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
67 *
68 * Licensed under the GNU/GPL. See COPYING for details.
69 */
70 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
71 if (!ccdev)
72 return;
73 bus = ccdev->bus;
74 +
75 + /* We support SLOW only on 6..9 */
76 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
77 + mode = SSB_CLKMODE_DYNAMIC;
78 +
79 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
80 + return; /* PMU controls clockmode, separated function needed */
81 + SSB_WARN_ON(ccdev->id.revision >= 20);
82 +
83 /* chipcommon cores prior to rev6 don't support dynamic clock control */
84 if (ccdev->id.revision < 6)
85 return;
86 - /* chipcommon cores rev10 are a whole new ball game */
87 +
88 + /* ChipCommon cores rev10+ need testing */
89 if (ccdev->id.revision >= 10)
90 return;
91 +
92 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
93 return;
94
95 switch (mode) {
96 - case SSB_CLKMODE_SLOW:
97 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
98 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
99 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
100 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
101 break;
102 case SSB_CLKMODE_FAST:
103 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
104 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
105 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
106 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
107 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
108 + if (ccdev->id.revision < 10) {
109 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
110 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
111 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
112 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
113 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
114 + } else {
115 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
116 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
117 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
118 + /* udelay(150); TODO: not available in early init */
119 + }
120 break;
121 case SSB_CLKMODE_DYNAMIC:
122 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
123 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
124 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
125 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
126 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
127 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
128 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
129 -
130 - /* for dynamic control, we have to release our xtal_pu "force on" */
131 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
132 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
133 + if (ccdev->id.revision < 10) {
134 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
135 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
136 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
137 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
138 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
139 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
140 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
141 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
142 +
143 + /* For dynamic control, we have to release our xtal_pu
144 + * "force on" */
145 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
146 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
147 + } else {
148 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
149 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
150 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
151 + }
152 break;
153 default:
154 SSB_WARN_ON(1);
155 @@ -209,6 +235,24 @@ static void chipco_powercontrol_init(str
156 }
157 }
158
159 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
160 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
161 +{
162 + struct ssb_bus *bus = cc->dev->bus;
163 +
164 + switch (bus->chip_id) {
165 + case 0x4312:
166 + case 0x4322:
167 + case 0x4328:
168 + return 7000;
169 + case 0x4325:
170 + /* TODO: */
171 + default:
172 + return 15000;
173 + }
174 +}
175 +
176 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
177 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
178 {
179 struct ssb_bus *bus = cc->dev->bus;
180 @@ -218,6 +262,12 @@ static void calc_fast_powerup_delay(stru
181
182 if (bus->bustype != SSB_BUSTYPE_PCI)
183 return;
184 +
185 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
186 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
187 + return;
188 + }
189 +
190 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
191 return;
192
193 @@ -233,6 +283,15 @@ void ssb_chipcommon_init(struct ssb_chip
194 {
195 if (!cc->dev)
196 return; /* We don't have a ChipCommon */
197 + if (cc->dev->id.revision >= 11)
198 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
199 + ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
200 +
201 + if (cc->dev->id.revision >= 20) {
202 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
203 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
204 + }
205 +
206 ssb_pmu_init(cc);
207 chipco_powercontrol_init(cc);
208 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
209 @@ -370,6 +429,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
210 {
211 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
212 }
213 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
214
215 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
216 {
217 --- a/drivers/ssb/driver_chipcommon_pmu.c
218 +++ b/drivers/ssb/driver_chipcommon_pmu.c
219 @@ -2,7 +2,7 @@
220 * Sonics Silicon Backplane
221 * Broadcom ChipCommon Power Management Unit driver
222 *
223 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
224 + * Copyright 2009, Michael Buesch <m@bues.ch>
225 * Copyright 2007, Broadcom Corporation
226 *
227 * Licensed under the GNU/GPL. See COPYING for details.
228 @@ -28,6 +28,21 @@ static void ssb_chipco_pll_write(struct
229 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
230 }
231
232 +static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
233 + u32 offset, u32 mask, u32 set)
234 +{
235 + u32 value;
236 +
237 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
238 + chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
239 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
240 + value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
241 + value &= mask;
242 + value |= set;
243 + chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
244 + chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
245 +}
246 +
247 struct pmu0_plltab_entry {
248 u16 freq; /* Crystal frequency in kHz.*/
249 u8 xf; /* Crystal frequency value for PMU control */
250 @@ -317,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
251 case 0x5354:
252 ssb_pmu0_pllinit_r0(cc, crystalfreq);
253 break;
254 + case 0x4322:
255 + if (cc->pmu.rev == 2) {
256 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
257 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
258 + }
259 + break;
260 default:
261 ssb_printk(KERN_ERR PFX
262 "ERROR: PLL init unknown for device %04X\n",
263 @@ -396,12 +417,15 @@ static void ssb_pmu_resources_init(struc
264 u32 min_msk = 0, max_msk = 0;
265 unsigned int i;
266 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
267 - unsigned int updown_tab_size;
268 + unsigned int updown_tab_size = 0;
269 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
270 - unsigned int depend_tab_size;
271 + unsigned int depend_tab_size = 0;
272
273 switch (bus->chip_id) {
274 case 0x4312:
275 + min_msk = 0xCBB;
276 + break;
277 + case 0x4322:
278 /* We keep the default settings:
279 * min_msk = 0xCBB
280 * max_msk = 0x7FFFF
281 @@ -480,9 +504,9 @@ static void ssb_pmu_resources_init(struc
282 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
283 }
284
285 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
286 void ssb_pmu_init(struct ssb_chipcommon *cc)
287 {
288 - struct ssb_bus *bus = cc->dev->bus;
289 u32 pmucap;
290
291 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
292 @@ -494,15 +518,91 @@ void ssb_pmu_init(struct ssb_chipcommon
293 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
294 cc->pmu.rev, pmucap);
295
296 - if (cc->pmu.rev >= 1) {
297 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
298 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
299 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
300 - } else {
301 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
302 - SSB_CHIPCO_PMU_CTL_NOILPONW);
303 - }
304 - }
305 + if (cc->pmu.rev == 1)
306 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
307 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
308 + else
309 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
310 + SSB_CHIPCO_PMU_CTL_NOILPONW);
311 ssb_pmu_pll_init(cc);
312 ssb_pmu_resources_init(cc);
313 }
314 +
315 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
316 + enum ssb_pmu_ldo_volt_id id, u32 voltage)
317 +{
318 + struct ssb_bus *bus = cc->dev->bus;
319 + u32 addr, shift, mask;
320 +
321 + switch (bus->chip_id) {
322 + case 0x4328:
323 + case 0x5354:
324 + switch (id) {
325 + case LDO_VOLT1:
326 + addr = 2;
327 + shift = 25;
328 + mask = 0xF;
329 + break;
330 + case LDO_VOLT2:
331 + addr = 3;
332 + shift = 1;
333 + mask = 0xF;
334 + break;
335 + case LDO_VOLT3:
336 + addr = 3;
337 + shift = 9;
338 + mask = 0xF;
339 + break;
340 + case LDO_PAREF:
341 + addr = 3;
342 + shift = 17;
343 + mask = 0x3F;
344 + break;
345 + default:
346 + SSB_WARN_ON(1);
347 + return;
348 + }
349 + break;
350 + case 0x4312:
351 + if (SSB_WARN_ON(id != LDO_PAREF))
352 + return;
353 + addr = 0;
354 + shift = 21;
355 + mask = 0x3F;
356 + break;
357 + default:
358 + return;
359 + }
360 +
361 + ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
362 + (voltage & mask) << shift);
363 +}
364 +
365 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
366 +{
367 + struct ssb_bus *bus = cc->dev->bus;
368 + int ldo;
369 +
370 + switch (bus->chip_id) {
371 + case 0x4312:
372 + ldo = SSB_PMURES_4312_PA_REF_LDO;
373 + break;
374 + case 0x4328:
375 + ldo = SSB_PMURES_4328_PA_REF_LDO;
376 + break;
377 + case 0x5354:
378 + ldo = SSB_PMURES_5354_PA_REF_LDO;
379 + break;
380 + default:
381 + return;
382 + }
383 +
384 + if (on)
385 + chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
386 + else
387 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
388 + chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
389 +}
390 +
391 +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
392 +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
393 --- a/drivers/ssb/driver_gige.c
394 +++ b/drivers/ssb/driver_gige.c
395 @@ -3,7 +3,7 @@
396 * Broadcom Gigabit Ethernet core driver
397 *
398 * Copyright 2008, Broadcom Corporation
399 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
400 + * Copyright 2008, Michael Buesch <m@bues.ch>
401 *
402 * Licensed under the GNU/GPL. See COPYING for details.
403 */
404 @@ -12,6 +12,7 @@
405 #include <linux/ssb/ssb_driver_gige.h>
406 #include <linux/pci.h>
407 #include <linux/pci_regs.h>
408 +#include <linux/slab.h>
409
410
411 /*
412 @@ -105,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
413 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
414 }
415
416 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
417 - int reg, int size, u32 *val)
418 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
419 + unsigned int devfn, int reg,
420 + int size, u32 *val)
421 {
422 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
423 unsigned long flags;
424 @@ -135,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
425 return PCIBIOS_SUCCESSFUL;
426 }
427
428 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
429 - int reg, int size, u32 val)
430 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
431 + unsigned int devfn, int reg,
432 + int size, u32 val)
433 {
434 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
435 unsigned long flags;
436 @@ -165,7 +168,8 @@ static int ssb_gige_pci_write_config(str
437 return PCIBIOS_SUCCESSFUL;
438 }
439
440 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
441 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
442 + const struct ssb_device_id *id)
443 {
444 struct ssb_gige *dev;
445 u32 base, tmslow, tmshigh;
446 --- a/drivers/ssb/driver_mipscore.c
447 +++ b/drivers/ssb/driver_mipscore.c
448 @@ -3,7 +3,7 @@
449 * Broadcom MIPS core driver
450 *
451 * Copyright 2005, Broadcom Corporation
452 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
453 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
454 *
455 * Licensed under the GNU/GPL. See COPYING for details.
456 */
457 @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
458 set_irq(dev, irq++);
459 }
460 break;
461 - /* fallthrough */
462 case SSB_DEV_PCI:
463 case SSB_DEV_ETHERNET:
464 case SSB_DEV_ETHERNET_GBIT:
465 @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
466 set_irq(dev, irq++);
467 break;
468 }
469 + /* fallthrough */
470 + case SSB_DEV_EXTIF:
471 + set_irq(dev, 0);
472 + break;
473 }
474 }
475 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
476 --- a/drivers/ssb/driver_pcicore.c
477 +++ b/drivers/ssb/driver_pcicore.c
478 @@ -3,7 +3,7 @@
479 * Broadcom PCI-core driver
480 *
481 * Copyright 2005, Broadcom Corporation
482 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
483 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
484 *
485 * Licensed under the GNU/GPL. See COPYING for details.
486 */
487 @@ -15,6 +15,11 @@
488
489 #include "ssb_private.h"
490
491 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
492 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
493 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
494 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
495 + u8 address, u16 data);
496
497 static inline
498 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
499 @@ -246,20 +251,12 @@ static struct pci_controller ssb_pcicore
500 .pci_ops = &ssb_pcicore_pciops,
501 .io_resource = &ssb_pcicore_io_resource,
502 .mem_resource = &ssb_pcicore_mem_resource,
503 - .mem_offset = 0x24000000,
504 };
505
506 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
507 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
508 -
509 /* This function is called when doing a pci_enable_device().
510 * We must first check if the device is a device on the PCI-core bridge. */
511 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
512 {
513 - struct resource *res;
514 - int pos, size;
515 - u32 *base;
516 -
517 if (d->bus->ops != &ssb_pcicore_pciops) {
518 /* This is not a device on the PCI-core bridge. */
519 return -ENODEV;
520 @@ -268,27 +265,6 @@ int ssb_pcicore_plat_dev_init(struct pci
521 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
522 pci_name(d));
523
524 - /* Fix up resource bases */
525 - for (pos = 0; pos < 6; pos++) {
526 - res = &d->resource[pos];
527 - if (res->flags & IORESOURCE_IO)
528 - base = &ssb_pcicore_pcibus_iobase;
529 - else
530 - base = &ssb_pcicore_pcibus_membase;
531 - res->flags |= IORESOURCE_PCI_FIXED;
532 - if (res->end) {
533 - size = res->end - res->start + 1;
534 - if (*base & (size - 1))
535 - *base = (*base + size) & ~(size - 1);
536 - res->start = *base;
537 - res->end = res->start + size - 1;
538 - *base += size;
539 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
540 - }
541 - /* Fix up PCI bridge BAR0 only */
542 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
543 - break;
544 - }
545 /* Fix up interrupt lines */
546 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
547 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
548 @@ -338,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
549 return ssb_mips_irq(extpci_core->dev) + 2;
550 }
551
552 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
553 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
554 {
555 u32 val;
556
557 @@ -403,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
558 register_pci_controller(&ssb_pcicore_controller);
559 }
560
561 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
562 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
563 {
564 struct ssb_bus *bus = pc->dev->bus;
565 u16 chipid_top;
566 @@ -432,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
567 }
568 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
569
570 +/**************************************************
571 + * Workarounds.
572 + **************************************************/
573 +
574 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
575 +{
576 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
577 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
578 + tmp &= ~0xF000;
579 + tmp |= (pc->dev->core_index << 12);
580 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
581 + }
582 +}
583 +
584 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
585 +{
586 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
587 +}
588 +
589 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
590 +{
591 + const u8 serdes_pll_device = 0x1D;
592 + const u8 serdes_rx_device = 0x1F;
593 + u16 tmp;
594 +
595 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
596 + ssb_pcicore_polarity_workaround(pc));
597 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
598 + if (tmp & 0x4000)
599 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
600 +}
601 +
602 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
603 +{
604 + struct ssb_device *pdev = pc->dev;
605 + struct ssb_bus *bus = pdev->bus;
606 + u32 tmp;
607 +
608 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
609 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
610 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
611 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
612 +
613 + if (pdev->id.revision < 5) {
614 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
615 + tmp &= ~SSB_IMCFGLO_SERTO;
616 + tmp |= 2;
617 + tmp &= ~SSB_IMCFGLO_REQTO;
618 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
619 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
620 + ssb_commit_settings(bus);
621 + } else if (pdev->id.revision >= 11) {
622 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
623 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
624 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
625 + }
626 +}
627 +
628 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
629 +{
630 + u32 tmp;
631 + u8 rev = pc->dev->id.revision;
632 +
633 + if (rev == 0 || rev == 1) {
634 + /* TLP Workaround register. */
635 + tmp = ssb_pcie_read(pc, 0x4);
636 + tmp |= 0x8;
637 + ssb_pcie_write(pc, 0x4, tmp);
638 + }
639 + if (rev == 1) {
640 + /* DLLP Link Control register. */
641 + tmp = ssb_pcie_read(pc, 0x100);
642 + tmp |= 0x40;
643 + ssb_pcie_write(pc, 0x100, tmp);
644 + }
645 +
646 + if (rev == 0) {
647 + const u8 serdes_rx_device = 0x1F;
648 +
649 + ssb_pcie_mdio_write(pc, serdes_rx_device,
650 + 2 /* Timer */, 0x8128);
651 + ssb_pcie_mdio_write(pc, serdes_rx_device,
652 + 6 /* CDR */, 0x0100);
653 + ssb_pcie_mdio_write(pc, serdes_rx_device,
654 + 7 /* CDR BW */, 0x1466);
655 + } else if (rev == 3 || rev == 4 || rev == 5) {
656 + /* TODO: DLLP Power Management Threshold */
657 + ssb_pcicore_serdes_workaround(pc);
658 + /* TODO: ASPM */
659 + } else if (rev == 7) {
660 + /* TODO: No PLL down */
661 + }
662 +
663 + if (rev >= 6) {
664 + /* Miscellaneous Configuration Fixup */
665 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
666 + if (!(tmp & 0x8000))
667 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
668 + tmp | 0x8000);
669 + }
670 +}
671
672 /**************************************************
673 * Generic and Clientmode operation code.
674 **************************************************/
675
676 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
677 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
678 {
679 + struct ssb_device *pdev = pc->dev;
680 + struct ssb_bus *bus = pdev->bus;
681 +
682 + if (bus->bustype == SSB_BUSTYPE_PCI)
683 + ssb_pcicore_fix_sprom_core_index(pc);
684 +
685 /* Disable PCI interrupts. */
686 - ssb_write32(pc->dev, SSB_INTVEC, 0);
687 + ssb_write32(pdev, SSB_INTVEC, 0);
688 +
689 + /* Additional PCIe always once-executed workarounds */
690 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
691 + ssb_pcicore_serdes_workaround(pc);
692 + /* TODO: ASPM */
693 + /* TODO: Clock Request Update */
694 + }
695 }
696
697 -void ssb_pcicore_init(struct ssb_pcicore *pc)
698 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
699 {
700 struct ssb_device *dev = pc->dev;
701 - struct ssb_bus *bus;
702
703 if (!dev)
704 return;
705 - bus = dev->bus;
706 if (!ssb_device_is_enabled(dev))
707 ssb_device_enable(dev, 0);
708
709 @@ -475,58 +563,104 @@ static void ssb_pcie_write(struct ssb_pc
710 pcicore_write32(pc, 0x134, data);
711 }
712
713 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
714 - u8 address, u16 data)
715 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
716 {
717 const u16 mdio_control = 0x128;
718 const u16 mdio_data = 0x12C;
719 u32 v;
720 int i;
721
722 + v = (1 << 30); /* Start of Transaction */
723 + v |= (1 << 28); /* Write Transaction */
724 + v |= (1 << 17); /* Turnaround */
725 + v |= (0x1F << 18);
726 + v |= (phy << 4);
727 + pcicore_write32(pc, mdio_data, v);
728 +
729 + udelay(10);
730 + for (i = 0; i < 200; i++) {
731 + v = pcicore_read32(pc, mdio_control);
732 + if (v & 0x100 /* Trans complete */)
733 + break;
734 + msleep(1);
735 + }
736 +}
737 +
738 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
739 +{
740 + const u16 mdio_control = 0x128;
741 + const u16 mdio_data = 0x12C;
742 + int max_retries = 10;
743 + u16 ret = 0;
744 + u32 v;
745 + int i;
746 +
747 v = 0x80; /* Enable Preamble Sequence */
748 v |= 0x2; /* MDIO Clock Divisor */
749 pcicore_write32(pc, mdio_control, v);
750
751 + if (pc->dev->id.revision >= 10) {
752 + max_retries = 200;
753 + ssb_pcie_mdio_set_phy(pc, device);
754 + }
755 +
756 v = (1 << 30); /* Start of Transaction */
757 - v |= (1 << 28); /* Write Transaction */
758 + v |= (1 << 29); /* Read Transaction */
759 v |= (1 << 17); /* Turnaround */
760 - v |= (u32)device << 22;
761 + if (pc->dev->id.revision < 10)
762 + v |= (u32)device << 22;
763 v |= (u32)address << 18;
764 - v |= data;
765 pcicore_write32(pc, mdio_data, v);
766 /* Wait for the device to complete the transaction */
767 udelay(10);
768 - for (i = 0; i < 10; i++) {
769 + for (i = 0; i < max_retries; i++) {
770 v = pcicore_read32(pc, mdio_control);
771 - if (v & 0x100 /* Trans complete */)
772 + if (v & 0x100 /* Trans complete */) {
773 + udelay(10);
774 + ret = pcicore_read32(pc, mdio_data);
775 break;
776 + }
777 msleep(1);
778 }
779 pcicore_write32(pc, mdio_control, 0);
780 + return ret;
781 }
782
783 -static void ssb_broadcast_value(struct ssb_device *dev,
784 - u32 address, u32 data)
785 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
786 + u8 address, u16 data)
787 {
788 - /* This is used for both, PCI and ChipCommon core, so be careful. */
789 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
790 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
791 + const u16 mdio_control = 0x128;
792 + const u16 mdio_data = 0x12C;
793 + int max_retries = 10;
794 + u32 v;
795 + int i;
796
797 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
798 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
799 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
800 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
801 -}
802 + v = 0x80; /* Enable Preamble Sequence */
803 + v |= 0x2; /* MDIO Clock Divisor */
804 + pcicore_write32(pc, mdio_control, v);
805
806 -static void ssb_commit_settings(struct ssb_bus *bus)
807 -{
808 - struct ssb_device *dev;
809 + if (pc->dev->id.revision >= 10) {
810 + max_retries = 200;
811 + ssb_pcie_mdio_set_phy(pc, device);
812 + }
813
814 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
815 - if (WARN_ON(!dev))
816 - return;
817 - /* This forces an update of the cached registers. */
818 - ssb_broadcast_value(dev, 0xFD8, 0);
819 + v = (1 << 30); /* Start of Transaction */
820 + v |= (1 << 28); /* Write Transaction */
821 + v |= (1 << 17); /* Turnaround */
822 + if (pc->dev->id.revision < 10)
823 + v |= (u32)device << 22;
824 + v |= (u32)address << 18;
825 + v |= data;
826 + pcicore_write32(pc, mdio_data, v);
827 + /* Wait for the device to complete the transaction */
828 + udelay(10);
829 + for (i = 0; i < max_retries; i++) {
830 + v = pcicore_read32(pc, mdio_control);
831 + if (v & 0x100 /* Trans complete */)
832 + break;
833 + msleep(1);
834 + }
835 + pcicore_write32(pc, mdio_control, 0);
836 }
837
838 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
839 @@ -551,13 +685,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
840 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
841
842 /* Enable interrupts for this device. */
843 - if (bus->host_pci &&
844 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
845 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
846 u32 coremask;
847
848 /* Calculate the "coremask" for the device. */
849 coremask = (1 << dev->core_index);
850
851 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
852 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
853 if (err)
854 goto out;
855 @@ -579,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
856 if (pc->setup_done)
857 goto out;
858 if (pdev->id.coreid == SSB_DEV_PCI) {
859 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
860 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
861 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
862 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
863 -
864 - if (pdev->id.revision < 5) {
865 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
866 - tmp &= ~SSB_IMCFGLO_SERTO;
867 - tmp |= 2;
868 - tmp &= ~SSB_IMCFGLO_REQTO;
869 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
870 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
871 - ssb_commit_settings(bus);
872 - } else if (pdev->id.revision >= 11) {
873 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
874 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
875 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
876 - }
877 + ssb_pcicore_pci_setup_workarounds(pc);
878 } else {
879 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
880 - //TODO: Better make defines for all these magic PCIE values.
881 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
882 - /* TLP Workaround register. */
883 - tmp = ssb_pcie_read(pc, 0x4);
884 - tmp |= 0x8;
885 - ssb_pcie_write(pc, 0x4, tmp);
886 - }
887 - if (pdev->id.revision == 0) {
888 - const u8 serdes_rx_device = 0x1F;
889 -
890 - ssb_pcie_mdio_write(pc, serdes_rx_device,
891 - 2 /* Timer */, 0x8128);
892 - ssb_pcie_mdio_write(pc, serdes_rx_device,
893 - 6 /* CDR */, 0x0100);
894 - ssb_pcie_mdio_write(pc, serdes_rx_device,
895 - 7 /* CDR BW */, 0x1466);
896 - } else if (pdev->id.revision == 1) {
897 - /* DLLP Link Control register. */
898 - tmp = ssb_pcie_read(pc, 0x100);
899 - tmp |= 0x40;
900 - ssb_pcie_write(pc, 0x100, tmp);
901 - }
902 + ssb_pcicore_pcie_setup_workarounds(pc);
903 }
904 pc->setup_done = 1;
905 out:
906 --- a/drivers/ssb/main.c
907 +++ b/drivers/ssb/main.c
908 @@ -3,7 +3,7 @@
909 * Subsystem core
910 *
911 * Copyright 2005, Broadcom Corporation
912 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
913 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
914 *
915 * Licensed under the GNU/GPL. See COPYING for details.
916 */
917 @@ -12,11 +12,14 @@
918
919 #include <linux/delay.h>
920 #include <linux/io.h>
921 +#include <linux/module.h>
922 #include <linux/ssb/ssb.h>
923 #include <linux/ssb/ssb_regs.h>
924 #include <linux/ssb/ssb_driver_gige.h>
925 #include <linux/dma-mapping.h>
926 #include <linux/pci.h>
927 +#include <linux/mmc/sdio_func.h>
928 +#include <linux/slab.h>
929
930 #include <pcmcia/cs_types.h>
931 #include <pcmcia/cs.h>
932 @@ -88,6 +91,25 @@ found:
933 }
934 #endif /* CONFIG_SSB_PCMCIAHOST */
935
936 +#ifdef CONFIG_SSB_SDIOHOST
937 +struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
938 +{
939 + struct ssb_bus *bus;
940 +
941 + ssb_buses_lock();
942 + list_for_each_entry(bus, &buses, list) {
943 + if (bus->bustype == SSB_BUSTYPE_SDIO &&
944 + bus->host_sdio == func)
945 + goto found;
946 + }
947 + bus = NULL;
948 +found:
949 + ssb_buses_unlock();
950 +
951 + return bus;
952 +}
953 +#endif /* CONFIG_SSB_SDIOHOST */
954 +
955 int ssb_for_each_bus_call(unsigned long data,
956 int (*func)(struct ssb_bus *bus, unsigned long data))
957 {
958 @@ -120,6 +142,19 @@ static void ssb_device_put(struct ssb_de
959 put_device(dev->dev);
960 }
961
962 +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
963 +{
964 + if (drv)
965 + get_driver(&drv->drv);
966 + return drv;
967 +}
968 +
969 +static inline void ssb_driver_put(struct ssb_driver *drv)
970 +{
971 + if (drv)
972 + put_driver(&drv->drv);
973 +}
974 +
975 static int ssb_device_resume(struct device *dev)
976 {
977 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
978 @@ -190,90 +225,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
979 EXPORT_SYMBOL(ssb_bus_suspend);
980
981 #ifdef CONFIG_SSB_SPROM
982 -int ssb_devices_freeze(struct ssb_bus *bus)
983 +/** ssb_devices_freeze - Freeze all devices on the bus.
984 + *
985 + * After freezing no device driver will be handling a device
986 + * on this bus anymore. ssb_devices_thaw() must be called after
987 + * a successful freeze to reactivate the devices.
988 + *
989 + * @bus: The bus.
990 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
991 + */
992 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
993 {
994 - struct ssb_device *dev;
995 - struct ssb_driver *drv;
996 - int err = 0;
997 - int i;
998 - pm_message_t state = PMSG_FREEZE;
999 + struct ssb_device *sdev;
1000 + struct ssb_driver *sdrv;
1001 + unsigned int i;
1002 +
1003 + memset(ctx, 0, sizeof(*ctx));
1004 + ctx->bus = bus;
1005 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
1006
1007 - /* First check that we are capable to freeze all devices. */
1008 for (i = 0; i < bus->nr_devices; i++) {
1009 - dev = &(bus->devices[i]);
1010 - if (!dev->dev ||
1011 - !dev->dev->driver ||
1012 - !device_is_registered(dev->dev))
1013 - continue;
1014 - drv = drv_to_ssb_drv(dev->dev->driver);
1015 - if (!drv)
1016 + sdev = ssb_device_get(&bus->devices[i]);
1017 +
1018 + if (!sdev->dev || !sdev->dev->driver ||
1019 + !device_is_registered(sdev->dev)) {
1020 + ssb_device_put(sdev);
1021 continue;
1022 - if (!drv->suspend) {
1023 - /* Nope, can't suspend this one. */
1024 - return -EOPNOTSUPP;
1025 }
1026 - }
1027 - /* Now suspend all devices */
1028 - for (i = 0; i < bus->nr_devices; i++) {
1029 - dev = &(bus->devices[i]);
1030 - if (!dev->dev ||
1031 - !dev->dev->driver ||
1032 - !device_is_registered(dev->dev))
1033 - continue;
1034 - drv = drv_to_ssb_drv(dev->dev->driver);
1035 - if (!drv)
1036 + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
1037 + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
1038 + ssb_device_put(sdev);
1039 continue;
1040 - err = drv->suspend(dev, state);
1041 - if (err) {
1042 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
1043 - dev_name(dev->dev));
1044 - goto err_unwind;
1045 }
1046 + sdrv->remove(sdev);
1047 + ctx->device_frozen[i] = 1;
1048 }
1049
1050 return 0;
1051 -err_unwind:
1052 - for (i--; i >= 0; i--) {
1053 - dev = &(bus->devices[i]);
1054 - if (!dev->dev ||
1055 - !dev->dev->driver ||
1056 - !device_is_registered(dev->dev))
1057 - continue;
1058 - drv = drv_to_ssb_drv(dev->dev->driver);
1059 - if (!drv)
1060 - continue;
1061 - if (drv->resume)
1062 - drv->resume(dev);
1063 - }
1064 - return err;
1065 }
1066
1067 -int ssb_devices_thaw(struct ssb_bus *bus)
1068 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
1069 + *
1070 + * This will re-attach the device drivers and re-init the devices.
1071 + *
1072 + * @ctx: The context structure from ssb_devices_freeze()
1073 + */
1074 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
1075 {
1076 - struct ssb_device *dev;
1077 - struct ssb_driver *drv;
1078 - int err;
1079 - int i;
1080 + struct ssb_bus *bus = ctx->bus;
1081 + struct ssb_device *sdev;
1082 + struct ssb_driver *sdrv;
1083 + unsigned int i;
1084 + int err, result = 0;
1085
1086 for (i = 0; i < bus->nr_devices; i++) {
1087 - dev = &(bus->devices[i]);
1088 - if (!dev->dev ||
1089 - !dev->dev->driver ||
1090 - !device_is_registered(dev->dev))
1091 + if (!ctx->device_frozen[i])
1092 continue;
1093 - drv = drv_to_ssb_drv(dev->dev->driver);
1094 - if (!drv)
1095 + sdev = &bus->devices[i];
1096 +
1097 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
1098 continue;
1099 - if (SSB_WARN_ON(!drv->resume))
1100 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
1101 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
1102 continue;
1103 - err = drv->resume(dev);
1104 +
1105 + err = sdrv->probe(sdev, &sdev->id);
1106 if (err) {
1107 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1108 - dev_name(dev->dev));
1109 + dev_name(sdev->dev));
1110 + result = err;
1111 }
1112 + ssb_driver_put(sdrv);
1113 + ssb_device_put(sdev);
1114 }
1115
1116 - return 0;
1117 + return result;
1118 }
1119 #endif /* CONFIG_SSB_SPROM */
1120
1121 @@ -360,6 +386,35 @@ static int ssb_device_uevent(struct devi
1122 ssb_dev->id.revision);
1123 }
1124
1125 +#define ssb_config_attr(attrib, field, format_string) \
1126 +static ssize_t \
1127 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
1128 +{ \
1129 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
1130 +}
1131 +
1132 +ssb_config_attr(core_num, core_index, "%u\n")
1133 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
1134 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
1135 +ssb_config_attr(revision, id.revision, "%u\n")
1136 +ssb_config_attr(irq, irq, "%u\n")
1137 +static ssize_t
1138 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
1139 +{
1140 + return sprintf(buf, "%s\n",
1141 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
1142 +}
1143 +
1144 +static struct device_attribute ssb_device_attrs[] = {
1145 + __ATTR_RO(name),
1146 + __ATTR_RO(core_num),
1147 + __ATTR_RO(coreid),
1148 + __ATTR_RO(vendor),
1149 + __ATTR_RO(revision),
1150 + __ATTR_RO(irq),
1151 + __ATTR_NULL,
1152 +};
1153 +
1154 static struct bus_type ssb_bustype = {
1155 .name = "ssb",
1156 .match = ssb_bus_match,
1157 @@ -369,6 +424,7 @@ static struct bus_type ssb_bustype = {
1158 .suspend = ssb_device_suspend,
1159 .resume = ssb_device_resume,
1160 .uevent = ssb_device_uevent,
1161 + .dev_attrs = ssb_device_attrs,
1162 };
1163
1164 static void ssb_buses_lock(void)
1165 @@ -461,6 +517,7 @@ static int ssb_devices_register(struct s
1166 #ifdef CONFIG_SSB_PCIHOST
1167 sdev->irq = bus->host_pci->irq;
1168 dev->parent = &bus->host_pci->dev;
1169 + sdev->dma_dev = dev->parent;
1170 #endif
1171 break;
1172 case SSB_BUSTYPE_PCMCIA:
1173 @@ -469,8 +526,14 @@ static int ssb_devices_register(struct s
1174 dev->parent = &bus->host_pcmcia->dev;
1175 #endif
1176 break;
1177 + case SSB_BUSTYPE_SDIO:
1178 +#ifdef CONFIG_SSB_SDIOHOST
1179 + dev->parent = &bus->host_sdio->dev;
1180 +#endif
1181 + break;
1182 case SSB_BUSTYPE_SSB:
1183 dev->dma_mask = &dev->coherent_dma_mask;
1184 + sdev->dma_dev = dev;
1185 break;
1186 }
1187
1188 @@ -497,7 +560,7 @@ error:
1189 }
1190
1191 /* Needs ssb_buses_lock() */
1192 -static int ssb_attach_queued_buses(void)
1193 +static int __devinit ssb_attach_queued_buses(void)
1194 {
1195 struct ssb_bus *bus, *n;
1196 int err = 0;
1197 @@ -708,9 +771,9 @@ out:
1198 return err;
1199 }
1200
1201 -static int ssb_bus_register(struct ssb_bus *bus,
1202 - ssb_invariants_func_t get_invariants,
1203 - unsigned long baseaddr)
1204 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
1205 + ssb_invariants_func_t get_invariants,
1206 + unsigned long baseaddr)
1207 {
1208 int err;
1209
1210 @@ -724,12 +787,18 @@ static int ssb_bus_register(struct ssb_b
1211 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1212 if (err)
1213 goto out;
1214 +
1215 + /* Init SDIO-host device (if any), before the scan */
1216 + err = ssb_sdio_init(bus);
1217 + if (err)
1218 + goto err_disable_xtal;
1219 +
1220 ssb_buses_lock();
1221 bus->busnumber = next_busnumber;
1222 /* Scan for devices (cores) */
1223 err = ssb_bus_scan(bus, baseaddr);
1224 if (err)
1225 - goto err_disable_xtal;
1226 + goto err_sdio_exit;
1227
1228 /* Init PCI-host device (if any) */
1229 err = ssb_pci_init(bus);
1230 @@ -776,6 +845,8 @@ err_pci_exit:
1231 ssb_pci_exit(bus);
1232 err_unmap:
1233 ssb_iounmap(bus);
1234 +err_sdio_exit:
1235 + ssb_sdio_exit(bus);
1236 err_disable_xtal:
1237 ssb_buses_unlock();
1238 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1239 @@ -783,8 +854,8 @@ err_disable_xtal:
1240 }
1241
1242 #ifdef CONFIG_SSB_PCIHOST
1243 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
1244 - struct pci_dev *host_pci)
1245 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
1246 + struct pci_dev *host_pci)
1247 {
1248 int err;
1249
1250 @@ -796,6 +867,9 @@ int ssb_bus_pcibus_register(struct ssb_b
1251 if (!err) {
1252 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1253 "PCI device %s\n", dev_name(&host_pci->dev));
1254 + } else {
1255 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1256 + " of SSB with error %d\n", err);
1257 }
1258
1259 return err;
1260 @@ -804,9 +878,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
1261 #endif /* CONFIG_SSB_PCIHOST */
1262
1263 #ifdef CONFIG_SSB_PCMCIAHOST
1264 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1265 - struct pcmcia_device *pcmcia_dev,
1266 - unsigned long baseaddr)
1267 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1268 + struct pcmcia_device *pcmcia_dev,
1269 + unsigned long baseaddr)
1270 {
1271 int err;
1272
1273 @@ -825,9 +899,32 @@ int ssb_bus_pcmciabus_register(struct ss
1274 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
1275 #endif /* CONFIG_SSB_PCMCIAHOST */
1276
1277 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
1278 - unsigned long baseaddr,
1279 - ssb_invariants_func_t get_invariants)
1280 +#ifdef CONFIG_SSB_SDIOHOST
1281 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
1282 + struct sdio_func *func,
1283 + unsigned int quirks)
1284 +{
1285 + int err;
1286 +
1287 + bus->bustype = SSB_BUSTYPE_SDIO;
1288 + bus->host_sdio = func;
1289 + bus->ops = &ssb_sdio_ops;
1290 + bus->quirks = quirks;
1291 +
1292 + err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1293 + if (!err) {
1294 + ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1295 + "SDIO device %s\n", sdio_func_id(func));
1296 + }
1297 +
1298 + return err;
1299 +}
1300 +EXPORT_SYMBOL(ssb_bus_sdiobus_register);
1301 +#endif /* CONFIG_SSB_PCMCIAHOST */
1302 +
1303 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
1304 + unsigned long baseaddr,
1305 + ssb_invariants_func_t get_invariants)
1306 {
1307 int err;
1308
1309 @@ -908,8 +1005,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
1310 switch (plltype) {
1311 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1312 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1313 - return SSB_CHIPCO_CLK_T6_M0;
1314 - return SSB_CHIPCO_CLK_T6_M1;
1315 + return SSB_CHIPCO_CLK_T6_M1;
1316 + return SSB_CHIPCO_CLK_T6_M0;
1317 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1318 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1319 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1320 @@ -1024,23 +1121,22 @@ static u32 ssb_tmslow_reject_bitmask(str
1321 {
1322 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1323
1324 - /* The REJECT bit changed position in TMSLOW between
1325 - * Backplane revisions. */
1326 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
1327 switch (rev) {
1328 case SSB_IDLOW_SSBREV_22:
1329 - return SSB_TMSLOW_REJECT_22;
1330 + case SSB_IDLOW_SSBREV_24:
1331 + case SSB_IDLOW_SSBREV_26:
1332 + return SSB_TMSLOW_REJECT;
1333 case SSB_IDLOW_SSBREV_23:
1334 return SSB_TMSLOW_REJECT_23;
1335 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
1336 - case SSB_IDLOW_SSBREV_25: /* same here */
1337 - case SSB_IDLOW_SSBREV_26: /* same here */
1338 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1339 case SSB_IDLOW_SSBREV_27: /* same here */
1340 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
1341 + return SSB_TMSLOW_REJECT; /* this is a guess */
1342 default:
1343 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1344 WARN_ON(1);
1345 }
1346 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
1347 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1348 }
1349
1350 int ssb_device_is_enabled(struct ssb_device *dev)
1351 @@ -1099,10 +1195,10 @@ void ssb_device_enable(struct ssb_device
1352 }
1353 EXPORT_SYMBOL(ssb_device_enable);
1354
1355 -/* Wait for a bit in a register to get set or unset.
1356 +/* Wait for bitmask in a register to get set or cleared.
1357 * timeout is in units of ten-microseconds */
1358 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1359 - int timeout, int set)
1360 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1361 + int timeout, int set)
1362 {
1363 int i;
1364 u32 val;
1365 @@ -1110,7 +1206,7 @@ static int ssb_wait_bit(struct ssb_devic
1366 for (i = 0; i < timeout; i++) {
1367 val = ssb_read32(dev, reg);
1368 if (set) {
1369 - if (val & bitmask)
1370 + if ((val & bitmask) == bitmask)
1371 return 0;
1372 } else {
1373 if (!(val & bitmask))
1374 @@ -1127,20 +1223,38 @@ static int ssb_wait_bit(struct ssb_devic
1375
1376 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1377 {
1378 - u32 reject;
1379 + u32 reject, val;
1380
1381 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1382 return;
1383
1384 reject = ssb_tmslow_reject_bitmask(dev);
1385 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1386 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1387 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1388 - ssb_write32(dev, SSB_TMSLOW,
1389 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1390 - reject | SSB_TMSLOW_RESET |
1391 - core_specific_flags);
1392 - ssb_flush_tmslow(dev);
1393 +
1394 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1395 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1396 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1397 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1398 +
1399 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1400 + val = ssb_read32(dev, SSB_IMSTATE);
1401 + val |= SSB_IMSTATE_REJECT;
1402 + ssb_write32(dev, SSB_IMSTATE, val);
1403 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1404 + 0);
1405 + }
1406 +
1407 + ssb_write32(dev, SSB_TMSLOW,
1408 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1409 + reject | SSB_TMSLOW_RESET |
1410 + core_specific_flags);
1411 + ssb_flush_tmslow(dev);
1412 +
1413 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1414 + val = ssb_read32(dev, SSB_IMSTATE);
1415 + val &= ~SSB_IMSTATE_REJECT;
1416 + ssb_write32(dev, SSB_IMSTATE, val);
1417 + }
1418 + }
1419
1420 ssb_write32(dev, SSB_TMSLOW,
1421 reject | SSB_TMSLOW_RESET |
1422 @@ -1149,13 +1263,34 @@ void ssb_device_disable(struct ssb_devic
1423 }
1424 EXPORT_SYMBOL(ssb_device_disable);
1425
1426 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
1427 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1428 +{
1429 + u16 chip_id = dev->bus->chip_id;
1430 +
1431 + if (dev->id.coreid == SSB_DEV_80211) {
1432 + return (chip_id == 0x4322 || chip_id == 43221 ||
1433 + chip_id == 43231 || chip_id == 43222);
1434 + }
1435 +
1436 + return 0;
1437 +}
1438 +
1439 u32 ssb_dma_translation(struct ssb_device *dev)
1440 {
1441 switch (dev->bus->bustype) {
1442 case SSB_BUSTYPE_SSB:
1443 return 0;
1444 case SSB_BUSTYPE_PCI:
1445 - return SSB_PCI_DMA;
1446 + if (dev->bus->host_pci->is_pcie &&
1447 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1448 + return SSB_PCIE_DMA_H32;
1449 + } else {
1450 + if (ssb_dma_translation_special_bit(dev))
1451 + return SSB_PCIE_DMA_H32;
1452 + else
1453 + return SSB_PCI_DMA;
1454 + }
1455 default:
1456 __ssb_dma_not_implemented(dev);
1457 }
1458 @@ -1272,20 +1407,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
1459
1460 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1461 {
1462 - struct ssb_chipcommon *cc;
1463 int err;
1464 enum ssb_clkmode mode;
1465
1466 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1467 if (err)
1468 goto error;
1469 - cc = &bus->chipco;
1470 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1471 - ssb_chipco_set_clockmode(cc, mode);
1472
1473 #ifdef CONFIG_SSB_DEBUG
1474 bus->powered_up = 1;
1475 #endif
1476 +
1477 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1478 + ssb_chipco_set_clockmode(&bus->chipco, mode);
1479 +
1480 return 0;
1481 error:
1482 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1483 @@ -1293,6 +1428,37 @@ error:
1484 }
1485 EXPORT_SYMBOL(ssb_bus_powerup);
1486
1487 +static void ssb_broadcast_value(struct ssb_device *dev,
1488 + u32 address, u32 data)
1489 +{
1490 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1491 + /* This is used for both, PCI and ChipCommon core, so be careful. */
1492 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1493 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1494 +#endif
1495 +
1496 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1497 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1498 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1499 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1500 +}
1501 +
1502 +void ssb_commit_settings(struct ssb_bus *bus)
1503 +{
1504 + struct ssb_device *dev;
1505 +
1506 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1507 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1508 +#else
1509 + dev = bus->chipco.dev;
1510 +#endif
1511 + if (WARN_ON(!dev))
1512 + return;
1513 + /* This forces an update of the cached registers. */
1514 + ssb_broadcast_value(dev, 0xFD8, 0);
1515 +}
1516 +EXPORT_SYMBOL(ssb_commit_settings);
1517 +
1518 u32 ssb_admatch_base(u32 adm)
1519 {
1520 u32 base = 0;
1521 @@ -1358,8 +1524,10 @@ static int __init ssb_modinit(void)
1522 ssb_buses_lock();
1523 err = ssb_attach_queued_buses();
1524 ssb_buses_unlock();
1525 - if (err)
1526 + if (err) {
1527 bus_unregister(&ssb_bustype);
1528 + goto out;
1529 + }
1530
1531 err = b43_pci_ssb_bridge_init();
1532 if (err) {
1533 @@ -1375,7 +1543,7 @@ static int __init ssb_modinit(void)
1534 /* don't fail SSB init because of this */
1535 err = 0;
1536 }
1537 -
1538 +out:
1539 return err;
1540 }
1541 /* ssb must be initialized after PCI but before the ssb drivers.
1542 --- a/drivers/ssb/pci.c
1543 +++ b/drivers/ssb/pci.c
1544 @@ -1,7 +1,7 @@
1545 /*
1546 * Sonics Silicon Backplane PCI-Hostbus related functions.
1547 *
1548 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
1549 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
1550 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1551 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1552 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1553 @@ -17,6 +17,7 @@
1554
1555 #include <linux/ssb/ssb.h>
1556 #include <linux/ssb/ssb_regs.h>
1557 +#include <linux/slab.h>
1558 #include <linux/pci.h>
1559 #include <linux/delay.h>
1560
1561 @@ -167,10 +168,16 @@ err_pci:
1562 }
1563
1564 /* Get the word-offset for a SSB_SPROM_XXX define. */
1565 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
1566 +#define SPOFF(offset) ((offset) / sizeof(u16))
1567 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
1568 -#define SPEX(_outvar, _offset, _mask, _shift) \
1569 +#define SPEX16(_outvar, _offset, _mask, _shift) \
1570 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
1571 +#define SPEX32(_outvar, _offset, _mask, _shift) \
1572 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
1573 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
1574 +#define SPEX(_outvar, _offset, _mask, _shift) \
1575 + SPEX16(_outvar, _offset, _mask, _shift)
1576 +
1577
1578 static inline u8 ssb_crc8(u8 crc, u8 data)
1579 {
1580 @@ -247,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
1581 int i;
1582
1583 for (i = 0; i < bus->sprom_size; i++)
1584 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
1585 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
1586
1587 return 0;
1588 }
1589 @@ -278,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
1590 ssb_printk("75%%");
1591 else if (i % 2)
1592 ssb_printk(".");
1593 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
1594 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1595 mmiowb();
1596 msleep(20);
1597 }
1598 @@ -399,6 +406,46 @@ static void sprom_extract_r123(struct ss
1599 out->antenna_gain.ghz5.a3 = gain;
1600 }
1601
1602 +/* Revs 4 5 and 8 have partially shared layout */
1603 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
1604 +{
1605 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
1606 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
1607 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
1608 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
1609 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
1610 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
1611 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
1612 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
1613 +
1614 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
1615 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
1616 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
1617 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
1618 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
1619 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
1620 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
1621 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
1622 +
1623 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
1624 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
1625 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
1626 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
1627 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
1628 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
1629 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
1630 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
1631 +
1632 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
1633 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
1634 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
1635 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
1636 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
1637 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
1638 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
1639 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
1640 +}
1641 +
1642 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1643 {
1644 int i;
1645 @@ -421,10 +468,14 @@ static void sprom_extract_r45(struct ssb
1646 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1647 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1648 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1649 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1650 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1651 } else {
1652 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1653 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1654 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1655 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1656 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
1657 }
1658 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
1659 SSB_SPROM4_ANTAVAIL_A_SHIFT);
1660 @@ -464,22 +515,32 @@ static void sprom_extract_r45(struct ssb
1661 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1662 sizeof(out->antenna_gain.ghz5));
1663
1664 + sprom_extract_r458(out, in);
1665 +
1666 /* TODO - get remaining rev 4 stuff needed */
1667 }
1668
1669 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1670 {
1671 int i;
1672 - u16 v;
1673 + u16 v, o;
1674 + u16 pwr_info_offset[] = {
1675 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1676 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1677 + };
1678 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1679 + ARRAY_SIZE(out->core_pwr_info));
1680
1681 /* extract the MAC address */
1682 for (i = 0; i < 3; i++) {
1683 - v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
1684 + v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1685 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1686 }
1687 SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
1688 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1689 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
1690 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
1691 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
1692 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
1693 SSB_SPROM8_ANTAVAIL_A_SHIFT);
1694 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
1695 @@ -490,12 +551,55 @@ static void sprom_extract_r8(struct ssb_
1696 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
1697 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
1698 SSB_SPROM8_ITSSI_A_SHIFT);
1699 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
1700 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
1701 + SSB_SPROM8_MAXP_AL_SHIFT);
1702 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
1703 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
1704 SSB_SPROM8_GPIOA_P1_SHIFT);
1705 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
1706 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
1707 SSB_SPROM8_GPIOB_P3_SHIFT);
1708 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
1709 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
1710 + SSB_SPROM8_TRI5G_SHIFT);
1711 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
1712 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
1713 + SSB_SPROM8_TRI5GH_SHIFT);
1714 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
1715 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
1716 + SSB_SPROM8_RXPO5G_SHIFT);
1717 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
1718 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
1719 + SSB_SPROM8_RSSISMC2G_SHIFT);
1720 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
1721 + SSB_SPROM8_RSSISAV2G_SHIFT);
1722 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
1723 + SSB_SPROM8_BXA2G_SHIFT);
1724 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
1725 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
1726 + SSB_SPROM8_RSSISMC5G_SHIFT);
1727 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
1728 + SSB_SPROM8_RSSISAV5G_SHIFT);
1729 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
1730 + SSB_SPROM8_BXA5G_SHIFT);
1731 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
1732 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
1733 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
1734 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
1735 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
1736 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
1737 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
1738 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
1739 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
1740 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
1741 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
1742 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
1743 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
1744 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
1745 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
1746 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
1747 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1748
1749 /* Extract the antenna gain values. */
1750 SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1751 @@ -509,6 +613,63 @@ static void sprom_extract_r8(struct ssb_
1752 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1753 sizeof(out->antenna_gain.ghz5));
1754
1755 + /* Extract cores power info info */
1756 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1757 + o = pwr_info_offset[i];
1758 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1759 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1760 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1761 + SSB_SPROM8_2G_MAXP, 0);
1762 +
1763 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1764 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1765 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1766 +
1767 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1768 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1769 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1770 + SSB_SPROM8_5G_MAXP, 0);
1771 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1772 + SSB_SPROM8_5GH_MAXP, 0);
1773 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1774 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1775 +
1776 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1777 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1778 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1779 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1780 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1781 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1782 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1783 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1784 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1785 + }
1786 +
1787 + /* Extract FEM info */
1788 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1789 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1790 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
1791 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1792 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
1793 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1794 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
1795 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1796 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
1797 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1798 +
1799 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
1800 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1801 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
1802 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1803 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
1804 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1805 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
1806 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1807 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1808 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1809 +
1810 + sprom_extract_r458(out, in);
1811 +
1812 /* TODO - get remaining rev 8 stuff needed */
1813 }
1814
1815 @@ -521,36 +682,34 @@ static int sprom_extract(struct ssb_bus
1816 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1817 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1818 memset(out->et1mac, 0xFF, 6);
1819 +
1820 if ((bus->chip_id & 0xFF00) == 0x4400) {
1821 /* Workaround: The BCM44XX chip has a stupid revision
1822 * number stored in the SPROM.
1823 * Always extract r1. */
1824 out->revision = 1;
1825 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1826 + }
1827 +
1828 + switch (out->revision) {
1829 + case 1:
1830 + case 2:
1831 + case 3:
1832 sprom_extract_r123(out, in);
1833 - } else if (bus->chip_id == 0x4321) {
1834 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
1835 - out->revision = 4;
1836 + break;
1837 + case 4:
1838 + case 5:
1839 sprom_extract_r45(out, in);
1840 - } else {
1841 - switch (out->revision) {
1842 - case 1:
1843 - case 2:
1844 - case 3:
1845 - sprom_extract_r123(out, in);
1846 - break;
1847 - case 4:
1848 - case 5:
1849 - sprom_extract_r45(out, in);
1850 - break;
1851 - case 8:
1852 - sprom_extract_r8(out, in);
1853 - break;
1854 - default:
1855 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1856 - " revision %d detected. Will extract"
1857 - " v1\n", out->revision);
1858 - sprom_extract_r123(out, in);
1859 - }
1860 + break;
1861 + case 8:
1862 + sprom_extract_r8(out, in);
1863 + break;
1864 + default:
1865 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1866 + " revision %d detected. Will extract"
1867 + " v1\n", out->revision);
1868 + out->revision = 1;
1869 + sprom_extract_r123(out, in);
1870 }
1871
1872 if (out->boardflags_lo == 0xFFFF)
1873 @@ -564,13 +723,34 @@ static int sprom_extract(struct ssb_bus
1874 static int ssb_pci_sprom_get(struct ssb_bus *bus,
1875 struct ssb_sprom *sprom)
1876 {
1877 - const struct ssb_sprom *fallback;
1878 - int err = -ENOMEM;
1879 + int err;
1880 u16 *buf;
1881
1882 + if (!ssb_is_sprom_available(bus)) {
1883 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
1884 + return -ENODEV;
1885 + }
1886 + if (bus->chipco.dev) { /* can be unavailable! */
1887 + /*
1888 + * get SPROM offset: SSB_SPROM_BASE1 except for
1889 + * chipcommon rev >= 31 or chip ID is 0x4312 and
1890 + * chipcommon status & 3 == 2
1891 + */
1892 + if (bus->chipco.dev->id.revision >= 31)
1893 + bus->sprom_offset = SSB_SPROM_BASE31;
1894 + else if (bus->chip_id == 0x4312 &&
1895 + (bus->chipco.status & 0x03) == 2)
1896 + bus->sprom_offset = SSB_SPROM_BASE31;
1897 + else
1898 + bus->sprom_offset = SSB_SPROM_BASE1;
1899 + } else {
1900 + bus->sprom_offset = SSB_SPROM_BASE1;
1901 + }
1902 + ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
1903 +
1904 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
1905 if (!buf)
1906 - goto out;
1907 + return -ENOMEM;
1908 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
1909 sprom_do_read(bus, buf);
1910 err = sprom_check_crc(buf, bus->sprom_size);
1911 @@ -580,17 +760,24 @@ static int ssb_pci_sprom_get(struct ssb_
1912 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1913 GFP_KERNEL);
1914 if (!buf)
1915 - goto out;
1916 + return -ENOMEM;
1917 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
1918 sprom_do_read(bus, buf);
1919 err = sprom_check_crc(buf, bus->sprom_size);
1920 if (err) {
1921 /* All CRC attempts failed.
1922 * Maybe there is no SPROM on the device?
1923 - * If we have a fallback, use that. */
1924 - fallback = ssb_get_fallback_sprom();
1925 - if (fallback) {
1926 - memcpy(sprom, fallback, sizeof(*sprom));
1927 + * Now we ask the arch code if there is some sprom
1928 + * available for this device in some other storage */
1929 + err = ssb_fill_sprom_with_fallback(bus, sprom);
1930 + if (err) {
1931 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
1932 + " fallback SPROM failed (err %d)\n",
1933 + err);
1934 + } else {
1935 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1936 + " revision %d provided by"
1937 + " platform.\n", sprom->revision);
1938 err = 0;
1939 goto out_free;
1940 }
1941 @@ -602,19 +789,15 @@ static int ssb_pci_sprom_get(struct ssb_
1942
1943 out_free:
1944 kfree(buf);
1945 -out:
1946 return err;
1947 }
1948
1949 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
1950 struct ssb_boardinfo *bi)
1951 {
1952 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
1953 - &bi->vendor);
1954 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
1955 - &bi->type);
1956 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1957 - &bi->rev);
1958 + bi->vendor = bus->host_pci->subsystem_vendor;
1959 + bi->type = bus->host_pci->subsystem_device;
1960 + bi->rev = bus->host_pci->revision;
1961 }
1962
1963 int ssb_pci_get_invariants(struct ssb_bus *bus,
1964 --- a/drivers/ssb/pcihost_wrapper.c
1965 +++ b/drivers/ssb/pcihost_wrapper.c
1966 @@ -6,12 +6,13 @@
1967 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
1968 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
1969 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
1970 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
1971 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
1972 *
1973 * Licensed under the GNU/GPL. See COPYING for details.
1974 */
1975
1976 #include <linux/pci.h>
1977 +#include <linux/slab.h>
1978 #include <linux/ssb/ssb.h>
1979
1980
1981 @@ -52,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
1982 # define ssb_pcihost_resume NULL
1983 #endif /* CONFIG_PM */
1984
1985 -static int ssb_pcihost_probe(struct pci_dev *dev,
1986 - const struct pci_device_id *id)
1987 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
1988 + const struct pci_device_id *id)
1989 {
1990 struct ssb_bus *ssb;
1991 int err = -ENOMEM;
1992 const char *name;
1993 + u32 val;
1994
1995 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
1996 if (!ssb)
1997 @@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
1998 goto err_pci_disable;
1999 pci_set_master(dev);
2000
2001 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
2002 + * PCI Tx retries from interfering with C3 CPU state */
2003 + pci_read_config_dword(dev, 0x40, &val);
2004 + if ((val & 0x0000ff00) != 0)
2005 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
2006 +
2007 err = ssb_bus_pcibus_register(ssb, dev);
2008 if (err)
2009 goto err_pci_release_regions;
2010 @@ -102,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
2011 pci_set_drvdata(dev, NULL);
2012 }
2013
2014 -int ssb_pcihost_register(struct pci_driver *driver)
2015 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
2016 {
2017 driver->probe = ssb_pcihost_probe;
2018 driver->remove = ssb_pcihost_remove;
2019 --- a/drivers/ssb/pcmcia.c
2020 +++ b/drivers/ssb/pcmcia.c
2021 @@ -3,7 +3,7 @@
2022 * PCMCIA-Hostbus related functions
2023 *
2024 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2025 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2026 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2027 *
2028 * Licensed under the GNU/GPL. See COPYING for details.
2029 */
2030 @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
2031 } \
2032 } while (0)
2033
2034 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
2035 - struct ssb_init_invariants *iv)
2036 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
2037 + tuple_t *tuple,
2038 + void *priv)
2039 +{
2040 + struct ssb_sprom *sprom = priv;
2041 +
2042 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
2043 + return -EINVAL;
2044 + if (tuple->TupleDataLen != ETH_ALEN + 2)
2045 + return -EINVAL;
2046 + if (tuple->TupleData[1] != ETH_ALEN)
2047 + return -EINVAL;
2048 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
2049 + return 0;
2050 +};
2051 +
2052 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
2053 + tuple_t *tuple,
2054 + void *priv)
2055 {
2056 - tuple_t tuple;
2057 - int res;
2058 - unsigned char buf[32];
2059 + struct ssb_init_invariants *iv = priv;
2060 struct ssb_sprom *sprom = &iv->sprom;
2061 struct ssb_boardinfo *bi = &iv->boardinfo;
2062 const char *error_description;
2063
2064 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
2065 + switch (tuple->TupleData[0]) {
2066 + case SSB_PCMCIA_CIS_ID:
2067 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
2068 + (tuple->TupleDataLen != 7),
2069 + "id tpl size");
2070 + bi->vendor = tuple->TupleData[1] |
2071 + ((u16)tuple->TupleData[2] << 8);
2072 + break;
2073 + case SSB_PCMCIA_CIS_BOARDREV:
2074 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2075 + "boardrev tpl size");
2076 + sprom->board_rev = tuple->TupleData[1];
2077 + break;
2078 + case SSB_PCMCIA_CIS_PA:
2079 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
2080 + (tuple->TupleDataLen != 10),
2081 + "pa tpl size");
2082 + sprom->pa0b0 = tuple->TupleData[1] |
2083 + ((u16)tuple->TupleData[2] << 8);
2084 + sprom->pa0b1 = tuple->TupleData[3] |
2085 + ((u16)tuple->TupleData[4] << 8);
2086 + sprom->pa0b2 = tuple->TupleData[5] |
2087 + ((u16)tuple->TupleData[6] << 8);
2088 + sprom->itssi_a = tuple->TupleData[7];
2089 + sprom->itssi_bg = tuple->TupleData[7];
2090 + sprom->maxpwr_a = tuple->TupleData[8];
2091 + sprom->maxpwr_bg = tuple->TupleData[8];
2092 + break;
2093 + case SSB_PCMCIA_CIS_OEMNAME:
2094 + /* We ignore this. */
2095 + break;
2096 + case SSB_PCMCIA_CIS_CCODE:
2097 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2098 + "ccode tpl size");
2099 + sprom->country_code = tuple->TupleData[1];
2100 + break;
2101 + case SSB_PCMCIA_CIS_ANTENNA:
2102 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2103 + "ant tpl size");
2104 + sprom->ant_available_a = tuple->TupleData[1];
2105 + sprom->ant_available_bg = tuple->TupleData[1];
2106 + break;
2107 + case SSB_PCMCIA_CIS_ANTGAIN:
2108 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2109 + "antg tpl size");
2110 + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
2111 + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
2112 + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
2113 + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
2114 + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
2115 + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
2116 + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
2117 + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
2118 + break;
2119 + case SSB_PCMCIA_CIS_BFLAGS:
2120 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
2121 + (tuple->TupleDataLen != 5),
2122 + "bfl tpl size");
2123 + sprom->boardflags_lo = tuple->TupleData[1] |
2124 + ((u16)tuple->TupleData[2] << 8);
2125 + break;
2126 + case SSB_PCMCIA_CIS_LEDS:
2127 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
2128 + "leds tpl size");
2129 + sprom->gpio0 = tuple->TupleData[1];
2130 + sprom->gpio1 = tuple->TupleData[2];
2131 + sprom->gpio2 = tuple->TupleData[3];
2132 + sprom->gpio3 = tuple->TupleData[4];
2133 + break;
2134 + }
2135 + return -ENOSPC; /* continue with next entry */
2136 +
2137 +error:
2138 + ssb_printk(KERN_ERR PFX
2139 + "PCMCIA: Failed to fetch device invariants: %s\n",
2140 + error_description);
2141 + return -ENODEV;
2142 +}
2143 +
2144 +
2145 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
2146 + struct ssb_init_invariants *iv)
2147 +{
2148 + struct ssb_sprom *sprom = &iv->sprom;
2149 + int res;
2150 +
2151 memset(sprom, 0xFF, sizeof(*sprom));
2152 sprom->revision = 1;
2153 sprom->boardflags_lo = 0;
2154 sprom->boardflags_hi = 0;
2155
2156 /* First fetch the MAC address. */
2157 - memset(&tuple, 0, sizeof(tuple));
2158 - tuple.DesiredTuple = CISTPL_FUNCE;
2159 - tuple.TupleData = buf;
2160 - tuple.TupleDataMax = sizeof(buf);
2161 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
2162 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
2163 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2164 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
2165 - while (1) {
2166 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
2167 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
2168 - break;
2169 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2170 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
2171 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2172 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
2173 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
2174 + ssb_pcmcia_get_mac, sprom);
2175 + if (res != 0) {
2176 + ssb_printk(KERN_ERR PFX
2177 + "PCMCIA: Failed to fetch MAC address\n");
2178 + return -ENODEV;
2179 }
2180 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
2181 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
2182
2183 /* Fetch the vendor specific tuples. */
2184 - memset(&tuple, 0, sizeof(tuple));
2185 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
2186 - tuple.TupleData = buf;
2187 - tuple.TupleDataMax = sizeof(buf);
2188 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
2189 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
2190 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2191 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
2192 - while (1) {
2193 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
2194 - switch (tuple.TupleData[0]) {
2195 - case SSB_PCMCIA_CIS_ID:
2196 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
2197 - (tuple.TupleDataLen != 7),
2198 - "id tpl size");
2199 - bi->vendor = tuple.TupleData[1] |
2200 - ((u16)tuple.TupleData[2] << 8);
2201 - break;
2202 - case SSB_PCMCIA_CIS_BOARDREV:
2203 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2204 - "boardrev tpl size");
2205 - sprom->board_rev = tuple.TupleData[1];
2206 - break;
2207 - case SSB_PCMCIA_CIS_PA:
2208 - GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
2209 - (tuple.TupleDataLen != 10),
2210 - "pa tpl size");
2211 - sprom->pa0b0 = tuple.TupleData[1] |
2212 - ((u16)tuple.TupleData[2] << 8);
2213 - sprom->pa0b1 = tuple.TupleData[3] |
2214 - ((u16)tuple.TupleData[4] << 8);
2215 - sprom->pa0b2 = tuple.TupleData[5] |
2216 - ((u16)tuple.TupleData[6] << 8);
2217 - sprom->itssi_a = tuple.TupleData[7];
2218 - sprom->itssi_bg = tuple.TupleData[7];
2219 - sprom->maxpwr_a = tuple.TupleData[8];
2220 - sprom->maxpwr_bg = tuple.TupleData[8];
2221 - break;
2222 - case SSB_PCMCIA_CIS_OEMNAME:
2223 - /* We ignore this. */
2224 - break;
2225 - case SSB_PCMCIA_CIS_CCODE:
2226 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2227 - "ccode tpl size");
2228 - sprom->country_code = tuple.TupleData[1];
2229 - break;
2230 - case SSB_PCMCIA_CIS_ANTENNA:
2231 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2232 - "ant tpl size");
2233 - sprom->ant_available_a = tuple.TupleData[1];
2234 - sprom->ant_available_bg = tuple.TupleData[1];
2235 - break;
2236 - case SSB_PCMCIA_CIS_ANTGAIN:
2237 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2238 - "antg tpl size");
2239 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
2240 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
2241 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
2242 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
2243 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
2244 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
2245 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
2246 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
2247 - break;
2248 - case SSB_PCMCIA_CIS_BFLAGS:
2249 - GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
2250 - (tuple.TupleDataLen != 5),
2251 - "bfl tpl size");
2252 - sprom->boardflags_lo = tuple.TupleData[1] |
2253 - ((u16)tuple.TupleData[2] << 8);
2254 - break;
2255 - case SSB_PCMCIA_CIS_LEDS:
2256 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
2257 - "leds tpl size");
2258 - sprom->gpio0 = tuple.TupleData[1];
2259 - sprom->gpio1 = tuple.TupleData[2];
2260 - sprom->gpio2 = tuple.TupleData[3];
2261 - sprom->gpio3 = tuple.TupleData[4];
2262 - break;
2263 - }
2264 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2265 - if (res == -ENOSPC)
2266 - break;
2267 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
2268 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2269 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
2270 - }
2271 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
2272 + ssb_pcmcia_do_get_invariants, iv);
2273 + if ((res == 0) || (res == -ENOSPC))
2274 + return 0;
2275
2276 - return 0;
2277 -error:
2278 ssb_printk(KERN_ERR PFX
2279 - "PCMCIA: Failed to fetch device invariants: %s\n",
2280 - error_description);
2281 + "PCMCIA: Failed to fetch device invariants\n");
2282 return -ENODEV;
2283 }
2284
2285 --- a/drivers/ssb/scan.c
2286 +++ b/drivers/ssb/scan.c
2287 @@ -2,7 +2,7 @@
2288 * Sonics Silicon Backplane
2289 * Bus scanning
2290 *
2291 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
2292 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
2293 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
2294 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
2295 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
2296 @@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid)
2297 static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
2298 u16 offset)
2299 {
2300 + u32 lo, hi;
2301 +
2302 switch (bus->bustype) {
2303 case SSB_BUSTYPE_SSB:
2304 offset += current_coreidx * SSB_CORE_SIZE;
2305 @@ -174,7 +176,12 @@ static u32 scan_read32(struct ssb_bus *b
2306 offset -= 0x800;
2307 } else
2308 ssb_pcmcia_switch_segment(bus, 0);
2309 - break;
2310 + lo = readw(bus->mmio + offset);
2311 + hi = readw(bus->mmio + offset + 2);
2312 + return lo | (hi << 16);
2313 + case SSB_BUSTYPE_SDIO:
2314 + offset += current_coreidx * SSB_CORE_SIZE;
2315 + return ssb_sdio_scan_read32(bus, offset);
2316 }
2317 return readl(bus->mmio + offset);
2318 }
2319 @@ -188,6 +195,8 @@ static int scan_switchcore(struct ssb_bu
2320 return ssb_pci_switch_coreidx(bus, coreidx);
2321 case SSB_BUSTYPE_PCMCIA:
2322 return ssb_pcmcia_switch_coreidx(bus, coreidx);
2323 + case SSB_BUSTYPE_SDIO:
2324 + return ssb_sdio_scan_switch_coreidx(bus, coreidx);
2325 }
2326 return 0;
2327 }
2328 @@ -206,6 +215,8 @@ void ssb_iounmap(struct ssb_bus *bus)
2329 SSB_BUG_ON(1); /* Can't reach this code. */
2330 #endif
2331 break;
2332 + case SSB_BUSTYPE_SDIO:
2333 + break;
2334 }
2335 bus->mmio = NULL;
2336 bus->mapped_device = NULL;
2337 @@ -230,6 +241,10 @@ static void __iomem *ssb_ioremap(struct
2338 SSB_BUG_ON(1); /* Can't reach this code. */
2339 #endif
2340 break;
2341 + case SSB_BUSTYPE_SDIO:
2342 + /* Nothing to ioremap in the SDIO case, just fake it */
2343 + mmio = (void __iomem *)baseaddr;
2344 + break;
2345 }
2346
2347 return mmio;
2348 @@ -245,7 +260,10 @@ static int we_support_multiple_80211_cor
2349 #ifdef CONFIG_SSB_PCIHOST
2350 if (bus->bustype == SSB_BUSTYPE_PCI) {
2351 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2352 - bus->host_pci->device == 0x4324)
2353 + ((bus->host_pci->device == 0x4313) ||
2354 + (bus->host_pci->device == 0x431A) ||
2355 + (bus->host_pci->device == 0x4321) ||
2356 + (bus->host_pci->device == 0x4324)))
2357 return 1;
2358 }
2359 #endif /* CONFIG_SSB_PCIHOST */
2360 @@ -294,8 +312,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2361 } else {
2362 if (bus->bustype == SSB_BUSTYPE_PCI) {
2363 bus->chip_id = pcidev_to_chipid(bus->host_pci);
2364 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
2365 - &bus->chip_rev);
2366 + bus->chip_rev = bus->host_pci->revision;
2367 bus->chip_package = 0;
2368 } else {
2369 bus->chip_id = 0x4710;
2370 @@ -339,7 +356,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2371 dev->bus = bus;
2372 dev->ops = bus->ops;
2373
2374 - ssb_dprintk(KERN_INFO PFX
2375 + printk(KERN_DEBUG PFX
2376 "Core %d found: %s "
2377 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
2378 i, ssb_core_name(dev->id.coreid),
2379 @@ -407,6 +424,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
2380 bus->pcicore.dev = dev;
2381 #endif /* CONFIG_SSB_DRIVER_PCICORE */
2382 break;
2383 + case SSB_DEV_ETHERNET:
2384 + if (bus->bustype == SSB_BUSTYPE_PCI) {
2385 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2386 + (bus->host_pci->device & 0xFF00) == 0x4300) {
2387 + /* This is a dangling ethernet core on a
2388 + * wireless device. Ignore it. */
2389 + continue;
2390 + }
2391 + }
2392 + break;
2393 default:
2394 break;
2395 }
2396 --- /dev/null
2397 +++ b/drivers/ssb/sdio.c
2398 @@ -0,0 +1,610 @@
2399 +/*
2400 + * Sonics Silicon Backplane
2401 + * SDIO-Hostbus related functions
2402 + *
2403 + * Copyright 2009 Albert Herranz <albert_herranz@yahoo.es>
2404 + *
2405 + * Based on drivers/ssb/pcmcia.c
2406 + * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2407 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2408 + *
2409 + * Licensed under the GNU/GPL. See COPYING for details.
2410 + *
2411 + */
2412 +
2413 +#include <linux/ssb/ssb.h>
2414 +#include <linux/delay.h>
2415 +#include <linux/io.h>
2416 +#include <linux/etherdevice.h>
2417 +#include <linux/mmc/sdio_func.h>
2418 +
2419 +#include "ssb_private.h"
2420 +
2421 +/* Define the following to 1 to enable a printk on each coreswitch. */
2422 +#define SSB_VERBOSE_SDIOCORESWITCH_DEBUG 0
2423 +
2424 +
2425 +/* Hardware invariants CIS tuples */
2426 +#define SSB_SDIO_CIS 0x80
2427 +#define SSB_SDIO_CIS_SROMREV 0x00
2428 +#define SSB_SDIO_CIS_ID 0x01
2429 +#define SSB_SDIO_CIS_BOARDREV 0x02
2430 +#define SSB_SDIO_CIS_PA 0x03
2431 +#define SSB_SDIO_CIS_PA_PA0B0_LO 0
2432 +#define SSB_SDIO_CIS_PA_PA0B0_HI 1
2433 +#define SSB_SDIO_CIS_PA_PA0B1_LO 2
2434 +#define SSB_SDIO_CIS_PA_PA0B1_HI 3
2435 +#define SSB_SDIO_CIS_PA_PA0B2_LO 4
2436 +#define SSB_SDIO_CIS_PA_PA0B2_HI 5
2437 +#define SSB_SDIO_CIS_PA_ITSSI 6
2438 +#define SSB_SDIO_CIS_PA_MAXPOW 7
2439 +#define SSB_SDIO_CIS_OEMNAME 0x04
2440 +#define SSB_SDIO_CIS_CCODE 0x05
2441 +#define SSB_SDIO_CIS_ANTENNA 0x06
2442 +#define SSB_SDIO_CIS_ANTGAIN 0x07
2443 +#define SSB_SDIO_CIS_BFLAGS 0x08
2444 +#define SSB_SDIO_CIS_LEDS 0x09
2445 +
2446 +#define CISTPL_FUNCE_LAN_NODE_ID 0x04 /* same as in PCMCIA */
2447 +
2448 +
2449 +/*
2450 + * Function 1 miscellaneous registers.
2451 + *
2452 + * Definitions match src/include/sbsdio.h from the
2453 + * Android Open Source Project
2454 + * http://android.git.kernel.org/?p=platform/system/wlan/broadcom.git
2455 + *
2456 + */
2457 +#define SBSDIO_FUNC1_SBADDRLOW 0x1000a /* SB Address window Low (b15) */
2458 +#define SBSDIO_FUNC1_SBADDRMID 0x1000b /* SB Address window Mid (b23-b16) */
2459 +#define SBSDIO_FUNC1_SBADDRHIGH 0x1000c /* SB Address window High (b24-b31) */
2460 +
2461 +/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
2462 +#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid address bits in SBADDRLOW */
2463 +#define SBSDIO_SBADDRMID_MASK 0xff /* Valid address bits in SBADDRMID */
2464 +#define SBSDIO_SBADDRHIGH_MASK 0xff /* Valid address bits in SBADDRHIGH */
2465 +
2466 +#define SBSDIO_SB_OFT_ADDR_MASK 0x7FFF /* sb offset addr is <= 15 bits, 32k */
2467 +
2468 +/* REVISIT: this flag doesn't seem to matter */
2469 +#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x8000 /* forces 32-bit SB access */
2470 +
2471 +
2472 +/*
2473 + * Address map within the SDIO function address space (128K).
2474 + *
2475 + * Start End Description
2476 + * ------- ------- ------------------------------------------
2477 + * 0x00000 0x0ffff selected backplane address window (64K)
2478 + * 0x10000 0x1ffff backplane control registers (max 64K)
2479 + *
2480 + * The current address window is configured by writing to registers
2481 + * SBADDRLOW, SBADDRMID and SBADDRHIGH.
2482 + *
2483 + * In order to access the contents of a 32-bit Silicon Backplane address
2484 + * the backplane address window must be first loaded with the highest
2485 + * 16 bits of the target address. Then, an access must be done to the
2486 + * SDIO function address space using the lower 15 bits of the address.
2487 + * Bit 15 of the address must be set when doing 32 bit accesses.
2488 + *
2489 + * 10987654321098765432109876543210
2490 + * WWWWWWWWWWWWWWWWW SB Address Window
2491 + * OOOOOOOOOOOOOOOO Offset within SB Address Window
2492 + * a 32-bit access flag
2493 + */
2494 +
2495 +
2496 +/*
2497 + * SSB I/O via SDIO.
2498 + *
2499 + * NOTE: SDIO address @addr is 17 bits long (SDIO address space is 128K).
2500 + */
2501 +
2502 +static inline struct device *ssb_sdio_dev(struct ssb_bus *bus)
2503 +{
2504 + return &bus->host_sdio->dev;
2505 +}
2506 +
2507 +/* host claimed */
2508 +static int ssb_sdio_writeb(struct ssb_bus *bus, unsigned int addr, u8 val)
2509 +{
2510 + int error = 0;
2511 +
2512 + sdio_writeb(bus->host_sdio, val, addr, &error);
2513 + if (unlikely(error)) {
2514 + dev_dbg(ssb_sdio_dev(bus), "%08X <- %02x, error %d\n",
2515 + addr, val, error);
2516 + }
2517 +
2518 + return error;
2519 +}
2520 +
2521 +#if 0
2522 +static u8 ssb_sdio_readb(struct ssb_bus *bus, unsigned int addr)
2523 +{
2524 + u8 val;
2525 + int error = 0;
2526 +
2527 + val = sdio_readb(bus->host_sdio, addr, &error);
2528 + if (unlikely(error)) {
2529 + dev_dbg(ssb_sdio_dev(bus), "%08X -> %02x, error %d\n",
2530 + addr, val, error);
2531 + }
2532 +
2533 + return val;
2534 +}
2535 +#endif
2536 +
2537 +/* host claimed */
2538 +static int ssb_sdio_set_sbaddr_window(struct ssb_bus *bus, u32 address)
2539 +{
2540 + int error;
2541 +
2542 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRLOW,
2543 + (address >> 8) & SBSDIO_SBADDRLOW_MASK);
2544 + if (error)
2545 + goto out;
2546 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRMID,
2547 + (address >> 16) & SBSDIO_SBADDRMID_MASK);
2548 + if (error)
2549 + goto out;
2550 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRHIGH,
2551 + (address >> 24) & SBSDIO_SBADDRHIGH_MASK);
2552 + if (error)
2553 + goto out;
2554 + bus->sdio_sbaddr = address;
2555 +out:
2556 + if (error) {
2557 + dev_dbg(ssb_sdio_dev(bus), "failed to set address window"
2558 + " to 0x%08x, error %d\n", address, error);
2559 + }
2560 +
2561 + return error;
2562 +}
2563 +
2564 +/* for enumeration use only */
2565 +u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset)
2566 +{
2567 + u32 val;
2568 + int error;
2569 +
2570 + sdio_claim_host(bus->host_sdio);
2571 + val = sdio_readl(bus->host_sdio, offset, &error);
2572 + sdio_release_host(bus->host_sdio);
2573 + if (unlikely(error)) {
2574 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n",
2575 + bus->sdio_sbaddr >> 16, offset, val, error);
2576 + }
2577 +
2578 + return val;
2579 +}
2580 +
2581 +/* for enumeration use only */
2582 +int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
2583 +{
2584 + u32 sbaddr;
2585 + int error;
2586 +
2587 + sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
2588 + sdio_claim_host(bus->host_sdio);
2589 + error = ssb_sdio_set_sbaddr_window(bus, sbaddr);
2590 + sdio_release_host(bus->host_sdio);
2591 + if (error) {
2592 + dev_err(ssb_sdio_dev(bus), "failed to switch to core %u,"
2593 + " error %d\n", coreidx, error);
2594 + goto out;
2595 + }
2596 +out:
2597 + return error;
2598 +}
2599 +
2600 +/* host must be already claimed */
2601 +int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev)
2602 +{
2603 + u8 coreidx = dev->core_index;
2604 + u32 sbaddr;
2605 + int error = 0;
2606 +
2607 + sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
2608 + if (unlikely(bus->sdio_sbaddr != sbaddr)) {
2609 +#if SSB_VERBOSE_SDIOCORESWITCH_DEBUG
2610 + dev_info(ssb_sdio_dev(bus),
2611 + "switching to %s core, index %d\n",
2612 + ssb_core_name(dev->id.coreid), coreidx);
2613 +#endif
2614 + error = ssb_sdio_set_sbaddr_window(bus, sbaddr);
2615 + if (error) {
2616 + dev_dbg(ssb_sdio_dev(bus), "failed to switch to"
2617 + " core %u, error %d\n", coreidx, error);
2618 + goto out;
2619 + }
2620 + bus->mapped_device = dev;
2621 + }
2622 +
2623 +out:
2624 + return error;
2625 +}
2626 +
2627 +static u8 ssb_sdio_read8(struct ssb_device *dev, u16 offset)
2628 +{
2629 + struct ssb_bus *bus = dev->bus;
2630 + u8 val = 0xff;
2631 + int error = 0;
2632 +
2633 + sdio_claim_host(bus->host_sdio);
2634 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2635 + goto out;
2636 + offset |= bus->sdio_sbaddr & 0xffff;
2637 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2638 + val = sdio_readb(bus->host_sdio, offset, &error);
2639 + if (error) {
2640 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %02x, error %d\n",
2641 + bus->sdio_sbaddr >> 16, offset, val, error);
2642 + }
2643 +out:
2644 + sdio_release_host(bus->host_sdio);
2645 +
2646 + return val;
2647 +}
2648 +
2649 +static u16 ssb_sdio_read16(struct ssb_device *dev, u16 offset)
2650 +{
2651 + struct ssb_bus *bus = dev->bus;
2652 + u16 val = 0xffff;
2653 + int error = 0;
2654 +
2655 + sdio_claim_host(bus->host_sdio);
2656 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2657 + goto out;
2658 + offset |= bus->sdio_sbaddr & 0xffff;
2659 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2660 + val = sdio_readw(bus->host_sdio, offset, &error);
2661 + if (error) {
2662 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %04x, error %d\n",
2663 + bus->sdio_sbaddr >> 16, offset, val, error);
2664 + }
2665 +out:
2666 + sdio_release_host(bus->host_sdio);
2667 +
2668 + return val;
2669 +}
2670 +
2671 +static u32 ssb_sdio_read32(struct ssb_device *dev, u16 offset)
2672 +{
2673 + struct ssb_bus *bus = dev->bus;
2674 + u32 val = 0xffffffff;
2675 + int error = 0;
2676 +
2677 + sdio_claim_host(bus->host_sdio);
2678 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2679 + goto out;
2680 + offset |= bus->sdio_sbaddr & 0xffff;
2681 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2682 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2683 + val = sdio_readl(bus->host_sdio, offset, &error);
2684 + if (error) {
2685 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n",
2686 + bus->sdio_sbaddr >> 16, offset, val, error);
2687 + }
2688 +out:
2689 + sdio_release_host(bus->host_sdio);
2690 +
2691 + return val;
2692 +}
2693 +
2694 +#ifdef CONFIG_SSB_BLOCKIO
2695 +static void ssb_sdio_block_read(struct ssb_device *dev, void *buffer,
2696 + size_t count, u16 offset, u8 reg_width)
2697 +{
2698 + size_t saved_count = count;
2699 + struct ssb_bus *bus = dev->bus;
2700 + int error = 0;
2701 +
2702 + sdio_claim_host(bus->host_sdio);
2703 + if (unlikely(ssb_sdio_switch_core(bus, dev))) {
2704 + error = -EIO;
2705 + memset(buffer, 0xff, count);
2706 + goto err_out;
2707 + }
2708 + offset |= bus->sdio_sbaddr & 0xffff;
2709 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2710 +
2711 + switch (reg_width) {
2712 + case sizeof(u8): {
2713 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2714 + break;
2715 + }
2716 + case sizeof(u16): {
2717 + SSB_WARN_ON(count & 1);
2718 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2719 + break;
2720 + }
2721 + case sizeof(u32): {
2722 + SSB_WARN_ON(count & 3);
2723 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2724 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2725 + break;
2726 + }
2727 + default:
2728 + SSB_WARN_ON(1);
2729 + }
2730 + if (!error)
2731 + goto out;
2732 +
2733 +err_out:
2734 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n",
2735 + bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error);
2736 +out:
2737 + sdio_release_host(bus->host_sdio);
2738 +}
2739 +#endif /* CONFIG_SSB_BLOCKIO */
2740 +
2741 +static void ssb_sdio_write8(struct ssb_device *dev, u16 offset, u8 val)
2742 +{
2743 + struct ssb_bus *bus = dev->bus;
2744 + int error = 0;
2745 +
2746 + sdio_claim_host(bus->host_sdio);
2747 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2748 + goto out;
2749 + offset |= bus->sdio_sbaddr & 0xffff;
2750 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2751 + sdio_writeb(bus->host_sdio, val, offset, &error);
2752 + if (error) {
2753 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %02x, error %d\n",
2754 + bus->sdio_sbaddr >> 16, offset, val, error);
2755 + }
2756 +out:
2757 + sdio_release_host(bus->host_sdio);
2758 +}
2759 +
2760 +static void ssb_sdio_write16(struct ssb_device *dev, u16 offset, u16 val)
2761 +{
2762 + struct ssb_bus *bus = dev->bus;
2763 + int error = 0;
2764 +
2765 + sdio_claim_host(bus->host_sdio);
2766 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2767 + goto out;
2768 + offset |= bus->sdio_sbaddr & 0xffff;
2769 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2770 + sdio_writew(bus->host_sdio, val, offset, &error);
2771 + if (error) {
2772 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %04x, error %d\n",
2773 + bus->sdio_sbaddr >> 16, offset, val, error);
2774 + }
2775 +out:
2776 + sdio_release_host(bus->host_sdio);
2777 +}
2778 +
2779 +static void ssb_sdio_write32(struct ssb_device *dev, u16 offset, u32 val)
2780 +{
2781 + struct ssb_bus *bus = dev->bus;
2782 + int error = 0;
2783 +
2784 + sdio_claim_host(bus->host_sdio);
2785 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2786 + goto out;
2787 + offset |= bus->sdio_sbaddr & 0xffff;
2788 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2789 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2790 + sdio_writel(bus->host_sdio, val, offset, &error);
2791 + if (error) {
2792 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %08x, error %d\n",
2793 + bus->sdio_sbaddr >> 16, offset, val, error);
2794 + }
2795 + if (bus->quirks & SSB_QUIRK_SDIO_READ_AFTER_WRITE32)
2796 + sdio_readl(bus->host_sdio, 0, &error);
2797 +out:
2798 + sdio_release_host(bus->host_sdio);
2799 +}
2800 +
2801 +#ifdef CONFIG_SSB_BLOCKIO
2802 +static void ssb_sdio_block_write(struct ssb_device *dev, const void *buffer,
2803 + size_t count, u16 offset, u8 reg_width)
2804 +{
2805 + size_t saved_count = count;
2806 + struct ssb_bus *bus = dev->bus;
2807 + int error = 0;
2808 +
2809 + sdio_claim_host(bus->host_sdio);
2810 + if (unlikely(ssb_sdio_switch_core(bus, dev))) {
2811 + error = -EIO;
2812 + memset((void *)buffer, 0xff, count);
2813 + goto err_out;
2814 + }
2815 + offset |= bus->sdio_sbaddr & 0xffff;
2816 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2817 +
2818 + switch (reg_width) {
2819 + case sizeof(u8):
2820 + error = sdio_writesb(bus->host_sdio, offset,
2821 + (void *)buffer, count);
2822 + break;
2823 + case sizeof(u16):
2824 + SSB_WARN_ON(count & 1);
2825 + error = sdio_writesb(bus->host_sdio, offset,
2826 + (void *)buffer, count);
2827 + break;
2828 + case sizeof(u32):
2829 + SSB_WARN_ON(count & 3);
2830 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2831 + error = sdio_writesb(bus->host_sdio, offset,
2832 + (void *)buffer, count);
2833 + break;
2834 + default:
2835 + SSB_WARN_ON(1);
2836 + }
2837 + if (!error)
2838 + goto out;
2839 +
2840 +err_out:
2841 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n",
2842 + bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error);
2843 +out:
2844 + sdio_release_host(bus->host_sdio);
2845 +}
2846 +
2847 +#endif /* CONFIG_SSB_BLOCKIO */
2848 +
2849 +/* Not "static", as it's used in main.c */
2850 +const struct ssb_bus_ops ssb_sdio_ops = {
2851 + .read8 = ssb_sdio_read8,
2852 + .read16 = ssb_sdio_read16,
2853 + .read32 = ssb_sdio_read32,
2854 + .write8 = ssb_sdio_write8,
2855 + .write16 = ssb_sdio_write16,
2856 + .write32 = ssb_sdio_write32,
2857 +#ifdef CONFIG_SSB_BLOCKIO
2858 + .block_read = ssb_sdio_block_read,
2859 + .block_write = ssb_sdio_block_write,
2860 +#endif
2861 +};
2862 +
2863 +#define GOTO_ERROR_ON(condition, description) do { \
2864 + if (unlikely(condition)) { \
2865 + error_description = description; \
2866 + goto error; \
2867 + } \
2868 + } while (0)
2869 +
2870 +int ssb_sdio_get_invariants(struct ssb_bus *bus,
2871 + struct ssb_init_invariants *iv)
2872 +{
2873 + struct ssb_sprom *sprom = &iv->sprom;
2874 + struct ssb_boardinfo *bi = &iv->boardinfo;
2875 + const char *error_description = "none";
2876 + struct sdio_func_tuple *tuple;
2877 + void *mac;
2878 +
2879 + memset(sprom, 0xFF, sizeof(*sprom));
2880 + sprom->boardflags_lo = 0;
2881 + sprom->boardflags_hi = 0;
2882 +
2883 + tuple = bus->host_sdio->tuples;
2884 + while (tuple) {
2885 + switch (tuple->code) {
2886 + case 0x22: /* extended function */
2887 + switch (tuple->data[0]) {
2888 + case CISTPL_FUNCE_LAN_NODE_ID:
2889 + GOTO_ERROR_ON((tuple->size != 7) &&
2890 + (tuple->data[1] != 6),
2891 + "mac tpl size");
2892 + /* fetch the MAC address. */
2893 + mac = tuple->data + 2;
2894 + memcpy(sprom->il0mac, mac, ETH_ALEN);
2895 + memcpy(sprom->et1mac, mac, ETH_ALEN);
2896 + break;
2897 + default:
2898 + break;
2899 + }
2900 + break;
2901 + case 0x80: /* vendor specific tuple */
2902 + switch (tuple->data[0]) {
2903 + case SSB_SDIO_CIS_SROMREV:
2904 + GOTO_ERROR_ON(tuple->size != 2,
2905 + "sromrev tpl size");
2906 + sprom->revision = tuple->data[1];
2907 + break;
2908 + case SSB_SDIO_CIS_ID:
2909 + GOTO_ERROR_ON((tuple->size != 5) &&
2910 + (tuple->size != 7),
2911 + "id tpl size");
2912 + bi->vendor = tuple->data[1] |
2913 + (tuple->data[2]<<8);
2914 + break;
2915 + case SSB_SDIO_CIS_BOARDREV:
2916 + GOTO_ERROR_ON(tuple->size != 2,
2917 + "boardrev tpl size");
2918 + sprom->board_rev = tuple->data[1];
2919 + break;
2920 + case SSB_SDIO_CIS_PA:
2921 + GOTO_ERROR_ON((tuple->size != 9) &&
2922 + (tuple->size != 10),
2923 + "pa tpl size");
2924 + sprom->pa0b0 = tuple->data[1] |
2925 + ((u16)tuple->data[2] << 8);
2926 + sprom->pa0b1 = tuple->data[3] |
2927 + ((u16)tuple->data[4] << 8);
2928 + sprom->pa0b2 = tuple->data[5] |
2929 + ((u16)tuple->data[6] << 8);
2930 + sprom->itssi_a = tuple->data[7];
2931 + sprom->itssi_bg = tuple->data[7];
2932 + sprom->maxpwr_a = tuple->data[8];
2933 + sprom->maxpwr_bg = tuple->data[8];
2934 + break;
2935 + case SSB_SDIO_CIS_OEMNAME:
2936 + /* Not present */
2937 + break;
2938 + case SSB_SDIO_CIS_CCODE:
2939 + GOTO_ERROR_ON(tuple->size != 2,
2940 + "ccode tpl size");
2941 + sprom->country_code = tuple->data[1];
2942 + break;
2943 + case SSB_SDIO_CIS_ANTENNA:
2944 + GOTO_ERROR_ON(tuple->size != 2,
2945 + "ant tpl size");
2946 + sprom->ant_available_a = tuple->data[1];
2947 + sprom->ant_available_bg = tuple->data[1];
2948 + break;
2949 + case SSB_SDIO_CIS_ANTGAIN:
2950 + GOTO_ERROR_ON(tuple->size != 2,
2951 + "antg tpl size");
2952 + sprom->antenna_gain.ghz24.a0 = tuple->data[1];
2953 + sprom->antenna_gain.ghz24.a1 = tuple->data[1];
2954 + sprom->antenna_gain.ghz24.a2 = tuple->data[1];
2955 + sprom->antenna_gain.ghz24.a3 = tuple->data[1];
2956 + sprom->antenna_gain.ghz5.a0 = tuple->data[1];
2957 + sprom->antenna_gain.ghz5.a1 = tuple->data[1];
2958 + sprom->antenna_gain.ghz5.a2 = tuple->data[1];
2959 + sprom->antenna_gain.ghz5.a3 = tuple->data[1];
2960 + break;
2961 + case SSB_SDIO_CIS_BFLAGS:
2962 + GOTO_ERROR_ON((tuple->size != 3) &&
2963 + (tuple->size != 5),
2964 + "bfl tpl size");
2965 + sprom->boardflags_lo = tuple->data[1] |
2966 + ((u16)tuple->data[2] << 8);
2967 + break;
2968 + case SSB_SDIO_CIS_LEDS:
2969 + GOTO_ERROR_ON(tuple->size != 5,
2970 + "leds tpl size");
2971 + sprom->gpio0 = tuple->data[1];
2972 + sprom->gpio1 = tuple->data[2];
2973 + sprom->gpio2 = tuple->data[3];
2974 + sprom->gpio3 = tuple->data[4];
2975 + break;
2976 + default:
2977 + break;
2978 + }
2979 + break;
2980 + default:
2981 + break;
2982 + }
2983 + tuple = tuple->next;
2984 + }
2985 +
2986 + return 0;
2987 +error:
2988 + dev_err(ssb_sdio_dev(bus), "failed to fetch device invariants: %s\n",
2989 + error_description);
2990 + return -ENODEV;
2991 +}
2992 +
2993 +void ssb_sdio_exit(struct ssb_bus *bus)
2994 +{
2995 + if (bus->bustype != SSB_BUSTYPE_SDIO)
2996 + return;
2997 + /* Nothing to do here. */
2998 +}
2999 +
3000 +int ssb_sdio_init(struct ssb_bus *bus)
3001 +{
3002 + if (bus->bustype != SSB_BUSTYPE_SDIO)
3003 + return 0;
3004 +
3005 + bus->sdio_sbaddr = ~0;
3006 +
3007 + return 0;
3008 +}
3009 --- a/drivers/ssb/sprom.c
3010 +++ b/drivers/ssb/sprom.c
3011 @@ -2,7 +2,7 @@
3012 * Sonics Silicon Backplane
3013 * Common SPROM support routines
3014 *
3015 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
3016 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
3017 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
3018 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
3019 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
3020 @@ -14,9 +14,10 @@
3021 #include "ssb_private.h"
3022
3023 #include <linux/ctype.h>
3024 +#include <linux/slab.h>
3025
3026
3027 -static const struct ssb_sprom *fallback_sprom;
3028 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
3029
3030
3031 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
3032 @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3033 u16 *sprom;
3034 int res = 0, err = -ENOMEM;
3035 size_t sprom_size_words = bus->sprom_size;
3036 + struct ssb_freeze_context freeze;
3037
3038 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
3039 if (!sprom)
3040 @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3041 err = -ERESTARTSYS;
3042 if (mutex_lock_interruptible(&bus->sprom_mutex))
3043 goto out_kfree;
3044 - err = ssb_devices_freeze(bus);
3045 - if (err == -EOPNOTSUPP) {
3046 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
3047 - "No suspend support. Is CONFIG_PM enabled?\n");
3048 - goto out_unlock;
3049 - }
3050 + err = ssb_devices_freeze(bus, &freeze);
3051 if (err) {
3052 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
3053 goto out_unlock;
3054 }
3055 res = sprom_write(bus, sprom);
3056 - err = ssb_devices_thaw(bus);
3057 + err = ssb_devices_thaw(&freeze);
3058 if (err)
3059 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
3060 out_unlock:
3061 @@ -148,34 +145,56 @@ out:
3062 }
3063
3064 /**
3065 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
3066 - *
3067 - * @sprom: The SPROM data structure to register.
3068 + * ssb_arch_register_fallback_sprom - Registers a method providing a
3069 + * fallback SPROM if no SPROM is found.
3070 *
3071 - * With this function the architecture implementation may register a fallback
3072 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
3073 - * where no valid SPROM can be found in the shadow registers.
3074 + * @sprom_callback: The callback function.
3075 *
3076 - * This function is useful for weird architectures that have a half-assed SSB device
3077 - * hardwired to their PCI bus.
3078 + * With this function the architecture implementation may register a
3079 + * callback handler which fills the SPROM data structure. The fallback is
3080 + * only used for PCI based SSB devices, where no valid SPROM can be found
3081 + * in the shadow registers.
3082 + *
3083 + * This function is useful for weird architectures that have a half-assed
3084 + * SSB device hardwired to their PCI bus.
3085 + *
3086 + * Note that it does only work with PCI attached SSB devices. PCMCIA
3087 + * devices currently don't use this fallback.
3088 + * Architectures must provide the SPROM for native SSB devices anyway, so
3089 + * the fallback also isn't used for native devices.
3090 *
3091 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
3092 - * don't use this fallback.
3093 - * Architectures must provide the SPROM for native SSB devices anyway,
3094 - * so the fallback also isn't used for native devices.
3095 - *
3096 - * This function is available for architecture code, only. So it is not exported.
3097 + * This function is available for architecture code, only. So it is not
3098 + * exported.
3099 */
3100 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
3101 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
3102 + struct ssb_sprom *out))
3103 {
3104 - if (fallback_sprom)
3105 + if (get_fallback_sprom)
3106 return -EEXIST;
3107 - fallback_sprom = sprom;
3108 + get_fallback_sprom = sprom_callback;
3109
3110 return 0;
3111 }
3112
3113 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
3114 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
3115 {
3116 - return fallback_sprom;
3117 + if (!get_fallback_sprom)
3118 + return -ENOENT;
3119 +
3120 + return get_fallback_sprom(bus, out);
3121 +}
3122 +
3123 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
3124 +bool ssb_is_sprom_available(struct ssb_bus *bus)
3125 +{
3126 + /* status register only exists on chipcomon rev >= 11 and we need check
3127 + for >= 31 only */
3128 + /* this routine differs from specs as we do not access SPROM directly
3129 + on PCMCIA */
3130 + if (bus->bustype == SSB_BUSTYPE_PCI &&
3131 + bus->chipco.dev && /* can be unavailable! */
3132 + bus->chipco.dev->id.revision >= 31)
3133 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
3134 +
3135 + return true;
3136 }
3137 --- a/drivers/ssb/ssb_private.h
3138 +++ b/drivers/ssb/ssb_private.h
3139 @@ -114,6 +114,46 @@ static inline int ssb_pcmcia_init(struct
3140 }
3141 #endif /* CONFIG_SSB_PCMCIAHOST */
3142
3143 +/* sdio.c */
3144 +#ifdef CONFIG_SSB_SDIOHOST
3145 +extern int ssb_sdio_get_invariants(struct ssb_bus *bus,
3146 + struct ssb_init_invariants *iv);
3147 +
3148 +extern u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset);
3149 +extern int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev);
3150 +extern int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx);
3151 +extern int ssb_sdio_hardware_setup(struct ssb_bus *bus);
3152 +extern void ssb_sdio_exit(struct ssb_bus *bus);
3153 +extern int ssb_sdio_init(struct ssb_bus *bus);
3154 +
3155 +extern const struct ssb_bus_ops ssb_sdio_ops;
3156 +#else /* CONFIG_SSB_SDIOHOST */
3157 +static inline u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset)
3158 +{
3159 + return 0;
3160 +}
3161 +static inline int ssb_sdio_switch_core(struct ssb_bus *bus,
3162 + struct ssb_device *dev)
3163 +{
3164 + return 0;
3165 +}
3166 +static inline int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
3167 +{
3168 + return 0;
3169 +}
3170 +static inline int ssb_sdio_hardware_setup(struct ssb_bus *bus)
3171 +{
3172 + return 0;
3173 +}
3174 +static inline void ssb_sdio_exit(struct ssb_bus *bus)
3175 +{
3176 +}
3177 +static inline int ssb_sdio_init(struct ssb_bus *bus)
3178 +{
3179 + return 0;
3180 +}
3181 +#endif /* CONFIG_SSB_SDIOHOST */
3182 +
3183
3184 /* scan.c */
3185 extern const char *ssb_core_name(u16 coreid);
3186 @@ -131,24 +171,33 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3187 const char *buf, size_t count,
3188 int (*sprom_check_crc)(const u16 *sprom, size_t size),
3189 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
3190 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
3191 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
3192 + struct ssb_sprom *out);
3193
3194
3195 /* core.c */
3196 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
3197 -extern int ssb_devices_freeze(struct ssb_bus *bus);
3198 -extern int ssb_devices_thaw(struct ssb_bus *bus);
3199 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
3200 int ssb_for_each_bus_call(unsigned long data,
3201 int (*func)(struct ssb_bus *bus, unsigned long data));
3202 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
3203
3204 +struct ssb_freeze_context {
3205 + /* Pointer to the bus */
3206 + struct ssb_bus *bus;
3207 + /* Boolean list to indicate whether a device is frozen on this bus. */
3208 + bool device_frozen[SSB_MAX_NR_CORES];
3209 +};
3210 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
3211 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
3212 +
3213 +
3214
3215 /* b43_pci_bridge.c */
3216 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
3217 extern int __init b43_pci_ssb_bridge_init(void);
3218 extern void __exit b43_pci_ssb_bridge_exit(void);
3219 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
3220 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
3221 static inline int b43_pci_ssb_bridge_init(void)
3222 {
3223 return 0;
3224 @@ -156,6 +205,6 @@ static inline int b43_pci_ssb_bridge_ini
3225 static inline void b43_pci_ssb_bridge_exit(void)
3226 {
3227 }
3228 -#endif /* CONFIG_SSB_PCIHOST */
3229 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
3230
3231 #endif /* LINUX_SSB_PRIVATE_H_ */
3232 --- a/include/linux/pci_ids.h
3233 +++ b/include/linux/pci_ids.h
3234 @@ -2017,6 +2017,7 @@
3235 #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
3236 #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
3237
3238 +#define PCI_VENDOR_ID_BCM_GVC 0x14a4
3239 #define PCI_VENDOR_ID_BROADCOM 0x14e4
3240 #define PCI_DEVICE_ID_TIGON3_5752 0x1600
3241 #define PCI_DEVICE_ID_TIGON3_5752M 0x1601
3242 --- a/include/linux/ssb/ssb.h
3243 +++ b/include/linux/ssb/ssb.h
3244 @@ -16,6 +16,12 @@ struct pcmcia_device;
3245 struct ssb_bus;
3246 struct ssb_driver;
3247
3248 +struct ssb_sprom_core_pwr_info {
3249 + u8 itssi_2g, itssi_5g;
3250 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
3251 + u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
3252 +};
3253 +
3254 struct ssb_sprom {
3255 u8 revision;
3256 u8 il0mac[6]; /* MAC address for 802.11b/g */
3257 @@ -25,26 +31,64 @@ struct ssb_sprom {
3258 u8 et1phyaddr; /* MII address for enet1 */
3259 u8 et0mdcport; /* MDIO for enet0 */
3260 u8 et1mdcport; /* MDIO for enet1 */
3261 - u8 board_rev; /* Board revision number from SPROM. */
3262 + u16 board_rev; /* Board revision number from SPROM. */
3263 u8 country_code; /* Country Code */
3264 - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
3265 - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
3266 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
3267 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
3268 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
3269 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
3270 u16 pa0b0;
3271 u16 pa0b1;
3272 u16 pa0b2;
3273 u16 pa1b0;
3274 u16 pa1b1;
3275 u16 pa1b2;
3276 + u16 pa1lob0;
3277 + u16 pa1lob1;
3278 + u16 pa1lob2;
3279 + u16 pa1hib0;
3280 + u16 pa1hib1;
3281 + u16 pa1hib2;
3282 u8 gpio0; /* GPIO pin 0 */
3283 u8 gpio1; /* GPIO pin 1 */
3284 u8 gpio2; /* GPIO pin 2 */
3285 u8 gpio3; /* GPIO pin 3 */
3286 - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
3287 - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
3288 + u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
3289 + u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
3290 + u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
3291 + u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
3292 u8 itssi_a; /* Idle TSSI Target for A-PHY */
3293 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
3294 - u16 boardflags_lo; /* Boardflags (low 16 bits) */
3295 - u16 boardflags_hi; /* Boardflags (high 16 bits) */
3296 + u8 tri2g; /* 2.4GHz TX isolation */
3297 + u8 tri5gl; /* 5.2GHz TX isolation */
3298 + u8 tri5g; /* 5.3GHz TX isolation */
3299 + u8 tri5gh; /* 5.8GHz TX isolation */
3300 + u8 txpid2g[4]; /* 2GHz TX power index */
3301 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
3302 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
3303 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
3304 + u8 rxpo2g; /* 2GHz RX power offset */
3305 + u8 rxpo5g; /* 5GHz RX power offset */
3306 + u8 rssisav2g; /* 2GHz RSSI params */
3307 + u8 rssismc2g;
3308 + u8 rssismf2g;
3309 + u8 bxa2g; /* 2GHz BX arch */
3310 + u8 rssisav5g; /* 5GHz RSSI params */
3311 + u8 rssismc5g;
3312 + u8 rssismf5g;
3313 + u8 bxa5g; /* 5GHz BX arch */
3314 + u16 cck2gpo; /* CCK power offset */
3315 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
3316 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
3317 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
3318 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
3319 + u16 boardflags_lo; /* Board flags (bits 0-15) */
3320 + u16 boardflags_hi; /* Board flags (bits 16-31) */
3321 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
3322 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
3323 + /* TODO store board flags in a single u64 */
3324 +
3325 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
3326
3327 /* Antenna gain values for up to 4 antennas
3328 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
3329 @@ -58,14 +102,23 @@ struct ssb_sprom {
3330 } ghz5; /* 5GHz band */
3331 } antenna_gain;
3332
3333 - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
3334 + struct {
3335 + struct {
3336 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
3337 + } ghz2;
3338 + struct {
3339 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
3340 + } ghz5;
3341 + } fem;
3342 +
3343 + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
3344 };
3345
3346 /* Information about the PCB the circuitry is soldered on. */
3347 struct ssb_boardinfo {
3348 u16 vendor;
3349 u16 type;
3350 - u16 rev;
3351 + u8 rev;
3352 };
3353
3354
3355 @@ -137,7 +190,7 @@ struct ssb_device {
3356 * is an optimization. */
3357 const struct ssb_bus_ops *ops;
3358
3359 - struct device *dev;
3360 + struct device *dev, *dma_dev;
3361
3362 struct ssb_bus *bus;
3363 struct ssb_device_id id;
3364 @@ -195,10 +248,9 @@ struct ssb_driver {
3365 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
3366
3367 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
3368 -static inline int ssb_driver_register(struct ssb_driver *drv)
3369 -{
3370 - return __ssb_driver_register(drv, THIS_MODULE);
3371 -}
3372 +#define ssb_driver_register(drv) \
3373 + __ssb_driver_register(drv, THIS_MODULE)
3374 +
3375 extern void ssb_driver_unregister(struct ssb_driver *drv);
3376
3377
3378 @@ -208,6 +260,7 @@ enum ssb_bustype {
3379 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
3380 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
3381 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
3382 + SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
3383 };
3384
3385 /* board_vendor */
3386 @@ -238,20 +291,33 @@ struct ssb_bus {
3387
3388 const struct ssb_bus_ops *ops;
3389
3390 - /* The core in the basic address register window. (PCI bus only) */
3391 + /* The core currently mapped into the MMIO window.
3392 + * Not valid on all host-buses. So don't use outside of SSB. */
3393 struct ssb_device *mapped_device;
3394 - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
3395 - u8 mapped_pcmcia_seg;
3396 + union {
3397 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
3398 + u8 mapped_pcmcia_seg;
3399 + /* Current SSB base address window for SDIO. */
3400 + u32 sdio_sbaddr;
3401 + };
3402 /* Lock for core and segment switching.
3403 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
3404 spinlock_t bar_lock;
3405
3406 - /* The bus this backplane is running on. */
3407 + /* The host-bus this backplane is running on. */
3408 enum ssb_bustype bustype;
3409 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
3410 - struct pci_dev *host_pci;
3411 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
3412 - struct pcmcia_device *host_pcmcia;
3413 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
3414 + union {
3415 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
3416 + struct pci_dev *host_pci;
3417 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
3418 + struct pcmcia_device *host_pcmcia;
3419 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
3420 + struct sdio_func *host_sdio;
3421 + };
3422 +
3423 + /* See enum ssb_quirks */
3424 + unsigned int quirks;
3425
3426 #ifdef CONFIG_SSB_SPROM
3427 /* Mutex to protect the SPROM writing. */
3428 @@ -260,7 +326,8 @@ struct ssb_bus {
3429
3430 /* ID information about the Chip. */
3431 u16 chip_id;
3432 - u16 chip_rev;
3433 + u8 chip_rev;
3434 + u16 sprom_offset;
3435 u16 sprom_size; /* number of words in sprom */
3436 u8 chip_package;
3437
3438 @@ -306,6 +373,11 @@ struct ssb_bus {
3439 #endif /* DEBUG */
3440 };
3441
3442 +enum ssb_quirks {
3443 + /* SDIO connected card requires performing a read after writing a 32-bit value */
3444 + SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
3445 +};
3446 +
3447 /* The initialization-invariants. */
3448 struct ssb_init_invariants {
3449 /* Versioning information about the PCB. */
3450 @@ -336,12 +408,23 @@ extern int ssb_bus_pcmciabus_register(st
3451 struct pcmcia_device *pcmcia_dev,
3452 unsigned long baseaddr);
3453 #endif /* CONFIG_SSB_PCMCIAHOST */
3454 +#ifdef CONFIG_SSB_SDIOHOST
3455 +extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
3456 + struct sdio_func *sdio_func,
3457 + unsigned int quirks);
3458 +#endif /* CONFIG_SSB_SDIOHOST */
3459 +
3460
3461 extern void ssb_bus_unregister(struct ssb_bus *bus);
3462
3463 +/* Does the device have an SPROM? */
3464 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
3465 +
3466 /* Set a fallback SPROM.
3467 * See kdoc at the function definition for complete documentation. */
3468 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
3469 +extern int ssb_arch_register_fallback_sprom(
3470 + int (*sprom_callback)(struct ssb_bus *bus,
3471 + struct ssb_sprom *out));
3472
3473 /* Suspend a SSB bus.
3474 * Call this from the parent bus suspend routine. */
3475 @@ -612,6 +695,7 @@ extern int ssb_bus_may_powerdown(struct
3476 * Otherwise static always-on powercontrol will be used. */
3477 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
3478
3479 +extern void ssb_commit_settings(struct ssb_bus *bus);
3480
3481 /* Various helper functions */
3482 extern u32 ssb_admatch_base(u32 adm);
3483 --- a/include/linux/ssb/ssb_driver_chipcommon.h
3484 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
3485 @@ -8,7 +8,7 @@
3486 * gpio interface, extbus, and support for serial and parallel flashes.
3487 *
3488 * Copyright 2005, Broadcom Corporation
3489 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
3490 + * Copyright 2006, Michael Buesch <m@bues.ch>
3491 *
3492 * Licensed under the GPL version 2. See COPYING for details.
3493 */
3494 @@ -53,6 +53,7 @@
3495 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
3496 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
3497 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
3498 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
3499 #define SSB_CHIPCO_CORECTL 0x0008
3500 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
3501 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
3502 @@ -122,6 +123,8 @@
3503 #define SSB_CHIPCO_FLASHDATA 0x0048
3504 #define SSB_CHIPCO_BCAST_ADDR 0x0050
3505 #define SSB_CHIPCO_BCAST_DATA 0x0054
3506 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
3507 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
3508 #define SSB_CHIPCO_GPIOIN 0x0060
3509 #define SSB_CHIPCO_GPIOOUT 0x0064
3510 #define SSB_CHIPCO_GPIOOUTEN 0x0068
3511 @@ -130,6 +133,9 @@
3512 #define SSB_CHIPCO_GPIOIRQ 0x0074
3513 #define SSB_CHIPCO_WATCHDOG 0x0080
3514 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
3515 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
3516 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
3517 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
3518 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
3519 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
3520 #define SSB_CHIPCO_CLOCK_N 0x0090
3521 @@ -188,8 +194,10 @@
3522 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
3523 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
3524 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
3525 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
3526 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
3527 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
3528 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
3529 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
3530 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
3531 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
3532 #define SSB_CHIPCO_UART0_DATA 0x0300
3533 #define SSB_CHIPCO_UART0_IMR 0x0304
3534 @@ -385,6 +393,7 @@
3535
3536
3537 /** Chip specific Chip-Status register contents. */
3538 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
3539 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
3540 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
3541 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
3542 @@ -398,6 +407,18 @@
3543 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
3544 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
3545
3546 +/** Macros to determine SPROM presence based on Chip-Status register. */
3547 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
3548 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3549 + SSB_CHIPCO_CHST_4325_OTP_SEL)
3550 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
3551 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
3552 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
3553 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3554 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
3555 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3556 + SSB_CHIPCO_CHST_4325_OTP_SEL))
3557 +
3558
3559
3560 /** Clockcontrol masks and values **/
3561 @@ -564,6 +585,7 @@ struct ssb_chipcommon_pmu {
3562 struct ssb_chipcommon {
3563 struct ssb_device *dev;
3564 u32 capabilities;
3565 + u32 status;
3566 /* Fast Powerup Delay constant */
3567 u16 fast_pwrup_delay;
3568 struct ssb_chipcommon_pmu pmu;
3569 @@ -629,5 +651,15 @@ extern int ssb_chipco_serial_init(struct
3570 /* PMU support */
3571 extern void ssb_pmu_init(struct ssb_chipcommon *cc);
3572
3573 +enum ssb_pmu_ldo_volt_id {
3574 + LDO_PAREF = 0,
3575 + LDO_VOLT1,
3576 + LDO_VOLT2,
3577 + LDO_VOLT3,
3578 +};
3579 +
3580 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
3581 + enum ssb_pmu_ldo_volt_id id, u32 voltage);
3582 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
3583
3584 #endif /* LINUX_SSB_CHIPCO_H_ */
3585 --- a/include/linux/ssb/ssb_regs.h
3586 +++ b/include/linux/ssb/ssb_regs.h
3587 @@ -85,6 +85,8 @@
3588 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
3589 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
3590 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
3591 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
3592 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
3593 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
3594 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
3595 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
3596 @@ -95,7 +97,7 @@
3597 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
3598 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
3599 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
3600 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
3601 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
3602 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
3603 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
3604 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
3605 @@ -162,7 +164,7 @@
3606
3607 /* SPROM shadow area. If not otherwise noted, fields are
3608 * two bytes wide. Note that the SPROM can _only_ be read
3609 - * in two-byte quantinies.
3610 + * in two-byte quantities.
3611 */
3612 #define SSB_SPROMSIZE_WORDS 64
3613 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
3614 @@ -170,26 +172,27 @@
3615 #define SSB_SPROMSIZE_WORDS_R4 220
3616 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
3617 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
3618 -#define SSB_SPROM_BASE 0x1000
3619 -#define SSB_SPROM_REVISION 0x107E
3620 +#define SSB_SPROM_BASE1 0x1000
3621 +#define SSB_SPROM_BASE31 0x0800
3622 +#define SSB_SPROM_REVISION 0x007E
3623 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
3624 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
3625 #define SSB_SPROM_REVISION_CRC_SHIFT 8
3626
3627 /* SPROM Revision 1 */
3628 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
3629 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
3630 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
3631 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
3632 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
3633 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
3634 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
3635 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
3636 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
3637 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
3638 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
3639 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
3640 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
3641 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
3642 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
3643 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
3644 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
3645 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
3646 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
3647 -#define SSB_SPROM1_BINF 0x105C /* Board info */
3648 +#define SSB_SPROM1_BINF 0x005C /* Board info */
3649 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
3650 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
3651 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
3652 @@ -197,63 +200,63 @@
3653 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
3654 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
3655 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
3656 -#define SSB_SPROM1_PA0B0 0x105E
3657 -#define SSB_SPROM1_PA0B1 0x1060
3658 -#define SSB_SPROM1_PA0B2 0x1062
3659 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
3660 +#define SSB_SPROM1_PA0B0 0x005E
3661 +#define SSB_SPROM1_PA0B1 0x0060
3662 +#define SSB_SPROM1_PA0B2 0x0062
3663 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
3664 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
3665 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
3666 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
3667 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
3668 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
3669 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
3670 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
3671 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
3672 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
3673 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
3674 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
3675 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
3676 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
3677 -#define SSB_SPROM1_PA1B0 0x106A
3678 -#define SSB_SPROM1_PA1B1 0x106C
3679 -#define SSB_SPROM1_PA1B2 0x106E
3680 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
3681 +#define SSB_SPROM1_PA1B0 0x006A
3682 +#define SSB_SPROM1_PA1B1 0x006C
3683 +#define SSB_SPROM1_PA1B2 0x006E
3684 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
3685 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
3686 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
3687 #define SSB_SPROM1_ITSSI_A_SHIFT 8
3688 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
3689 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
3690 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
3691 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
3692 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
3693 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
3694 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
3695 #define SSB_SPROM1_AGAIN_A_SHIFT 8
3696
3697 /* SPROM Revision 2 (inherits from rev 1) */
3698 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
3699 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
3700 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
3701 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
3702 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
3703 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
3704 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
3705 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
3706 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
3707 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
3708 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
3709 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
3710 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
3711 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
3712 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
3713 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
3714 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
3715 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
3716 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
3717 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
3718 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
3719 #define SSB_SPROM2_OPO_VALUE 0x00FF
3720 #define SSB_SPROM2_OPO_UNUSED 0xFF00
3721 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
3722 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
3723
3724 /* SPROM Revision 3 (inherits most data from rev 2) */
3725 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
3726 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
3727 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
3728 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
3729 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
3730 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
3731 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
3732 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
3733 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
3734 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
3735 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
3736 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
3737 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
3738 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
3739 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
3740 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
3741 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
3742 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
3743 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
3744 @@ -264,104 +267,291 @@
3745 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
3746
3747 /* SPROM Revision 4 */
3748 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
3749 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
3750 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
3751 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
3752 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
3753 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
3754 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
3755 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
3756 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
3757 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
3758 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
3759 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
3760 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
3761 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
3762 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
3763 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
3764 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
3765 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
3766 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
3767 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
3768 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
3769 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
3770 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
3771 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
3772 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
3773 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
3774 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
3775 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
3776 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
3777 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
3778 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
3779 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
3780 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
3781 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
3782 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
3783 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
3784 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
3785 #define SSB_SPROM4_AGAIN0_SHIFT 0
3786 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
3787 #define SSB_SPROM4_AGAIN1_SHIFT 8
3788 -#define SSB_SPROM4_AGAIN23 0x1060
3789 +#define SSB_SPROM4_AGAIN23 0x0060
3790 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
3791 #define SSB_SPROM4_AGAIN2_SHIFT 0
3792 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
3793 #define SSB_SPROM4_AGAIN3_SHIFT 8
3794 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
3795 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
3796 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
3797 +#define SSB_SPROM4_TXPID2G0 0x00FF
3798 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
3799 +#define SSB_SPROM4_TXPID2G1 0xFF00
3800 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
3801 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
3802 +#define SSB_SPROM4_TXPID2G2 0x00FF
3803 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
3804 +#define SSB_SPROM4_TXPID2G3 0xFF00
3805 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
3806 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
3807 +#define SSB_SPROM4_TXPID5G0 0x00FF
3808 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
3809 +#define SSB_SPROM4_TXPID5G1 0xFF00
3810 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
3811 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
3812 +#define SSB_SPROM4_TXPID5G2 0x00FF
3813 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
3814 +#define SSB_SPROM4_TXPID5G3 0xFF00
3815 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
3816 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
3817 +#define SSB_SPROM4_TXPID5GL0 0x00FF
3818 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
3819 +#define SSB_SPROM4_TXPID5GL1 0xFF00
3820 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
3821 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
3822 +#define SSB_SPROM4_TXPID5GL2 0x00FF
3823 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
3824 +#define SSB_SPROM4_TXPID5GL3 0xFF00
3825 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
3826 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
3827 +#define SSB_SPROM4_TXPID5GH0 0x00FF
3828 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
3829 +#define SSB_SPROM4_TXPID5GH1 0xFF00
3830 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
3831 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
3832 +#define SSB_SPROM4_TXPID5GH2 0x00FF
3833 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
3834 +#define SSB_SPROM4_TXPID5GH3 0xFF00
3835 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
3836 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
3837 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
3838 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
3839 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
3840 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
3841 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
3842 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
3843 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
3844 #define SSB_SPROM4_ITSSI_A_SHIFT 8
3845 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
3846 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
3847 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
3848 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
3849 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
3850 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
3851 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
3852 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
3853 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
3854 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
3855 -#define SSB_SPROM4_PA0B2 0x1086
3856 -#define SSB_SPROM4_PA1B0 0x108E
3857 -#define SSB_SPROM4_PA1B1 0x1090
3858 -#define SSB_SPROM4_PA1B2 0x1092
3859 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
3860 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
3861 +#define SSB_SPROM4_PA0B2 0x0086
3862 +#define SSB_SPROM4_PA1B0 0x008E
3863 +#define SSB_SPROM4_PA1B1 0x0090
3864 +#define SSB_SPROM4_PA1B2 0x0092
3865
3866 /* SPROM Revision 5 (inherits most data from rev 4) */
3867 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
3868 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
3869 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
3870 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
3871 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
3872 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
3873 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
3874 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
3875 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
3876 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
3877 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
3878 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
3879 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
3880 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
3881 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
3882 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
3883 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
3884 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
3885 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
3886 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
3887
3888 /* SPROM Revision 8 */
3889 -#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */
3890 -#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */
3891 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
3892 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
3893 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
3894 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
3895 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
3896 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
3897 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
3898 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
3899 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
3900 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
3901 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
3902 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
3903 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
3904 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
3905 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
3906 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
3907 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
3908 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
3909 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
3910 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
3911 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
3912 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
3913 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
3914 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
3915 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
3916 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
3917 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
3918 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
3919 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
3920 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
3921 #define SSB_SPROM8_AGAIN0_SHIFT 0
3922 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
3923 #define SSB_SPROM8_AGAIN1_SHIFT 8
3924 -#define SSB_SPROM8_AGAIN23 0x10A0
3925 +#define SSB_SPROM8_AGAIN23 0x00A0
3926 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
3927 #define SSB_SPROM8_AGAIN2_SHIFT 0
3928 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
3929 #define SSB_SPROM8_AGAIN3_SHIFT 8
3930 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
3931 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
3932 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
3933 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
3934 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
3935 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
3936 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
3937 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
3938 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */
3939 -#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
3940 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
3941 +#define SSB_SPROM8_RSSISMF2G 0x000F
3942 +#define SSB_SPROM8_RSSISMC2G 0x00F0
3943 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
3944 +#define SSB_SPROM8_RSSISAV2G 0x0700
3945 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
3946 +#define SSB_SPROM8_BXA2G 0x1800
3947 +#define SSB_SPROM8_BXA2G_SHIFT 11
3948 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
3949 +#define SSB_SPROM8_RSSISMF5G 0x000F
3950 +#define SSB_SPROM8_RSSISMC5G 0x00F0
3951 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
3952 +#define SSB_SPROM8_RSSISAV5G 0x0700
3953 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
3954 +#define SSB_SPROM8_BXA5G 0x1800
3955 +#define SSB_SPROM8_BXA5G_SHIFT 11
3956 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
3957 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
3958 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
3959 +#define SSB_SPROM8_TRI5G_SHIFT 8
3960 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
3961 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
3962 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
3963 +#define SSB_SPROM8_TRI5GH_SHIFT 8
3964 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
3965 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
3966 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
3967 +#define SSB_SPROM8_RXPO5G_SHIFT 8
3968 +#define SSB_SPROM8_FEM2G 0x00AE
3969 +#define SSB_SPROM8_FEM5G 0x00B0
3970 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
3971 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
3972 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
3973 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
3974 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
3975 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
3976 +#define SSB_SROM8_FEM_TR_ISO 0x0700
3977 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
3978 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
3979 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
3980 +#define SSB_SPROM8_THERMAL 0x00B2
3981 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
3982 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
3983 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
3984 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
3985 +
3986 +/* There are 4 blocks with power info sharing the same layout */
3987 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
3988 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
3989 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
3990 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
3991 +
3992 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
3993 +#define SSB_SPROM8_2G_MAXP 0x00FF
3994 +#define SSB_SPROM8_2G_ITSSI 0xFF00
3995 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
3996 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
3997 +#define SSB_SROM8_2G_PA_1 0x04
3998 +#define SSB_SROM8_2G_PA_2 0x06
3999 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
4000 +#define SSB_SPROM8_5G_MAXP 0x00FF
4001 +#define SSB_SPROM8_5G_ITSSI 0xFF00
4002 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
4003 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
4004 +#define SSB_SPROM8_5GH_MAXP 0x00FF
4005 +#define SSB_SPROM8_5GL_MAXP 0xFF00
4006 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
4007 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
4008 +#define SSB_SROM8_5G_PA_1 0x0E
4009 +#define SSB_SROM8_5G_PA_2 0x10
4010 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
4011 +#define SSB_SROM8_5GL_PA_1 0x14
4012 +#define SSB_SROM8_5GL_PA_2 0x16
4013 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
4014 +#define SSB_SROM8_5GH_PA_1 0x1A
4015 +#define SSB_SROM8_5GH_PA_2 0x1C
4016 +
4017 +/* TODO: Make it deprecated */
4018 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
4019 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
4020 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
4021 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
4022 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */
4023 -#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
4024 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
4025 +#define SSB_SPROM8_PA0B1 0x00C4
4026 +#define SSB_SPROM8_PA0B2 0x00C6
4027 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
4028 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
4029 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
4030 #define SSB_SPROM8_ITSSI_A_SHIFT 8
4031 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
4032 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
4033 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
4034 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
4035 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
4036 +#define SSB_SPROM8_PA1B1 0x00CE
4037 +#define SSB_SPROM8_PA1B2 0x00D0
4038 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
4039 +#define SSB_SPROM8_PA1LOB1 0x00D4
4040 +#define SSB_SPROM8_PA1LOB2 0x00D6
4041 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
4042 +#define SSB_SPROM8_PA1HIB1 0x00DA
4043 +#define SSB_SPROM8_PA1HIB2 0x00DC
4044 +
4045 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
4046 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
4047 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
4048 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
4049 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
4050 +
4051 +/* Values for boardflags_lo read from SPROM */
4052 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
4053 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
4054 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
4055 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
4056 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
4057 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
4058 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
4059 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
4060 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
4061 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
4062 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
4063 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
4064 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
4065 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
4066 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
4067 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
4068 +
4069 +/* Values for boardflags_hi read from SPROM */
4070 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
4071 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
4072 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
4073 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
4074 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
4075 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
4076 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
4077 +
4078 +/* Values for boardflags2_lo read from SPROM */
4079 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
4080 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
4081 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
4082 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
4083 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
4084 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
4085 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
4086 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
4087 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
4088 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
4089 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
4090
4091 /* Values for SSB_SPROM1_BINF_CCODE */
4092 enum {
4093 --- a/drivers/ssb/driver_extif.c
4094 +++ b/drivers/ssb/driver_extif.c
4095 @@ -3,7 +3,7 @@
4096 * Broadcom EXTIF core driver
4097 *
4098 * Copyright 2005, Broadcom Corporation
4099 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
4100 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
4101 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
4102 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
4103 *
4104 --- a/drivers/ssb/embedded.c
4105 +++ b/drivers/ssb/embedded.c
4106 @@ -3,7 +3,7 @@
4107 * Embedded systems support code
4108 *
4109 * Copyright 2005-2008, Broadcom Corporation
4110 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
4111 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
4112 *
4113 * Licensed under the GNU/GPL. See COPYING for details.
4114 */
Personal OpenWRT clone
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