target/linux/generic-2.6/patches-2.6.28/022-mips_div64_gcc4.4.0.patch

   1 From: Ralf Baechle <ralf@linux-mips.org>
   2 Date: Thu, 30 Apr 2009 16:14:56 +0000 (+0200)
   3 Subject: MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
   4 X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=a1b68289997030df64cba8478d5767fe10e42a58
   5
   6 MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
   7
   8 The inline assembler used on 32-bit kernels was using the "h" constraint
   9 which was considered dangerous and removed for gcc 4.4.0.
  10
  11 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  12 ---
  13
  14 --- a/arch/mips/include/asm/div64.h
  15 +++ b/arch/mips/include/asm/div64.h
  16 @@ -6,105 +6,63 @@
  17   * License.  See the file "COPYING" in the main directory of this archive
  18   * for more details.
  19   */
  20 -#ifndef _ASM_DIV64_H
  21 -#define _ASM_DIV64_H
  22 +#ifndef __ASM_DIV64_H
  23 +#define __ASM_DIV64_H
  24
  25 -#include <linux/types.h>
  26 +#include <asm-generic/div64.h>
  27
  28 -#if (_MIPS_SZLONG == 32)
  29 +#if BITS_PER_LONG == 64
  30
  31 -#include <asm/compiler.h>
  32 +#include <linux/types.h>
  33
  34  /*
  35   * No traps on overflows for any of these...
  36   */
  37
  38 -#define do_div64_32(res, high, low, base) ({ \
  39 -       unsigned long __quot32, __mod32; \
  40 -       unsigned long __cf, __tmp, __tmp2, __i; \
  41 -       \
  42 -       __asm__(".set   push\n\t" \
  43 -               ".set   noat\n\t" \
  44 -               ".set   noreorder\n\t" \
  45 -               "move   %2, $0\n\t" \
  46 -               "move   %3, $0\n\t" \
  47 -               "b      1f\n\t" \
  48 -               " li    %4, 0x21\n" \
  49 -               "0:\n\t" \
  50 -               "sll    $1, %0, 0x1\n\t" \
  51 -               "srl    %3, %0, 0x1f\n\t" \
  52 -               "or     %0, $1, %5\n\t" \
  53 -               "sll    %1, %1, 0x1\n\t" \
  54 -               "sll    %2, %2, 0x1\n" \
  55 -               "1:\n\t" \
  56 -               "bnez   %3, 2f\n\t" \
  57 -               " sltu  %5, %0, %z6\n\t" \
  58 -               "bnez   %5, 3f\n" \
  59 -               "2:\n\t" \
  60 -               " addiu %4, %4, -1\n\t" \
  61 -               "subu   %0, %0, %z6\n\t" \
  62 -               "addiu  %2, %2, 1\n" \
  63 -               "3:\n\t" \
  64 -               "bnez   %4, 0b\n\t" \
  65 -               " srl   %5, %1, 0x1f\n\t" \
  66 -               ".set   pop" \
  67 -               : "=&r" (__mod32), "=&r" (__tmp), \
  68 -                 "=&r" (__quot32), "=&r" (__cf), \
  69 -                 "=&r" (__i), "=&r" (__tmp2) \
  70 -               : "Jr" (base), "0" (high), "1" (low)); \
  71 -       \
  72 -       (res) = __quot32; \
  73 -       __mod32; })
  74 -
  75 -#define do_div(n, base) ({ \
  76 -       unsigned long long __quot; \
  77 -       unsigned long __mod; \
  78 -       unsigned long long __div; \
  79 -       unsigned long __upper, __low, __high, __base; \
  80 -       \
  81 -       __div = (n); \
  82 -       __base = (base); \
  83 -       \
  84 -       __high = __div >> 32; \
  85 -       __low = __div; \
  86 -       __upper = __high; \
  87 -       \
  88 -       if (__high) \
  89 -               __asm__("divu   $0, %z2, %z3" \
  90 -                       : "=h" (__upper), "=l" (__high) \
  91 -                       : "Jr" (__high), "Jr" (__base) \
  92 -                       : GCC_REG_ACCUM); \
  93 -       \
  94 -       __mod = do_div64_32(__low, __upper, __low, __base); \
  95 -       \
  96 -       __quot = __high; \
  97 -       __quot = __quot << 32 | __low; \
  98 -       (n) = __quot; \
  99 -       __mod; })
 100 -
 101 -#endif /* (_MIPS_SZLONG == 32) */
 102 -
 103 -#if (_MIPS_SZLONG == 64)
 104 -
 105 -/*
 106 - * Hey, we're already 64-bit, no
 107 - * need to play games..
 108 - */
 109 -#define do_div(n, base) ({ \
 110 -       unsigned long __quot; \
 111 -       unsigned int __mod; \
 112 -       unsigned long __div; \
 113 -       unsigned int __base; \
 114 -       \
 115 -       __div = (n); \
 116 -       __base = (base); \
 117 -       \
 118 -       __mod = __div % __base; \
 119 -       __quot = __div / __base; \
 120 -       \
 121 -       (n) = __quot; \
 122 -       __mod; })
 123 +#define __div64_32(n, base)                                            \
 124 +({                                                                     \
 125 +       unsigned long __cf, __tmp, __tmp2, __i;                         \
 126 +       unsigned long __quot32, __mod32;                                \
 127 +       unsigned long __high, __low;                                    \
 128 +       unsigned long long __n;                                         \
 129 +                                                                       \
 130 +       __high = *__n >> 32;                                            \
 131 +       __low = __n;                                                    \
 132 +       __asm__(                                                        \
 133 +       "       .set    push                                    \n"     \
 134 +       "       .set    noat                                    \n"     \
 135 +       "       .set    noreorder                               \n"     \
 136 +       "       move    %2, $0                                  \n"     \
 137 +       "       move    %3, $0                                  \n"     \
 138 +       "       b       1f                                      \n"     \
 139 +       "        li     %4, 0x21                                \n"     \
 140 +       "0:                                                     \n"     \
 141 +       "       sll     $1, %0, 0x1                             \n"     \
 142 +       "       srl     %3, %0, 0x1f                            \n"     \
 143 +       "       or      %0, $1, %5                              \n"     \
 144 +       "       sll     %1, %1, 0x1                             \n"     \
 145 +       "       sll     %2, %2, 0x1                             \n"     \
 146 +       "1:                                                     \n"     \
 147 +       "       bnez    %3, 2f                                  \n"     \
 148 +       "        sltu   %5, %0, %z6                             \n"     \
 149 +       "       bnez    %5, 3f                                  \n"     \
 150 +       "2:                                                     \n"     \
 151 +       "        addiu  %4, %4, -1                              \n"     \
 152 +       "       subu    %0, %0, %z6                             \n"     \
 153 +       "       addiu   %2, %2, 1                               \n"     \
 154 +       "3:                                                     \n"     \
 155 +       "       bnez    %4, 0b\n\t"                                     \
 156 +       "        srl    %5, %1, 0x1f\n\t"                               \
 157 +       "       .set    pop"                                            \
 158 +       : "=&r" (__mod32), "=&r" (__tmp),                               \
 159 +         "=&r" (__quot32), "=&r" (__cf),                               \
 160 +         "=&r" (__i), "=&r" (__tmp2)                                   \
 161 +       : "Jr" (base), "0" (__high), "1" (__low));                      \
 162 +                                                                       \
 163 +       (__n) = __quot32;                                               \
 164 +       __mod32;                                                        \
 165 +})
 166
 167 -#endif /* (_MIPS_SZLONG == 64) */
 168 +#endif /* BITS_PER_LONG == 64 */
 169
 170 -#endif /* _ASM_DIV64_H */
 171 +#endif /* __ASM_DIV64_H */