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[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux-2.4.30/Makefile linux-2.4.30.dev/Makefile
2 --- linux-2.4.30/Makefile 2005-06-14 18:42:06.000000000 +0200
3 +++ linux-2.4.30.dev/Makefile 2005-06-14 15:36:59.000000000 +0200
4 @@ -91,7 +91,7 @@
5
6 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
7
8 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
9 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
10 -fno-strict-aliasing -fno-common
11 ifndef CONFIG_FRAME_POINTER
12 CFLAGS += -fomit-frame-pointer
13 diff -urN linux-2.4.30/arch/mips/Makefile linux-2.4.30.dev/arch/mips/Makefile
14 --- linux-2.4.30/arch/mips/Makefile 2005-06-14 18:42:06.000000000 +0200
15 +++ linux-2.4.30.dev/arch/mips/Makefile 2005-06-14 15:36:59.000000000 +0200
16 @@ -369,6 +369,16 @@
17 endif
18
19 #
20 +# Texas Instruments AR7
21 +#
22 +
23 +ifdef CONFIG_AR7
24 +LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
25 +SUBDIRS += arch/mips/ar7 arch/mips/ar7/avalanche
26 +LOADADDR += 0x94020000
27 +endif
28 +
29 +#
30 # DECstation family
31 #
32 ifdef CONFIG_DECSTATION
33 diff -urN linux-2.4.30/arch/mips/ar7/Makefile linux-2.4.30.dev/arch/mips/ar7/Makefile
34 --- linux-2.4.30/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
35 +++ linux-2.4.30.dev/arch/mips/ar7/Makefile 2005-06-14 15:36:59.000000000 +0200
36 @@ -0,0 +1,12 @@
37 +.S.s:
38 + $(CPP) $(AFLAGS) $< -o $*.s
39 +
40 +.S.o:
41 + $(CC) $(AFLAGS) -c $< -o $*.o
42 +
43 +O_TARGET := ar7.o
44 +
45 +obj-y := tnetd73xx_misc.o
46 +obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
47 +
48 +include $(TOPDIR)/Rules.make
49 diff -urN linux-2.4.30/arch/mips/ar7/avalanche/Makefile linux-2.4.30.dev/arch/mips/ar7/avalanche/Makefile
50 --- linux-2.4.30/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100
51 +++ linux-2.4.30.dev/arch/mips/ar7/avalanche/Makefile 2005-06-14 15:36:59.000000000 +0200
52 @@ -0,0 +1,13 @@
53 +.S.s:
54 + $(CPP) $(AFLAGS) $< -o $*.s
55 +
56 +.S.o:
57 + $(CC) $(AFLAGS) -c $< -o $*.o
58 +
59 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
60 +
61 +O_TARGET := avalanche.o
62 +
63 +obj-y += avalanche_paging.o avalanche_jump.o
64 +
65 +include $(TOPDIR)/Rules.make
66 diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_jump.S
67 --- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100
68 +++ linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-06-14 15:36:59.000000000 +0200
69 @@ -0,0 +1,69 @@
70 +#include <linux/config.h>
71 +#include <linux/threads.h>
72 +
73 +#include <asm/asm.h>
74 +#include <asm/cacheops.h>
75 +#include <asm/current.h>
76 +#include <asm/offset.h>
77 +#include <asm/processor.h>
78 +#include <asm/regdef.h>
79 +#include <asm/cachectl.h>
80 +#include <asm/mipsregs.h>
81 +#include <asm/stackframe.h>
82 +
83 +.text
84 +
85 +.set noreorder
86 +.set noat
87 +
88 +/* TLB Miss Vector */
89 +
90 +LEAF(jump_tlb_miss)
91 + .set mips2
92 + lui k0,0x9400
93 + ori k0,0
94 + jr k0
95 + nop
96 +END(jump_tlb_miss)
97 +
98 + /* Unused TLB Miss Vector */
99 +
100 +LEAF(jump_tlb_miss_unused)
101 + .set mips2
102 + lui k0,0x9400
103 + ori k0,0x80
104 + jr k0
105 + nop
106 +END(jump_tlb_miss_unused)
107 +
108 + /* Cache Error Vector */
109 +
110 +LEAF(jump_cache_error)
111 + .set mips2
112 + lui k0,0x9400
113 + ori k0,0x100
114 + jr k0
115 + nop
116 +END(jump_cache_error)
117 +
118 + /* General Exception */
119 +
120 +LEAF(jump_general_exception)
121 + .set mips2
122 + lui k0,0x9400
123 + ori k0,0x180
124 + jr k0
125 + nop
126 +END(jump_general_exception)
127 +
128 + /* Dedicated Interrupt */
129 +
130 +LEAF(jump_dedicated_interrupt)
131 + .set mips2
132 + lui k0,0x9400
133 + ori k0,0x200
134 + jr k0
135 + nop
136 +END(jump_dedicated_interrupt)
137 +
138 + .set at
139 diff -urN linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_paging.c
140 --- linux-2.4.30/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 01:00:00.000000000 +0100
141 +++ linux-2.4.30.dev/arch/mips/ar7/avalanche/avalanche_paging.c 2005-06-14 15:36:59.000000000 +0200
142 @@ -0,0 +1,314 @@
143 +/*
144 + * -*- linux-c -*-
145 + * This file is subject to the terms and conditions of the GNU General Public
146 + * License. See the file "COPYING" in the main directory of this archive
147 + * for more details.
148 + *
149 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
150 + * Copyright (C) 2002 Texas Instruments, Inc.
151 + *
152 + */
153 +
154 +/*
155 + * This file takes care of the "memory hole" issue that exists with the standard
156 + * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
157 + * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
158 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
159 + *
160 + * -JAH
161 + */
162 +#include <linux/config.h>
163 +#include <linux/signal.h>
164 +#include <linux/sched.h>
165 +#include <linux/kernel.h>
166 +#include <linux/errno.h>
167 +#include <linux/string.h>
168 +#include <linux/types.h>
169 +#include <linux/ptrace.h>
170 +#include <linux/mman.h>
171 +#include <linux/mm.h>
172 +#include <linux/swap.h>
173 +#include <linux/smp.h>
174 +#include <linux/init.h>
175 +#ifdef CONFIG_BLK_DEV_INITRD
176 +#include <linux/blk.h>
177 +#endif /* CONFIG_BLK_DEV_INITRD */
178 +#include <linux/highmem.h>
179 +#include <linux/bootmem.h>
180 +
181 +#include <asm/processor.h>
182 +#include <asm/system.h>
183 +#include <asm/uaccess.h>
184 +#include <asm/pgtable.h>
185 +#include <asm/pgalloc.h>
186 +#include <asm/mmu_context.h>
187 +#include <asm/io.h>
188 +#include <asm/tlb.h>
189 +#include <asm/cpu.h>
190 +
191 +#define __MEMORY_START CONFIG_AR7_MEMORY
192 +
193 +#ifdef CONFIG_DISCONTIGMEM
194 +pg_data_t discontig_page_data[NR_NODES];
195 +bootmem_data_t discontig_node_bdata[NR_NODES];
196 +#endif
197 +
198 +static unsigned long totalram_pages;
199 +/* static unsigned long totalhigh_pages; */
200 +
201 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
202 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
203 +
204 +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
205 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
206 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
207 +
208 +unsigned long bootmap_size;
209 +
210 +extern char *prom_getenv(char *envname);
211 +
212 +/*
213 + * We have upto 8 empty zeroed pages so we can map one of the right colour
214 + * when needed. This is necessary only on R4000 / R4400 SC and MC versions
215 + * where we have to avoid VCED / VECI exceptions for good performance at
216 + * any price. Since page is never written to after the initialization we
217 + * don't have to care about aliases on other CPUs.
218 + */
219 +
220 +static inline unsigned long setup_zero_pages(void)
221 +{
222 + unsigned long order, size;
223 + struct page *page;
224 + if(current_cpu_data.options & MIPS_CPU_VCE)
225 + order = 3;
226 + else
227 + order = 0;
228 +
229 + empty_zero_page = __get_free_pages(GFP_KERNEL, order);
230 +
231 + if (!empty_zero_page)
232 + panic("Oh boy, that early out of memory?");
233 +
234 + page = virt_to_page(empty_zero_page);
235 +
236 + while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
237 + set_bit(PG_reserved, &page->flags);
238 + set_page_count(page, 0);
239 + page++;
240 + }
241 +
242 + size = PAGE_SIZE << order;
243 + zero_page_mask = (size - 1) & PAGE_MASK;
244 + memset((void *)empty_zero_page, 0, size);
245 +
246 + return 1UL << order;
247 +}
248 +
249 +/*
250 + * paging_init() sets up the page tables
251 + *
252 + * This routines also unmaps the page at virtual kernel address 0, so
253 + * that we can trap those pesky NULL-reference errors in the kernel.
254 + */
255 +void __init paging_init(void)
256 +{
257 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
258 + unsigned long low, start_pfn;
259 +
260 + /* Initialize the entire pgd. */
261 + pgd_init((unsigned long)swapper_pg_dir);
262 + pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
263 +
264 +
265 + start_pfn = START_PFN;
266 + // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
267 + low = MAX_LOW_PFN;
268 +
269 + /* Avalanche DMA-able memory 0x14000000+memsize */
270 +
271 + zones_size[ZONE_DMA] = low - start_pfn;
272 +
273 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
274 +
275 +#ifdef CONFIG_DISCONTIGMEM
276 + zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
277 + zones_size[ZONE_NORMAL] = 0;
278 + free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
279 +#endif /* CONFIG_DISCONTIGMEM */
280 +
281 +}
282 +
283 +extern char _ftext, _etext, _fdata, _edata, _end;
284 +extern char __init_begin, __init_end;
285 +
286 +void __init mem_init(void)
287 +{
288 + int codesize, reservedpages, datasize, initsize;
289 + int tmp;
290 +
291 + max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
292 + high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
293 +
294 + /* free up the memory associated with Adam2 -
295 + * that is the, after the first page that is
296 + * reserved all the way up to the start of the kernel
297 + */
298 + free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
299 + (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
300 +
301 + /* this will put all low memory onto the freelists */
302 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
303 +
304 + /* Setup zeroed pages */
305 + totalram_pages -= setup_zero_pages();
306 +
307 +
308 +#ifdef CONFIG_DISCONTIGMEM
309 + totalram_pages += free_all_bootmem_node(NODE_DATA(1));
310 +#endif
311 + reservedpages = 0;
312 + for (tmp = 0; tmp < num_physpages; tmp++)
313 + /*
314 + * Only count reserved RAM pages
315 + */
316 + if (PageReserved(mem_map+tmp))
317 + reservedpages++;
318 +
319 + codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
320 + datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
321 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
322 +
323 + printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
324 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
325 + max_mapnr << (PAGE_SHIFT-10),
326 + codesize >> 10,
327 + reservedpages << (PAGE_SHIFT-10),
328 + datasize >> 10,
329 + initsize >> 10);
330 +
331 +}
332 +
333 +/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
334 +
335 +void avalanche_bootmem_init(void)
336 +{
337 + unsigned long start_pfn, max_pfn;
338 + unsigned long max_low_pfn;
339 + unsigned int memsize,memory_end,memory_start;
340 + char *memsize_str;
341 +
342 + memsize_str = prom_getenv("memsize");
343 + if (!memsize_str) {
344 + memsize = 0x02000000;
345 + } else {
346 + memsize = simple_strtol(memsize_str, NULL, 0);
347 + }
348 +
349 +
350 + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
351 + memory_end = memory_start + memsize;
352 +
353 + /*
354 + * Find the highest memory page fram number we have available
355 + */
356 +
357 + max_pfn = PFN_DOWN(__pa(memory_end));
358 +
359 + /*
360 + * Determine the low and high memory ranges
361 + */
362 +
363 + max_low_pfn = max_pfn;
364 +
365 + /*
366 + * Partially used pages are not usable - thus we are
367 + * rounding upwards:
368 + */
369 +
370 + start_pfn = PFN_UP(__pa(&_end));
371 +
372 + /*
373 + * Find a proper area for the bootmem bitmap. After this
374 + * bootstrap step all allocations (until the page allocator is
375 + * intact) must be done via bootmem_alloc().
376 + */
377 +
378 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
379 + __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
380 +
381 +
382 + /*
383 + * Register fully available low RAM pages with the bootmem allocator.
384 + */
385 +
386 + {
387 + unsigned long curr_pfn, last_pfn, pages;
388 +
389 + /*
390 + * We are rounding up the start address of usable memory:
391 + */
392 + curr_pfn = PFN_UP(__MEMORY_START);
393 +
394 + /*
395 + * ... and at the end of the usable range downwards:
396 + */
397 + last_pfn = PFN_DOWN(__pa(memory_end));
398 +
399 + if (last_pfn > max_low_pfn)
400 + last_pfn = max_low_pfn;
401 +
402 + pages = last_pfn - curr_pfn;
403 +
404 +
405 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
406 + PFN_PHYS(pages));
407 + }
408 +
409 + /*
410 + * Reserve the kernel text and
411 + * Reserve the bootmem bitmap. We do this in two steps (first step
412 + * was init_bootmem()), because this catches the (definitely buggy)
413 + * case of us accidentally initializing the bootmem allocator with
414 + * an invalid RAM area.
415 + */
416 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
417 + (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
418 +
419 + /*
420 + * reserve physical page 0 - it's a special BIOS page on many boxes,
421 + * enabling clean reboots, SMP operation, laptop functions.
422 + */
423 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
424 +}
425 +
426 +extern char __init_begin, __init_end;
427 +
428 +void free_initmem(void)
429 +{
430 + unsigned long addr;
431 + // prom_free_prom_memory ();
432 +
433 + addr = (unsigned long) &__init_begin;
434 + while (addr < (unsigned long) &__init_end) {
435 + ClearPageReserved(virt_to_page(addr));
436 + set_page_count(virt_to_page(addr), 1);
437 + free_page(addr);
438 + totalram_pages++;
439 + addr += PAGE_SIZE;
440 + }
441 + printk("Freeing unused kernel memory: %dk freed\n",
442 + (&__init_end - &__init_begin) >> 10);
443 +}
444 +
445 +void si_meminfo(struct sysinfo *val)
446 +{
447 + val->totalram = totalram_pages;
448 + val->sharedram = 0;
449 + val->freeram = nr_free_pages();
450 + val->bufferram = atomic_read(&buffermem_pages);
451 + val->totalhigh = 0;
452 + val->freehigh = nr_free_highpages();
453 + val->mem_unit = PAGE_SIZE;
454 +
455 + return;
456 +}
457 diff -urN linux-2.4.30/arch/mips/ar7/cmdline.c linux-2.4.30.dev/arch/mips/ar7/cmdline.c
458 --- linux-2.4.30/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
459 +++ linux-2.4.30.dev/arch/mips/ar7/cmdline.c 2005-06-14 15:36:59.000000000 +0200
460 @@ -0,0 +1,64 @@
461 +/*
462 + * Carsten Langgaard, carstenl@mips.com
463 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
464 + *
465 + * This program is free software; you can distribute it and/or modify it
466 + * under the terms of the GNU General Public License (Version 2) as
467 + * published by the Free Software Foundation.
468 + *
469 + * This program is distributed in the hope it will be useful, but WITHOUT
470 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
471 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
472 + * for more details.
473 + *
474 + * You should have received a copy of the GNU General Public License along
475 + * with this program; if not, write to the Free Software Foundation, Inc.,
476 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
477 + *
478 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
479 + */
480 +#include <linux/init.h>
481 +#include <linux/string.h>
482 +
483 +#include <asm/bootinfo.h>
484 +
485 +extern int prom_argc;
486 +extern int *_prom_argv;
487 +
488 +/*
489 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
490 + * This macro take care of sign extension.
491 + */
492 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
493 +
494 +char arcs_cmdline[CL_SIZE];
495 +
496 +char * __init prom_getcmdline(void)
497 +{
498 + return &(arcs_cmdline[0]);
499 +}
500 +
501 +
502 +void __init prom_init_cmdline(void)
503 +{
504 + char *cp;
505 + int actr;
506 +
507 + actr = 1; /* Always ignore argv[0] */
508 +
509 + cp = &(arcs_cmdline[0]);
510 +#ifdef CONFIG_CMDLINE_BOOL
511 + strcpy(cp, CONFIG_CMDLINE);
512 + cp += strlen(CONFIG_CMDLINE);
513 + *cp++ = ' ';
514 +#endif
515 + while(actr < prom_argc) {
516 + strcpy(cp, prom_argv(actr));
517 + cp += strlen(prom_argv(actr));
518 + *cp++ = ' ';
519 + actr++;
520 + }
521 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
522 + --cp;
523 + *cp = '\0';
524 +}
525 diff -urN linux-2.4.30/arch/mips/ar7/init.c linux-2.4.30.dev/arch/mips/ar7/init.c
526 --- linux-2.4.30/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
527 +++ linux-2.4.30.dev/arch/mips/ar7/init.c 2005-06-14 19:15:15.000000000 +0200
528 @@ -0,0 +1,144 @@
529 +/*
530 + * Carsten Langgaard, carstenl@mips.com
531 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
532 + *
533 + * This program is free software; you can distribute it and/or modify it
534 + * under the terms of the GNU General Public License (Version 2) as
535 + * published by the Free Software Foundation.
536 + *
537 + * This program is distributed in the hope it will be useful, but WITHOUT
538 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
539 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
540 + * for more details.
541 + *
542 + * You should have received a copy of the GNU General Public License along
543 + * with this program; if not, write to the Free Software Foundation, Inc.,
544 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
545 + *
546 + * PROM library initialisation code.
547 + */
548 +#include <linux/config.h>
549 +#include <linux/init.h>
550 +#include <linux/string.h>
551 +#include <linux/kernel.h>
552 +
553 +#include <asm/io.h>
554 +#include <asm/mips-boards/prom.h>
555 +#include <asm/mips-boards/generic.h>
556 +
557 +/* Environment variable */
558 +typedef struct {
559 + char *name;
560 + char *val;
561 +} t_env_var;
562 +
563 +int prom_argc;
564 +int *_prom_argv, *_prom_envp;
565 +
566 +/* max # of Adam2 environment variables */
567 +#define MAX_ENV_ENTRY 80
568 +
569 +static t_env_var local_envp[MAX_ENV_ENTRY];
570 +
571 +int init_debug = 0;
572 +
573 +char *prom_getenv(char *envname)
574 +{
575 + /*
576 + * Return a pointer to the given environment variable.
577 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
578 + * in the PROM structures are only 32-bit, so we need some
579 + * workarounds, if we are running in 64-bit mode.
580 + */
581 + int i, index=0;
582 + t_env_var *env = (t_env_var *) local_envp;
583 +
584 + i = strlen(envname);
585 + while (env->name) {
586 + if(strncmp(envname, env->name, i) == 0) {
587 + return(env->val);
588 + }
589 + env++;
590 + }
591 +
592 + return NULL;
593 +}
594 +
595 +static inline unsigned char str2hexnum(unsigned char c)
596 +{
597 + if (c >= '0' && c <= '9')
598 + return c - '0';
599 + if (c >= 'a' && c <= 'f')
600 + return c - 'a' + 10;
601 + return 0; /* foo */
602 +}
603 +
604 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
605 +{
606 + int i;
607 +
608 + for (i = 0; i < 6; i++) {
609 + unsigned char num;
610 +
611 + if((*str == '.') || (*str == ':'))
612 + str++;
613 + num = str2hexnum(*str++) << 4;
614 + num |= (str2hexnum(*str++));
615 + ea[i] = num;
616 + }
617 +}
618 +
619 +int get_ethernet_addr(char *ethernet_addr)
620 +{
621 + char *ethaddr_str;
622 +
623 + ethaddr_str = prom_getenv("ethaddr");
624 + if (!ethaddr_str) {
625 + printk("ethaddr not set in boot prom\n");
626 + return -1;
627 + }
628 + str2eaddr(ethernet_addr, ethaddr_str);
629 +
630 + if (init_debug > 1) {
631 + int i;
632 + printk("get_ethernet_addr: ");
633 + for (i=0; i<5; i++)
634 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
635 + printk("%02x\n", *(ethernet_addr+i));
636 + }
637 +
638 + return 0;
639 +}
640 +
641 +int __init prom_init(int argc, char **argv, char **envp)
642 +{
643 + int i;
644 + t_env_var *env = (t_env_var *) envp;
645 +
646 + prom_argc = argc;
647 + _prom_argv = (int *)argv;
648 + _prom_envp = (int *)envp;
649 +
650 + /* Copy what we need locally so we are not dependent on
651 + * bootloader RAM. In Adam2, the environment parameters
652 + * are in flash but the table that references them is in
653 + * RAM
654 + */
655 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
656 + if (env->name) {
657 + local_envp[i].name = env->name;
658 + local_envp[i].val = env->val;
659 + } else {
660 + local_envp[i].name = NULL;
661 + local_envp[i].val = NULL;
662 + }
663 + }
664 +
665 + set_io_port_base(0);
666 +
667 + prom_printf("\nLINUX started...\n");
668 + prom_init_cmdline();
669 + prom_meminit();
670 +
671 + return 0;
672 +}
673 diff -urN linux-2.4.30/arch/mips/ar7/irq.c linux-2.4.30.dev/arch/mips/ar7/irq.c
674 --- linux-2.4.30/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
675 +++ linux-2.4.30.dev/arch/mips/ar7/irq.c 2005-06-14 15:36:59.000000000 +0200
676 @@ -0,0 +1,669 @@
677 +/*
678 + * Nitin Dhingra, iamnd@ti.com
679 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
680 + *
681 + * ########################################################################
682 + *
683 + * This program is free software; you can distribute it and/or modify it
684 + * under the terms of the GNU General Public License (Version 2) as
685 + * published by the Free Software Foundation.
686 + *
687 + * This program is distributed in the hope it will be useful, but WITHOUT
688 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
689 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
690 + * for more details.
691 + *
692 + * You should have received a copy of the GNU General Public License along
693 + * with this program; if not, write to the Free Software Foundation, Inc.,
694 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
695 + *
696 + * ########################################################################
697 + *
698 + * Routines for generic manipulation of the interrupts found on the Texas
699 + * Instruments avalanche board
700 + *
701 + */
702 +
703 +#include <linux/config.h>
704 +#include <linux/init.h>
705 +#include <linux/sched.h>
706 +#include <linux/slab.h>
707 +#include <linux/interrupt.h>
708 +#include <linux/kernel_stat.h>
709 +#include <linux/proc_fs.h>
710 +#include <asm/irq.h>
711 +#include <asm/mips-boards/prom.h>
712 +#include <asm/ar7/ar7.h>
713 +#include <asm/ar7/avalanche_intc.h>
714 +#include <asm/gdb-stub.h>
715 +
716 +
717 +#define shutdown_avalanche_irq disable_avalanche_irq
718 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
719 +
720 +static unsigned int startup_avalanche_irq(unsigned int irq);
721 +static void end_avalanche_irq(unsigned int irq);
722 +void enable_avalanche_irq(unsigned int irq_nr);
723 +void disable_avalanche_irq(unsigned int irq_nr);
724 +
725 +static struct hw_interrupt_type avalanche_irq_type = {
726 + "TI AVALANCHE",
727 + startup_avalanche_irq,
728 + shutdown_avalanche_irq,
729 + enable_avalanche_irq,
730 + disable_avalanche_irq,
731 + mask_and_ack_avalanche_irq,
732 + end_avalanche_irq,
733 + NULL
734 +};
735 +
736 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
737 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
738 +
739 +
740 +unsigned long spurious_count = 0;
741 +
742 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
743 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
744 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
745 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
746 +
747 +extern asmlinkage void mipsIRQ(void);
748 +
749 +
750 +/*
751 + * The avalanche/MIPS interrupt line numbers are used to represent the
752 + * interrupts within the irqaction arrays. The index notation is
753 + * is as follows:
754 + *
755 + * 0-7 MIPS CPU Exceptions (HW/SW)
756 + * 8-47 Primary Interrupts (Avalanche)
757 + * 48-79 Secondary Interrupts (Avalanche)
758 + *
759 + */
760 +
761 +
762 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
763 +{
764 + NULL, NULL, NULL, NULL,
765 + NULL, NULL, NULL, NULL,
766 + NULL, NULL, NULL, NULL,
767 + NULL, NULL, NULL, NULL,
768 + NULL, NULL, NULL, NULL,
769 + NULL, NULL, NULL, NULL,
770 + NULL, NULL, NULL, NULL,
771 + NULL, NULL, NULL, NULL,
772 + NULL, NULL, NULL, NULL,
773 + NULL, NULL, NULL, NULL
774 +};
775 +
776 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
777 +{
778 + NULL, NULL, NULL, NULL,
779 + NULL, NULL, NULL, NULL,
780 + NULL, NULL, NULL, NULL,
781 + NULL, NULL, NULL, NULL,
782 + NULL, NULL, NULL, NULL,
783 + NULL, NULL, NULL, NULL,
784 + NULL, NULL, NULL, NULL,
785 + NULL, NULL, NULL, NULL
786 +};
787 +
788 +/*
789 + This remaps interrupts to exist on other channels than the default
790 + channels. essentially we can use the line # as the index for this
791 + array
792 + */
793 +
794 +
795 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
796 +unsigned long uni_secondary_interrupt = 0;
797 +
798 +static struct irqaction r4ktimer_action = {
799 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
800 +};
801 +
802 +static struct irqaction *irq_action[8] = {
803 + NULL, /* SW int 0 */
804 + NULL, /* SW int 1 */
805 + NULL, /* HW int 0 */
806 + NULL,
807 + NULL,
808 + NULL, /* HW int 3 */
809 + NULL, /* HW int 4 */
810 + &r4ktimer_action /* HW int 5 */
811 +};
812 +
813 +static void end_avalanche_irq(unsigned int irq)
814 +{
815 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
816 + enable_avalanche_irq(irq);
817 +}
818 +
819 +void disable_avalanche_irq(unsigned int irq_nr)
820 +{
821 + unsigned long flags;
822 + unsigned long chan_nr=0;
823 + unsigned long int_bit=0;
824 +
825 + if(irq_nr >= AVALANCHE_INT_END)
826 + {
827 + printk("whee, invalid irq_nr %d\n", irq_nr);
828 + panic("IRQ, you lose...");
829 + }
830 +
831 + save_and_cli(flags);
832 +
833 +
834 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
835 + {
836 + /* disable mips exception */
837 +
838 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
839 + change_c0_status(ST0_IM,int_bit);
840 + restore_flags(flags);
841 + return;
842 + }
843 +
844 + /* irq_nr represents the line number for the interrupt. We must
845 + * disable the channel number associated with that line number.
846 + */
847 +
848 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
849 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
850 + else
851 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
852 +
853 + /* disable the interrupt channel bit */
854 +
855 + /* primary interrupt #'s 0-31 */
856 +
857 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
858 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
859 +
860 + /* primary interrupt #'s 32-39 */
861 +
862 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
863 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
864 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
865 +
866 + else /* secondary interrupt #'s 0-31 */
867 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
868 +
869 + restore_flags(flags);
870 +}
871 +
872 +void enable_avalanche_irq(unsigned int irq_nr)
873 +{
874 + unsigned long flags;
875 + unsigned long chan_nr=0;
876 + unsigned long int_bit=0;
877 +
878 + if(irq_nr > AVALANCHE_INT_END) {
879 + printk("whee, invalid irq_nr %d\n", irq_nr);
880 + panic("IRQ, you lose...");
881 + }
882 +
883 + save_and_cli(flags);
884 +
885 +
886 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
887 + {
888 + /* Enable MIPS exceptions */
889 + int_bit = read_c0_status();
890 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
891 + restore_flags(flags);
892 + return;
893 + }
894 +
895 + /* irq_nr represents the line number for the interrupt. We must
896 + * disable the channel number associated with that line number.
897 + */
898 +
899 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
900 + chan_nr = AVINTNUM(irq_nr);
901 + else
902 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
903 +
904 + /* enable the interrupt channel bit */
905 +
906 + /* primary interrupt #'s 0-31 */
907 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
908 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
909 +
910 + /* primary interrupt #'s 32 throuth 39 */
911 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
912 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
913 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
914 +
915 + else /* secondary interrupt #'s 0-31 */
916 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
917 +
918 + restore_flags(flags);
919 +}
920 +
921 +static unsigned int startup_avalanche_irq(unsigned int irq)
922 +{
923 + enable_avalanche_irq(irq);
924 + return 0; /* never anything pending */
925 +}
926 +
927 +
928 +int get_irq_list(char *buf)
929 +{
930 + int i, len = 0;
931 + int num = 0;
932 + struct irqaction *action;
933 +
934 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
935 + {
936 + action = irq_action[i];
937 + if (!action)
938 + continue;
939 + len += sprintf(buf+len, "%2d: %8d %c %s",
940 + num, kstat.irqs[0][num],
941 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
942 + action->name);
943 + for (action=action->next; action; action = action->next) {
944 + len += sprintf(buf+len, ",%s %s",
945 + (action->flags & SA_INTERRUPT) ? " +" : "",
946 + action->name);
947 + }
948 + len += sprintf(buf+len, " [MIPS interrupt]\n");
949 + }
950 +
951 +
952 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
953 + {
954 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
955 + action = hw0_irq_action_primary[i];
956 + else
957 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
958 + if (!action)
959 + continue;
960 + len += sprintf(buf+len, "%2d: %8d %c %s",
961 + num, kstat.irqs[0][ LNXINTNUM(i) ],
962 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
963 + action->name);
964 +
965 + for (action=action->next; action; action = action->next)
966 + {
967 + len += sprintf(buf+len, ",%s %s",
968 + (action->flags & SA_INTERRUPT) ? " +" : "",
969 + action->name);
970 + }
971 +
972 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
973 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
974 + else
975 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
976 +
977 + }
978 +
979 + return len;
980 +}
981 +
982 +int request_irq(unsigned int irq,
983 + void (*handler)(int, void *, struct pt_regs *),
984 + unsigned long irqflags,
985 + const char * devname,
986 + void *dev_id)
987 +{
988 + struct irqaction *action;
989 +
990 + if (irq > AVALANCHE_INT_END)
991 + return -EINVAL;
992 + if (!handler)
993 + return -EINVAL;
994 +
995 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
996 + if(!action)
997 + return -ENOMEM;
998 +
999 + action->handler = handler;
1000 + action->flags = irqflags;
1001 + action->mask = 0;
1002 + action->name = devname;
1003 + irq_desc_ti[irq].action = action;
1004 + action->dev_id = dev_id;
1005 +
1006 + action->next = 0;
1007 +
1008 + if(irq < MIPS_EXCEPTION_OFFSET)
1009 + {
1010 + irq_action[irq] = action;
1011 + enable_avalanche_irq(irq);
1012 + return 0;
1013 + }
1014 +
1015 + if(irq < AVALANCHE_INT_END_PRIMARY)
1016 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
1017 + else
1018 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
1019 +
1020 + enable_avalanche_irq(irq);
1021 +
1022 + return 0;
1023 +}
1024 +
1025 +void free_irq(unsigned int irq, void *dev_id)
1026 +{
1027 + struct irqaction *action;
1028 +
1029 + if (irq > AVALANCHE_INT_END) {
1030 + printk("Trying to free IRQ%d\n",irq);
1031 + return;
1032 + }
1033 +
1034 + if(irq < MIPS_EXCEPTION_OFFSET)
1035 + {
1036 + action = irq_action[irq];
1037 + irq_action[irq] = NULL;
1038 + irq_desc_ti[irq].action = NULL;
1039 + disable_avalanche_irq(irq);
1040 + kfree(action);
1041 + return;
1042 + }
1043 +
1044 + if(irq < AVALANCHE_INT_END_PRIMARY) {
1045 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
1046 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
1047 + irq_desc_ti[irq].action = NULL;
1048 + }
1049 + else {
1050 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1051 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1052 + irq_desc_ti[irq].action = NULL;
1053 + }
1054 +
1055 + disable_avalanche_irq(irq);
1056 + kfree(action);
1057 +}
1058 +
1059 +#ifdef CONFIG_KGDB
1060 +extern void breakpoint(void);
1061 +extern int remote_debug;
1062 +#endif
1063 +
1064 +//void init_IRQ(void) __init;
1065 +void __init init_IRQ(void)
1066 +{
1067 + int i;
1068 +
1069 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1070 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1071 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1072 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1073 +
1074 + /* Disable interrupts and clear pending
1075 + */
1076 +
1077 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
1078 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
1079 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
1080 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
1081 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
1082 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
1083 +
1084 +
1085 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
1086 + /* hack for speeding up the pacing. */
1087 + printk("the pacing pre-scalar has been set as 600.\n");
1088 + avalanche_hw0_ipaceregs->ipacep = 600;
1089 + /* Channel to line mapping, Line to Channel mapping */
1090 +
1091 + for(i = 0; i < 40; i++)
1092 + avalanche_int_set(i,i);
1093 +
1094 + /* Now safe to set the exception vector. */
1095 + set_except_vector(0, mipsIRQ);
1096 +
1097 + /* Setup the IRQ description array. These will be mapped
1098 + * as flat interrupts numbers. The mapping is as follows
1099 + *
1100 + * 0-7 MIPS CPU Exceptions (HW/SW)
1101 + * 8-46 Primary Interrupts (Avalanche)
1102 + * 47-78 Secondary Interrupts (Avalanche)
1103 + */
1104 +
1105 + for (i = 0; i <= AVALANCHE_INT_END; i++)
1106 + {
1107 + irq_desc_ti[i].status = IRQ_DISABLED;
1108 + irq_desc_ti[i].action = 0;
1109 + irq_desc_ti[i].depth = 1;
1110 + irq_desc_ti[i].handler = &avalanche_irq_type;
1111 + }
1112 +
1113 +#ifdef CONFIG_KGDB
1114 + if (remote_debug)
1115 + {
1116 + set_debug_traps();
1117 + breakpoint();
1118 + }
1119 +#endif
1120 +}
1121 +
1122 +
1123 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1124 +{
1125 + struct irqaction *action;
1126 + int irq, cpu = smp_processor_id();
1127 + unsigned long int_line_number,status;
1128 + int i,secondary = 0;
1129 + int chan_nr=0;
1130 +
1131 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1132 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1133 +
1134 +
1135 + if(chan_nr < 32)
1136 + {
1137 + if( chan_nr != uni_secondary_interrupt)
1138 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1139 +
1140 + }
1141 +
1142 + if((chan_nr < 40) && (chan_nr > 31))
1143 + {
1144 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1145 + }
1146 +
1147 +
1148 + /* If the Priority Interrupt Index Register returns 40 then no
1149 + * interrupts are pending
1150 + */
1151 +
1152 + if(chan_nr == 40)
1153 + return;
1154 +
1155 + if(chan_nr == uni_secondary_interrupt)
1156 + {
1157 + status = avalanche_hw0_ecregs->exsr;
1158 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1159 + {
1160 + if (status & 1<<i)
1161 + {
1162 + /* clear secondary interrupt */
1163 + avalanche_hw0_ecregs->excr = 1 << i;
1164 + break;
1165 + }
1166 + }
1167 + irq = i;
1168 + secondary = 1;
1169 +
1170 + /* clear the universal secondary interrupt */
1171 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1172 +
1173 + }
1174 + else
1175 + irq = chan_nr;
1176 +
1177 + /* Suraj Add code to clear secondary interrupt */
1178 +
1179 + if(secondary)
1180 + action = hw0_irq_action_secondary[irq];
1181 + else
1182 + action = hw0_irq_action_primary[irq];
1183 +
1184 + /* if action == NULL, then we don't have a handler for the irq */
1185 +
1186 + if ( action == NULL ) {
1187 + printk("No handler for hw0 irq: %i\n", irq);
1188 + return;
1189 + }
1190 +
1191 + irq_enter(cpu,irq);
1192 + if(secondary)
1193 + {
1194 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1195 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1196 + }
1197 + else
1198 + {
1199 + kstat.irqs[0][irq + 8]++;
1200 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
1201 + }
1202 +
1203 + irq_exit(cpu,irq);
1204 +
1205 + if(softirq_pending(cpu))
1206 + do_softirq();
1207 +
1208 + return;
1209 +}
1210 +
1211 +void avalanche_int_set(int channel, int line)
1212 +{
1213 + switch(channel)
1214 + {
1215 + case(0):
1216 + avalanche_hw0_chregs->cintnr0 = line;
1217 + break;
1218 + case(1):
1219 + avalanche_hw0_chregs->cintnr1 = line;
1220 + break;
1221 + case(2):
1222 + avalanche_hw0_chregs->cintnr2 = line;
1223 + break;
1224 + case(3):
1225 + avalanche_hw0_chregs->cintnr3 = line;
1226 + break;
1227 + case(4):
1228 + avalanche_hw0_chregs->cintnr4 = line;
1229 + break;
1230 + case(5):
1231 + avalanche_hw0_chregs->cintnr5 = line;
1232 + break;
1233 + case(6):
1234 + avalanche_hw0_chregs->cintnr6 = line;
1235 + break;
1236 + case(7):
1237 + avalanche_hw0_chregs->cintnr7 = line;
1238 + break;
1239 + case(8):
1240 + avalanche_hw0_chregs->cintnr8 = line;
1241 + break;
1242 + case(9):
1243 + avalanche_hw0_chregs->cintnr9 = line;
1244 + break;
1245 + case(10):
1246 + avalanche_hw0_chregs->cintnr10 = line;
1247 + break;
1248 + case(11):
1249 + avalanche_hw0_chregs->cintnr11 = line;
1250 + break;
1251 + case(12):
1252 + avalanche_hw0_chregs->cintnr12 = line;
1253 + break;
1254 + case(13):
1255 + avalanche_hw0_chregs->cintnr13 = line;
1256 + break;
1257 + case(14):
1258 + avalanche_hw0_chregs->cintnr14 = line;
1259 + break;
1260 + case(15):
1261 + avalanche_hw0_chregs->cintnr15 = line;
1262 + break;
1263 + case(16):
1264 + avalanche_hw0_chregs->cintnr16 = line;
1265 + break;
1266 + case(17):
1267 + avalanche_hw0_chregs->cintnr17 = line;
1268 + break;
1269 + case(18):
1270 + avalanche_hw0_chregs->cintnr18 = line;
1271 + break;
1272 + case(19):
1273 + avalanche_hw0_chregs->cintnr19 = line;
1274 + break;
1275 + case(20):
1276 + avalanche_hw0_chregs->cintnr20 = line;
1277 + break;
1278 + case(21):
1279 + avalanche_hw0_chregs->cintnr21 = line;
1280 + break;
1281 + case(22):
1282 + avalanche_hw0_chregs->cintnr22 = line;
1283 + break;
1284 + case(23):
1285 + avalanche_hw0_chregs->cintnr23 = line;
1286 + break;
1287 + case(24):
1288 + avalanche_hw0_chregs->cintnr24 = line;
1289 + break;
1290 + case(25):
1291 + avalanche_hw0_chregs->cintnr25 = line;
1292 + break;
1293 + case(26):
1294 + avalanche_hw0_chregs->cintnr26 = line;
1295 + break;
1296 + case(27):
1297 + avalanche_hw0_chregs->cintnr27 = line;
1298 + break;
1299 + case(28):
1300 + avalanche_hw0_chregs->cintnr28 = line;
1301 + break;
1302 + case(29):
1303 + avalanche_hw0_chregs->cintnr29 = line;
1304 + break;
1305 + case(30):
1306 + avalanche_hw0_chregs->cintnr30 = line;
1307 + break;
1308 + case(31):
1309 + avalanche_hw0_chregs->cintnr31 = line;
1310 + break;
1311 + case(32):
1312 + avalanche_hw0_chregs->cintnr32 = line;
1313 + break;
1314 + case(33):
1315 + avalanche_hw0_chregs->cintnr33 = line;
1316 + break;
1317 + case(34):
1318 + avalanche_hw0_chregs->cintnr34 = line;
1319 + break;
1320 + case(35):
1321 + avalanche_hw0_chregs->cintnr35 = line;
1322 + break;
1323 + case(36):
1324 + avalanche_hw0_chregs->cintnr36 = line;
1325 + break;
1326 + case(37):
1327 + avalanche_hw0_chregs->cintnr37 = line;
1328 + break;
1329 + case(38):
1330 + avalanche_hw0_chregs->cintnr38 = line;
1331 + break;
1332 + case(39):
1333 + avalanche_hw0_chregs->cintnr39 = line;
1334 + break;
1335 + default:
1336 + printk("Error: Unknown Avalanche interrupt channel\n");
1337 + }
1338 +
1339 + line_to_channel[line] = channel; /* Suraj check */
1340 +
1341 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
1342 + uni_secondary_interrupt = line;
1343 +
1344 +}
1345 +
1346 diff -urN linux-2.4.30/arch/mips/ar7/memory.c linux-2.4.30.dev/arch/mips/ar7/memory.c
1347 --- linux-2.4.30/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
1348 +++ linux-2.4.30.dev/arch/mips/ar7/memory.c 2005-06-14 15:36:59.000000000 +0200
1349 @@ -0,0 +1,130 @@
1350 +/*
1351 + * Carsten Langgaard, carstenl@mips.com
1352 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1353 + *
1354 + * ########################################################################
1355 + *
1356 + * This program is free software; you can distribute it and/or modify it
1357 + * under the terms of the GNU General Public License (Version 2) as
1358 + * published by the Free Software Foundation.
1359 + *
1360 + * This program is distributed in the hope it will be useful, but WITHOUT
1361 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1362 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1363 + * for more details.
1364 + *
1365 + * You should have received a copy of the GNU General Public License along
1366 + * with this program; if not, write to the Free Software Foundation, Inc.,
1367 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1368 + *
1369 + * ########################################################################
1370 + *
1371 + * PROM library functions for acquiring/using memory descriptors given to
1372 + * us from the YAMON.
1373 + *
1374 + */
1375 +#include <linux/config.h>
1376 +#include <linux/init.h>
1377 +#include <linux/mm.h>
1378 +#include <linux/bootmem.h>
1379 +
1380 +#include <asm/bootinfo.h>
1381 +#include <asm/page.h>
1382 +#include <asm/mips-boards/prom.h>
1383 +#include <asm/ar7/ar7.h>
1384 +
1385 +enum yamon_memtypes {
1386 + yamon_dontuse,
1387 + yamon_prom,
1388 + yamon_free,
1389 +};
1390 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1391 +
1392 +/* References to section boundaries */
1393 +extern char _end;
1394 +
1395 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1396 +
1397 +
1398 +struct prom_pmemblock * __init prom_getmdesc(void)
1399 +{
1400 + char *memsize_str;
1401 + unsigned int memsize;
1402 +
1403 + memsize_str = prom_getenv("memsize");
1404 + if (!memsize_str) {
1405 + memsize = 0x02000000;
1406 + } else {
1407 + memsize = simple_strtol(memsize_str, NULL, 0);
1408 + }
1409 +
1410 + memset(mdesc, 0, sizeof(mdesc));
1411 +
1412 + mdesc[0].type = yamon_dontuse;
1413 + mdesc[0].base = 0x00000000;
1414 + mdesc[0].size = AVALANCHE_SDRAM_BASE;
1415 +
1416 + mdesc[1].type = yamon_prom;
1417 + mdesc[1].base = AVALANCHE_SDRAM_BASE;
1418 + mdesc[1].size = 0x00020000;
1419 +
1420 + mdesc[2].type = yamon_free;
1421 + mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000;
1422 + mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base;
1423 +
1424 + return &mdesc[0];
1425 +}
1426 +
1427 +static int __init prom_memtype_classify (unsigned int type)
1428 +{
1429 + switch (type) {
1430 + case yamon_free:
1431 + return BOOT_MEM_RAM;
1432 + case yamon_prom:
1433 + return BOOT_MEM_ROM_DATA;
1434 + default:
1435 + return BOOT_MEM_RESERVED;
1436 + }
1437 +}
1438 +
1439 +void __init prom_meminit(void)
1440 +{
1441 + struct prom_pmemblock *p;
1442 +
1443 + p = prom_getmdesc();
1444 +
1445 + while (p->size) {
1446 + long type;
1447 + unsigned long base, size;
1448 +
1449 + type = prom_memtype_classify (p->type);
1450 + base = p->base;
1451 + size = p->size;
1452 +
1453 + add_memory_region(base, size, type);
1454 + p++;
1455 + }
1456 +}
1457 +
1458 +void __init prom_free_prom_memory (void)
1459 +{
1460 + int i;
1461 + unsigned long freed = 0;
1462 + unsigned long addr;
1463 +
1464 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1465 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1466 + continue;
1467 +
1468 + addr = boot_mem_map.map[i].addr;
1469 + while (addr < boot_mem_map.map[i].addr
1470 + + boot_mem_map.map[i].size) {
1471 + ClearPageReserved(virt_to_page(__va(addr)));
1472 + set_page_count(virt_to_page(__va(addr)), 1);
1473 + free_page((unsigned long)__va(addr));
1474 + addr += PAGE_SIZE;
1475 + freed += PAGE_SIZE;
1476 + }
1477 + }
1478 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1479 +}
1480 diff -urN linux-2.4.30/arch/mips/ar7/mipsIRQ.S linux-2.4.30.dev/arch/mips/ar7/mipsIRQ.S
1481 --- linux-2.4.30/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1482 +++ linux-2.4.30.dev/arch/mips/ar7/mipsIRQ.S 2005-06-14 15:36:59.000000000 +0200
1483 @@ -0,0 +1,120 @@
1484 +/*
1485 + * Carsten Langgaard, carstenl@mips.com
1486 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1487 + *
1488 + * ########################################################################
1489 + *
1490 + * This program is free software; you can distribute it and/or modify it
1491 + * under the terms of the GNU General Public License (Version 2) as
1492 + * published by the Free Software Foundation.
1493 + *
1494 + * This program is distributed in the hope it will be useful, but WITHOUT
1495 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1496 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1497 + * for more details.
1498 + *
1499 + * You should have received a copy of the GNU General Public License along
1500 + * with this program; if not, write to the Free Software Foundation, Inc.,
1501 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1502 + *
1503 + * ########################################################################
1504 + *
1505 + * Interrupt exception dispatch code.
1506 + *
1507 + */
1508 +#include <linux/config.h>
1509 +
1510 +#include <asm/asm.h>
1511 +#include <asm/mipsregs.h>
1512 +#include <asm/regdef.h>
1513 +#include <asm/stackframe.h>
1514 +
1515 +/* A lot of complication here is taken away because:
1516 + *
1517 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1518 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1519 + * common case is one pending IRQ so optimize in that direction.
1520 + *
1521 + * 2) We need not check against bits in the status register IRQ mask, that
1522 + * would make this routine slow as hell.
1523 + *
1524 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1525 + * between like BSD spl() brain-damage.
1526 + *
1527 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1528 + * IRQs which we don't use at all and all external interrupt sources are
1529 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1530 + *
1531 + * MIPS IRQ Source
1532 + * -------- ------
1533 + * 0 Software (ignored)
1534 + * 1 Software (ignored)
1535 + * 2 Combined hardware interrupt (hw0)
1536 + * 3 Hardware (ignored)
1537 + * 4 Hardware (ignored)
1538 + * 5 Hardware (ignored)
1539 + * 6 Hardware (ignored)
1540 + * 7 R4k timer (what we use)
1541 + *
1542 + * Note: On the SEAD board thing are a little bit different.
1543 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1544 + * wired to UART1.
1545 + *
1546 + * We handle the IRQ according to _our_ priority which is:
1547 + *
1548 + * Highest ---- R4k Timer
1549 + * Lowest ---- Combined hardware interrupt
1550 + *
1551 + * then we just return, if multiple IRQs are pending then we will just take
1552 + * another exception, big deal.
1553 + */
1554 +
1555 +.text
1556 +.set noreorder
1557 +.set noat
1558 + .align 5
1559 +NESTED(mipsIRQ, PT_SIZE, sp)
1560 + SAVE_ALL
1561 + CLI
1562 + .set at
1563 +
1564 + mfc0 s0, CP0_CAUSE # get irq bits
1565 +
1566 + /* First we check for r4k counter/timer IRQ. */
1567 + andi a0, s0, CAUSEF_IP7
1568 + beq a0, zero, 1f
1569 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1570 +
1571 + /* Wheee, a timer interrupt. */
1572 + move a0, sp
1573 + jal ar7_timer_interrupt
1574 + nop
1575 +
1576 + j ret_from_irq
1577 + nop
1578 +
1579 + 1:
1580 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1581 + nop
1582 +
1583 + /* Wheee, combined hardware level zero interrupt. */
1584 + jal avalanche_hw0_irqdispatch
1585 + move a0, sp # delay slot
1586 +
1587 + j ret_from_irq
1588 + nop # delay slot
1589 +
1590 + 1:
1591 + /*
1592 + * Here by mistake? This is possible, what can happen is that by the
1593 + * time we take the exception the IRQ pin goes low, so just leave if
1594 + * this is the case.
1595 + */
1596 + move a1,s0
1597 + PRINT("Got interrupt: c0_cause = %08x\n")
1598 + mfc0 a1, CP0_EPC
1599 + PRINT("c0_epc = %08x\n")
1600 +
1601 + j ret_from_irq
1602 + nop
1603 +END(mipsIRQ)
1604 diff -urN linux-2.4.30/arch/mips/ar7/printf.c linux-2.4.30.dev/arch/mips/ar7/printf.c
1605 --- linux-2.4.30/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
1606 +++ linux-2.4.30.dev/arch/mips/ar7/printf.c 2005-06-14 15:36:59.000000000 +0200
1607 @@ -0,0 +1,51 @@
1608 +/*
1609 + * Carsten Langgaard, carstenl@mips.com
1610 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1611 + *
1612 + * This program is free software; you can distribute it and/or modify it
1613 + * under the terms of the GNU General Public License (Version 2) as
1614 + * published by the Free Software Foundation.
1615 + *
1616 + * This program is distributed in the hope it will be useful, but WITHOUT
1617 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1618 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1619 + * for more details.
1620 + *
1621 + * You should have received a copy of the GNU General Public License along
1622 + * with this program; if not, write to the Free Software Foundation, Inc.,
1623 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1624 + *
1625 + * Putting things on the screen/serial line using Adam2 facilities.
1626 + */
1627 +
1628 +#include <linux/config.h>
1629 +#include <linux/init.h>
1630 +#include <linux/kernel.h>
1631 +#include <linux/serial_reg.h>
1632 +#include <linux/spinlock.h>
1633 +#include <asm/io.h>
1634 +#include <asm/serial.h>
1635 +#include <asm/addrspace.h>
1636 +#include <asm/ar7/ar7.h>
1637 +
1638 +static char ppbuf[1024];
1639 +
1640 +void (*prom_print_str)(unsigned int out, char *s, int len);
1641 +
1642 +void prom_printf(char *fmt, ...) __init;
1643 +void prom_printf(char *fmt, ...)
1644 +{
1645 + va_list args;
1646 + int len;
1647 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
1648 +
1649 + va_start(args, fmt);
1650 + vsprintf(ppbuf, fmt, args);
1651 + len = strlen(ppbuf);
1652 +
1653 + prom_print_str(1, ppbuf, len);
1654 +
1655 + va_end(args);
1656 + return;
1657 +
1658 +}
1659 diff -urN linux-2.4.30/arch/mips/ar7/reset.c linux-2.4.30.dev/arch/mips/ar7/reset.c
1660 --- linux-2.4.30/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
1661 +++ linux-2.4.30.dev/arch/mips/ar7/reset.c 2005-06-14 15:36:59.000000000 +0200
1662 @@ -0,0 +1,54 @@
1663 +/*
1664 + * Carsten Langgaard, carstenl@mips.com
1665 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1666 + *
1667 + * ########################################################################
1668 + *
1669 + * This program is free software; you can distribute it and/or modify it
1670 + * under the terms of the GNU General Public License (Version 2) as
1671 + * published by the Free Software Foundation.
1672 + *
1673 + * This program is distributed in the hope it will be useful, but WITHOUT
1674 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1675 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1676 + * for more details.
1677 + *
1678 + * You should have received a copy of the GNU General Public License along
1679 + * with this program; if not, write to the Free Software Foundation, Inc.,
1680 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1681 + *
1682 + * ########################################################################
1683 + *
1684 + * Reset the MIPS boards.
1685 + *
1686 + */
1687 +#include <linux/config.h>
1688 +
1689 +#include <asm/reboot.h>
1690 +#include <asm/mips-boards/generic.h>
1691 +
1692 +static void ar7_machine_restart(char *command);
1693 +static void ar7_machine_halt(void);
1694 +static void ar7_machine_power_off(void);
1695 +
1696 +static void ar7_machine_restart(char *command)
1697 +{
1698 +
1699 +}
1700 +
1701 +static void ar7_machine_halt(void)
1702 +{
1703 +
1704 +}
1705 +
1706 +static void ar7_machine_power_off(void)
1707 +{
1708 +
1709 +}
1710 +
1711 +void ar7_reboot_setup(void)
1712 +{
1713 + _machine_restart = ar7_machine_restart;
1714 + _machine_halt = ar7_machine_halt;
1715 + _machine_power_off = ar7_machine_power_off;
1716 +}
1717 diff -urN linux-2.4.30/arch/mips/ar7/setup.c linux-2.4.30.dev/arch/mips/ar7/setup.c
1718 --- linux-2.4.30/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
1719 +++ linux-2.4.30.dev/arch/mips/ar7/setup.c 2005-06-14 15:36:59.000000000 +0200
1720 @@ -0,0 +1,150 @@
1721 +/*
1722 + * Carsten Langgaard, carstenl@mips.com
1723 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
1724 + *
1725 + * This program is free software; you can distribute it and/or modify it
1726 + * under the terms of the GNU General Public License (Version 2) as
1727 + * published by the Free Software Foundation.
1728 + *
1729 + * This program is distributed in the hope it will be useful, but WITHOUT
1730 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1731 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1732 + * for more details.
1733 + *
1734 + * You should have received a copy of the GNU General Public License along
1735 + * with this program; if not, write to the Free Software Foundation, Inc.,
1736 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1737 + */
1738 +#include <linux/config.h>
1739 +#include <linux/init.h>
1740 +#include <linux/sched.h>
1741 +#include <linux/mc146818rtc.h>
1742 +#include <linux/ioport.h>
1743 +
1744 +#include <asm/cpu.h>
1745 +#include <asm/bootinfo.h>
1746 +#include <asm/irq.h>
1747 +#include <asm/mips-boards/generic.h>
1748 +#include <asm/mips-boards/prom.h>
1749 +
1750 +#include <asm/dma.h>
1751 +#include <asm/time.h>
1752 +#include <asm/traps.h>
1753 +
1754 +
1755 +#define _LINK_KSEG0_
1756 +#define LITTLE_ENDIAN
1757 +#include <asm/ar7/tnetd73xx.h>
1758 +#include <asm/ar7/tnetd73xx_misc.h>
1759 +
1760 +// Specific for ar7wrd
1761 +unsigned int tnetd73xx_vbus_freq;
1762 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
1763 +#define AFECLK_FREQ 35328000
1764 +#define REFCLK_FREQ 25000000
1765 +#define OSC3_FREQ 24000000
1766 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
1767 +
1768 +#if defined(CONFIG_AR7_MARVELL)
1769 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
1770 +#else
1771 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
1772 +#endif
1773 +
1774 +
1775 +#ifdef CONFIG_KGDB
1776 +extern void rs_kgdb_hook(int);
1777 +int remote_debug = 0;
1778 +#endif
1779 +
1780 +extern struct rtc_ops no_rtc_ops;
1781 +
1782 +extern void ar7_reboot_setup(void);
1783 +
1784 +extern void ar7_time_init(void);
1785 +extern void ar7_timer_setup(struct irqaction *irq);
1786 +
1787 +/* maybe some of this is not needed? */
1788 +static void ar7_platform_init(void)
1789 +{
1790 + //tnetd73xx_gpio_init();
1791 +
1792 + tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET);
1793 + //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
1794 + //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);
1795 +
1796 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET);
1797 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET);
1798 +
1799 + tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);
1800 +
1801 + tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2;
1802 +
1803 +#if defined(CONFIG_AR7WRD)
1804 + if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) {
1805 + tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150));
1806 + }
1807 +#endif
1808 +
1809 +}
1810 +
1811 +const char *get_system_type(void)
1812 +{
1813 + return "Texas Instruments AR7";
1814 +}
1815 +
1816 +void __init ar7_setup(void)
1817 +{
1818 +#ifdef CONFIG_KGDB
1819 + int rs_putDebugChar(char);
1820 + char rs_getDebugChar(void);
1821 + extern int (*generic_putDebugChar)(char);
1822 + extern char (*generic_getDebugChar)(void);
1823 +#endif
1824 + char *argptr;
1825 +
1826 +#ifdef CONFIG_SERIAL_CONSOLE
1827 + argptr = prom_getcmdline();
1828 + if ((argptr = strstr(argptr, "console=")) == NULL) {
1829 + argptr = prom_getcmdline();
1830 + strcat(argptr, " console=ttyS0,38400");
1831 + }
1832 +#endif
1833 +
1834 +#ifdef CONFIG_KGDB
1835 + argptr = prom_getcmdline();
1836 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
1837 + int line;
1838 + argptr += strlen("kgdb=ttyS");
1839 + if (*argptr != '0' && *argptr != '1')
1840 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
1841 + "falling back to /dev/ttyS1\n", *argptr);
1842 + line = *argptr == '0' ? 0 : 1;
1843 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
1844 + line ? 1 : 0);
1845 +
1846 + rs_kgdb_hook(line);
1847 + generic_putDebugChar = rs_putDebugChar;
1848 + generic_getDebugChar = rs_getDebugChar;
1849 +
1850 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
1851 + "please connect your debugger\n", line ? 1 : 0);
1852 +
1853 + remote_debug = 1;
1854 + /* Breakpoints are in init_IRQ() */
1855 + }
1856 +#endif
1857 +
1858 + argptr = prom_getcmdline();
1859 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
1860 + cpu_data[0].options &= ~MIPS_CPU_FPU;
1861 +
1862 + rtc_ops = &no_rtc_ops;
1863 +
1864 + ar7_platform_init();
1865 +
1866 + ar7_reboot_setup();
1867 +
1868 + board_time_init = ar7_time_init;
1869 + board_timer_setup = ar7_timer_setup;
1870 +}
1871 diff -urN linux-2.4.30/arch/mips/ar7/time.c linux-2.4.30.dev/arch/mips/ar7/time.c
1872 --- linux-2.4.30/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
1873 +++ linux-2.4.30.dev/arch/mips/ar7/time.c 2005-06-14 15:36:59.000000000 +0200
1874 @@ -0,0 +1,125 @@
1875 +/*
1876 + * Carsten Langgaard, carstenl@mips.com
1877 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1878 + *
1879 + * ########################################################################
1880 + *
1881 + * This program is free software; you can distribute it and/or modify it
1882 + * under the terms of the GNU General Public License (Version 2) as
1883 + * published by the Free Software Foundation.
1884 + *
1885 + * This program is distributed in the hope it will be useful, but WITHOUT
1886 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1887 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1888 + * for more details.
1889 + *
1890 + * You should have received a copy of the GNU General Public License along
1891 + * with this program; if not, write to the Free Software Foundation, Inc.,
1892 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1893 + *
1894 + * ########################################################################
1895 + *
1896 + * Setting up the clock on the MIPS boards.
1897 + *
1898 + */
1899 +
1900 +#include <linux/types.h>
1901 +#include <linux/config.h>
1902 +#include <linux/init.h>
1903 +#include <linux/kernel_stat.h>
1904 +#include <linux/sched.h>
1905 +#include <linux/spinlock.h>
1906 +
1907 +#include <asm/mipsregs.h>
1908 +#include <asm/ptrace.h>
1909 +#include <asm/hardirq.h>
1910 +#include <asm/div64.h>
1911 +
1912 +#include <linux/interrupt.h>
1913 +#include <linux/mc146818rtc.h>
1914 +#include <linux/timex.h>
1915 +
1916 +#include <asm/mips-boards/generic.h>
1917 +#include <asm/mips-boards/prom.h>
1918 +#include <asm/ar7/ar7.h>
1919 +
1920 +extern asmlinkage void mipsIRQ(void);
1921 +
1922 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
1923 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1924 +
1925 +#define MIPS_CPU_TIMER_IRQ 7
1926 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1927 +
1928 +static inline void ack_r4ktimer(unsigned long newval)
1929 +{
1930 + write_c0_compare(newval);
1931 +}
1932 +
1933 +void ar7_timer_interrupt(struct pt_regs *regs)
1934 +{
1935 + int cpu = smp_processor_id();
1936 +
1937 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
1938 +
1939 + if (r4k_offset == 0)
1940 + goto null;
1941 +
1942 + do {
1943 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
1944 + do_timer(regs);
1945 + r4k_cur += r4k_offset;
1946 + ack_r4ktimer(r4k_cur);
1947 +
1948 + } while (((unsigned long)read_c0_count()
1949 + - r4k_cur) < 0x7fffffff);
1950 +
1951 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
1952 +
1953 + if (softirq_pending(cpu))
1954 + do_softirq();
1955 +
1956 + return;
1957 +
1958 +null:
1959 + ack_r4ktimer(0);
1960 +}
1961 +
1962 +/*
1963 + * Figure out the r4k offset, the amount to increment the compare
1964 + * register for each time tick.
1965 + */
1966 +static unsigned long __init cal_r4koff(void)
1967 +{
1968 + return ((CONFIG_AR7_FREQUENCY*500000)/HZ);
1969 +}
1970 +
1971 +void __init ar7_time_init(void)
1972 +{
1973 + unsigned long flags;
1974 + unsigned int est_freq;
1975 +
1976 + set_except_vector(0, mipsIRQ);
1977 + write_c0_count(0);
1978 +
1979 + printk("calculating r4koff... ");
1980 + r4k_offset = cal_r4koff();
1981 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1982 +
1983 + est_freq = 2*r4k_offset*HZ;
1984 + est_freq += 5000; /* round */
1985 + est_freq -= est_freq%10000;
1986 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1987 + (est_freq%1000000)*100/1000000);
1988 +}
1989 +
1990 +void __init ar7_timer_setup(struct irqaction *irq)
1991 +{
1992 + /* we are using the cpu counter for timer interrupts */
1993 + irq->handler = no_action; /* we use our own handler */
1994 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1995 +
1996 + r4k_cur = (read_c0_count() + r4k_offset);
1997 + write_c0_compare(r4k_cur);
1998 + set_c0_status(ALLINTS);
1999 +}
2000 diff -urN linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c linux-2.4.30.dev/arch/mips/ar7/tnetd73xx_misc.c
2001 --- linux-2.4.30/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
2002 +++ linux-2.4.30.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-06-14 15:36:59.000000000 +0200
2003 @@ -0,0 +1,924 @@
2004 +/******************************************************************************
2005 + * FILE PURPOSE: TNETD73xx Misc modules API Source
2006 + ******************************************************************************
2007 + * FILE NAME: tnetd73xx_misc.c
2008 + *
2009 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
2010 + * FSER Modules API
2011 + * As per TNETD73xx specifications
2012 + *
2013 + * REVISION HISTORY:
2014 + * 27 Nov 02 - Sharath Kumar PSP TII
2015 + * 14 Feb 03 - Anant Gole PSP TII
2016 + *
2017 + * (C) Copyright 2002, Texas Instruments, Inc
2018 + *******************************************************************************/
2019 +
2020 +#define LITTLE_ENDIAN
2021 +#define _LINK_KSEG0_
2022 +
2023 +#include <linux/types.h>
2024 +#include <asm/ar7/tnetd73xx.h>
2025 +#include <asm/ar7/tnetd73xx_misc.h>
2026 +
2027 +/* TNETD73XX Revision */
2028 +u32 tnetd73xx_get_revision(void)
2029 +{
2030 + /* Read Chip revision register - This register is from GPIO module */
2031 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2032 +}
2033 +
2034 +/*****************************************************************************
2035 + * Reset Control Module
2036 + *****************************************************************************/
2037 +
2038 +
2039 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2040 +{
2041 + u32 reset_status;
2042 +
2043 + /* read current reset register */
2044 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2045 +
2046 + if (reset_ctrl == OUT_OF_RESET)
2047 + {
2048 + /* bring module out of reset */
2049 + reset_status |= (1 << reset_module);
2050 + }
2051 + else
2052 + {
2053 + /* put module in reset */
2054 + reset_status &= (~(1 << reset_module));
2055 + }
2056 +
2057 + /* write to the reset register */
2058 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2059 +}
2060 +
2061 +
2062 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2063 +{
2064 + u32 reset_status;
2065 +
2066 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2067 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2068 +}
2069 +
2070 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2071 +{
2072 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2073 +}
2074 +
2075 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2076 +
2077 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2078 +{
2079 + u32 sys_reset_status;
2080 +
2081 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2082 +
2083 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2084 +}
2085 +
2086 +
2087 +/*****************************************************************************
2088 + * Power Control Module
2089 + *****************************************************************************/
2090 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2091 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2092 +
2093 +
2094 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2095 +{
2096 + u32 power_status;
2097 +
2098 + /* read current power down control register */
2099 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2100 +
2101 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2102 + {
2103 + /* power down the module */
2104 + power_status |= (1 << power_module);
2105 + }
2106 + else
2107 + {
2108 + /* power on the module */
2109 + power_status &= (~(1 << power_module));
2110 + }
2111 +
2112 + /* write to the reset register */
2113 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2114 +}
2115 +
2116 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2117 +{
2118 + u32 power_status;
2119 +
2120 + /* read current power down control register */
2121 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2122 +
2123 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2124 +}
2125 +
2126 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2127 +{
2128 + u32 power_status;
2129 +
2130 + /* read current power down control register */
2131 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2132 +
2133 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2134 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2135 +
2136 + /* write to power down control register */
2137 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2138 +}
2139 +
2140 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2141 +{
2142 + u32 power_status;
2143 +
2144 + /* read current power down control register */
2145 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2146 +
2147 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2148 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2149 +
2150 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2151 +}
2152 +
2153 +
2154 +/*****************************************************************************
2155 + * Wakeup Control
2156 + *****************************************************************************/
2157 +
2158 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2159 +
2160 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2161 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2162 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2163 +{
2164 + u32 wakeup_status;
2165 +
2166 + /* read the wakeup control register */
2167 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2168 +
2169 + /* enable/disable */
2170 + if (wakeup_ctrl == WAKEUP_ENABLED)
2171 + {
2172 + /* enable wakeup */
2173 + wakeup_status |= wakeup_int;
2174 + }
2175 + else
2176 + {
2177 + /* disable wakeup */
2178 + wakeup_status &= (~wakeup_int);
2179 + }
2180 +
2181 + /* set polarity */
2182 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2183 + {
2184 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2185 + }
2186 + else
2187 + {
2188 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2189 + }
2190 +
2191 + /* write the wakeup control register */
2192 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2193 +}
2194 +
2195 +
2196 +/*****************************************************************************
2197 + * FSER Control
2198 + *****************************************************************************/
2199 +
2200 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2201 +{
2202 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2203 +}
2204 +
2205 +/*****************************************************************************
2206 + * Clock Control
2207 + *****************************************************************************/
2208 +
2209 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2210 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2211 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2212 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2213 +
2214 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2215 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2216 +
2217 +#define CLKC_PRE_DIVIDER 0x0000001F
2218 +#define CLKC_POST_DIVIDER 0x001F0000
2219 +
2220 +#define CLKC_PLL_STATUS 0x1
2221 +#define CLKC_PLL_FACTOR 0x0000F000
2222 +
2223 +#define BOOTCR_PLL_BYPASS (1 << 5)
2224 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2225 +
2226 +#define MIPS_PLL_SELECT 0x00030000
2227 +#define SYSTEM_PLL_SELECT 0x0000C000
2228 +#define USB_PLL_SELECT 0x000C0000
2229 +#define ADSLSS_PLL_SELECT 0x00C00000
2230 +
2231 +#define MIPS_AFECLKI_SELECT 0x00000000
2232 +#define MIPS_REFCLKI_SELECT 0x00010000
2233 +#define MIPS_XTAL3IN_SELECT 0x00020000
2234 +
2235 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2236 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2237 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2238 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2239 +
2240 +#define USB_SYSPLL_SELECT 0x00000000
2241 +#define USB_REFCLKI_SELECT 0x00040000
2242 +#define USB_XTAL3IN_SELECT 0x00080000
2243 +#define USB_MIPSPLL_SELECT 0x000C0000
2244 +
2245 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2246 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2247 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2248 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2249 +
2250 +#define SYS_MAX CLK_MHZ(150)
2251 +#define SYS_MIN CLK_MHZ(1)
2252 +
2253 +#define MIPS_SYNC_MAX SYS_MAX
2254 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2255 +#define MIPS_MIN CLK_MHZ(1)
2256 +
2257 +#define USB_MAX CLK_MHZ(100)
2258 +#define USB_MIN CLK_MHZ(1)
2259 +
2260 +#define ADSL_MAX CLK_MHZ(180)
2261 +#define ADSL_MIN CLK_MHZ(1)
2262 +
2263 +#define PLL_MUL_MAXFACTOR 15
2264 +#define MAX_DIV_VALUE 32
2265 +#define MIN_DIV_VALUE 1
2266 +
2267 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2268 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2269 +
2270 +#define DIVIDER_LOCK_TIME 10100
2271 +#define PLL_LOCK_TIME 10100 * 75
2272 +
2273 +
2274 +
2275 + /****************************************************************************
2276 + * DATA PURPOSE: PRIVATE Variables
2277 + **************************************************************************/
2278 + static u32 *clk_src[4];
2279 + static u32 mips_pll_out;
2280 + static u32 sys_pll_out;
2281 + static u32 afeclk_inp;
2282 + static u32 refclk_inp;
2283 + static u32 xtal_inp;
2284 + static u32 present_min;
2285 + static u32 present_max;
2286 +
2287 + /* Forward References */
2288 + static u32 find_gcd(u32 min, u32 max);
2289 + static u32 compute_prediv( u32 divider, u32 min, u32 max);
2290 + static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2291 + static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2292 + static void find_approx(u32 *,u32 *,u32);
2293 +
2294 + /****************************************************************************
2295 + * FUNCTION: tnetd73xx_clkc_init
2296 + ****************************************************************************
2297 + * Description: The routine initializes the internal variables depending on
2298 + * on the sources selected for different clocks.
2299 + ***************************************************************************/
2300 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2301 +{
2302 +
2303 + u32 choice;
2304 +
2305 + afeclk_inp = afeclk;
2306 + refclk_inp = refclk;
2307 + xtal_inp = xtal3in;
2308 +
2309 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2310 + switch(choice)
2311 + {
2312 + case MIPS_AFECLKI_SELECT:
2313 + clk_src[CLKC_MIPS] = &afeclk_inp;
2314 + break;
2315 +
2316 + case MIPS_REFCLKI_SELECT:
2317 + clk_src[CLKC_MIPS] = &refclk_inp;
2318 + break;
2319 +
2320 + case MIPS_XTAL3IN_SELECT:
2321 + clk_src[CLKC_MIPS] = &xtal_inp;
2322 + break;
2323 +
2324 + default :
2325 + clk_src[CLKC_MIPS] = 0;
2326 +
2327 + }
2328 +
2329 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2330 + switch(choice)
2331 + {
2332 + case SYSTEM_AFECLKI_SELECT:
2333 + clk_src[CLKC_SYS] = &afeclk_inp;
2334 + break;
2335 +
2336 + case SYSTEM_REFCLKI_SELECT:
2337 + clk_src[CLKC_SYS] = &refclk_inp;
2338 + break;
2339 +
2340 + case SYSTEM_XTAL3IN_SELECT:
2341 + clk_src[CLKC_SYS] = &xtal_inp;
2342 + break;
2343 +
2344 + case SYSTEM_MIPSPLL_SELECT:
2345 + clk_src[CLKC_SYS] = &mips_pll_out;
2346 + break;
2347 +
2348 + default :
2349 + clk_src[CLKC_SYS] = 0;
2350 +
2351 + }
2352 +
2353 +
2354 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2355 + switch(choice)
2356 + {
2357 + case ADSLSS_AFECLKI_SELECT:
2358 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2359 + break;
2360 +
2361 + case ADSLSS_REFCLKI_SELECT:
2362 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2363 + break;
2364 +
2365 + case ADSLSS_XTAL3IN_SELECT:
2366 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2367 + break;
2368 +
2369 + case ADSLSS_MIPSPLL_SELECT:
2370 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2371 + break;
2372 +
2373 + default :
2374 + clk_src[CLKC_ADSLSS] = 0;
2375 +
2376 + }
2377 +
2378 +
2379 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2380 + switch(choice)
2381 + {
2382 + case USB_SYSPLL_SELECT:
2383 + clk_src[CLKC_USB] = &sys_pll_out ;
2384 + break;
2385 +
2386 + case USB_REFCLKI_SELECT:
2387 + clk_src[CLKC_USB] = &refclk_inp;
2388 + break;
2389 +
2390 + case USB_XTAL3IN_SELECT:
2391 + clk_src[CLKC_USB] = &xtal_inp;
2392 + break;
2393 +
2394 + case USB_MIPSPLL_SELECT:
2395 + clk_src[CLKC_USB] = &mips_pll_out;
2396 + break;
2397 +
2398 + default :
2399 + clk_src[CLKC_USB] = 0;
2400 +
2401 + }
2402 +}
2403 +
2404 +
2405 +
2406 +/****************************************************************************
2407 + * FUNCTION: tnetd73xx_clkc_set_freq
2408 + ****************************************************************************
2409 + * Description: The above routine is called to set the output_frequency of the
2410 + * selected clock(using clk_id) to the required value given
2411 + * by the variable output_freq.
2412 + ***************************************************************************/
2413 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2414 +(
2415 + TNETD73XX_CLKC_ID_T clk_id,
2416 + u32 output_freq
2417 + )
2418 +{
2419 + u32 base_freq;
2420 + u32 multiplier;
2421 + u32 divider;
2422 + u32 min_prediv;
2423 + u32 max_prediv;
2424 + u32 prediv;
2425 + u32 postdiv;
2426 + u32 temp;
2427 +
2428 + /* check if PLLs are bypassed*/
2429 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2430 + {
2431 + return TNETD73XX_ERR_ERROR;
2432 + }
2433 +
2434 + /*check if the requested output_frequency is in valid range*/
2435 + switch( clk_id )
2436 + {
2437 + case CLKC_SYS:
2438 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2439 + {
2440 + return TNETD73XX_ERR_ERROR;
2441 + }
2442 + present_min = SYS_MIN;
2443 + present_max = SYS_MAX;
2444 + break;
2445 +
2446 + case CLKC_MIPS:
2447 + if((output_freq < MIPS_MIN) ||
2448 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2449 + {
2450 + return TNETD73XX_ERR_ERROR;
2451 + }
2452 + present_min = MIPS_MIN;
2453 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2454 + break;
2455 +
2456 + case CLKC_USB:
2457 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2458 + {
2459 + return TNETD73XX_ERR_ERROR;
2460 + }
2461 + present_min = USB_MIN;
2462 + present_max = USB_MAX;
2463 + break;
2464 +
2465 + case CLKC_ADSLSS:
2466 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2467 + {
2468 + return TNETD73XX_ERR_ERROR;
2469 + }
2470 + present_min = ADSL_MIN;
2471 + present_max = ADSL_MAX;
2472 + break;
2473 + }
2474 +
2475 +
2476 + base_freq = get_base_frequency(clk_id);
2477 +
2478 +
2479 + /* check for minimum base frequency value */
2480 + if( base_freq < MIN_PLL_INP_FREQ)
2481 + {
2482 + return TNETD73XX_ERR_ERROR;
2483 + }
2484 +
2485 + get_val(output_freq, base_freq, &multiplier, &divider);
2486 +
2487 + /* check multiplier range */
2488 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2489 + {
2490 + return TNETD73XX_ERR_ERROR;
2491 + }
2492 +
2493 + /* check divider value */
2494 + if( divider == 0 )
2495 + {
2496 + return TNETD73XX_ERR_ERROR;
2497 + }
2498 +
2499 + /*compute minimum and maximum predivider values */
2500 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2501 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2502 +
2503 + /*adjust the value of divider so that it not less than minimum predivider value*/
2504 + if (divider < min_prediv)
2505 + {
2506 + temp = CEIL(min_prediv, divider);
2507 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2508 + {
2509 + return TNETD73XX_ERR_ERROR ;
2510 + }
2511 + else
2512 + {
2513 + multiplier = temp * multiplier;
2514 + divider = min_prediv;
2515 + }
2516 +
2517 + }
2518 +
2519 + /* compute predivider and postdivider values */
2520 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2521 + postdiv = CEIL(divider,prediv);
2522 +
2523 + /*return fail if postdivider value falls out of range */
2524 + if(postdiv > MAX_DIV_VALUE)
2525 + {
2526 + return TNETD73XX_ERR_ERROR;
2527 + }
2528 +
2529 +
2530 + /*write predivider and postdivider values*/
2531 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2532 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2533 +
2534 + /*wait for divider output to stabilise*/
2535 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2536 +
2537 + /*write to PLL clock register*/
2538 +
2539 + if(clk_id == CLKC_SYS)
2540 + {
2541 + /* but before writing put DRAM to hold mode */
2542 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2543 + }
2544 + /*Bring PLL into div mode */
2545 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2546 +
2547 + /*compute the word to be written to PLLCR
2548 + *corresponding to multiplier value
2549 + */
2550 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2551 +
2552 + /* wait till PLL enters div mode */
2553 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2554 + /*nothing*/;
2555 +
2556 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2557 +
2558 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2559 + /*nothing*/;
2560 +
2561 +
2562 + /*wait for External pll to lock*/
2563 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2564 +
2565 + if(clk_id == CLKC_SYS)
2566 + {
2567 + /* Bring DRAM out of hold */
2568 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2569 + }
2570 +
2571 + return TNETD73XX_ERR_OK ;
2572 +}
2573 +
2574 +/****************************************************************************
2575 + * FUNCTION: tnetd73xx_clkc_get_freq
2576 + ****************************************************************************
2577 + * Description: The above routine is called to get the output_frequency of the
2578 + * selected clock( clk_id)
2579 + ***************************************************************************/
2580 +u32 tnetd73xx_clkc_get_freq
2581 +(
2582 + TNETD73XX_CLKC_ID_T clk_id
2583 + )
2584 +{
2585 +
2586 + u32 clk_ctrl_register;
2587 + u32 clk_pll_setting;
2588 + u32 clk_predivider;
2589 + u32 clk_postdivider;
2590 + u16 pll_factor;
2591 + u32 base_freq;
2592 + u32 divider;
2593 +
2594 + base_freq = get_base_frequency(clk_id);
2595 +
2596 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2597 +
2598 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2599 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2600 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2601 +
2602 + divider = clk_predivider * clk_postdivider;
2603 +
2604 +
2605 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2606 + {
2607 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2608 + }
2609 +
2610 +
2611 + else
2612 + {
2613 + /* return the current clock speed based upon the PLL setting */
2614 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2615 +
2616 + /* Get the PLL multiplication factor */
2617 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2618 +
2619 + /* Check if we're in divide mode or multiply mode */
2620 + if((clk_pll_setting & 0x1) == 0)
2621 + {
2622 + /* We're in divide mode */
2623 + if(pll_factor < 0x10)
2624 + return (CEIL(base_freq >> 1, divider));
2625 + else
2626 + return (CEIL(base_freq >> 2, divider));
2627 + }
2628 +
2629 + else /* We're in PLL mode */
2630 + {
2631 + /* See if PLLNDIV & PLLDIV are set */
2632 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2633 + {
2634 + if(clk_pll_setting & 0x1000)
2635 + {
2636 + /* clk = base_freq * k/2 */
2637 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2638 + }
2639 + else
2640 + {
2641 + /* clk = base_freq * (k-1) / 4)*/
2642 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2643 + }
2644 + }
2645 + else
2646 + {
2647 + if(pll_factor < 0x10)
2648 + {
2649 + /* clk = base_freq * k */
2650 + return(CEIL(base_freq * pll_factor, divider));
2651 + }
2652 +
2653 + else
2654 + {
2655 + /* clk = base_freq */
2656 + return(CEIL(base_freq, divider));
2657 + }
2658 + }
2659 + }
2660 + return(0); /* Should never reach here */
2661 +
2662 + }
2663 +
2664 +}
2665 +
2666 +
2667 +/* local helper functions */
2668 +
2669 +/****************************************************************************
2670 + * FUNCTION: get_base_frequency
2671 + ****************************************************************************
2672 + * Description: The above routine is called to get base frequency of the clocks.
2673 + ***************************************************************************/
2674 +
2675 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
2676 +{
2677 + /* update the current MIPs PLL output value, if the required
2678 + * source is MIPS PLL
2679 + */
2680 + if ( clk_src[clk_id] == &mips_pll_out)
2681 + {
2682 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
2683 + }
2684 +
2685 +
2686 + /* update the current System PLL output value, if the required
2687 + * source is system PLL
2688 + */
2689 + if ( clk_src[clk_id] == &sys_pll_out)
2690 + {
2691 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
2692 + }
2693 +
2694 + return (*clk_src[clk_id]);
2695 +
2696 +}
2697 +
2698 +
2699 +
2700 +/****************************************************************************
2701 + * FUNCTION: find_gcd
2702 + ****************************************************************************
2703 + * Description: The above routine is called to find gcd of 2 numbers.
2704 + ***************************************************************************/
2705 +static u32 find_gcd
2706 +(
2707 + u32 min,
2708 + u32 max
2709 + )
2710 +{
2711 + if (max % min == 0)
2712 + {
2713 + return min;
2714 + }
2715 + else
2716 + {
2717 + return find_gcd(max % min, min);
2718 + }
2719 +}
2720 +
2721 +/****************************************************************************
2722 + * FUNCTION: compute_prediv
2723 + ****************************************************************************
2724 + * Description: The above routine is called to compute predivider value
2725 + ***************************************************************************/
2726 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
2727 +{
2728 + u16 prediv;
2729 +
2730 + /* return the divider itself it it falls within the range of predivider*/
2731 + if (min <= divider && divider <= max)
2732 + {
2733 + return divider;
2734 + }
2735 +
2736 + /* find a value for prediv such that it is a factor of divider */
2737 + for (prediv = max; prediv >= min ; prediv--)
2738 + {
2739 + if ( (divider % prediv) == 0 )
2740 + {
2741 + return prediv;
2742 + }
2743 + }
2744 +
2745 + /* No such factor exists, return min as prediv */
2746 + return min;
2747 +}
2748 +
2749 +/****************************************************************************
2750 + * FUNCTION: get_val
2751 + ****************************************************************************
2752 + * Description: This routine is called to get values of divider and multiplier.
2753 + ***************************************************************************/
2754 +
2755 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
2756 +{
2757 + u32 temp_mul;
2758 + u32 temp_div;
2759 + u32 gcd;
2760 + u32 min_freq;
2761 + u32 max_freq;
2762 +
2763 + /* find gcd of base_freq, output_freq */
2764 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
2765 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
2766 + gcd = find_gcd(min_freq , max_freq);
2767 +
2768 + if(gcd == 0)
2769 + return; /* ERROR */
2770 +
2771 + /* compute values of multiplier and divider */
2772 + temp_mul = output_freq / gcd;
2773 + temp_div = base_freq / gcd;
2774 +
2775 +
2776 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
2777 + if( temp_mul > PLL_MUL_MAXFACTOR )
2778 + {
2779 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
2780 + return;
2781 +
2782 + find_approx(&temp_mul,&temp_div,base_freq);
2783 + }
2784 +
2785 + *multiplier = temp_mul;
2786 + *divider = temp_div;
2787 +}
2788 +
2789 +/****************************************************************************
2790 + * FUNCTION: find_approx
2791 + ****************************************************************************
2792 + * Description: This function gets the approx value of num/denom.
2793 + ***************************************************************************/
2794 +
2795 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
2796 +{
2797 + u32 num1;
2798 + u32 denom1;
2799 + u32 num2;
2800 + u32 denom2;
2801 + int32_t closest;
2802 + int32_t prev_closest;
2803 + u32 temp_num;
2804 + u32 temp_denom;
2805 + u32 normalize;
2806 + u32 gcd;
2807 + u32 output_freq;
2808 +
2809 + num1 = *num;
2810 + denom1 = *denom;
2811 +
2812 + prev_closest = 0x7fffffff; /* maximum possible value */
2813 + num2 = num1;
2814 + denom2 = denom1;
2815 +
2816 + /* start with max */
2817 + for(temp_num = 15; temp_num >=1; temp_num--)
2818 + {
2819 +
2820 + temp_denom = CEIL(temp_num * denom1, num1);
2821 + output_freq = (temp_num * base_freq) / temp_denom;
2822 +
2823 + if(temp_denom < 1)
2824 + {
2825 + break;
2826 + }
2827 + else
2828 + {
2829 + normalize = CEIL(num1,temp_num);
2830 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
2831 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
2832 + {
2833 + prev_closest = closest;
2834 + num2 = temp_num;
2835 + denom2 = temp_denom;
2836 + }
2837 +
2838 + }
2839 +
2840 + }
2841 +
2842 + gcd = find_gcd(num2,denom2);
2843 + num2 = num2 / gcd;
2844 + denom2 = denom2 /gcd;
2845 +
2846 + *num = num2;
2847 + *denom = denom2;
2848 +}
2849 +
2850 +
2851 +/*****************************************************************************
2852 + * GPIO Control
2853 + *****************************************************************************/
2854 +
2855 +/****************************************************************************
2856 + * FUNCTION: tnetd73xx_gpio_init
2857 + ***************************************************************************/
2858 +void tnetd73xx_gpio_init()
2859 +{
2860 + /* Bring module out of reset */
2861 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2862 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
2863 +}
2864 +
2865 +/****************************************************************************
2866 + * FUNCTION: tnetd73xx_gpio_ctrl
2867 + ***************************************************************************/
2868 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
2869 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
2870 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
2871 +{
2872 + u32 pin_status;
2873 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
2874 + if (pin_mode == GPIO_PIN)
2875 + {
2876 + pin_status |= (1 << gpio_pin);
2877 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2878 +
2879 + /* Set pin direction */
2880 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
2881 + if (pin_direction == GPIO_INPUT_PIN)
2882 + {
2883 + pin_status |= (1 << gpio_pin);
2884 + }
2885 + else /* GPIO_OUTPUT_PIN */
2886 + {
2887 + pin_status &= (~(1 << gpio_pin));
2888 + }
2889 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
2890 + }
2891 + else /* FUNCTIONAL PIN */
2892 + {
2893 + pin_status &= (~(1 << gpio_pin));
2894 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
2895 + }
2896 +
2897 +}
2898 +
2899 +/****************************************************************************
2900 + * FUNCTION: tnetd73xx_gpio_out
2901 + ***************************************************************************/
2902 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
2903 +{
2904 + u32 pin_value;
2905 +
2906 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
2907 + if (value == 1)
2908 + {
2909 + pin_value |= (1 << gpio_pin);
2910 + }
2911 + else
2912 + {
2913 + pin_value &= (~(1 << gpio_pin));
2914 + }
2915 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
2916 +}
2917 +
2918 +/****************************************************************************
2919 + * FUNCTION: tnetd73xx_gpio_in
2920 + ***************************************************************************/
2921 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
2922 +{
2923 + u32 pin_value;
2924 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
2925 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
2926 +}
2927 +
2928 diff -urN linux-2.4.30/arch/mips/config-shared.in linux-2.4.30.dev/arch/mips/config-shared.in
2929 --- linux-2.4.30/arch/mips/config-shared.in 2005-06-14 18:42:06.000000000 +0200
2930 +++ linux-2.4.30.dev/arch/mips/config-shared.in 2005-06-14 15:36:59.000000000 +0200
2931 @@ -20,6 +20,15 @@
2932 mainmenu_option next_comment
2933 comment 'Machine selection'
2934 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
2935 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
2936 +if [ "$CONFIG_AR7" = "y" ]; then
2937 + choice 'Texas Instruments Reference Platform' \
2938 + "AR7DB CONFIG_AR7DB \
2939 + AR7RD CONFIG_AR7RD \
2940 + AR7WRD CONFIG_AR7WRD" AR7DB
2941 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_FREQUENCY 150
2942 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
2943 +fi
2944 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
2945 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
2946 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
2947 @@ -239,6 +248,11 @@
2948 define_bool CONFIG_NONCOHERENT_IO y
2949 define_bool CONFIG_PC_KEYB y
2950 fi
2951 +if [ "$CONFIG_AR7" = "y" ]; then
2952 + define_bool CONFIG_NONCOHERENT_IO y
2953 + define_bool CONFIG_SWAP_IO_SPACE y
2954 + define_bool CONFIG_AR7_PAGING y
2955 +fi
2956 if [ "$CONFIG_CASIO_E55" = "y" ]; then
2957 define_bool CONFIG_IRQ_CPU y
2958 define_bool CONFIG_NONCOHERENT_IO y
2959 @@ -736,6 +750,7 @@
2960 mainmenu_option next_comment
2961 comment 'General setup'
2962 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2963 + "$CONFIG_AR7" = "y" -o \
2964 "$CONFIG_CASIO_E55" = "y" -o \
2965 "$CONFIG_DDB5074" = "y" -o \
2966 "$CONFIG_DDB5476" = "y" -o \
2967 @@ -797,6 +812,7 @@
2968 bool 'Networking support' CONFIG_NET
2969
2970 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
2971 + "$CONFIG_AR7" = "y" -o \
2972 "$CONFIG_CASIO_E55" = "y" -o \
2973 "$CONFIG_DECSTATION" = "y" -o \
2974 "$CONFIG_IBM_WORKPAD" = "y" -o \
2975 diff -urN linux-2.4.30/arch/mips/kernel/irq.c linux-2.4.30.dev/arch/mips/kernel/irq.c
2976 --- linux-2.4.30/arch/mips/kernel/irq.c 2005-06-14 18:42:06.000000000 +0200
2977 +++ linux-2.4.30.dev/arch/mips/kernel/irq.c 2005-06-14 15:36:59.000000000 +0200
2978 @@ -76,6 +76,7 @@
2979 * Generic, controller-independent functions:
2980 */
2981
2982 +#ifndef CONFIG_AR7
2983 int get_irq_list(char *buf)
2984 {
2985 int i, j;
2986 @@ -110,6 +111,7 @@
2987 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
2988 return p - buf;
2989 }
2990 +#endif
2991
2992 #ifdef CONFIG_SMP
2993 int global_irq_holder = NO_PROC_ID;
2994 @@ -525,6 +527,7 @@
2995 *
2996 */
2997
2998 +#ifndef CONFIG_AR7
2999 int request_irq(unsigned int irq,
3000 void (*handler)(int, void *, struct pt_regs *),
3001 unsigned long irqflags,
3002 @@ -569,6 +572,7 @@
3003 kfree(action);
3004 return retval;
3005 }
3006 +#endif
3007
3008 /**
3009 * free_irq - free an interrupt
3010 @@ -588,6 +592,7 @@
3011 * the machine.
3012 */
3013
3014 +#ifndef CONFIG_AR7
3015 void free_irq(unsigned int irq, void *dev_id)
3016 {
3017 irq_desc_t *desc;
3018 @@ -629,6 +634,7 @@
3019 return;
3020 }
3021 }
3022 +#endif
3023
3024 /*
3025 * IRQ autodetection code..
3026 diff -urN linux-2.4.30/arch/mips/kernel/setup.c linux-2.4.30.dev/arch/mips/kernel/setup.c
3027 --- linux-2.4.30/arch/mips/kernel/setup.c 2005-06-14 18:42:06.000000000 +0200
3028 +++ linux-2.4.30.dev/arch/mips/kernel/setup.c 2005-06-14 15:36:59.000000000 +0200
3029 @@ -109,6 +109,7 @@
3030 unsigned long isa_slot_offset;
3031 EXPORT_SYMBOL(isa_slot_offset);
3032
3033 +extern void avalanche_bootmem_init(void);
3034 extern void SetUpBootInfo(void);
3035 extern void load_mmu(void);
3036 extern asmlinkage void start_kernel(void);
3037 @@ -267,6 +268,9 @@
3038 #endif /* CONFIG_BLK_DEV_INITRD */
3039
3040 /* Find the highest page frame number we have available. */
3041 +#ifdef CONFIG_AR7_PAGING
3042 + avalanche_bootmem_init();
3043 +#else
3044 max_pfn = 0;
3045 first_usable_pfn = -1UL;
3046 for (i = 0; i < boot_mem_map.nr_map; i++) {
3047 @@ -376,7 +380,7 @@
3048
3049 /* Reserve the bootmap memory. */
3050 reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3051 -
3052 +#endif
3053 #ifdef CONFIG_BLK_DEV_INITRD
3054 /* Board specific code should have set up initrd_start and initrd_end */
3055 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
3056 @@ -494,6 +498,7 @@
3057 void hp_setup(void);
3058 void au1x00_setup(void);
3059 void frame_info_init(void);
3060 + void ar7_setup(void);
3061
3062 frame_info_init();
3063 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3064 @@ -691,6 +696,11 @@
3065 pmc_yosemite_setup();
3066 break;
3067 #endif
3068 +#ifdef CONFIG_AR7
3069 + case MACH_GROUP_UNKNOWN:
3070 + ar7_setup();
3071 + break;
3072 +#endif
3073 default:
3074 panic("Unsupported architecture");
3075 }
3076 diff -urN linux-2.4.30/arch/mips/kernel/traps.c linux-2.4.30.dev/arch/mips/kernel/traps.c
3077 --- linux-2.4.30/arch/mips/kernel/traps.c 2005-06-14 18:42:06.000000000 +0200
3078 +++ linux-2.4.30.dev/arch/mips/kernel/traps.c 2005-06-14 15:36:59.000000000 +0200
3079 @@ -40,6 +40,10 @@
3080 #include <asm/uaccess.h>
3081 #include <asm/mmu_context.h>
3082
3083 +#ifdef CONFIG_AR7
3084 +#include <asm/ar7/ar7.h>
3085 +#endif
3086 +
3087 extern asmlinkage void handle_mod(void);
3088 extern asmlinkage void handle_tlbl(void);
3089 extern asmlinkage void handle_tlbs(void);
3090 @@ -869,9 +873,15 @@
3091
3092 exception_handlers[n] = handler;
3093 if (n == 0 && cpu_has_divec) {
3094 +#ifdef CONFIG_AR7
3095 + *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
3096 + (0x03ffffff & (handler >> 2));
3097 + flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
3098 +#else
3099 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3100 (0x03ffffff & (handler >> 2));
3101 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3102 +#endif
3103 }
3104 return (void *)old_handler;
3105 }
3106 @@ -920,14 +930,46 @@
3107 void __init trap_init(void)
3108 {
3109 extern char except_vec1_generic;
3110 + extern char except_vec2_generic;
3111 extern char except_vec3_generic, except_vec3_r4000;
3112 extern char except_vec_ejtag_debug;
3113 extern char except_vec4;
3114 unsigned long i;
3115
3116 +#ifdef CONFIG_AR7
3117 + extern char jump_tlb_miss, jump_tlb_miss_unused;
3118 + extern char jump_cache_error,jump_general_exception;
3119 + extern char jump_dedicated_interrupt;
3120 + clear_c0_status(ST0_BEV);
3121 +#endif
3122 +
3123 /* Copy the generic exception handler code to it's final destination. */
3124 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3125 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
3126 + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3127
3128 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3129 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3130 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3131 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3132 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3133 +
3134 +#ifdef CONFIG_AR7
3135 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
3136 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
3137 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3138 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3139 +
3140 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3141 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3142 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3143 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3144 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3145 +#else
3146 + memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3147 +#endif
3148 + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
3149 +
3150 /*
3151 * Setup default vectors
3152 */
3153 @@ -951,8 +993,12 @@
3154 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
3155 * interrupt processing overhead. Use it where available.
3156 */
3157 +#ifdef CONFIG_AR7
3158 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
3159 +#else
3160 if (cpu_has_divec)
3161 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
3162 +#endif
3163
3164 /*
3165 * Some CPUs can enable/disable for cache parity detection, but does
3166 @@ -991,12 +1037,17 @@
3167 if (cpu_has_mcheck)
3168 set_except_vector(24, handle_mcheck);
3169
3170 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3171 +#ifdef CONFIG_AR7
3172 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3173 +#else
3174 if (cpu_has_vce)
3175 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
3176 else if (cpu_has_4kex)
3177 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3178 else
3179 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
3180 +#endif
3181
3182 if (current_cpu_data.cputype == CPU_R6000 ||
3183 current_cpu_data.cputype == CPU_R6000A) {
3184 @@ -1023,7 +1074,11 @@
3185 if (board_nmi_handler_setup)
3186 board_nmi_handler_setup();
3187
3188 +#ifdef CONFIG_AR7
3189 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3190 +#else
3191 flush_icache_range(KSEG0, KSEG0 + 0x400);
3192 +#endif
3193
3194 per_cpu_trap_init();
3195 }
3196 diff -urN linux-2.4.30/arch/mips/lib/promlib.c linux-2.4.30.dev/arch/mips/lib/promlib.c
3197 --- linux-2.4.30/arch/mips/lib/promlib.c 2005-06-14 18:42:06.000000000 +0200
3198 +++ linux-2.4.30.dev/arch/mips/lib/promlib.c 2005-06-14 15:36:59.000000000 +0200
3199 @@ -1,3 +1,4 @@
3200 +#ifndef CONFIG_AR7
3201 #include <stdarg.h>
3202 #include <linux/kernel.h>
3203
3204 @@ -22,3 +23,4 @@
3205 }
3206 va_end(args);
3207 }
3208 +#endif
3209 diff -urN linux-2.4.30/arch/mips/mm/init.c linux-2.4.30.dev/arch/mips/mm/init.c
3210 --- linux-2.4.30/arch/mips/mm/init.c 2005-06-14 18:42:06.000000000 +0200
3211 +++ linux-2.4.30.dev/arch/mips/mm/init.c 2005-06-14 15:36:59.000000000 +0200
3212 @@ -40,8 +40,10 @@
3213
3214 mmu_gather_t mmu_gathers[NR_CPUS];
3215 unsigned long highstart_pfn, highend_pfn;
3216 +#ifndef CONFIG_AR7_PAGING
3217 static unsigned long totalram_pages;
3218 static unsigned long totalhigh_pages;
3219 +#endif
3220
3221 void pgd_init(unsigned long page)
3222 {
3223 @@ -235,6 +237,7 @@
3224 #endif
3225 }
3226
3227 +#ifndef CONFIG_AR7_PAGING
3228 void __init paging_init(void)
3229 {
3230 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3231 @@ -272,6 +275,7 @@
3232
3233 free_area_init(zones_size);
3234 }
3235 +#endif
3236
3237 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3238 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
3239 @@ -298,6 +302,7 @@
3240 return 0;
3241 }
3242
3243 +#ifndef CONFIG_AR7_PAGING
3244 void __init mem_init(void)
3245 {
3246 unsigned long codesize, reservedpages, datasize, initsize;
3247 @@ -359,6 +364,7 @@
3248 initsize >> 10,
3249 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
3250 }
3251 +#endif
3252
3253 #ifdef CONFIG_BLK_DEV_INITRD
3254 void free_initrd_mem(unsigned long start, unsigned long end)
3255 @@ -376,6 +382,7 @@
3256 }
3257 #endif
3258
3259 +#ifndef CONFIG_AR7_PAGING
3260 extern char __init_begin, __init_end;
3261 extern void prom_free_prom_memory(void) __init;
3262
3263 @@ -383,7 +390,9 @@
3264 {
3265 unsigned long addr;
3266
3267 +#ifndef CONFIG_AR7
3268 prom_free_prom_memory ();
3269 +#endif
3270
3271 addr = (unsigned long) &__init_begin;
3272 while (addr < (unsigned long) &__init_end) {
3273 @@ -409,3 +418,4 @@
3274
3275 return;
3276 }
3277 +#endif
3278 diff -urN linux-2.4.30/arch/mips/mm/tlb-r4k.c linux-2.4.30.dev/arch/mips/mm/tlb-r4k.c
3279 --- linux-2.4.30/arch/mips/mm/tlb-r4k.c 2005-06-14 18:42:06.000000000 +0200
3280 +++ linux-2.4.30.dev/arch/mips/mm/tlb-r4k.c 2005-06-14 15:36:59.000000000 +0200
3281 @@ -20,6 +20,10 @@
3282 #include <asm/pgtable.h>
3283 #include <asm/system.h>
3284
3285 +#ifdef CONFIG_AR7
3286 +#include <asm/ar7/ar7.h>
3287 +#endif
3288 +
3289 extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
3290
3291 /* CP0 hazard avoidance. */
3292 @@ -375,7 +379,12 @@
3293 else if (current_cpu_data.cputype == CPU_R4600)
3294 memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
3295 else
3296 +#ifdef CONFIG_AR7
3297 + memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
3298 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
3299 +#else
3300 memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
3301 flush_icache_range(KSEG0, KSEG0 + 0x80);
3302 +#endif
3303 }
3304 }
3305 diff -urN linux-2.4.30/drivers/char/serial.c linux-2.4.30.dev/drivers/char/serial.c
3306 --- linux-2.4.30/drivers/char/serial.c 2005-06-14 18:42:06.000000000 +0200
3307 +++ linux-2.4.30.dev/drivers/char/serial.c 2005-06-14 15:36:59.000000000 +0200
3308 @@ -419,7 +419,40 @@
3309 return 0;
3310 }
3311
3312 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3313 +#if defined(CONFIG_AR7)
3314 +
3315 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
3316 +{
3317 + return (inb(info->port + (offset * 4)) & 0xff);
3318 +}
3319 +
3320 +
3321 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
3322 +{
3323 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3324 + return (inb(info->port + (offset * 4)) & 0xff);
3325 +#else
3326 + return (inb_p(info->port + (offset * 4)) & 0xff);
3327 +#endif
3328 +}
3329 +
3330 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
3331 +{
3332 + outb(value, info->port + (offset * 4));
3333 +}
3334 +
3335 +
3336 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
3337 + int value)
3338 +{
3339 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3340 + outb(value, info->port + (offset * 4));
3341 +#else
3342 + outb_p(value, info->port + (offset * 4));
3343 +#endif
3344 +}
3345 +
3346 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3347
3348 #include <asm/mips-boards/atlas.h>
3349
3350 @@ -478,8 +511,10 @@
3351 * needed for certain old 386 machines, I've left these #define's
3352 * in....
3353 */
3354 +#ifdef CONFIG_AR7
3355 #define serial_inp(info, offset) serial_in(info, offset)
3356 #define serial_outp(info, offset, value) serial_out(info, offset, value)
3357 +#endif
3358
3359
3360 /*
3361 @@ -1728,7 +1763,15 @@
3362 /* Special case since 134 is really 134.5 */
3363 quot = (2*baud_base / 269);
3364 else if (baud)
3365 +#ifdef CONFIG_AR7
3366 + quot = get_avalanche_vbus_freq() / baud;
3367 +
3368 + if ((quot%16)>7)
3369 + quot += 8;
3370 + quot /=16;
3371 +#else
3372 quot = baud_base / baud;
3373 +#endif
3374 }
3375 /* If the quotient is zero refuse the change */
3376 if (!quot && old_termios) {
3377 @@ -5552,8 +5595,10 @@
3378 state->irq = irq_cannonicalize(state->irq);
3379 if (state->hub6)
3380 state->io_type = SERIAL_IO_HUB6;
3381 +#ifdef CONFIG_AR7
3382 if (state->port && check_region(state->port,8))
3383 continue;
3384 +#endif
3385 #ifdef CONFIG_MCA
3386 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
3387 continue;
3388 @@ -6009,7 +6054,15 @@
3389 info->io_type = state->io_type;
3390 info->iomem_base = state->iomem_base;
3391 info->iomem_reg_shift = state->iomem_reg_shift;
3392 +#ifdef CONFIG_AR7
3393 + quot = get_avalanche_vbus_freq() / baud;
3394 +
3395 + if ((quot%16)>7)
3396 + quot += 8;
3397 + quot /=16;
3398 +#else
3399 quot = state->baud_base / baud;
3400 +#endif
3401 cval = cflag & (CSIZE | CSTOPB);
3402 #if defined(__powerpc__) || defined(__alpha__)
3403 cval >>= 8;
3404 diff -urN linux-2.4.30/include/asm-mips/ar7/ar7.h linux-2.4.30.dev/include/asm-mips/ar7/ar7.h
3405 --- linux-2.4.30/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
3406 +++ linux-2.4.30.dev/include/asm-mips/ar7/ar7.h 2005-06-14 15:36:59.000000000 +0200
3407 @@ -0,0 +1,137 @@
3408 +#ifndef _MIPS_AR7_H
3409 +#define _MIPS_AR7_H
3410 +
3411 +#include <linux/config.h>
3412 +#include <asm/addrspace.h>
3413 +
3414 +
3415 +#ifndef LITTLE_ENDIAN
3416 +#define LITTLE_ENDIAN
3417 +#endif
3418 +
3419 +#ifndef _LINK_KSEG0_
3420 +#define _LINK_KSEG0_
3421 +#endif
3422 +
3423 +#include <asm/ar7/tnetd73xx.h>
3424 +
3425 +#define AVALANCHE_UART0_INT 7
3426 +#define AVALANCHE_UART1_INT 8
3427 +
3428 +#define MIPS_EXCEPTION_OFFSET 8
3429 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3430 +
3431 +/*
3432 + * AR7 board SDRAM base address. This is used to setup the
3433 + * bootmem tables
3434 + */
3435 +
3436 +#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
3437 +#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE
3438 +
3439 +
3440 +/*
3441 + * AR7 board vectors
3442 + */
3443 +
3444 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3445 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3446 +
3447 +
3448 +/*
3449 + * Yamon Prom print address.
3450 + */
3451 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3452 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3453 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3454 +
3455 +/*
3456 + * AR7 Reset and PSU standby register.
3457 + */
3458 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
3459 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
3460 +#define AVALANCHE_GORESET 0x1
3461 +#define AVALANCHE_GOSTBY 0x1
3462 +#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
3463 +
3464 +/*
3465 + * Avalanche UART register base.
3466 + */
3467 +
3468 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3469 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3470 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3471 +
3472 +/*
3473 + * AVALANCHE DMA controller base
3474 + */
3475 +
3476 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
3477 +
3478 +
3479 +
3480 +/*
3481 + * GPIO register map
3482 + */
3483 +
3484 +/* to be obtained from avalanche_map.h */
3485 +#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904))
3486 +#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908))
3487 +#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C))
3488 +#define AVALANCHE_GPIO_PIN_COUNT 32
3489 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0}
3490 +
3491 +
3492 +// Let us define board specific information here.
3493 +
3494 +#if defined(CONFIG_AR7DB)
3495 +
3496 +#define AFECLK_FREQ 35328000
3497 +#define REFCLK_FREQ 25000000
3498 +#define OSC3_FREQ 24000000
3499 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3500 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555
3501 +
3502 +#endif
3503 +
3504 +
3505 +#if defined(CONFIG_AR7RD)
3506 +
3507 +#define AFECLK_FREQ 35328000
3508 +#define REFCLK_FREQ 25000000
3509 +#define OSC3_FREQ 24000000
3510 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3511 +
3512 +#if defined(CONFIG_AR7_MARVELL)
3513 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3514 +#else
3515 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3516 +#endif
3517 +
3518 +#endif
3519 +
3520 +
3521 +#if defined(CONFIG_AR7WRD)
3522 +
3523 +#define AFECLK_FREQ 35328000
3524 +#define REFCLK_FREQ 25000000
3525 +#define OSC3_FREQ 24000000
3526 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3527 +
3528 +#if defined(CONFIG_AR7_MARVELL)
3529 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3530 +#else
3531 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3532 +#endif
3533 +
3534 +#endif
3535 +
3536 +extern unsigned int tnetd73xx_vbus_freq;
3537 +#define AVALANCHE_VBUS_FREQ tnetd73xx_vbus_freq
3538 +
3539 +static inline unsigned int get_avalanche_vbus_freq(void)
3540 +{
3541 + return (tnetd73xx_vbus_freq);
3542 +}
3543 +
3544 +#endif /*_MIPS_AR7_H */
3545 diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche.h
3546 --- linux-2.4.30/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100
3547 +++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche.h 2005-06-14 15:36:59.000000000 +0200
3548 @@ -0,0 +1,183 @@
3549 +/* $Id$
3550 + *
3551 + * avalanche.h
3552 + *
3553 + * Jeff Harrell, jharrell@ti.com
3554 + * Copyright (C) 2000,2001,2002 Texas Instruments Inc.
3555 + *
3556 + *
3557 + * ########################################################################
3558 + *
3559 + * This program is free software; you can distribute it and/or modify it
3560 + * under the terms of the GNU General Public License (Version 2) as
3561 + * published by the Free Software Foundation.
3562 + *
3563 + * This program is distributed in the hope it will be useful, but WITHOUT
3564 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3565 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3566 + * for more details.
3567 + *
3568 + * You should have received a copy of the GNU General Public License along
3569 + * with this program; if not, write to the Free Software Foundation, Inc.,
3570 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3571 + *
3572 + * ########################################################################
3573 + *
3574 + * Defines of the AVALANCHE board specific address-MAP, registers, etc.
3575 + *
3576 + */
3577 +#ifndef _MIPS_AVALANCHE_H
3578 +#define _MIPS_AVALANCHE_H
3579 +
3580 +#include <asm/addrspace.h>
3581 +
3582 +/*
3583 + * AVALANCHE board SDRAM base address. This is used to setup the
3584 + * bootmem tables
3585 + */
3586 +
3587 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
3588 +
3589 +/*
3590 + * AVALANCHE board vectors
3591 + */
3592 +
3593 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3594 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3595 +/*
3596 + * Avalanche RTC-device indirect register access.
3597 + */
3598 +
3599 +#define EVM3_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
3600 +#define EVM3_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
3601 +
3602 +/*
3603 + * Evm3 interrupt controller register base (primary)
3604 + */
3605 +
3606 +#define AVALANCHE_ICTRL_REGS_BASE (KSEG1ADDR(0x08612400))
3607 +
3608 +/*
3609 + * Avalanche exception controller register base (secondary)
3610 + */
3611 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE+0x80)
3612 +
3613 +
3614 +/*
3615 + * Avalanche Interrupt Channel Control register base
3616 + */
3617 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3618 +
3619 +
3620 +/*
3621 + * Avalanche UART register base.
3622 + */
3623 +
3624 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3625 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3626 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3627 +/*
3628 + * AVALANCHE DMA controller base
3629 + */
3630 +
3631 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
3632 +
3633 +
3634 +/*
3635 + * AVALANCHE display register base.
3636 + */
3637 +
3638 +#define EVM3_ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1D000038))
3639 +#define EVM3_ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */
3640 +
3641 +
3642 +#define EVM3_ASCIIPOS0 0x1D000038
3643 +#define EVM3_ASCIIPOS1 0x1D000039
3644 +#define EVM3_ASCIIPOS2 0x1D00003A
3645 +#define EVM3_ASCIIPOS3 0x1D00003B
3646 +#define EVM3_ASCIIPOS4 0x1D00003C
3647 +#define EVM3_ASCIIPOS5 0x1D00003D
3648 +#define EVM3_ASCIIPOS6 0x1D00003E
3649 +#define EVM3_ASCIIPOS7 0x1D00003F
3650 +
3651 +/*
3652 + * Yamon Prom print address.
3653 + */
3654 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3655 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3656 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3657 +
3658 +/*
3659 + * Evm3 Reset and PSU standby register.
3660 + */
3661 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
3662 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
3663 +#define AVALANCHE_GORESET 0x1
3664 +#define AVALANCHE_GOSTBY 0x1
3665 +
3666 +/************************************************************************
3667 + * PERIPHERAL BUS LEDs (P-LED):
3668 +*************************************************************************/
3669 +
3670 +/************************************************************************
3671 + * P-LED Register Addresses
3672 +*************************************************************************/
3673 +
3674 +#define EVM3_PLED (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED */
3675 +
3676 +
3677 +/************************************************************************
3678 + * Register field encodings
3679 +*************************************************************************/
3680 +
3681 +/******** reg: PLED ********/
3682 +/* bits 7:0: VAL */
3683 +#define EVM3_PLED_VAL_MSK 0xff
3684 +
3685 +/* bit 0: */
3686 +#define EVM3_PLED_BIT0_SHF 0
3687 +#define EVM3_PLED_BIT0_MSK (1 << EVM3_PLED_BIT0_SHF)
3688 +#define EVM3_PLED_BIT0_ON EVM3_PLED_BIT0_MSK
3689 +
3690 +/* bit 1: */
3691 +#define EVM3_PLED_BIT1_SHF 1
3692 +#define EVM3_PLED_BIT1_MSK (1 << EVM3_PLED_BIT1_SHF)
3693 +#define EVM3_PLED_BIT1_ON EVM3_PLED_BIT1_MSK
3694 +
3695 +/* bit 2: */
3696 +#define EVM3_PLED_BIT2_SHF 2
3697 +#define EVM3_PLED_BIT2_MSK (1 << EVM3_PLED_BIT2_SHF)
3698 +#define EVM3_PLED_BIT2_ON EVM3_PLED_BIT2_MSK
3699 +
3700 +/* bit 3: */
3701 +#define EVM3_PLED_BIT3_SHF 3
3702 +#define EVM3_PLED_BIT3_MSK (1 << EVM3_PLED_BIT3_SHF)
3703 +#define EVM3_PLED_BIT3_ON EVM3_PLED_BIT3_MSK
3704 +
3705 +/* bit 4: */
3706 +#define EVM3_PLED_BIT4_SHF 4
3707 +#define EVM3_PLED_BIT4_MSK (1 << EVM3_PLED_BIT4_SHF)
3708 +#define EVM3_PLED_BIT4_ON EVM3_PLED_BIT4_MSK
3709 +
3710 +/* bit 5: */
3711 +#define EVM3_PLED_BIT5_SHF 5
3712 +#define EVM3_PLED_BIT5_MSK (1 << EVM3_PLED_BIT5_SHF)
3713 +#define EVM3_PLED_BIT5_ON EVM3_PLED_BIT5_MSK
3714 +
3715 +/* bit 6: */
3716 +#define EVM3_PLED_BIT6_SHF 6
3717 +#define EVM3_PLED_BIT6_MSK (1 << EVM3_PLED_BIT6_SHF)
3718 +#define EVM3_PLED_BIT6_ON EVM3_PLED_BIT6_MSK
3719 +
3720 +/* bit 7: */
3721 +#define EVM3_PLED_BIT7_SHF 7
3722 +#define EVM3_PLED_BIT7_MSK (1 << EVM3_PLED_BIT7_SHF)
3723 +#define EVM3_PLED_BIT7_ON EVM3_PLED_BIT7_MSK
3724 +
3725 +#endif /* !(_MIPS_AVALANCHE_H) */
3726 +
3727 +
3728 +
3729 +
3730 +
3731 +
3732 diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_int.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_int.h
3733 --- linux-2.4.30/include/asm-mips/ar7/avalanche_int.h 1970-01-01 01:00:00.000000000 +0100
3734 +++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_int.h 2005-06-14 15:36:59.000000000 +0200
3735 @@ -0,0 +1,298 @@
3736 +/* $Id$
3737 + *
3738 + * avalancheint.h
3739 + *
3740 + * Jeff Harrell, jharrell@ti.com
3741 + * Copyright (C) 2000,2001 Texas Instruments , Inc.
3742 + *
3743 + * ########################################################################
3744 + *
3745 + * This program is free software; you can distribute it and/or modify it
3746 + * under the terms of the GNU General Public License (Version 2) as
3747 + * published by the Free Software Foundation.
3748 + *
3749 + * This program is distributed in the hope it will be useful, but WITHOUT
3750 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3751 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3752 + * for more details.
3753 + *
3754 + * You should have received a copy of the GNU General Public License along
3755 + * with this program; if not, write to the Free Software Foundation, Inc.,
3756 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3757 + *
3758 + * ########################################################################
3759 + *
3760 + * Defines for the AVALANCHE interrupt controller.
3761 + *
3762 + */
3763 +#ifndef _MIPS_AVALANCHEINT_H
3764 +#define _MIPS_AVALANCHEINT_H
3765 +
3766 +#include <linux/config.h>
3767 +
3768 +/* Avalanche Interrupt number */
3769 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
3770 +/* Linux Interrupt number */
3771 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3772 +/* Number of IRQ supported on hw interrupt 0. */
3773 +
3774 +//#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
3775 +//#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
3776 +
3777 +
3778 +#define MIPS_EXCEPTION_OFFSET 8
3779 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
3780 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
3781 +
3782 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
3783 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
3784 +
3785 +
3786 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
3787 + + MIPS_EXCEPTION_OFFSET - 1)
3788 +
3789 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
3790 +{
3791 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 */ /* 0x00 */
3792 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 */ /* 0x04 */
3793 + volatile unsigned long unused1; /* 0x08 */
3794 + volatile unsigned long unused2; /* 0x0C */
3795 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 */ /* 0x10 */
3796 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 */ /* 0x14 */
3797 + volatile unsigned long unused3; /* 0x18 */
3798 + volatile unsigned long unused4; /* 0x1C */
3799 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 */ /* 0x20 */
3800 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 */ /* 0x24 */
3801 + volatile unsigned long unused5; /* 0x28 */
3802 + volatile unsigned long unused6; /* 0x2C */
3803 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 */ /* 0x30 */
3804 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 */ /* 0x34 */
3805 + volatile unsigned long unused7; /* 0x38 */
3806 + volatile unsigned long unused8; /* 0x3c */
3807 + volatile unsigned long pintir; /* Priority Interrupt Index Register */ /* 0x40 */
3808 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */
3809 + volatile unsigned long unused9; /* 0x48 */
3810 + volatile unsigned long unused10; /* 0x4C */
3811 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 1*/ /* 0x50 */
3812 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 2*/ /* 0x54 */
3813 +};
3814 +
3815 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
3816 +{
3817 + volatile unsigned long exsr; /* Exceptions Status/Set register */ /* 0x80 */
3818 + volatile unsigned long reserved; /* 0x84 */
3819 + volatile unsigned long excr; /* Exceptions Clear Register */ /* 0x88 */
3820 + volatile unsigned long reserved1; /* 0x8c */
3821 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) */ /* 0x90 */
3822 + volatile unsigned long reserved2; /* 0x94 */
3823 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */
3824 +};
3825 +
3826 +struct avalanche_channel_int_number
3827 +{
3828 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register */ /* 0x200 */
3829 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register */ /* 0x204 */
3830 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register */ /* 0x208 */
3831 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register */ /* 0x20C */
3832 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register */ /* 0x210 */
3833 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register */ /* 0x214 */
3834 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register */ /* 0x218 */
3835 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register */ /* 0x21C */
3836 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register */ /* 0x220 */
3837 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register */ /* 0x224 */
3838 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register */ /* 0x228 */
3839 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register */ /* 0x22C */
3840 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register */ /* 0x230 */
3841 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register */ /* 0x234 */
3842 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register */ /* 0x238 */
3843 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register */ /* 0x23C */
3844 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register */ /* 0x240 */
3845 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register */ /* 0x244 */
3846 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register */ /* 0x248 */
3847 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register */ /* 0x24C */
3848 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register */ /* 0x250 */
3849 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register */ /* 0x254 */
3850 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register */ /* 0x358 */
3851 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register */ /* 0x35C */
3852 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register */ /* 0x260 */
3853 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register */ /* 0x264 */
3854 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register */ /* 0x268 */
3855 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register */ /* 0x26C */
3856 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register */ /* 0x270 */
3857 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register */ /* 0x274 */
3858 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register */ /* 0x278 */
3859 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register */ /* 0x27C */
3860 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register */ /* 0x280 */
3861 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register */ /* 0x284 */
3862 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register */ /* 0x288 */
3863 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register */ /* 0x28C */
3864 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register */ /* 0x290 */
3865 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register */ /* 0x294 */
3866 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register */ /* 0x298 */
3867 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register */ /* 0x29C */
3868 +};
3869 +
3870 +struct avalanche_interrupt_line_to_channel
3871 +{
3872 + unsigned long int_line0; /* Start of primary interrupts */
3873 + unsigned long int_line1;
3874 + unsigned long int_line2;
3875 + unsigned long int_line3;
3876 + unsigned long int_line4;
3877 + unsigned long int_line5;
3878 + unsigned long int_line6;
3879 + unsigned long int_line7;
3880 + unsigned long int_line8;
3881 + unsigned long int_line9;
3882 + unsigned long int_line10;
3883 + unsigned long int_line11;
3884 + unsigned long int_line12;
3885 + unsigned long int_line13;
3886 + unsigned long int_line14;
3887 + unsigned long int_line15;
3888 + unsigned long int_line16;
3889 + unsigned long int_line17;
3890 + unsigned long int_line18;
3891 + unsigned long int_line19;
3892 + unsigned long int_line20;
3893 + unsigned long int_line21;
3894 + unsigned long int_line22;
3895 + unsigned long int_line23;
3896 + unsigned long int_line24;
3897 + unsigned long int_line25;
3898 + unsigned long int_line26;
3899 + unsigned long int_line27;
3900 + unsigned long int_line28;
3901 + unsigned long int_line29;
3902 + unsigned long int_line30;
3903 + unsigned long int_line31;
3904 + unsigned long int_line32;
3905 + unsigned long int_line33;
3906 + unsigned long int_line34;
3907 + unsigned long int_line35;
3908 + unsigned long int_line36;
3909 + unsigned long int_line37;
3910 + unsigned long int_line38;
3911 + unsigned long int_line39;
3912 +};
3913 +
3914 +/* Interrupt Line #'s (Avalanche peripherals) */
3915 +
3916 +/*------------------------------*/
3917 +/* Avalanche primary interrupts */
3918 +/*------------------------------*/
3919 +#define UNIFIED_SECONDARY_INTERRUPT 0
3920 +#define AVALANCHE_EXT_INT_0 1
3921 +#define AVALANCHE_EXT_INT_1 2
3922 +#define AVALANCHE_EXT_INT_2 3
3923 +#define AVALANCHE_EXT_INT_3 4
3924 +#define AVALANCHE_TIMER_0_INT 5
3925 +#define AVALANCHE_TIMER_1_INT 6
3926 +#define AVALANCHE_UART0_INT 7
3927 +#define AVALANCHE_UART1_INT 8
3928 +#define AVALANCHE_PDMA_INT0 9
3929 +#define AVALANCHE_PDMA_INT1 10
3930 +#define AVALANCHE_HDLC_TXA 11
3931 +#define AVALANCHE_HDLC_TXB 12
3932 +#define AVALANCHE_HDLC_RXA 13
3933 +#define AVALANCHE_HDLC_RXB 14
3934 +#define AVALANCHE_ATM_SAR_TXA 15
3935 +#define AVALANCHE_ATM_SAR_TXB 16
3936 +#define AVALANCHE_ATM_SAR_RXA 17
3937 +#define AVALANCHE_ATM_SAR_RXB 18
3938 +#define AVALANCHE_MAC_TXA 19
3939 +#define AVALANCHE_MAC_RXA 20
3940 +#define AVALANCHE_DSP_SUB0 21
3941 +#define AVALANCHE_DSP_SUB1 22
3942 +#define AVALANCHE_DES_INT 23
3943 +#define AVALANCHE_USB_INT 24
3944 +#define AVALANCHE_PCI_INTA 25
3945 +#define AVALANCHE_PCI_INTB 26
3946 +#define AVALANCHE_PCI_INTC 27
3947 +/* Line #28 Reserved */
3948 +#define AVALANCHE_I2CM_INT 29
3949 +#define AVALANCHE_PDMA_INT2 30
3950 +#define AVALANCHE_PDMA_INT3 31
3951 +#define AVALANCHE_CODEC 32
3952 +#define AVALANCHE_MAC_TXB 33
3953 +#define AVALANCHE_MAC_RXB 34
3954 +/* Line #35 Reserved */
3955 +/* Line #36 Reserved */
3956 +/* Line #37 Reserved */
3957 +/* Line #38 Reserved */
3958 +/* Line #39 Reserved */
3959 +
3960 +#define DEBUG_MISSED_INTS 1
3961 +
3962 +#ifdef DEBUG_MISSED_INTS
3963 +struct debug_missed_int
3964 +{
3965 + unsigned int atm_sar_txa;
3966 + unsigned int atm_sar_txb;
3967 + unsigned int atm_sar_rxa;
3968 + unsigned int atm_sar_rxb;
3969 + unsigned int mac_txa;
3970 + unsigned int mac_rxa;
3971 + unsigned int mac_txb;
3972 + unsigned int mac_rxb;
3973 +};
3974 +#endif /* DEBUG_MISSED_INTS */
3975 +
3976 +/*-----------------------------------*/
3977 +/* Avalanche Secondary Interrupts */
3978 +/*-----------------------------------*/
3979 +#define PRIMARY_INTS 40
3980 +
3981 +#define AVALANCHE_HDLC_STATUS (0 + PRIMARY_INTS)
3982 +#define AVALANCHE_SAR_STATUS (1 + PRIMARY_INTS)
3983 +/* Line #02 Reserved */
3984 +#define AVALANCHE_ETH_MACA_LNK_CHG (3 + PRIMARY_INTS)
3985 +#define AVALANCHE_ETH_MACA_MGT (4 + PRIMARY_INTS)
3986 +#define AVALANCHE_PCI_STATUS_INT (5 + PRIMARY_INTS)
3987 +/* Line #06 Reserved */
3988 +#define AVALANCHE_EXTERN_MEM_INT (7 + PRIMARY_INTS)
3989 +#define AVALANCHE_DSP_A_DOG (8 + PRIMARY_INTS)
3990 +#define AVALANCHE_DSP_B_DOG (9 + PRIMARY_INTS)
3991 +/* Line #10-#20 Reserved */
3992 +#define AVALANCHE_ETH_MACB_LNK_CHG (21 + PRIMARY_INTS)
3993 +#define AVALANCHE_ETH_MACB_MGT (22 + PRIMARY_INTS)
3994 +#define AVALANCHE_AAL2_STATUS (23 + PRIMARY_INTS)
3995 +/* Line #24-#31 Reserved */
3996 +
3997 +#define AVALANCHEINT_UART0 LNXINTNUM(AVALANCHE_UART0_INT)
3998 +#define AVALANCHEINT_UART1 LNXINTNUM(AVALANCHE_UART1_INT)
3999 +#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */
4000 +#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */
4001 +
4002 +#ifdef JIMK_INT_CTRLR
4003 +/*-----------------------------------*/
4004 +/* Jim Kennedy's Interrupt Controller*/
4005 +/*-----------------------------------*/
4006 +
4007 +/* to clear the interrupt write the bit back to the status reg */
4008 +
4009 +#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400))
4010 +#define JIMK_INT_MASK (*(volatile unsigned int *)(0xA8612404))
4011 +#define JIMK_SAR_STATUS (1<<0)
4012 +#define JIMK_SAR_TX_A (1<<1)
4013 +#define JIMK_SAR_TX_B (1<<2)
4014 +#define JIMK_SAR_RX_A (1<<3)
4015 +#define JIMK_SAR_RX_B (1<<4)
4016 +#define JIMK_AAL2_STATUS (1<<5)
4017 +#define JIMK_UART0_INT (1<<11)
4018 +
4019 +#ifdef SEAD_USB_DEVELOPMENT
4020 +#define JIMK_USB_INT (1<<0)
4021 +#endif /* SEAD_USB_DEVELOPMENT */
4022 +
4023 +#endif /* JIMK_INT_CTRLR */
4024 +
4025 +extern void avalanche_int_set(int channel, int line);
4026 +extern void avalancheint_init(void);
4027 +
4028 +
4029 +#endif /* !(_MIPS_AVALANCHEINT_H) */
4030 +
4031 +
4032 +
4033 +
4034 diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_intc.h
4035 --- linux-2.4.30/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
4036 +++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_intc.h 2005-06-14 15:36:59.000000000 +0200
4037 @@ -0,0 +1,273 @@
4038 + /*
4039 + * Nitin Dhingra, iamnd@ti.com
4040 + * Copyright (C) 2000 Texas Instruments Inc.
4041 + *
4042 + *
4043 + * ########################################################################
4044 + *
4045 + * This program is free software; you can distribute it and/or modify it
4046 + * under the terms of the GNU General Public License (Version 2) as
4047 + * published by the Free Software Foundation.
4048 + *
4049 + * This program is distributed in the hope it will be useful, but WITHOUT
4050 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4051 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4052 + * for more details.
4053 + *
4054 + * You should have received a copy of the GNU General Public License along
4055 + * with this program; if not, write to the Free Software Foundation, Inc.,
4056 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4057 + *
4058 + * ########################################################################
4059 + *
4060 + * Defines of the Sead board specific address-MAP, registers, etc.
4061 + *
4062 + */
4063 +#ifndef _AVALANCHE_INTC_H
4064 +#define _AVALANCHE_INTC_H
4065 +
4066 +#define MIPS_EXCEPTION_OFFSET 8
4067 +
4068 +/******************************************************************************
4069 + Avalanche Interrupt number
4070 +******************************************************************************/
4071 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
4072 +
4073 +/*******************************************************************************
4074 +*Linux Interrupt number
4075 +*******************************************************************************/
4076 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
4077 +
4078 +
4079 +
4080 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
4081 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
4082 +
4083 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
4084 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
4085 +
4086 +
4087 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
4088 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
4089 + + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
4090 +
4091 +
4092 +/*
4093 + * Avalanche interrupt controller register base (primary)
4094 + */
4095 +#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
4096 +
4097 +/******************************************************************************
4098 + * Avalanche exception controller register base (secondary)
4099 + ******************************************************************************/
4100 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
4101 +
4102 +
4103 +/******************************************************************************
4104 + * Avalanche Interrupt pacing register base (secondary)
4105 + ******************************************************************************/
4106 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
4107 +
4108 +
4109 +
4110 +/******************************************************************************
4111 + * Avalanche Interrupt Channel Control register base
4112 + *****************************************************************************/
4113 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
4114 +
4115 +
4116 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
4117 +{
4118 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
4119 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
4120 + volatile unsigned long unused1; /*0x08 */
4121 + volatile unsigned long unused2; /*0x0C */
4122 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
4123 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
4124 + volatile unsigned long unused3; /*0x18 */
4125 + volatile unsigned long unused4; /*0x1C */
4126 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
4127 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
4128 + volatile unsigned long unused5; /*0x28 */
4129 + volatile unsigned long unused6; /*0x2C */
4130 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
4131 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
4132 + volatile unsigned long unused7; /* 0x38 */
4133 + volatile unsigned long unused8; /* 0x3c */
4134 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
4135 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
4136 + volatile unsigned long unused9; /* 0x48 */
4137 + volatile unsigned long unused10; /* 0x4C */
4138 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
4139 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
4140 + volatile unsigned long unused11; /* 0x58 */
4141 + volatile unsigned long unused12; /*0x5C */
4142 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
4143 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
4144 +};
4145 +
4146 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
4147 +{
4148 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
4149 + volatile unsigned long reserved; /*0x84 */
4150 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
4151 + volatile unsigned long reserved1; /*0x8c */
4152 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
4153 + volatile unsigned long reserved2; /*0x94 */
4154 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
4155 +};
4156 +struct avalanche_ipace_regs
4157 +{
4158 +
4159 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
4160 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
4161 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
4162 +};
4163 +struct avalanche_channel_int_number
4164 +{
4165 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
4166 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
4167 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
4168 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
4169 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
4170 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
4171 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
4172 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
4173 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
4174 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
4175 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
4176 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
4177 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
4178 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
4179 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
4180 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
4181 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
4182 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
4183 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
4184 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
4185 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
4186 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
4187 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
4188 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
4189 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
4190 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
4191 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
4192 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
4193 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
4194 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
4195 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
4196 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
4197 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
4198 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
4199 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
4200 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
4201 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
4202 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
4203 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
4204 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
4205 +};
4206 +
4207 +struct avalanche_interrupt_line_to_channel
4208 +{
4209 + unsigned long int_line0; /* Start of primary interrupts */
4210 + unsigned long int_line1;
4211 + unsigned long int_line2;
4212 + unsigned long int_line3;
4213 + unsigned long int_line4;
4214 + unsigned long int_line5;
4215 + unsigned long int_line6;
4216 + unsigned long int_line7;
4217 + unsigned long int_line8;
4218 + unsigned long int_line9;
4219 + unsigned long int_line10;
4220 + unsigned long int_line11;
4221 + unsigned long int_line12;
4222 + unsigned long int_line13;
4223 + unsigned long int_line14;
4224 + unsigned long int_line15;
4225 + unsigned long int_line16;
4226 + unsigned long int_line17;
4227 + unsigned long int_line18;
4228 + unsigned long int_line19;
4229 + unsigned long int_line20;
4230 + unsigned long int_line21;
4231 + unsigned long int_line22;
4232 + unsigned long int_line23;
4233 + unsigned long int_line24;
4234 + unsigned long int_line25;
4235 + unsigned long int_line26;
4236 + unsigned long int_line27;
4237 + unsigned long int_line28;
4238 + unsigned long int_line29;
4239 + unsigned long int_line30;
4240 + unsigned long int_line31;
4241 + unsigned long int_line32;
4242 + unsigned long int_line33;
4243 + unsigned long int_line34;
4244 + unsigned long int_line35;
4245 + unsigned long int_line36;
4246 + unsigned long int_line37;
4247 + unsigned long int_line38;
4248 + unsigned long int_line39;
4249 +};
4250 +
4251 +
4252 +/* Interrupt Line #'s (Sangam peripherals) */
4253 +
4254 +/*------------------------------*/
4255 +/* Sangam primary interrupts */
4256 +/*------------------------------*/
4257 +
4258 +#define UNIFIED_SECONDARY_INTERRUPT 0
4259 +#define AVALANCHE_EXT_INT_0 1
4260 +#define AVALANCHE_EXT_INT_1 2
4261 +/* Line #3 Reserved */
4262 +/* Line #4 Reserved */
4263 +#define AVALANCHE_TIMER_0_INT 5
4264 +#define AVALANCHE_TIMER_1_INT 6
4265 +#define AVALANCHE_UART0_INT 7
4266 +#define AVALANCHE_UART1_INT 8
4267 +#define AVALANCHE_PDMA_INT0 9
4268 +#define AVALANCHE_PDMA_INT1 10
4269 +/* Line #11 Reserved */
4270 +/* Line #12 Reserved */
4271 +/* Line #13 Reserved */
4272 +/* Line #14 Reserved */
4273 +#define AVALANCHE_ATM_SAR_INT 15
4274 +/* Line #16 Reserved */
4275 +/* Line #17 Reserved */
4276 +/* Line #18 Reserved */
4277 +#define AVALANCHE_MAC0_INT 19
4278 +/* Line #20 Reserved */
4279 +#define AVALANCHE_VLYNQ0_INT 21
4280 +#define AVALANCHE_CODEC_WAKE_INT 22
4281 +/* Line #23 Reserved */
4282 +#define AVALANCHE_USB_INT 24
4283 +#define AVALANCHE_VLYNQ1_INT 25
4284 +/* Line #26 Reserved */
4285 +/* Line #27 Reserved */
4286 +#define AVALANCHE_MAC1_INT 28
4287 +#define AVALANCHE_I2CM_INT 29
4288 +#define AVALANCHE_PDMA_INT2 30
4289 +#define AVALANCHE_PDMA_INT3 31
4290 +/* Line #32 Reserved */
4291 +/* Line #33 Reserved */
4292 +/* Line #34 Reserved */
4293 +/* Line #35 Reserved */
4294 +/* Line #36 Reserved */
4295 +#define AVALANCHE_VDMA_VT_RX_INT 37
4296 +#define AVALANCHE_VDMA_VT_TX_INT 38
4297 +#define AVALANCHE_ADSLSS_INT 39
4298 +
4299 +/*-----------------------------------*/
4300 +/* Sangam Secondary Interrupts */
4301 +/*-----------------------------------*/
4302 +#define PRIMARY_INTS 40
4303 +
4304 +#define EMIF_INT (7 + PRIMARY_INTS)
4305 +
4306 +
4307 +extern void avalanche_int_set(int channel, int line);
4308 +
4309 +
4310 +#endif /* _AVALANCHE_INTC_H */
4311 diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_prom.h
4312 --- linux-2.4.30/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100
4313 +++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_prom.h 2005-06-14 15:36:59.000000000 +0200
4314 @@ -0,0 +1,54 @@
4315 +/* $Id$
4316 + *
4317 + * prom.h
4318 + *
4319 + * Carsten Langgaard, carstenl@mips.com
4320 + * Copyright (C) 1999 MIPS Technologies, Inc.
4321 + *
4322 + * ########################################################################
4323 + *
4324 + * This program is free software; you can distribute it and/or modify it
4325 + * under the terms of the GNU General Public License (Version 2) as
4326 + * published by the Free Software Foundation.
4327 + *
4328 + * This program is distributed in the hope it will be useful, but WITHOUT
4329 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4330 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4331 + * for more details.
4332 + *
4333 + * You should have received a copy of the GNU General Public License along
4334 + * with this program; if not, write to the Free Software Foundation, Inc.,
4335 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4336 + *
4337 + * ########################################################################
4338 + *
4339 + * Sead bootprom interface for the Linux kernel.
4340 + *
4341 + */
4342 +
4343 +#ifndef _MIPS_PROM_H
4344 +#define _MIPS_PROM_H
4345 +
4346 +extern char *prom_getcmdline(void);
4347 +extern char *prom_getenv(char *name);
4348 +extern void setup_prom_printf(void);
4349 +extern void prom_printf(char *fmt, ...);
4350 +extern void prom_init_cmdline(void);
4351 +extern void prom_meminit(void);
4352 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
4353 +extern void prom_free_prom_memory (void);
4354 +extern void sead_display_message(const char *str);
4355 +extern void sead_display_word(unsigned int num);
4356 +extern int get_ethernet_addr(char *ethernet_addr);
4357 +
4358 +/* Memory descriptor management. */
4359 +#define PROM_MAX_PMEMBLOCKS 32
4360 +struct prom_pmemblock {
4361 + unsigned long base; /* Within KSEG0. */
4362 + unsigned int size; /* In bytes. */
4363 + unsigned int type; /* free or prom memory */
4364 +};
4365 +
4366 +
4367 +#endif /* !(_MIPS_PROM_H) */
4368 +
4369 diff -urN linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h linux-2.4.30.dev/include/asm-mips/ar7/avalanche_regs.h
4370 --- linux-2.4.30/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
4371 +++ linux-2.4.30.dev/include/asm-mips/ar7/avalanche_regs.h 2005-06-14 15:36:59.000000000 +0200
4372 @@ -0,0 +1,567 @@
4373 +/*
4374 + * $Id$
4375 + * Avalanche Register Descriptions
4376 + *
4377 + * Jeff Harrell, jharrell@ti.com
4378 + * 2000 (c) Texas Instruments Inc.
4379 + */
4380 +
4381 +#ifndef __AVALANCHE_REGS_H
4382 +#define __AVALANCHE_REGS_H
4383 +
4384 +#include <asm/addrspace.h>
4385 +#include <linux/config.h>
4386 +
4387 +/*----------------------------------------*/
4388 +/* Base offsets within the Avalanche ASIC */
4389 +/*----------------------------------------*/
4390 +
4391 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
4392 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
4393 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
4394 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
4395 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
4396 +#define DES_BASE (KSEG1ADDR(0x08600000))
4397 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
4398 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
4399 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
4400 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
4401 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
4402 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
4403 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
4404 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
4405 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
4406 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
4407 +#define I2C_BASE (KSEG1ADDR(0x08611000))
4408 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
4409 +#define USB_BASE (KSEG1ADDR(0x08611200))
4410 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
4411 +#define DMA_BASE (KSEG1ADDR(0x08611400))
4412 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
4413 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
4414 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
4415 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
4416 +
4417 +/*---------------------------------*/
4418 +/* Device ID, chip version number */
4419 +/*---------------------------------*/
4420 +
4421 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
4422 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
4423 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
4424 +
4425 +/*----------------------------------*/
4426 +/* Reset Control VW changed to ptrs */
4427 +/*----------------------------------*/
4428 +
4429 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
4430 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
4431 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
4432 +
4433 +/* reset control bits */
4434 +
4435 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
4436 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
4437 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
4438 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
4439 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
4440 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
4441 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
4442 +/*
4443 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4444 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4445 + interface pins are inputs and must be reconfigured so as not to lose the
4446 + serial console interface
4447 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4448 +*/
4449 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
4450 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
4451 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
4452 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
4453 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
4454 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
4455 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
4456 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
4457 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
4458 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
4459 +
4460 +/*----------------------*/
4461 +/* Physical interfaces */
4462 +/*----------------------*/
4463 +
4464 +/* Phy loopback */
4465 +#define PHY_LOOPBACK 1
4466 +
4467 +
4468 +/* Phy 0 */
4469 +#define PHY0BASE (PHY_BASE)
4470 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
4471 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
4472 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
4473 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
4474 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
4475 +
4476 +
4477 +/* Phy 1 */
4478 +
4479 +#define PHY1BASE (PHY_BASE + 0x100000)
4480 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
4481 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
4482 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
4483 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
4484 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
4485 +
4486 +/* Phy 2 */
4487 +
4488 +#define PHY2BASE (PHY_BASE + 0x200000)
4489 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
4490 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
4491 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
4492 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
4493 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
4494 +
4495 +/*-------------------*/
4496 +/* Avalanche ATM SAR */
4497 +/*-------------------*/
4498 +
4499 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
4500 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
4501 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
4502 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
4503 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
4504 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
4505 +
4506 +/* Transmit completion ring registers */
4507 +
4508 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
4509 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
4510 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
4511 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
4512 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
4513 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
4514 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
4515 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
4516 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
4517 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
4518 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
4519 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
4520 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
4521 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
4522 +
4523 +/* Transmit Queue Packet registers */
4524 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
4525 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
4526 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
4527 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
4528 +/* Receive completion ring registers */
4529 +
4530 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
4531 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
4532 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
4533 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
4534 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
4535 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
4536 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
4537 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
4538 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
4539 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
4540 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
4541 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
4542 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
4543 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
4544 +
4545 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
4546 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
4547 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
4548 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
4549 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
4550 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
4551 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
4552 +
4553 +
4554 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
4555 +
4556 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
4557 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
4558 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
4559 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
4560 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
4561 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
4562 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
4563 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
4564 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
4565 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
4566 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
4567 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
4568 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
4569 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
4570 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
4571 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
4572 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
4573 +
4574 +
4575 +/*
4576 +
4577 +#define OAM_CPID_ADD 0xa30104e0
4578 +
4579 +#define OAM_LLID_ADD 0xa30104f0
4580 +
4581 +#define OAM_LLID_VAL 0xffffffff
4582 +
4583 +#define OAM_CORR_TAG 0xa3010500
4584 +
4585 +#define OAM_FAR_COUNT_ADD 0xa3010520
4586 +
4587 +#define OAM_NEAR_COUNT_ADD 0xa3010540
4588 +
4589 +#define OAM_CONFIG_REG_ADD 0xa3000018
4590 +*/
4591 +
4592 +
4593 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
4594 +
4595 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
4596 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
4597 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
4598 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
4599 +
4600 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
4601 +
4602 +
4603 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
4604 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
4605 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
4606 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
4607 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
4608 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
4609 +
4610 +/*------------------------------------------*/
4611 +/* DSL Interface */
4612 +/*------------------------------------------*/
4613 +
4614 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
4615 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
4616 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
4617 +
4618 +/* Fast */
4619 +
4620 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
4621 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
4622 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
4623 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
4624 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
4625 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
4626 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
4627 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
4628 +
4629 +/* Interleaved */
4630 +
4631 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
4632 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
4633 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
4634 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
4635 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
4636 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
4637 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
4638 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
4639 +
4640 +/*------------------------------------------*/
4641 +/* Broadband I/F */
4642 +/*------------------------------------------*/
4643 +
4644 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
4645 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
4646 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
4647 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
4648 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
4649 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
4650 +
4651 +#define AVBBIF_DISABLED 0x0
4652 +#define AVBBIF_LBT4040_INT 0x1
4653 +#define AVBBIF_XBUS 0x2
4654 +#define AVBBIF_LBT4040_EXT 0x4
4655 +
4656 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
4657 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
4658 +#define AVBBIF_TRANS_MASK 0xff000000
4659 +/*------------------------------------------*/
4660 +/* GPIO I/F */
4661 +/*------------------------------------------*/
4662 +
4663 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
4664 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
4665 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
4666 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
4667 +
4668 +#define GPIO_0 (1<<21)
4669 +#define GPIO_1 (1<<22)
4670 +#define GPIO_2 (1<<23)
4671 +#define GPIO_3 (1<<24)
4672 +#define EINT_1 (1<<18)
4673 +
4674 +/*
4675 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4676 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4677 + interface pins are inputs and must be reconfigured so as not to lose the
4678 + serial console interface
4679 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4680 +*/
4681 +
4682 +/*------------------------------------------*/
4683 +/* CLK_CTRL */
4684 +/*------------------------------------------*/
4685 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
4686 +
4687 +#define PCLK_0_HALF_VBUS (0<<16)
4688 +#define PCLK_EQ_INPUT (1<<16)
4689 +#define BBIF_CLK_HALF_VBUS (0<<17)
4690 +#define BBIF_CLK_EQ_VBUS (1<<17)
4691 +#define BBIF_CLK_EQ_BBCLK (3<<17)
4692 +#define DSP_MODCLK_DSPCLKI (0<<20)
4693 +#define DSP_MODCLK_REFCLKI (1<<20)
4694 +#define USB_CLK_EQ_USBCLKI (0<<21)
4695 +#define USB_CLK_EQ_REFCLKI (1<<21)
4696 +
4697 +/*------------------------------------------*/
4698 +/* PCI Control Registers */
4699 +/*------------------------------------------*/
4700 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
4701 +#define PCIC_CONTROL_CFG_DONE (1<<0)
4702 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
4703 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
4704 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
4705 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
4706 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
4707 +#define PCIC_CONTROL_MEM_MASK (1<<6)
4708 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
4709 +#define PCIC_CONTROL_IO_MASK (1<<8)
4710 +/* PCIC_CONTROL_RESERVED (1<<9) */
4711 +#define PCIC_CONTROL_BASE0_EN (1<<10)
4712 +#define PCIC_CONTROL_BASE1_EN (1<<11)
4713 +#define PCIC_CONTROL_BASE2_EN (1<<12)
4714 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
4715 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
4716 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
4717 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
4718 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
4719 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
4720 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
4721 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
4722 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
4723 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
4724 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
4725 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
4726 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
4727 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
4728 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
4729 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
4730 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
4731 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
4732 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
4733 +#define PCIC_INT_CLEAR_PM (1<<0)
4734 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
4735 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
4736 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
4737 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
4738 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
4739 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
4740 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
4741 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
4742 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
4743 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
4744 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
4745 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
4746 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
4747 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
4748 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
4749 +#define PCIC_INT_EN_AVAL_PM (1<<0)
4750 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
4751 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
4752 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
4753 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
4754 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
4755 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
4756 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
4757 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
4758 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
4759 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
4760 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
4761 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
4762 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
4763 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
4764 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
4765 +#define PCIC_INT_EN_PCI_PM (1<<0)
4766 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
4767 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
4768 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
4769 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
4770 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
4771 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
4772 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
4773 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
4774 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
4775 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
4776 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
4777 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
4778 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
4779 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
4780 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
4781 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
4782 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
4783 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
4784 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
4785 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
4786 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
4787 +/* PCIC_PM_CTL_RESERVED (1<<2) */
4788 +/* PCIC_PM_CTL_RESERVED (1<<3) */
4789 +/* PCIC_PM_CTL_RESERVED (1<<4) */
4790 +/* PCIC_PM_CTL_RESERVED (1<<5) */
4791 +/* PCIC_PM_CTL_RESERVED (1<<6) */
4792 +/* PCIC_PM_CTL_RESERVED (1<<7) */
4793 +/* PCIC_PM_CTL_RESERVED (1<<8) */
4794 +/* PCIC_PM_CTL_RESERVED (1<<9) */
4795 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
4796 +#define PCIC_PM_CTL_PMEIN (1<<11)
4797 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
4798 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
4799 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
4800 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
4801 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
4802 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
4803 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
4804 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
4805 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
4806 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
4807 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
4808 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
4809 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
4810 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
4811 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
4812 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
4813 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
4814 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
4815 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
4816 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
4817 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
4818 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
4819 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
4820 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
4821 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
4822 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
4823 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
4824 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
4825 +
4826 +/*------------------------------------------*/
4827 +/* IIC_INTERFACE */
4828 +/*------------------------------------------*/
4829 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
4830 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
4831 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
4832 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
4833 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
4834 +
4835 +#define I2CWRITE 0x200
4836 +#define I2CREAD 0x300
4837 +#define I2C_END_BURST 0x400
4838 +
4839 +/* read bits */
4840 +#define I2C_READ_ERROR 0x8000
4841 +#define I2C_READ_COMPLETE 0x4000
4842 +#define I2C_READ_BUSY 0x2000
4843 +
4844 +/* device types */
4845 +#define I2C_IO_EXPANDER 0x2
4846 +#define I2C_RTC 0xd
4847 +
4848 +/* device Addresses on I2C bus (EVM3) */
4849 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
4850 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
4851 +#define EVM3_RTC_I2C_ADDR 0x0
4852 +
4853 +/*------------------------------------------*/
4854 +/* Ethernet MAC register offset definitions */
4855 +/*------------------------------------------*/
4856 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
4857 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
4858 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
4859 +
4860 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4861 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
4862 +
4863 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
4864 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
4865 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
4866 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
4867 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
4868 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
4869 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
4870 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
4871 +
4872 +
4873 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
4874 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
4875 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
4876 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
4877 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
4878 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
4879 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
4880 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
4881 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
4882 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
4883 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
4884 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
4885 +
4886 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
4887 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
4888 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
4889 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
4890 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
4891 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
4892 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
4893 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
4894 +
4895 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
4896 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
4897 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
4898 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
4899 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
4900 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
4901 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
4902 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
4903 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
4904 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
4905 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
4906 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
4907 +
4908 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
4909 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
4910 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
4911 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
4912 +
4913 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
4914 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
4915 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
4916 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
4917 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
4918 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
4919 +
4920 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
4921 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
4922 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
4923 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
4924 +
4925 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
4926 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
4927 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
4928 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
4929 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
4930 +
4931 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
4932 +
4933 +#endif
4934 +
4935 +
4936 +
4937 +
4938 +
4939 +
4940 diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx.h
4941 --- linux-2.4.30/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
4942 +++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx.h 2005-06-14 15:36:59.000000000 +0200
4943 @@ -0,0 +1,340 @@
4944 +/******************************************************************************
4945 + * FILE PURPOSE: TNETD73xx Common Header File
4946 + ******************************************************************************
4947 + * FILE NAME: tnetd73xx.h
4948 + *
4949 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
4950 + *
4951 + * REVISION HISTORY:
4952 + * 27 Nov 02 - PSP TII
4953 + *
4954 + * (C) Copyright 2002, Texas Instruments, Inc
4955 + *******************************************************************************/
4956 +
4957 +/*
4958 + *
4959 + *
4960 + * These are const, typedef, and api definitions for tnetd73xx.
4961 + *
4962 + * NOTES:
4963 + * 1. This file may be included into both C and Assembly files.
4964 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
4965 + * avoid C data types (typedefs) below;
4966 + * - for .c files, you don't have to do anything special.
4967 + *
4968 + * 2. This file has a number of sections for each SOC subsystem. When adding
4969 + * a new constant, find the subsystem you are working on and follow the
4970 + * name pattern. If you are adding another typedef for your interface, please,
4971 + * place it with other typedefs and function prototypes.
4972 + *
4973 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
4974 + * cluttering. Include such items directly into the module's .c file or have a
4975 + * local .h file to pass data between smaller modules. This file defines only
4976 + * shared items.
4977 + */
4978 +
4979 +#ifndef __TNETD73XX_H__
4980 +#define __TNETD73XX_H__
4981 +
4982 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
4983 +
4984 +#include <linux/types.h>
4985 +
4986 +extern unsigned int tnetd73xx_mips_freq;
4987 +extern unsigned int tnetd73xx_vbus_freq;
4988 +
4989 +#include "tnetd73xx_err.h"
4990 +
4991 +#endif /* _ASMLANGUAGE */
4992 +
4993 +
4994 +/*******************************************************************************************
4995 +* Emerald core specific
4996 +******************************************************************************************** */
4997 +
4998 +#ifdef BIG_ENDIAN
4999 +#elif defined(LITTLE_ENDIAN)
5000 +#else
5001 +#error Need to define endianism
5002 +#endif
5003 +
5004 +#ifndef KSEG_MSK
5005 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
5006 +#endif
5007 +
5008 +#ifndef KSEG_INV_MASK
5009 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
5010 +#endif
5011 +
5012 +#ifndef KSEG0_BASE
5013 +#define KSEG0_BASE 0x80000000
5014 +#endif
5015 +
5016 +#ifndef KSEG1_BASE
5017 +#define KSEG1_BASE 0xA0000000
5018 +#endif
5019 +
5020 +#ifndef KSEG0
5021 +#define KSEG0(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
5022 +#endif
5023 +
5024 +#ifndef KSEG1
5025 +#define KSEG1(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
5026 +#endif
5027 +
5028 +#ifndef KUSEG
5029 +#define KUSEG(addr) ((u32)(addr) & ~KSEG_MSK)
5030 +#endif
5031 +
5032 +#ifndef PHYS_ADDR
5033 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
5034 +#endif
5035 +
5036 +#ifndef PHYS_TO_K0
5037 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
5038 +#endif
5039 +
5040 +#ifndef PHYS_TO_K1
5041 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
5042 +#endif
5043 +
5044 +#ifndef REG8_ADDR
5045 +#define REG8_ADDR(addr) (volatile u8 *)(PHYS_TO_K1(addr))
5046 +#define REG8_DATA(addr) (*(volatile u8 *)(PHYS_TO_K1(addr)))
5047 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
5048 +#define REG8_READ(addr, data) data = (u8) REG8_DATA(addr);
5049 +#endif
5050 +
5051 +#ifndef REG16_ADDR
5052 +#define REG16_ADDR(addr) (volatile u16 *)(PHYS_TO_K1(addr))
5053 +#define REG16_DATA(addr) (*(volatile u16 *)(PHYS_TO_K1(addr)))
5054 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
5055 +#define REG16_READ(addr, data) data = (u16) REG16_DATA(addr);
5056 +#endif
5057 +
5058 +#ifndef REG32_ADDR
5059 +#define REG32_ADDR(addr) (volatile u32 *)(PHYS_TO_K1(addr))
5060 +#define REG32_DATA(addr) (*(volatile u32 *)(PHYS_TO_K1(addr)))
5061 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
5062 +#define REG32_READ(addr, data) data = (u32) REG32_DATA(addr);
5063 +#endif
5064 +
5065 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
5066 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
5067 +#endif
5068 +
5069 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
5070 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
5071 +#endif
5072 +
5073 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
5074 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
5075 +#endif
5076 +
5077 +/* TNETD73XX chip definations */
5078 +
5079 +#define FREQ_1MHZ 1000000
5080 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
5081 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
5082 +
5083 +#ifdef AR7SEAD2
5084 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
5085 +#else
5086 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
5087 +#endif
5088 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
5089 +
5090 +
5091 +
5092 +/* Module base addresses */
5093 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
5094 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
5095 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
5096 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
5097 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
5098 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
5099 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
5100 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
5101 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
5102 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
5103 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
5104 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
5105 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
5106 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
5107 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
5108 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
5109 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
5110 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
5111 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
5112 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
5113 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
5114 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
5115 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
5116 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
5117 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
5118 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
5119 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
5120 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
5121 +
5122 +/* BBIF Registers */
5123 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
5124 +
5125 +/* Device Configuration Latch Registers */
5126 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
5127 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
5128 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
5129 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
5130 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
5131 +
5132 +/* GPIO Control */
5133 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
5134 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
5135 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
5136 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
5137 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
5138 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
5139 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
5140 +
5141 +/* Reset Control */
5142 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
5143 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
5144 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
5145 +
5146 +/* Power Control */
5147 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
5148 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
5149 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
5150 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
5151 +
5152 +/* Clock Control */
5153 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
5154 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
5155 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
5156 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
5157 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
5158 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
5159 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
5160 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
5161 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
5162 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
5163 +
5164 +/* EMIF control */
5165 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
5166 +
5167 +/* UART */
5168 +#ifdef AR7SEAD2
5169 +#define TNETD73XX_UART_FREQ 3686400
5170 +#else
5171 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
5172 +#endif
5173 +
5174 +/* Interrupt Controller */
5175 +
5176 +/* Primary interrupts */
5177 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
5178 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
5179 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
5180 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
5181 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
5182 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
5183 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
5184 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
5185 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
5186 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
5187 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
5188 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
5189 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
5190 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
5191 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
5192 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
5193 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
5194 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
5195 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
5196 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
5197 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
5198 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
5199 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
5200 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
5201 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
5202 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
5203 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
5204 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
5205 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
5206 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
5207 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
5208 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
5209 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
5210 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
5211 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
5212 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
5213 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
5214 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
5215 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
5216 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
5217 +
5218 +/* Secondary interrupts */
5219 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
5220 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
5221 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
5222 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
5223 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
5224 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
5225 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
5226 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
5227 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
5228 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
5229 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
5230 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
5231 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
5232 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
5233 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
5234 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
5235 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
5236 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
5237 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
5238 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
5239 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
5240 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
5241 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
5242 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
5243 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
5244 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
5245 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
5246 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
5247 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
5248 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
5249 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
5250 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
5251 +
5252 +/* These ugly macros are to access the -1 registers, like config1 */
5253 +#define MFC0_SEL1_OPCODE(dst, src)\
5254 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
5255 + nop; \
5256 + nop; \
5257 + nop
5258 +
5259 +#define MTC0_SEL1_OPCODE(dst, src)\
5260 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
5261 + nop; \
5262 + nop; \
5263 + nop
5264 +
5265 +
5266 +/* Below are Jade core specific */
5267 +#define CFG0_4K_IL_MASK 0x00380000
5268 +#define CFG0_4K_IL_SHIFT 19
5269 +#define CFG0_4K_IA_MASK 0x00070000
5270 +#define CFG0_4K_IA_SHIFT 16
5271 +#define CFG0_4K_IS_MASK 0x01c00000
5272 +#define CFG0_4K_IS_SHIFT 22
5273 +
5274 +#define CFG0_4K_DL_MASK 0x00001c00
5275 +#define CFG0_4K_DL_SHIFT 10
5276 +#define CFG0_4K_DA_MASK 0x00000380
5277 +#define CFG0_4K_DA_SHIFT 7
5278 +#define CFG0_4K_DS_MASK 0x0000E000
5279 +#define CFG0_4K_DS_SHIFT 13
5280 +
5281 +
5282 +
5283 +#endif /* __TNETD73XX_H_ */
5284 diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_err.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_err.h
5285 --- linux-2.4.30/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
5286 +++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-06-14 15:36:59.000000000 +0200
5287 @@ -0,0 +1,42 @@
5288 +/******************************************************************************
5289 + * FILE PURPOSE: TNETD73xx Error Definations Header File
5290 + ******************************************************************************
5291 + * FILE NAME: tnetd73xx_err.h
5292 + *
5293 + * DESCRIPTION: Error definations for TNETD73XX
5294 + *
5295 + * REVISION HISTORY:
5296 + * 27 Nov 02 - PSP TII
5297 + *
5298 + * (C) Copyright 2002, Texas Instruments, Inc
5299 + *******************************************************************************/
5300 +
5301 +
5302 +#ifndef __TNETD73XX_ERR_H__
5303 +#define __TNETD73XX_ERR_H__
5304 +
5305 +typedef enum TNETD73XX_ERR_t
5306 +{
5307 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
5308 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
5309 +
5310 + /* Pointers and args */
5311 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
5312 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
5313 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
5314 +
5315 + /* Memory issues */
5316 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
5317 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
5318 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
5319 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
5320 +
5321 + /* Device issues */
5322 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
5323 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
5324 +
5325 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
5326 +
5327 +} TNETD73XX_ERR;
5328 +
5329 +#endif /* __TNETD73XX_ERR_H__ */
5330 diff -urN linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_misc.h
5331 --- linux-2.4.30/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
5332 +++ linux-2.4.30.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-06-14 15:36:59.000000000 +0200
5333 @@ -0,0 +1,243 @@
5334 +/******************************************************************************
5335 + * FILE PURPOSE: TNETD73xx Misc modules API Header
5336 + ******************************************************************************
5337 + * FILE NAME: tnetd73xx_misc.h
5338 + *
5339 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
5340 + * FSER Modules API
5341 + * As per TNETD73xx specifications
5342 + *
5343 + * REVISION HISTORY:
5344 + * 27 Nov 02 - Sharath Kumar PSP TII
5345 + * 14 Feb 03 - Anant Gole PSP TII
5346 + *
5347 + * (C) Copyright 2002, Texas Instruments, Inc
5348 + *******************************************************************************/
5349 +
5350 +#ifndef __TNETD73XX_MISC_H__
5351 +#define __TNETD73XX_MISC_H__
5352 +
5353 +#include <linux/types.h>
5354 +
5355 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
5356 +
5357 +/*****************************************************************************
5358 + * Reset Control Module
5359 + *****************************************************************************/
5360 +
5361 +typedef enum TNETD73XX_RESET_MODULE_tag
5362 +{
5363 + RESET_MODULE_UART0 = 0,
5364 + RESET_MODULE_UART1 = 1,
5365 + RESET_MODULE_I2C = 2,
5366 + RESET_MODULE_TIMER0 = 3,
5367 + RESET_MODULE_TIMER1 = 4,
5368 + RESET_MODULE_GPIO = 6,
5369 + RESET_MODULE_ADSLSS = 7,
5370 + RESET_MODULE_USBS = 8,
5371 + RESET_MODULE_SAR = 9,
5372 + RESET_MODULE_VDMA_VT = 11,
5373 + RESET_MODULE_FSER = 12,
5374 + RESET_MODULE_VLYNQ1 = 16,
5375 + RESET_MODULE_EMAC0 = 17,
5376 + RESET_MODULE_DMA = 18,
5377 + RESET_MODULE_BIST = 19,
5378 + RESET_MODULE_VLYNQ0 = 20,
5379 + RESET_MODULE_EMAC1 = 21,
5380 + RESET_MODULE_MDIO = 22,
5381 + RESET_MODULE_ADSLSS_DSP = 23,
5382 + RESET_MODULE_EPHY = 26
5383 +} TNETD73XX_RESET_MODULE_T;
5384 +
5385 +typedef enum TNETD73XX_RESET_CTRL_tag
5386 +{
5387 + IN_RESET = 0,
5388 + OUT_OF_RESET
5389 +} TNETD73XX_RESET_CTRL_T;
5390 +
5391 +typedef enum TNETD73XX_SYS_RST_MODE_tag
5392 +{
5393 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
5394 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
5395 +} TNETD73XX_SYS_RST_MODE_T;
5396 +
5397 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
5398 +{
5399 + HARDWARE_RESET = 0,
5400 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
5401 + WATCHDOG_RESET,
5402 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
5403 +} TNETD73XX_SYS_RESET_STATUS_T;
5404 +
5405 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
5406 + TNETD73XX_RESET_CTRL_T reset_ctrl);
5407 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
5408 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
5409 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
5410 +
5411 +/*****************************************************************************
5412 + * Power Control Module
5413 + *****************************************************************************/
5414 +
5415 +typedef enum TNETD73XX_POWER_MODULE_tag
5416 +{
5417 + POWER_MODULE_USBSP = 0,
5418 + POWER_MODULE_WDTP = 1,
5419 + POWER_MODULE_UT0P = 2,
5420 + POWER_MODULE_UT1P = 3,
5421 + POWER_MODULE_IICP = 4,
5422 + POWER_MODULE_VDMAP = 5,
5423 + POWER_MODULE_GPIOP = 6,
5424 + POWER_MODULE_VLYNQ1P = 7,
5425 + POWER_MODULE_SARP = 8,
5426 + POWER_MODULE_ADSLP = 9,
5427 + POWER_MODULE_EMIFP = 10,
5428 + POWER_MODULE_ADSPP = 12,
5429 + POWER_MODULE_RAMP = 13,
5430 + POWER_MODULE_ROMP = 14,
5431 + POWER_MODULE_DMAP = 15,
5432 + POWER_MODULE_BISTP = 16,
5433 + POWER_MODULE_TIMER0P = 18,
5434 + POWER_MODULE_TIMER1P = 19,
5435 + POWER_MODULE_EMAC0P = 20,
5436 + POWER_MODULE_EMAC1P = 22,
5437 + POWER_MODULE_EPHYP = 24,
5438 + POWER_MODULE_VLYNQ0P = 27,
5439 +} TNETD73XX_POWER_MODULE_T;
5440 +
5441 +typedef enum TNETD73XX_POWER_CTRL_tag
5442 +{
5443 + POWER_CTRL_POWER_UP = 0,
5444 + POWER_CTRL_POWER_DOWN
5445 +} TNETD73XX_POWER_CTRL_T;
5446 +
5447 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
5448 +{
5449 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
5450 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
5451 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
5452 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
5453 +} TNETD73XX_SYS_POWER_MODE_T;
5454 +
5455 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
5456 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
5457 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
5458 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
5459 +
5460 +/*****************************************************************************
5461 + * Wakeup Control
5462 + *****************************************************************************/
5463 +
5464 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
5465 +{
5466 + WAKEUP_INT0 = 1,
5467 + WAKEUP_INT1 = 2,
5468 + WAKEUP_INT2 = 4,
5469 + WAKEUP_INT3 = 8
5470 +} TNETD73XX_WAKEUP_INTERRUPT_T;
5471 +
5472 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
5473 +{
5474 + WAKEUP_DISABLED = 0,
5475 + WAKEUP_ENABLED
5476 +} TNETD73XX_WAKEUP_CTRL_T;
5477 +
5478 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
5479 +{
5480 + WAKEUP_ACTIVE_HIGH = 0,
5481 + WAKEUP_ACTIVE_LOW
5482 +} TNETD73XX_WAKEUP_POLARITY_T;
5483 +
5484 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
5485 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
5486 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
5487 +
5488 +/*****************************************************************************
5489 + * FSER Control
5490 + *****************************************************************************/
5491 +
5492 +typedef enum TNETD73XX_FSER_MODE_tag
5493 +{
5494 + FSER_I2C = 0,
5495 + FSER_UART = 1
5496 +} TNETD73XX_FSER_MODE_T;
5497 +
5498 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
5499 +
5500 +/*****************************************************************************
5501 + * Clock Control
5502 + *****************************************************************************/
5503 +
5504 +#define CLK_MHZ(x) ( (x) * 1000000 )
5505 +
5506 +typedef enum TNETD73XX_CLKC_ID_tag
5507 +{
5508 + CLKC_SYS = 0,
5509 + CLKC_MIPS,
5510 + CLKC_USB,
5511 + CLKC_ADSLSS
5512 +} TNETD73XX_CLKC_ID_T;
5513 +
5514 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in);
5515 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, u32 output_freq);
5516 +u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
5517 +
5518 +/*****************************************************************************
5519 + * GPIO Control
5520 + *****************************************************************************/
5521 +
5522 +typedef enum TNETD73XX_GPIO_PIN_tag
5523 +{
5524 + GPIO_UART0_RD = 0,
5525 + GPIO_UART0_TD = 1,
5526 + GPIO_UART0_RTS = 2,
5527 + GPIO_UART0_CTS = 3,
5528 + GPIO_FSER_CLK = 4,
5529 + GPIO_FSER_D = 5,
5530 + GPIO_EXT_AFE_SCLK = 6,
5531 + GPIO_EXT_AFE_TX_FS = 7,
5532 + GPIO_EXT_AFE_TXD = 8,
5533 + GPIO_EXT_AFE_RS_FS = 9,
5534 + GPIO_EXT_AFE_RXD1 = 10,
5535 + GPIO_EXT_AFE_RXD0 = 11,
5536 + GPIO_EXT_AFE_CDIN = 12,
5537 + GPIO_EXT_AFE_CDOUT = 13,
5538 + GPIO_EPHY_SPEED100 = 14,
5539 + GPIO_EPHY_LINKON = 15,
5540 + GPIO_EPHY_ACTIVITY = 16,
5541 + GPIO_EPHY_FDUPLEX = 17,
5542 + GPIO_EINT0 = 18,
5543 + GPIO_EINT1 = 19,
5544 + GPIO_MBSP0_TCLK = 20,
5545 + GPIO_MBSP0_RCLK = 21,
5546 + GPIO_MBSP0_RD = 22,
5547 + GPIO_MBSP0_TD = 23,
5548 + GPIO_MBSP0_RFS = 24,
5549 + GPIO_MBSP0_TFS = 25,
5550 + GPIO_MII_DIO = 26,
5551 + GPIO_MII_DCLK = 27,
5552 +} TNETD73XX_GPIO_PIN_T;
5553 +
5554 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
5555 +{
5556 + FUNCTIONAL_PIN = 0,
5557 + GPIO_PIN = 1
5558 +} TNETD73XX_GPIO_PIN_MODE_T;
5559 +
5560 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
5561 +{
5562 + GPIO_OUTPUT_PIN = 0,
5563 + GPIO_INPUT_PIN = 1
5564 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
5565 +
5566 +void tnetd73xx_gpio_init(void);
5567 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
5568 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
5569 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
5570 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
5571 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
5572 +
5573 +/* TNETD73XX Revision */
5574 +u32 tnetd73xx_get_revision(void);
5575 +
5576 +#endif /* __TNETD73XX_MISC_H__ */
5577 diff -urN linux-2.4.30/include/asm-mips/io.h linux-2.4.30.dev/include/asm-mips/io.h
5578 --- linux-2.4.30/include/asm-mips/io.h 2005-06-14 18:42:07.000000000 +0200
5579 +++ linux-2.4.30.dev/include/asm-mips/io.h 2005-06-14 15:36:59.000000000 +0200
5580 @@ -63,8 +63,12 @@
5581 #ifdef CONFIG_64BIT_PHYS_ADDR
5582 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
5583 #else
5584 +#ifdef CONFIG_AR7_PAGING
5585 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
5586 +#else
5587 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
5588 #endif
5589 +#endif
5590
5591 #define IO_SPACE_LIMIT 0xffff
5592
5593 diff -urN linux-2.4.30/include/asm-mips/irq.h linux-2.4.30.dev/include/asm-mips/irq.h
5594 --- linux-2.4.30/include/asm-mips/irq.h 2005-06-14 18:42:07.000000000 +0200
5595 +++ linux-2.4.30.dev/include/asm-mips/irq.h 2005-06-14 15:36:59.000000000 +0200
5596 @@ -14,7 +14,12 @@
5597 #include <linux/config.h>
5598 #include <linux/linkage.h>
5599
5600 +#ifdef CONFIG_AR7
5601 +#include <asm/ar7/avalanche_intc.h>
5602 +#define NR_IRQS AVALANCHE_INT_END + 1
5603 +#else
5604 #define NR_IRQS 128 /* Largest number of ints of all machines. */
5605 +#endif
5606
5607 #ifdef CONFIG_I8259
5608 static inline int irq_cannonicalize(int irq)
5609 diff -urN linux-2.4.30/include/asm-mips/page.h linux-2.4.30.dev/include/asm-mips/page.h
5610 --- linux-2.4.30/include/asm-mips/page.h 2005-06-14 18:42:07.000000000 +0200
5611 +++ linux-2.4.30.dev/include/asm-mips/page.h 2005-06-14 15:36:59.000000000 +0200
5612 @@ -129,7 +129,11 @@
5613
5614 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
5615 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
5616 +#ifdef CONFIG_AR7_PAGING
5617 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
5618 +#else
5619 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
5620 +#endif
5621 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
5622
5623 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
5624 diff -urN linux-2.4.30/include/asm-mips/pgtable-32.h linux-2.4.30.dev/include/asm-mips/pgtable-32.h
5625 --- linux-2.4.30/include/asm-mips/pgtable-32.h 2005-06-14 18:42:07.000000000 +0200
5626 +++ linux-2.4.30.dev/include/asm-mips/pgtable-32.h 2005-06-14 15:36:59.000000000 +0200
5627 @@ -108,7 +108,18 @@
5628 * and a page entry and page directory to the page they refer to.
5629 */
5630
5631 -#ifdef CONFIG_CPU_VR41XX
5632 +#if defined(CONFIG_AR7_PAGING)
5633 +#define mk_pte(page, pgprot) \
5634 +({ \
5635 + pte_t __pte; \
5636 + \
5637 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
5638 + CONFIG_AR7_MEMORY) | \
5639 + pgprot_val(pgprot); \
5640 + \
5641 + __pte; \
5642 +})
5643 +#elif defined(CONFIG_CPU_VR41XX)
5644 #define mk_pte(page, pgprot) \
5645 ({ \
5646 pte_t __pte; \
5647 @@ -130,6 +141,7 @@
5648 })
5649 #endif
5650
5651 +
5652 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
5653 {
5654 #ifdef CONFIG_CPU_VR41XX
5655 @@ -175,7 +187,10 @@
5656 set_pte(ptep, __pte(0));
5657 }
5658
5659 -#ifdef CONFIG_CPU_VR41XX
5660 +#if defined(CONFIG_AR7_PAGING)
5661 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
5662 +#define pte_page(x) phys_to_page(pte_val(x))
5663 +#elif defined(CONFIG_CPU_VR41XX)
5664 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
5665 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
5666 #else
5667 diff -urN linux-2.4.30/include/asm-mips/serial.h linux-2.4.30.dev/include/asm-mips/serial.h
5668 --- linux-2.4.30/include/asm-mips/serial.h 2005-06-14 18:42:07.000000000 +0200
5669 +++ linux-2.4.30.dev/include/asm-mips/serial.h 2005-06-14 15:36:59.000000000 +0200
5670 @@ -65,6 +65,15 @@
5671
5672 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
5673
5674 +#ifdef CONFIG_AR7
5675 +#include <asm/ar7/ar7.h>
5676 +#define AR7_SERIAL_PORT_DEFNS \
5677 + { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
5678 + { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
5679 +#else
5680 +#define AR7_SERIAL_PORT_DEFNS
5681 +#endif
5682 +
5683 #ifdef CONFIG_MIPS_JAZZ
5684 #define _JAZZ_SERIAL_INIT(int, base) \
5685 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
5686 @@ -468,6 +477,7 @@
5687 #endif
5688
5689 #define SERIAL_PORT_DFNS \
5690 + AR7_SERIAL_PORT_DEFNS \
5691 ATLAS_SERIAL_PORT_DEFNS \
5692 AU1000_SERIAL_PORT_DEFNS \
5693 COBALT_SERIAL_PORT_DEFNS \
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