a7a5455dca367c3ad9be637b1909fb7cd28fd3d7
[openwrt.git] / target / linux / adm5120 / files / arch / mips / adm5120 / irq.c
1 /*
2 * $Id$
3 *
4 * ADM5120 specific interrupt handlers
5 *
6 * Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
7 * Copyright (C) 2007 OpenWrt.org
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 *
24 */
25
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31
32 #include <linux/io.h>
33 #include <asm/irq.h>
34 #include <asm/irq_cpu.h>
35 #include <asm/mipsregs.h>
36 #include <asm/bitops.h>
37
38 #include <adm5120_defs.h>
39 #include <adm5120_irq.h>
40
41 #define INTC_WRITE(reg, val) __raw_writel((val), \
42 (void __iomem *)(KSEG1ADDR(ADM5120_INTC_BASE) + reg))
43
44 #define INTC_READ(reg) __raw_readl(\
45 (void __iomem *)(KSEG1ADDR(ADM5120_INTC_BASE) + reg))
46
47 static void adm5120_intc_irq_unmask(unsigned int irq);
48 static void adm5120_intc_irq_mask(unsigned int irq);
49 static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type);
50
51 static struct irq_chip adm5120_intc_irq_chip = {
52 .name = "INTC",
53 .unmask = adm5120_intc_irq_unmask,
54 .mask = adm5120_intc_irq_mask,
55 .mask_ack = adm5120_intc_irq_mask,
56 .set_type = adm5120_intc_irq_set_type
57 };
58
59 static struct irqaction adm5120_intc_irq_action = {
60 .handler = no_action,
61 .name = "cascade [INTC]"
62 };
63
64 static void adm5120_intc_irq_unmask(unsigned int irq)
65 {
66 irq -= ADM5120_INTC_IRQ_BASE;
67 INTC_WRITE(INTC_REG_IRQ_ENABLE, 1 << irq);
68 }
69
70 static void adm5120_intc_irq_mask(unsigned int irq)
71 {
72 irq -= ADM5120_INTC_IRQ_BASE;
73 INTC_WRITE(INTC_REG_IRQ_DISABLE, 1 << irq);
74 }
75
76 static int adm5120_intc_irq_set_type(unsigned int irq, unsigned int flow_type)
77 {
78 unsigned int sense;
79 unsigned long mode;
80 int err = 0;
81
82 sense = flow_type & (IRQ_TYPE_SENSE_MASK);
83 switch (sense) {
84 case IRQ_TYPE_NONE:
85 case IRQ_TYPE_LEVEL_HIGH:
86 break;
87 case IRQ_TYPE_LEVEL_LOW:
88 switch (irq) {
89 case ADM5120_IRQ_GPIO2:
90 case ADM5120_IRQ_GPIO4:
91 break;
92 default:
93 err = -EINVAL;
94 break;
95 }
96 break;
97 default:
98 err = -EINVAL;
99 break;
100 }
101
102 if (err)
103 return err;
104
105 switch (irq) {
106 case ADM5120_IRQ_GPIO2:
107 case ADM5120_IRQ_GPIO4:
108 mode = INTC_READ(INTC_REG_INT_MODE);
109 if (sense == IRQ_TYPE_LEVEL_LOW)
110 mode |= (1 << (irq - ADM5120_INTC_IRQ_BASE));
111 else
112 mode &= ~(1 << (irq - ADM5120_INTC_IRQ_BASE));
113
114 INTC_WRITE(INTC_REG_INT_MODE, mode);
115 /* fallthrough */
116 default:
117 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
118 irq_desc[irq].status |= sense;
119 break;
120 }
121
122 return 0;
123 }
124
125 static void adm5120_intc_irq_dispatch(void)
126 {
127 unsigned long status;
128 int irq;
129
130 /* dispatch only one IRQ at a time */
131 status = INTC_READ(INTC_REG_IRQ_STATUS) & INTC_INT_ALL;
132
133 if (status) {
134 irq = ADM5120_INTC_IRQ_BASE+fls(status)-1;
135 do_IRQ(irq);
136 } else
137 spurious_interrupt();
138 }
139
140 asmlinkage void plat_irq_dispatch(void)
141 {
142 unsigned long pending;
143
144 pending = read_c0_status() & read_c0_cause() & ST0_IM;
145
146 if (pending & STATUSF_IP7)
147 do_IRQ(ADM5120_IRQ_COUNTER);
148 else if (pending & STATUSF_IP2)
149 adm5120_intc_irq_dispatch();
150 else
151 spurious_interrupt();
152 }
153
154 #define INTC_IRQ_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
155
156 static void __init adm5120_intc_irq_init(int base)
157 {
158 int i;
159
160 /* disable all interrupts */
161 INTC_WRITE(INTC_REG_IRQ_DISABLE, INTC_INT_ALL);
162
163 /* setup all interrupts to generate IRQ instead of FIQ */
164 INTC_WRITE(INTC_REG_INT_MODE, 0);
165
166 /* set active level for all external interrupts to HIGH */
167 INTC_WRITE(INTC_REG_INT_LEVEL, 0);
168
169 /* disable usage of the TEST_SOURCE register */
170 INTC_WRITE(INTC_REG_IRQ_SOURCE_SELECT, 0);
171
172 for (i = ADM5120_INTC_IRQ_BASE;
173 i <= ADM5120_INTC_IRQ_BASE+INTC_IRQ_LAST;
174 i++) {
175 irq_desc[i].status = INTC_IRQ_STATUS;
176 set_irq_chip_and_handler(i, &adm5120_intc_irq_chip,
177 handle_level_irq);
178 }
179
180 setup_irq(ADM5120_IRQ_INTC, &adm5120_intc_irq_action);
181 }
182
183 void __init arch_init_irq(void) {
184 mips_cpu_irq_init();
185 adm5120_intc_irq_init(ADM5120_INTC_IRQ_BASE);
186 }
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