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[openwrt.git] / target / linux / lantiq / patches / 104-board_xway.patch
1
2 --- /dev/null
3 +++ b/arch/mips/lantiq/xway/Kconfig
4 @@ -0,0 +1,19 @@
5 +if SOC_LANTIQ_XWAY
6 +
7 +menu "Mips Machine"
8 +
9 +config LANTIQ_MACH_EASY50812
10 + bool "Easy50812"
11 + default y
12 +
13 +config LANTIQ_MACH_EASY50712
14 + bool "Easy50712"
15 + default y
16 +
17 +config LANTIQ_MACH_EASY4010
18 + bool "Easy4010"
19 + default y
20 +
21 +endmenu
22 +
23 +endif
24 --- /dev/null
25 +++ b/arch/mips/lantiq/xway/gpio_ebu.c
26 @@ -0,0 +1,116 @@
27 +/*
28 + * This program is free software; you can redistribute it and/or modify it
29 + * under the terms of the GNU General Public License version 2 as published
30 + * by the Free Software Foundation.
31 + *
32 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
33 + */
34 +
35 +#include <linux/init.h>
36 +#include <linux/module.h>
37 +#include <linux/types.h>
38 +#include <linux/platform_device.h>
39 +#include <linux/mutex.h>
40 +#include <linux/gpio.h>
41 +
42 +#include <xway.h>
43 +
44 +#define LQ_EBU_BUSCON 0x1e7ff
45 +#define LQ_EBU_WP 0x80000000
46 +
47 +static int shadow = 0x0000;
48 +static void __iomem *virt;
49 +
50 +static int
51 +lq_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value)
52 +{
53 + return 0;
54 +}
55 +
56 +static void
57 +lq_ebu_apply(void)
58 +{
59 + unsigned long flags;
60 + spin_lock_irqsave(&ebu_lock, flags);
61 + lq_w32(LQ_EBU_BUSCON, LQ_EBU_BUSCON1);
62 + *((__u16*)virt) = shadow;
63 + lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
64 + spin_unlock_irqrestore(&ebu_lock, flags);
65 +}
66 +
67 +static void
68 +lq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
69 +{
70 + if(value)
71 + shadow |= (1 << offset);
72 + else
73 + shadow &= ~(1 << offset);
74 + lq_ebu_apply();
75 +}
76 +
77 +static struct gpio_chip
78 +lq_ebu_chip =
79 +{
80 + .label = "lq_ebu",
81 + .direction_output = lq_ebu_direction_output,
82 + .set = lq_ebu_set,
83 + .base = 32,
84 + .ngpio = 16,
85 + .can_sleep = 1,
86 + .owner = THIS_MODULE,
87 +};
88 +
89 +static int __devinit
90 +lq_ebu_probe(struct platform_device *pdev)
91 +{
92 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
93 + int ret = 0;
94 + if (!res)
95 + return -ENOENT;
96 + res = request_mem_region(res->start, resource_size(res),
97 + dev_name(&pdev->dev));
98 + if (!res)
99 + return -EBUSY;
100 +
101 + /* tell the ebu controller which mem addr we will be using */
102 + lq_w32(pdev->resource->start | 0x1, LQ_EBU_ADDRSEL1);
103 + lq_w32(LQ_EBU_BUSCON | LQ_EBU_WP, LQ_EBU_BUSCON1);
104 +
105 + virt = ioremap_nocache(res->start, resource_size(res));
106 + if (!virt)
107 + {
108 + dev_err(&pdev->dev, "Failed to ioremap mem region\n");
109 + ret = -ENOMEM;
110 + goto err_release_mem_region;
111 + }
112 + /* grab the default settings passed form the platform code */
113 + shadow = (unsigned int) pdev->dev.platform_data;
114 +
115 + ret = gpiochip_add(&lq_ebu_chip);
116 + if (!ret)
117 + {
118 + lq_ebu_apply();
119 + return 0;
120 + }
121 +
122 +err_release_mem_region:
123 + release_mem_region(res->start, resource_size(res));
124 + return ret;
125 +}
126 +
127 +static struct platform_driver
128 +lq_ebu_driver = {
129 + .probe = lq_ebu_probe,
130 + .driver = {
131 + .name = "lq_ebu",
132 + .owner = THIS_MODULE,
133 + },
134 +};
135 +
136 +static int __init
137 +init_lq_ebu(void)
138 +{
139 + return platform_driver_register(&lq_ebu_driver);
140 +}
141 +
142 +postcore_initcall(init_lq_ebu);
143 --- /dev/null
144 +++ b/arch/mips/lantiq/xway/gpio_leds.c
145 @@ -0,0 +1,161 @@
146 +/*
147 + * This program is free software; you can redistribute it and/or modify it
148 + * under the terms of the GNU General Public License version 2 as published
149 + * by the Free Software Foundation.
150 + *
151 + * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
152 + *
153 + */
154 +
155 +#include <linux/slab.h>
156 +#include <linux/init.h>
157 +#include <linux/module.h>
158 +#include <linux/types.h>
159 +#include <linux/platform_device.h>
160 +#include <linux/mutex.h>
161 +#include <linux/gpio.h>
162 +
163 +#include <xway.h>
164 +
165 +#define LQ_STP_BASE 0x1E100BB0
166 +#define LQ_STP_SIZE 0x40
167 +
168 +#define LQ_STP_CON0 0x00
169 +#define LQ_STP_CON1 0x04
170 +#define LQ_STP_CPU0 0x08
171 +#define LQ_STP_CPU1 0x0C
172 +#define LQ_STP_AR 0x10
173 +
174 +#define STP_CON0_SWU (1 << 31)
175 +
176 +#define LQ_STP_2HZ (0)
177 +#define LQ_STP_4HZ (1 << 23)
178 +#define LQ_STP_8HZ (2 << 23)
179 +#define LQ_STP_10HZ (3 << 23)
180 +#define LQ_STP_MASK (0xf << 23)
181 +
182 +#define LQ_STP_UPD_SRC_FPI (1 << 31)
183 +#define LQ_STP_UPD_MASK (3 << 30)
184 +#define LQ_STP_ADSL_SRC (3 << 24)
185 +
186 +#define LQ_STP_GROUP0 (1 << 0)
187 +
188 +#define LQ_STP_RISING 0
189 +#define LQ_STP_FALLING (1 << 26)
190 +#define LQ_STP_EDGE_MASK (1 << 26)
191 +
192 +#define lq_stp_r32(reg) __raw_readl(virt + reg)
193 +#define lq_stp_w32(val, reg) __raw_writel(val, virt + reg)
194 +#define lq_stp_w32_mask(clear, set, reg) \
195 + lq_w32((lq_r32(virt + reg) & ~clear) | set, virt + reg)
196 +
197 +static int shadow = 0xffff;
198 +static void __iomem *virt;
199 +
200 +static int
201 +lq_stp_direction_output(struct gpio_chip *chip, unsigned offset, int value)
202 +{
203 + return 0;
204 +}
205 +
206 +static void
207 +lq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
208 +{
209 + if(value)
210 + shadow |= (1 << offset);
211 + else
212 + shadow &= ~(1 << offset);
213 + lq_stp_w32(shadow, LQ_STP_CPU0);
214 +}
215 +
216 +static struct gpio_chip lq_stp_chip =
217 +{
218 + .label = "lq_stp",
219 + .direction_output = lq_stp_direction_output,
220 + .set = lq_stp_set,
221 + .base = 48,
222 + .ngpio = 24,
223 + .can_sleep = 1,
224 + .owner = THIS_MODULE,
225 +};
226 +
227 +static int
228 +lq_stp_hw_init(void)
229 +{
230 + /* the 3 pins used to control the external stp */
231 + lq_gpio_request(4, 1, 0, 1, "stp-st");
232 + lq_gpio_request(5, 1, 0, 1, "stp-d");
233 + lq_gpio_request(6, 1, 0, 1, "stp-sh");
234 +
235 + /* sane defaults */
236 + lq_stp_w32(0, LQ_STP_AR);
237 + lq_stp_w32(0, LQ_STP_CPU0);
238 + lq_stp_w32(0, LQ_STP_CPU1);
239 + lq_stp_w32(STP_CON0_SWU, LQ_STP_CON0);
240 + lq_stp_w32(0, LQ_STP_CON1);
241 +
242 + /* rising or falling edge */
243 + lq_stp_w32_mask(LQ_STP_EDGE_MASK, LQ_STP_FALLING, LQ_STP_CON0);
244 +
245 + /* per default stp 15-0 are set */
246 + lq_stp_w32_mask(0, LQ_STP_GROUP0, LQ_STP_CON1);
247 +
248 + /* stp are update periodically by the FPID */
249 + lq_stp_w32_mask(LQ_STP_UPD_MASK, LQ_STP_UPD_SRC_FPI, LQ_STP_CON1);
250 +
251 + /* set stp update speed */
252 + lq_stp_w32_mask(LQ_STP_MASK, LQ_STP_8HZ, LQ_STP_CON1);
253 +
254 + /* adsl 0 and 1 stp are updated by the arc */
255 + lq_stp_w32_mask(0, LQ_STP_ADSL_SRC, LQ_STP_CON0);
256 +
257 + lq_pmu_enable(PMU_LED);
258 + return 0;
259 +}
260 +
261 +static int
262 +lq_stp_probe(struct platform_device *pdev)
263 +{
264 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265 + int ret = 0;
266 + if (!res)
267 + return -ENOENT;
268 + res = request_mem_region(res->start, resource_size(res),
269 + dev_name(&pdev->dev));
270 + if (!res)
271 + return -EBUSY;
272 + virt = ioremap_nocache(res->start, resource_size(res));
273 + if(!virt)
274 + {
275 + ret = -ENOMEM;
276 + goto err_release_mem_region;
277 + }
278 + ret = gpiochip_add(&lq_stp_chip);
279 + if(!ret)
280 + return lq_stp_hw_init();
281 +
282 + iounmap(virt);
283 +err_release_mem_region:
284 + release_mem_region(res->start, resource_size(res));
285 + return ret;
286 +}
287 +
288 +static struct platform_driver lq_stp_driver = {
289 + .probe = lq_stp_probe,
290 + .driver = {
291 + .name = "lq_stp",
292 + .owner = THIS_MODULE,
293 + },
294 +};
295 +
296 +int __init
297 +init_lq_stp(void)
298 +{
299 + int ret = platform_driver_register(&lq_stp_driver);
300 + if (ret)
301 + printk(KERN_INFO
302 + "lq_stp: error registering platfom driver");
303 + return ret;
304 +}
305 +
306 +postcore_initcall(init_lq_stp);
307 --- /dev/null
308 +++ b/arch/mips/lantiq/xway/mach-easy4010.c
309 @@ -0,0 +1,82 @@
310 +/*
311 + * This program is free software; you can redistribute it and/or modify it
312 + * under the terms of the GNU General Public License version 2 as published
313 + * by the Free Software Foundation.
314 + *
315 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
316 + */
317 +
318 +#include <linux/init.h>
319 +#include <linux/platform_device.h>
320 +#include <linux/leds.h>
321 +#include <linux/gpio.h>
322 +#include <linux/gpio_buttons.h>
323 +#include <linux/mtd/mtd.h>
324 +#include <linux/mtd/partitions.h>
325 +#include <linux/mtd/physmap.h>
326 +#include <linux/input.h>
327 +
328 +#include <machine.h>
329 +
330 +#include <xway.h>
331 +#include <lantiq_platform.h>
332 +
333 +#include "devices.h"
334 +
335 +#ifdef CONFIG_MTD_PARTITIONS
336 +static struct mtd_partition easy4010_partitions[] =
337 +{
338 + {
339 + .name = "uboot",
340 + .offset = 0x0,
341 + .size = 0x20000,
342 + },
343 + {
344 + .name = "uboot_env",
345 + .offset = 0x20000,
346 + .size = 0x10000,
347 + },
348 + {
349 + .name = "linux",
350 + .offset = 0x30000,
351 + .size = 0x3D0000,
352 + },
353 +};
354 +#endif
355 +
356 +static struct physmap_flash_data easy4010_flash_data = {
357 +#ifdef CONFIG_MTD_PARTITIONS
358 + .nr_parts = ARRAY_SIZE(easy4010_partitions),
359 + .parts = easy4010_partitions,
360 +#endif
361 +};
362 +
363 +static struct lq_pci_data lq_pci_data = {
364 + .clock = PCI_CLOCK_INT,
365 + .gpio = PCI_GNT1 | PCI_REQ1,
366 + .irq = {
367 + [14] = INT_NUM_IM0_IRL0 + 22,
368 + },
369 +};
370 +
371 +static struct lq_eth_data lq_eth_data = {
372 + .mii_mode = REV_MII_MODE,
373 +};
374 +
375 +static void __init
376 +easy4010_init(void)
377 +{
378 + lq_register_gpio();
379 + lq_register_gpio_stp();
380 + lq_register_asc(0);
381 + lq_register_asc(1);
382 + lq_register_nor(&easy4010_flash_data);
383 + lq_register_wdt();
384 + lq_register_pci(&lq_pci_data);
385 + lq_register_ethernet(&lq_eth_data);
386 +}
387 +
388 +MIPS_MACHINE(LANTIQ_MACH_EASY4010,
389 + "EASY4010",
390 + "EASY4010 Eval Board",
391 + easy4010_init);
392 --- /dev/null
393 +++ b/arch/mips/lantiq/xway/mach-easy50712.c
394 @@ -0,0 +1,82 @@
395 +/*
396 + * This program is free software; you can redistribute it and/or modify it
397 + * under the terms of the GNU General Public License version 2 as published
398 + * by the Free Software Foundation.
399 + *
400 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
401 + */
402 +
403 +#include <linux/init.h>
404 +#include <linux/platform_device.h>
405 +#include <linux/leds.h>
406 +#include <linux/gpio.h>
407 +#include <linux/gpio_buttons.h>
408 +#include <linux/mtd/mtd.h>
409 +#include <linux/mtd/partitions.h>
410 +#include <linux/mtd/physmap.h>
411 +#include <linux/input.h>
412 +
413 +#include <machine.h>
414 +
415 +#include <xway.h>
416 +#include <lantiq_platform.h>
417 +
418 +#include "devices.h"
419 +
420 +#ifdef CONFIG_MTD_PARTITIONS
421 +static struct mtd_partition easy50712_partitions[] =
422 +{
423 + {
424 + .name = "uboot",
425 + .offset = 0x0,
426 + .size = 0x20000,
427 + },
428 + {
429 + .name = "uboot_env",
430 + .offset = 0x20000,
431 + .size = 0x10000,
432 + },
433 + {
434 + .name = "linux",
435 + .offset = 0x30000,
436 + .size = 0x3D0000,
437 + },
438 +};
439 +#endif
440 +
441 +static struct physmap_flash_data easy50712_flash_data = {
442 +#ifdef CONFIG_MTD_PARTITIONS
443 + .nr_parts = ARRAY_SIZE(easy50712_partitions),
444 + .parts = easy50712_partitions,
445 +#endif
446 +};
447 +
448 +static struct lq_pci_data lq_pci_data = {
449 + .clock = PCI_CLOCK_INT,
450 + .gpio = PCI_GNT1 | PCI_REQ1,
451 + .irq = {
452 + [14] = INT_NUM_IM0_IRL0 + 22,
453 + },
454 +};
455 +
456 +static struct lq_eth_data lq_eth_data = {
457 + .mii_mode = REV_MII_MODE,
458 +};
459 +
460 +static void __init
461 +easy50712_init(void)
462 +{
463 + lq_register_asc(0);
464 + lq_register_asc(1);
465 + lq_register_gpio();
466 + lq_register_gpio_stp();
467 + lq_register_nor(&easy50712_flash_data);
468 + lq_register_wdt();
469 + lq_register_pci(&lq_pci_data);
470 + lq_register_ethernet(&lq_eth_data);
471 +}
472 +
473 +MIPS_MACHINE(LANTIQ_MACH_EASY50712,
474 + "EASY50712",
475 + "EASY50712 Eval Board",
476 + easy50712_init);
477 --- /dev/null
478 +++ b/arch/mips/lantiq/xway/mach-easy50812.c
479 @@ -0,0 +1,81 @@
480 +/*
481 + * This program is free software; you can redistribute it and/or modify it
482 + * under the terms of the GNU General Public License version 2 as published
483 + * by the Free Software Foundation.
484 + *
485 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
486 + */
487 +
488 +#include <linux/init.h>
489 +#include <linux/platform_device.h>
490 +#include <linux/leds.h>
491 +#include <linux/gpio.h>
492 +#include <linux/gpio_buttons.h>
493 +#include <linux/mtd/mtd.h>
494 +#include <linux/mtd/partitions.h>
495 +#include <linux/mtd/physmap.h>
496 +#include <linux/input.h>
497 +
498 +#include <machine.h>
499 +
500 +#include <xway.h>
501 +#include <lantiq_platform.h>
502 +
503 +#include "devices.h"
504 +
505 +#ifdef CONFIG_MTD_PARTITIONS
506 +static struct mtd_partition easy50812_partitions[] =
507 +{
508 + {
509 + .name = "uboot",
510 + .offset = 0x0,
511 + .size = 0x40000,
512 + },
513 + {
514 + .name = "uboot_env",
515 + .offset = 0x40000,
516 + .size = 0x10000,
517 + },
518 + {
519 + .name = "linux",
520 + .offset = 0x50000,
521 + .size = 0x3B0000,
522 + },
523 +};
524 +#endif
525 +
526 +static struct physmap_flash_data easy50812_flash_data = {
527 +#ifdef CONFIG_MTD_PARTITIONS
528 + .nr_parts = ARRAY_SIZE(easy50812_partitions),
529 + .parts = easy50812_partitions,
530 +#endif
531 +};
532 +
533 +static struct lq_pci_data lq_pci_data = {
534 + .clock = PCI_CLOCK_INT,
535 + .gpio = PCI_GNT1 | PCI_REQ1,
536 + .irq = {
537 + [14] = INT_NUM_IM0_IRL0 + 22,
538 + },
539 +};
540 +
541 +static struct lq_eth_data lq_eth_data = {
542 + .mii_mode = REV_MII_MODE,
543 +};
544 +
545 +static void __init
546 +easy50812_init(void)
547 +{
548 + lq_register_gpio();
549 + lq_register_asc(0);
550 + lq_register_asc(1);
551 + lq_register_nor(&easy50812_flash_data);
552 + lq_register_wdt();
553 + lq_register_pci(&lq_pci_data);
554 + lq_register_ethernet(&lq_eth_data);
555 +}
556 +
557 +MIPS_MACHINE(LANTIQ_MACH_EASY50812,
558 + "EASY50812",
559 + "EASY50812 Eval Board",
560 + easy50812_init);
561 --- /dev/null
562 +++ b/arch/mips/lantiq/xway/prom.c
563 @@ -0,0 +1,52 @@
564 +/*
565 + * This program is free software; you can redistribute it and/or modify it
566 + * under the terms of the GNU General Public License version 2 as published
567 + * by the Free Software Foundation.
568 + *
569 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
570 + */
571 +
572 +#include <linux/module.h>
573 +#include <linux/clk.h>
574 +#include <asm/bootinfo.h>
575 +#include <asm/time.h>
576 +
577 +#include <xway.h>
578 +
579 +#include "../prom.h"
580 +
581 +#define SOC_DANUBE "Danube"
582 +#define SOC_TWINPASS "Twinpass"
583 +#define SOC_AR9 "AR9"
584 +
585 +void __init
586 +lq_soc_detect(struct lq_soc_info *i)
587 +{
588 + i->partnum = (lq_r32(LQ_MPS_CHIPID) & 0x0FFFFFFF) >> 12;
589 + i->rev = (lq_r32(LQ_MPS_CHIPID) & 0xF0000000) >> 28;
590 + switch (i->partnum)
591 + {
592 + case SOC_ID_DANUBE1:
593 + case SOC_ID_DANUBE2:
594 + i->name = SOC_DANUBE;
595 + i->type = SOC_TYPE_DANUBE;
596 + break;
597 +
598 + case SOC_ID_TWINPASS:
599 + i->name = SOC_TWINPASS;
600 + i->type = SOC_TYPE_DANUBE;
601 + break;
602 +
603 + case SOC_ID_ARX188:
604 + case SOC_ID_ARX168:
605 + case SOC_ID_ARX182:
606 + i->name = SOC_AR9;
607 + i->type = SOC_TYPE_AR9;
608 + break;
609 +
610 + default:
611 + printk(KERN_ERR "unknown chiprev : 0x%08X\n", i->partnum);
612 + while(1) { };
613 + break;
614 + }
615 +}
616 --- /dev/null
617 +++ b/arch/mips/lantiq/xway/devices.c
618 @@ -0,0 +1,313 @@
619 +/*
620 + * This program is free software; you can redistribute it and/or modify it
621 + * under the terms of the GNU General Public License version 2 as published
622 + * by the Free Software Foundation.
623 + *
624 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
625 + */
626 +
627 +#include <linux/init.h>
628 +#include <linux/module.h>
629 +#include <linux/types.h>
630 +#include <linux/string.h>
631 +#include <linux/mtd/physmap.h>
632 +#include <linux/kernel.h>
633 +#include <linux/reboot.h>
634 +#include <linux/platform_device.h>
635 +#include <linux/leds.h>
636 +#include <linux/etherdevice.h>
637 +#include <linux/reboot.h>
638 +#include <linux/time.h>
639 +#include <linux/io.h>
640 +#include <linux/gpio.h>
641 +#include <linux/gpio_buttons.h>
642 +#include <linux/leds.h>
643 +
644 +#include <asm/bootinfo.h>
645 +#include <asm/irq.h>
646 +
647 +#include <xway.h>
648 +#include <xway_irq.h>
649 +#include <lantiq_platform.h>
650 +
651 +#define IRQ_RES(resname,irq) {.name=#resname,.start=(irq),.flags=IORESOURCE_IRQ}
652 +
653 +/* gpio leds */
654 +static struct gpio_led_platform_data lq_gpio_led_data;
655 +
656 +static struct platform_device lq_gpio_leds =
657 +{
658 + .name = "leds-gpio",
659 + .dev = {
660 + .platform_data = (void *) &lq_gpio_led_data,
661 + }
662 +};
663 +
664 +void __init
665 +lq_register_gpio_leds(struct gpio_led *leds, int cnt)
666 +{
667 + lq_gpio_led_data.leds = leds;
668 + lq_gpio_led_data.num_leds = cnt;
669 + platform_device_register(&lq_gpio_leds);
670 +}
671 +
672 +/* gpio buttons */
673 +static struct gpio_buttons_platform_data lq_gpio_buttons_platform_data;
674 +
675 +static struct platform_device lq_gpio_buttons_platform_device =
676 +{
677 + .name = "gpio-buttons",
678 + .id = 0,
679 + .dev = {
680 + .platform_data = (void *) &lq_gpio_buttons_platform_data,
681 + },
682 +};
683 +
684 +void __init
685 +lq_register_gpio_buttons(struct gpio_button *buttons, int cnt)
686 +{
687 + lq_gpio_buttons_platform_data.buttons = buttons;
688 + lq_gpio_buttons_platform_data.nbuttons = cnt;
689 + platform_device_register(&lq_gpio_buttons_platform_device);
690 +}
691 +
692 +/* serial to parallel conversion */
693 +static struct resource lq_stp_resource =
694 +{
695 + .name = "stp",
696 + .start = LQ_STP_BASE,
697 + .end = LQ_STP_BASE + LQ_STP_SIZE - 1,
698 + .flags = IORESOURCE_MEM,
699 +};
700 +
701 +void __init
702 +lq_register_gpio_stp(void)
703 +{
704 + platform_device_register_simple("lq_stp", 0, &lq_stp_resource, 1);
705 +}
706 +
707 +/* nor flash */
708 +static struct resource lq_nor_resource =
709 +{
710 + .name = "nor",
711 + .start = LQ_FLASH_START,
712 + .end = LQ_FLASH_START + LQ_FLASH_MAX - 1,
713 + .flags = IORESOURCE_MEM,
714 +};
715 +
716 +static struct platform_device lq_nor =
717 +{
718 + .name = "lq_nor",
719 + .resource = &lq_nor_resource,
720 + .num_resources = 1,
721 +};
722 +
723 +void __init
724 +lq_register_nor(struct physmap_flash_data *data)
725 +{
726 + lq_nor.dev.platform_data = data;
727 + platform_device_register(&lq_nor);
728 +}
729 +
730 +/* watchdog */
731 +static struct resource lq_wdt_resource =
732 +{
733 + .name = "watchdog",
734 + .start = LQ_WDT_BASE,
735 + .end = LQ_WDT_BASE + LQ_WDT_SIZE - 1,
736 + .flags = IORESOURCE_MEM,
737 +};
738 +
739 +void __init
740 +lq_register_wdt(void)
741 +{
742 + platform_device_register_simple("lq_wdt", 0, &lq_wdt_resource, 1);
743 +}
744 +
745 +/* gpio */
746 +static struct resource lq_gpio_resource[] = {
747 + {
748 + .name = "gpio0",
749 + .start = LQ_GPIO0_BASE_ADDR,
750 + .end = LQ_GPIO0_BASE_ADDR + LQ_GPIO_SIZE - 1,
751 + .flags = IORESOURCE_MEM,
752 + }, {
753 + .name = "gpio1",
754 + .start = LQ_GPIO1_BASE_ADDR,
755 + .end = LQ_GPIO1_BASE_ADDR + LQ_GPIO_SIZE - 1,
756 + .flags = IORESOURCE_MEM,
757 + }
758 +};
759 +
760 +void __init
761 +lq_register_gpio(void)
762 +{
763 + platform_device_register_simple("lq_gpio", 0, &lq_gpio_resource[0], 1);
764 + platform_device_register_simple("lq_gpio", 1, &lq_gpio_resource[1], 1);
765 +}
766 +
767 +/* pci */
768 +static struct platform_device lq_pci =
769 +{
770 + .name = "lq_pci",
771 + .num_resources = 0,
772 +};
773 +
774 +void __init
775 +lq_register_pci(struct lq_pci_data *data)
776 +{
777 + lq_pci.dev.platform_data = data;
778 + platform_device_register(&lq_pci);
779 +}
780 +
781 +/* ebu */
782 +static struct resource lq_ebu_resource =
783 +{
784 + .name = "gpio_ebu",
785 + .start = LQ_EBU_GPIO_START,
786 + .end = LQ_EBU_GPIO_START + LQ_EBU_GPIO_SIZE - 1,
787 + .flags = IORESOURCE_MEM,
788 +};
789 +
790 +static struct platform_device lq_ebu =
791 +{
792 + .name = "lq_ebu",
793 + .resource = &lq_ebu_resource,
794 + .num_resources = 1,
795 +};
796 +
797 +void __init
798 +lq_register_gpio_ebu(unsigned int value)
799 +{
800 + lq_ebu.dev.platform_data = (void*) value;
801 + platform_device_register(&lq_ebu);
802 +}
803 +
804 +/* ethernet */
805 +unsigned char lq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
806 +
807 +static int __init
808 +lq_set_ethaddr(char *str)
809 +{
810 + sscanf(&str[8], "0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx:0%02hhx",
811 + &lq_ethaddr[0], &lq_ethaddr[1], &lq_ethaddr[2],
812 + &lq_ethaddr[3], &lq_ethaddr[4], &lq_ethaddr[5]);
813 + return 0;
814 +}
815 +__setup("ethaddr=", lq_set_ethaddr);
816 +
817 +static struct resource lq_ethernet_resources =
818 +{
819 + .name = "etop",
820 + .start = LQ_PPE32_BASE_ADDR,
821 + .end = LQ_PPE32_BASE_ADDR + LQ_PPE32_SIZE - 1,
822 + .flags = IORESOURCE_MEM,
823 +};
824 +
825 +static struct platform_device lq_ethernet =
826 +{
827 + .name = "lq_etop",
828 + .resource = &lq_ethernet_resources,
829 + .num_resources = 1,
830 +};
831 +
832 +void __init
833 +lq_register_ethernet(struct lq_eth_data *eth)
834 +{
835 + if(!eth)
836 + return;
837 + if(!eth->mac)
838 + eth->mac = lq_ethaddr;
839 + if(!is_valid_ether_addr(eth->mac))
840 + random_ether_addr(eth->mac);
841 + lq_ethernet.dev.platform_data = eth;
842 + platform_device_register(&lq_ethernet);
843 +}
844 +
845 +/* tapi */
846 +static struct resource mps_resources[] = {
847 + {
848 + .name = "voice-mem",
849 + .flags = IORESOURCE_MEM,
850 + .start = 0x1f107000,
851 + .end = 0x1f1073ff,
852 + },
853 + {
854 + .name = "voice-mailbox",
855 + .flags = IORESOURCE_MEM,
856 + .start = 0x1f200000,
857 + .end = 0x1f2007ff,
858 + },
859 +};
860 +
861 +static struct platform_device mps_device = {
862 + .name = "mps",
863 + .resource = mps_resources,
864 + .num_resources = ARRAY_SIZE(mps_resources),
865 +};
866 +
867 +static struct platform_device vmmc_device = {
868 + .name = "vmmc",
869 + .dev = {
870 + .parent = &mps_device.dev,
871 + },
872 +};
873 +
874 +void __init
875 +lq_register_tapi(void)
876 +{
877 +#define CP1_SIZE (1 << 20)
878 + dma_addr_t dma;
879 + mps_device.dev.platform_data =
880 + (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
881 + platform_device_register(&mps_device);
882 + platform_device_register(&vmmc_device);
883 +}
884 +
885 +/* asc ports */
886 +static struct resource lq_asc0_resources[] =
887 +{
888 + {
889 + .start = LQ_ASC0_BASE,
890 + .end = LQ_ASC0_BASE + LQ_ASC_SIZE - 1,
891 + .flags = IORESOURCE_MEM,
892 + },
893 + IRQ_RES(tx, INT_NUM_IM3_IRL0),
894 + IRQ_RES(rx, INT_NUM_IM3_IRL0 + 1),
895 + IRQ_RES(err, INT_NUM_IM3_IRL0 + 2),
896 +};
897 +
898 +static struct resource lq_asc1_resources[] =
899 +{
900 + {
901 + .start = LQ_ASC1_BASE,
902 + .end = LQ_ASC1_BASE + LQ_ASC_SIZE - 1,
903 + .flags = IORESOURCE_MEM,
904 + },
905 + IRQ_RES(tx, INT_NUM_IM3_IRL0 + 8),
906 + IRQ_RES(rx, INT_NUM_IM3_IRL0 + 9),
907 + IRQ_RES(err, INT_NUM_IM3_IRL0 + 10),
908 +};
909 +
910 +void __init
911 +lq_register_asc(int port)
912 +{
913 + switch (port) {
914 + case 0:
915 + platform_device_register_simple("lq_asc", 0,
916 + lq_asc0_resources, ARRAY_SIZE(lq_asc0_resources));
917 + break;
918 + case 1:
919 + platform_device_register_simple("lq_asc", 1,
920 + lq_asc1_resources, ARRAY_SIZE(lq_asc1_resources));
921 + break;
922 + default:
923 + break;
924 + }
925 +}
926 +
927 +void __init
928 +lq_register_crypto(const char *name)
929 +{
930 + platform_device_register_simple(name, 0, 0, 0);
931 +}
932 --- /dev/null
933 +++ b/arch/mips/lantiq/xway/devices.h
934 @@ -0,0 +1,26 @@
935 +/*
936 + * This program is free software; you can redistribute it and/or modify it
937 + * under the terms of the GNU General Public License version 2 as published
938 + * by the Free Software Foundation.
939 + *
940 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
941 + */
942 +
943 +#ifndef _LQ_DEVICES_H__
944 +#define _LQ_DEVICES_H__
945 +
946 +#include <lantiq_platform.h>
947 +#include <xway_irq.h>
948 +
949 +extern void __init lq_register_gpio(void);
950 +extern void __init lq_register_gpio_stp(void);
951 +extern void __init lq_register_gpio_ebu(unsigned int value);
952 +extern void __init lq_register_gpio_leds(struct gpio_led *leds, int cnt);
953 +extern void __init lq_register_pci(struct lq_pci_data *data);
954 +extern void __init lq_register_nor(struct physmap_flash_data *data);
955 +extern void __init lq_register_wdt(void);
956 +extern void __init lq_register_ethernet(struct lq_eth_data *eth);
957 +extern void __init lq_register_asc(int port);
958 +extern void __init lq_register_gpio_buttons(struct gpio_button *buttons, int cnt);
959 +
960 +#endif
961 --- /dev/null
962 +++ b/arch/mips/lantiq/xway/dma.c
963 @@ -0,0 +1,701 @@
964 +#include <linux/module.h>
965 +#include <linux/init.h>
966 +#include <linux/sched.h>
967 +#include <linux/kernel.h>
968 +#include <linux/slab.h>
969 +#include <linux/string.h>
970 +#include <linux/timer.h>
971 +#include <linux/fs.h>
972 +#include <linux/errno.h>
973 +#include <linux/stat.h>
974 +#include <linux/mm.h>
975 +#include <linux/tty.h>
976 +#include <linux/selection.h>
977 +#include <linux/kmod.h>
978 +#include <linux/vmalloc.h>
979 +#include <linux/interrupt.h>
980 +#include <linux/delay.h>
981 +#include <linux/uaccess.h>
982 +#include <linux/errno.h>
983 +#include <linux/io.h>
984 +
985 +#include <xway.h>
986 +#include <xway_irq.h>
987 +#include <xway_dma.h>
988 +
989 +#define LQ_DMA_CS ((u32 *)(LQ_DMA_BASE_ADDR + 0x18))
990 +#define LQ_DMA_CIE ((u32 *)(LQ_DMA_BASE_ADDR + 0x2C))
991 +#define LQ_DMA_IRNEN ((u32 *)(LQ_DMA_BASE_ADDR + 0xf4))
992 +#define LQ_DMA_CCTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x1C))
993 +#define LQ_DMA_CIS ((u32 *)(LQ_DMA_BASE_ADDR + 0x28))
994 +#define LQ_DMA_CDLEN ((u32 *)(LQ_DMA_BASE_ADDR + 0x24))
995 +#define LQ_DMA_PS ((u32 *)(LQ_DMA_BASE_ADDR + 0x40))
996 +#define LQ_DMA_PCTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x44))
997 +#define LQ_DMA_CTRL ((u32 *)(LQ_DMA_BASE_ADDR + 0x10))
998 +#define LQ_DMA_CPOLL ((u32 *)(LQ_DMA_BASE_ADDR + 0x14))
999 +#define LQ_DMA_CDBA ((u32 *)(LQ_DMA_BASE_ADDR + 0x20))
1000 +
1001 +/*25 descriptors for each dma channel,4096/8/20=25.xx*/
1002 +#define LQ_DMA_DESCRIPTOR_OFFSET 25
1003 +
1004 +#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */
1005 +#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */
1006 +#define DMA_INT_BUDGET 100 /*budget for interrupt handling */
1007 +#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */
1008 +
1009 +extern void lq_mask_and_ack_irq(unsigned int irq_nr);
1010 +extern void lq_enable_irq(unsigned int irq_nr);
1011 +extern void lq_disable_irq(unsigned int irq_nr);
1012 +
1013 +u64 *g_desc_list;
1014 +struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM];
1015 +struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM];
1016 +
1017 +static const char *global_device_name[MAX_DMA_DEVICE_NUM] =
1018 + { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" };
1019 +
1020 +struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = {
1021 + {"PPE", LQ_DMA_RX, 0, LQ_DMA_CH0_INT, 0},
1022 + {"PPE", LQ_DMA_TX, 0, LQ_DMA_CH1_INT, 0},
1023 + {"PPE", LQ_DMA_RX, 1, LQ_DMA_CH2_INT, 1},
1024 + {"PPE", LQ_DMA_TX, 1, LQ_DMA_CH3_INT, 1},
1025 + {"PPE", LQ_DMA_RX, 2, LQ_DMA_CH4_INT, 2},
1026 + {"PPE", LQ_DMA_TX, 2, LQ_DMA_CH5_INT, 2},
1027 + {"PPE", LQ_DMA_RX, 3, LQ_DMA_CH6_INT, 3},
1028 + {"PPE", LQ_DMA_TX, 3, LQ_DMA_CH7_INT, 3},
1029 + {"DEU", LQ_DMA_RX, 0, LQ_DMA_CH8_INT, 0},
1030 + {"DEU", LQ_DMA_TX, 0, LQ_DMA_CH9_INT, 0},
1031 + {"DEU", LQ_DMA_RX, 1, LQ_DMA_CH10_INT, 1},
1032 + {"DEU", LQ_DMA_TX, 1, LQ_DMA_CH11_INT, 1},
1033 + {"SPI", LQ_DMA_RX, 0, LQ_DMA_CH12_INT, 0},
1034 + {"SPI", LQ_DMA_TX, 0, LQ_DMA_CH13_INT, 0},
1035 + {"SDIO", LQ_DMA_RX, 0, LQ_DMA_CH14_INT, 0},
1036 + {"SDIO", LQ_DMA_TX, 0, LQ_DMA_CH15_INT, 0},
1037 + {"MCTRL0", LQ_DMA_RX, 0, LQ_DMA_CH16_INT, 0},
1038 + {"MCTRL0", LQ_DMA_TX, 0, LQ_DMA_CH17_INT, 0},
1039 + {"MCTRL1", LQ_DMA_RX, 1, LQ_DMA_CH18_INT, 1},
1040 + {"MCTRL1", LQ_DMA_TX, 1, LQ_DMA_CH19_INT, 1}
1041 +};
1042 +
1043 +struct dma_chan_map *chan_map = default_dma_map;
1044 +volatile u32 g_lq_dma_int_status;
1045 +volatile int g_lq_dma_in_process; /* 0=not in process, 1=in process */
1046 +
1047 +void do_dma_tasklet(unsigned long);
1048 +DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0);
1049 +
1050 +u8 *common_buffer_alloc(int len, int *byte_offset, void **opt)
1051 +{
1052 + u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL);
1053 +
1054 + *byte_offset = 0;
1055 +
1056 + return buffer;
1057 +}
1058 +
1059 +void common_buffer_free(u8 *dataptr, void *opt)
1060 +{
1061 + kfree(dataptr);
1062 +}
1063 +
1064 +void enable_ch_irq(struct dma_channel_info *pCh)
1065 +{
1066 + int chan_no = (int)(pCh - dma_chan);
1067 + unsigned long flag;
1068 +
1069 + local_irq_save(flag);
1070 + lq_w32(chan_no, LQ_DMA_CS);
1071 + lq_w32(0x4a, LQ_DMA_CIE);
1072 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1073 + local_irq_restore(flag);
1074 + lq_enable_irq(pCh->irq);
1075 +}
1076 +
1077 +void disable_ch_irq(struct dma_channel_info *pCh)
1078 +{
1079 + unsigned long flag;
1080 + int chan_no = (int) (pCh - dma_chan);
1081 +
1082 + local_irq_save(flag);
1083 + g_lq_dma_int_status &= ~(1 << chan_no);
1084 + lq_w32(chan_no, LQ_DMA_CS);
1085 + lq_w32(0, LQ_DMA_CIE);
1086 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN);
1087 + local_irq_restore(flag);
1088 + lq_mask_and_ack_irq(pCh->irq);
1089 +}
1090 +
1091 +void open_chan(struct dma_channel_info *pCh)
1092 +{
1093 + unsigned long flag;
1094 + int chan_no = (int)(pCh - dma_chan);
1095 +
1096 + local_irq_save(flag);
1097 + lq_w32(chan_no, LQ_DMA_CS);
1098 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 1, LQ_DMA_CCTRL);
1099 + if (pCh->dir == LQ_DMA_RX)
1100 + enable_ch_irq(pCh);
1101 + local_irq_restore(flag);
1102 +}
1103 +
1104 +void close_chan(struct dma_channel_info *pCh)
1105 +{
1106 + unsigned long flag;
1107 + int chan_no = (int) (pCh - dma_chan);
1108 +
1109 + local_irq_save(flag);
1110 + lq_w32(chan_no, LQ_DMA_CS);
1111 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1112 + disable_ch_irq(pCh);
1113 + local_irq_restore(flag);
1114 +}
1115 +
1116 +void reset_chan(struct dma_channel_info *pCh)
1117 +{
1118 + int chan_no = (int) (pCh - dma_chan);
1119 +
1120 + lq_w32(chan_no, LQ_DMA_CS);
1121 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1122 +}
1123 +
1124 +void rx_chan_intr_handler(int chan_no)
1125 +{
1126 + struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1127 + struct dma_channel_info *pCh = &dma_chan[chan_no];
1128 + struct rx_desc *rx_desc_p;
1129 + int tmp;
1130 + unsigned long flag;
1131 +
1132 + /*handle command complete interrupt */
1133 + rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc;
1134 + if (rx_desc_p->status.field.OWN == CPU_OWN
1135 + && rx_desc_p->status.field.C
1136 + && rx_desc_p->status.field.data_length < 1536){
1137 + /* Every thing is correct, then we inform the upper layer */
1138 + pDev->current_rx_chan = pCh->rel_chan_no;
1139 + if (pDev->intr_handler)
1140 + pDev->intr_handler(pDev, RCV_INT);
1141 + pCh->weight--;
1142 + } else {
1143 + local_irq_save(flag);
1144 + tmp = lq_r32(LQ_DMA_CS);
1145 + lq_w32(chan_no, LQ_DMA_CS);
1146 + lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1147 + lq_w32(tmp, LQ_DMA_CS);
1148 + g_lq_dma_int_status &= ~(1 << chan_no);
1149 + local_irq_restore(flag);
1150 + lq_enable_irq(dma_chan[chan_no].irq);
1151 + }
1152 +}
1153 +
1154 +inline void tx_chan_intr_handler(int chan_no)
1155 +{
1156 + struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev;
1157 + struct dma_channel_info *pCh = &dma_chan[chan_no];
1158 + int tmp;
1159 + unsigned long flag;
1160 +
1161 + local_irq_save(flag);
1162 + tmp = lq_r32(LQ_DMA_CS);
1163 + lq_w32(chan_no, LQ_DMA_CS);
1164 + lq_w32(lq_r32(LQ_DMA_CIS) | 0x7e, LQ_DMA_CIS);
1165 + lq_w32(tmp, LQ_DMA_CS);
1166 + g_lq_dma_int_status &= ~(1 << chan_no);
1167 + local_irq_restore(flag);
1168 + pDev->current_tx_chan = pCh->rel_chan_no;
1169 + if (pDev->intr_handler)
1170 + pDev->intr_handler(pDev, TRANSMIT_CPT_INT);
1171 +}
1172 +
1173 +void do_dma_tasklet(unsigned long unused)
1174 +{
1175 + int i;
1176 + int chan_no = 0;
1177 + int budget = DMA_INT_BUDGET;
1178 + int weight = 0;
1179 + unsigned long flag;
1180 +
1181 + while (g_lq_dma_int_status) {
1182 + if (budget-- < 0) {
1183 + tasklet_schedule(&dma_tasklet);
1184 + return;
1185 + }
1186 + chan_no = -1;
1187 + weight = 0;
1188 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1189 + if ((g_lq_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) {
1190 + if (dma_chan[i].weight > weight) {
1191 + chan_no = i;
1192 + weight = dma_chan[chan_no].weight;
1193 + }
1194 + }
1195 + }
1196 +
1197 + if (chan_no >= 0) {
1198 + if (chan_map[chan_no].dir == LQ_DMA_RX)
1199 + rx_chan_intr_handler(chan_no);
1200 + else
1201 + tx_chan_intr_handler(chan_no);
1202 + } else {
1203 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1204 + dma_chan[i].weight = dma_chan[i].default_weight;
1205 + }
1206 + }
1207 +
1208 + local_irq_save(flag);
1209 + g_lq_dma_in_process = 0;
1210 + if (g_lq_dma_int_status) {
1211 + g_lq_dma_in_process = 1;
1212 + tasklet_schedule(&dma_tasklet);
1213 + }
1214 + local_irq_restore(flag);
1215 +}
1216 +
1217 +irqreturn_t dma_interrupt(int irq, void *dev_id)
1218 +{
1219 + struct dma_channel_info *pCh;
1220 + int chan_no = 0;
1221 + int tmp;
1222 +
1223 + pCh = (struct dma_channel_info *)dev_id;
1224 + chan_no = (int)(pCh - dma_chan);
1225 + if (chan_no < 0 || chan_no > 19)
1226 + BUG();
1227 +
1228 + tmp = lq_r32(LQ_DMA_IRNEN);
1229 + lq_w32(0, LQ_DMA_IRNEN);
1230 + g_lq_dma_int_status |= 1 << chan_no;
1231 + lq_w32(tmp, LQ_DMA_IRNEN);
1232 + lq_mask_and_ack_irq(irq);
1233 +
1234 + if (!g_lq_dma_in_process) {
1235 + g_lq_dma_in_process = 1;
1236 + tasklet_schedule(&dma_tasklet);
1237 + }
1238 +
1239 + return IRQ_HANDLED;
1240 +}
1241 +
1242 +struct dma_device_info *dma_device_reserve(char *dev_name)
1243 +{
1244 + int i;
1245 +
1246 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1247 + if (strcmp(dev_name, dma_devs[i].device_name) == 0) {
1248 + if (dma_devs[i].reserved)
1249 + return NULL;
1250 + dma_devs[i].reserved = 1;
1251 + break;
1252 + }
1253 + }
1254 +
1255 + return &dma_devs[i];
1256 +}
1257 +EXPORT_SYMBOL(dma_device_reserve);
1258 +
1259 +void dma_device_release(struct dma_device_info *dev)
1260 +{
1261 + dev->reserved = 0;
1262 +}
1263 +EXPORT_SYMBOL(dma_device_release);
1264 +
1265 +void dma_device_register(struct dma_device_info *dev)
1266 +{
1267 + int i, j;
1268 + int chan_no = 0;
1269 + u8 *buffer;
1270 + int byte_offset;
1271 + unsigned long flag;
1272 + struct dma_device_info *pDev;
1273 + struct dma_channel_info *pCh;
1274 + struct rx_desc *rx_desc_p;
1275 + struct tx_desc *tx_desc_p;
1276 +
1277 + for (i = 0; i < dev->max_tx_chan_num; i++) {
1278 + pCh = dev->tx_chan[i];
1279 + if (pCh->control == LQ_DMA_CH_ON) {
1280 + chan_no = (int)(pCh - dma_chan);
1281 + for (j = 0; j < pCh->desc_len; j++) {
1282 + tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1283 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1284 + }
1285 + local_irq_save(flag);
1286 + lq_w32(chan_no, LQ_DMA_CS);
1287 + /* check if the descriptor length is changed */
1288 + if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1289 + lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1290 +
1291 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1292 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1293 + while (lq_r32(LQ_DMA_CCTRL) & 2)
1294 + ;
1295 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1296 + lq_w32(0x30100, LQ_DMA_CCTRL); /* reset and enable channel,enable channel later */
1297 + local_irq_restore(flag);
1298 + }
1299 + }
1300 +
1301 + for (i = 0; i < dev->max_rx_chan_num; i++) {
1302 + pCh = dev->rx_chan[i];
1303 + if (pCh->control == LQ_DMA_CH_ON) {
1304 + chan_no = (int)(pCh - dma_chan);
1305 +
1306 + for (j = 0; j < pCh->desc_len; j++) {
1307 + rx_desc_p = (struct rx_desc *)pCh->desc_base + j;
1308 + pDev = (struct dma_device_info *)(pCh->dma_dev);
1309 + buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j]));
1310 + if (!buffer)
1311 + break;
1312 +
1313 + dma_cache_inv((unsigned long) buffer, pCh->packet_size);
1314 +
1315 + rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer);
1316 + rx_desc_p->status.word = 0;
1317 + rx_desc_p->status.field.byte_offset = byte_offset;
1318 + rx_desc_p->status.field.OWN = DMA_OWN;
1319 + rx_desc_p->status.field.data_length = pCh->packet_size;
1320 + }
1321 +
1322 + local_irq_save(flag);
1323 + lq_w32(chan_no, LQ_DMA_CS);
1324 + /* check if the descriptor length is changed */
1325 + if (lq_r32(LQ_DMA_CDLEN) != pCh->desc_len)
1326 + lq_w32(pCh->desc_len, LQ_DMA_CDLEN);
1327 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1328 + lq_w32(lq_r32(LQ_DMA_CCTRL) | 2, LQ_DMA_CCTRL);
1329 + while (lq_r32(LQ_DMA_CCTRL) & 2)
1330 + ;
1331 + lq_w32(0x0a, LQ_DMA_CIE); /* fix me, should enable all the interrupts here? */
1332 + lq_w32(lq_r32(LQ_DMA_IRNEN) | (1 << chan_no), LQ_DMA_IRNEN);
1333 + lq_w32(0x30000, LQ_DMA_CCTRL);
1334 + local_irq_restore(flag);
1335 + lq_enable_irq(dma_chan[chan_no].irq);
1336 + }
1337 + }
1338 +}
1339 +EXPORT_SYMBOL(dma_device_register);
1340 +
1341 +void dma_device_unregister(struct dma_device_info *dev)
1342 +{
1343 + int i, j;
1344 + int chan_no;
1345 + struct dma_channel_info *pCh;
1346 + struct rx_desc *rx_desc_p;
1347 + struct tx_desc *tx_desc_p;
1348 + unsigned long flag;
1349 +
1350 + for (i = 0; i < dev->max_tx_chan_num; i++) {
1351 + pCh = dev->tx_chan[i];
1352 + if (pCh->control == LQ_DMA_CH_ON) {
1353 + chan_no = (int)(dev->tx_chan[i] - dma_chan);
1354 + local_irq_save(flag);
1355 + lq_w32(chan_no, LQ_DMA_CS);
1356 + pCh->curr_desc = 0;
1357 + pCh->prev_desc = 0;
1358 + pCh->control = LQ_DMA_CH_OFF;
1359 + lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1360 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1361 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1362 + while (lq_r32(LQ_DMA_CCTRL) & 1)
1363 + ;
1364 + local_irq_restore(flag);
1365 +
1366 + for (j = 0; j < pCh->desc_len; j++) {
1367 + tx_desc_p = (struct tx_desc *)pCh->desc_base + j;
1368 + if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C)
1369 + || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) {
1370 + dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]);
1371 + }
1372 + tx_desc_p->status.field.OWN = CPU_OWN;
1373 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1374 + }
1375 + /* TODO should free buffer that is not transferred by dma */
1376 + }
1377 + }
1378 +
1379 + for (i = 0; i < dev->max_rx_chan_num; i++) {
1380 + pCh = dev->rx_chan[i];
1381 + chan_no = (int)(dev->rx_chan[i] - dma_chan);
1382 + lq_disable_irq(pCh->irq);
1383 +
1384 + local_irq_save(flag);
1385 + g_lq_dma_int_status &= ~(1 << chan_no);
1386 + pCh->curr_desc = 0;
1387 + pCh->prev_desc = 0;
1388 + pCh->control = LQ_DMA_CH_OFF;
1389 +
1390 + lq_w32(chan_no, LQ_DMA_CS);
1391 + lq_w32(0, LQ_DMA_CIE); /* fix me, should disable all the interrupts here? */
1392 + lq_w32(lq_r32(LQ_DMA_IRNEN) & ~(1 << chan_no), LQ_DMA_IRNEN); /* disable interrupts */
1393 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~1, LQ_DMA_CCTRL);
1394 + while (lq_r32(LQ_DMA_CCTRL) & 1)
1395 + ;
1396 +
1397 + local_irq_restore(flag);
1398 + for (j = 0; j < pCh->desc_len; j++) {
1399 + rx_desc_p = (struct rx_desc *) pCh->desc_base + j;
1400 + if ((rx_desc_p->status.field.OWN == CPU_OWN
1401 + && rx_desc_p->status.field.C)
1402 + || (rx_desc_p->status.field.OWN == DMA_OWN
1403 + && rx_desc_p->status.field.data_length > 0)) {
1404 + dev->buffer_free((u8 *)
1405 + __va(rx_desc_p->Data_Pointer),
1406 + (void *) pCh->opt[j]);
1407 + }
1408 + }
1409 + }
1410 +}
1411 +EXPORT_SYMBOL(dma_device_unregister);
1412 +
1413 +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt)
1414 +{
1415 + u8 *buf;
1416 + int len;
1417 + int byte_offset = 0;
1418 + void *p = NULL;
1419 + struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan];
1420 + struct rx_desc *rx_desc_p;
1421 +
1422 + /* get the rx data first */
1423 + rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc;
1424 + if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C))
1425 + return 0;
1426 +
1427 + buf = (u8 *) __va(rx_desc_p->Data_Pointer);
1428 + *(u32 *)dataptr = (u32)buf;
1429 + len = rx_desc_p->status.field.data_length;
1430 +
1431 + if (opt)
1432 + *(int *)opt = (int)pCh->opt[pCh->curr_desc];
1433 +
1434 + /* replace with a new allocated buffer */
1435 + buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p);
1436 +
1437 + if (buf) {
1438 + dma_cache_inv((unsigned long) buf, pCh->packet_size);
1439 + pCh->opt[pCh->curr_desc] = p;
1440 + wmb();
1441 +
1442 + rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf);
1443 + rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size;
1444 + wmb();
1445 + } else {
1446 + *(u32 *) dataptr = 0;
1447 + if (opt)
1448 + *(int *) opt = 0;
1449 + len = 0;
1450 + }
1451 +
1452 + /* increase the curr_desc pointer */
1453 + pCh->curr_desc++;
1454 + if (pCh->curr_desc == pCh->desc_len)
1455 + pCh->curr_desc = 0;
1456 +
1457 + return len;
1458 +}
1459 +EXPORT_SYMBOL(dma_device_read);
1460 +
1461 +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt)
1462 +{
1463 + unsigned long flag;
1464 + u32 tmp, byte_offset;
1465 + struct dma_channel_info *pCh;
1466 + int chan_no;
1467 + struct tx_desc *tx_desc_p;
1468 + local_irq_save(flag);
1469 +
1470 + pCh = dma_dev->tx_chan[dma_dev->current_tx_chan];
1471 + chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan);
1472 +
1473 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1474 + while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) {
1475 + dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]);
1476 + memset(tx_desc_p, 0, sizeof(struct tx_desc));
1477 + pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len);
1478 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc;
1479 + }
1480 + tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc;
1481 + /* Check whether this descriptor is available */
1482 + if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) {
1483 + /* if not, the tell the upper layer device */
1484 + dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1485 + local_irq_restore(flag);
1486 + printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__);
1487 +
1488 + return 0;
1489 + }
1490 + pCh->opt[pCh->curr_desc] = opt;
1491 + /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */
1492 + byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4);
1493 + dma_cache_wback((unsigned long) dataptr, len);
1494 + wmb();
1495 + tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset;
1496 + wmb();
1497 + tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len;
1498 + wmb();
1499 +
1500 + pCh->curr_desc++;
1501 + if (pCh->curr_desc == pCh->desc_len)
1502 + pCh->curr_desc = 0;
1503 +
1504 + /*Check whether this descriptor is available */
1505 + tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc;
1506 + if (tx_desc_p->status.field.OWN == DMA_OWN) {
1507 + /*if not , the tell the upper layer device */
1508 + dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT);
1509 + }
1510 +
1511 + lq_w32(chan_no, LQ_DMA_CS);
1512 + tmp = lq_r32(LQ_DMA_CCTRL);
1513 +
1514 + if (!(tmp & 1))
1515 + pCh->open(pCh);
1516 +
1517 + local_irq_restore(flag);
1518 +
1519 + return len;
1520 +}
1521 +EXPORT_SYMBOL(dma_device_write);
1522 +
1523 +int map_dma_chan(struct dma_chan_map *map)
1524 +{
1525 + int i, j;
1526 + int result;
1527 +
1528 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++)
1529 + strcpy(dma_devs[i].device_name, global_device_name[i]);
1530 +
1531 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1532 + dma_chan[i].irq = map[i].irq;
1533 + result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]);
1534 + if (result) {
1535 + printk(KERN_WARNING "error, cannot get dma_irq!\n");
1536 + free_irq(dma_chan[i].irq, (void *) &dma_interrupt);
1537 +
1538 + return -EFAULT;
1539 + }
1540 + }
1541 +
1542 + for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) {
1543 + dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */
1544 + dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */
1545 + dma_devs[i].max_rx_chan_num = 0;
1546 + dma_devs[i].max_tx_chan_num = 0;
1547 + dma_devs[i].buffer_alloc = &common_buffer_alloc;
1548 + dma_devs[i].buffer_free = &common_buffer_free;
1549 + dma_devs[i].intr_handler = NULL;
1550 + dma_devs[i].tx_burst_len = 4;
1551 + dma_devs[i].rx_burst_len = 4;
1552 + if (i == 0) {
1553 + lq_w32(0, LQ_DMA_PS);
1554 + lq_w32(lq_r32(LQ_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), LQ_DMA_PCTRL); /*enable dma drop */
1555 + }
1556 +
1557 + if (i == 1) {
1558 + lq_w32(1, LQ_DMA_PS);
1559 + lq_w32(0x14, LQ_DMA_PCTRL); /*deu port setting */
1560 + }
1561 +
1562 + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1563 + dma_chan[j].byte_offset = 0;
1564 + dma_chan[j].open = &open_chan;
1565 + dma_chan[j].close = &close_chan;
1566 + dma_chan[j].reset = &reset_chan;
1567 + dma_chan[j].enable_irq = &enable_ch_irq;
1568 + dma_chan[j].disable_irq = &disable_ch_irq;
1569 + dma_chan[j].rel_chan_no = map[j].rel_chan_no;
1570 + dma_chan[j].control = LQ_DMA_CH_OFF;
1571 + dma_chan[j].default_weight = LQ_DMA_CH_DEFAULT_WEIGHT;
1572 + dma_chan[j].weight = dma_chan[j].default_weight;
1573 + dma_chan[j].curr_desc = 0;
1574 + dma_chan[j].prev_desc = 0;
1575 + }
1576 +
1577 + for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) {
1578 + if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) {
1579 + if (map[j].dir == LQ_DMA_RX) {
1580 + dma_chan[j].dir = LQ_DMA_RX;
1581 + dma_devs[i].max_rx_chan_num++;
1582 + dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j];
1583 + dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri;
1584 + dma_chan[j].dma_dev = (void *)&dma_devs[i];
1585 + } else if (map[j].dir == LQ_DMA_TX) {
1586 + /*TX direction */
1587 + dma_chan[j].dir = LQ_DMA_TX;
1588 + dma_devs[i].max_tx_chan_num++;
1589 + dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j];
1590 + dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri;
1591 + dma_chan[j].dma_dev = (void *)&dma_devs[i];
1592 + } else {
1593 + printk(KERN_WARNING "WRONG DMA MAP!\n");
1594 + }
1595 + }
1596 + }
1597 + }
1598 +
1599 + return 0;
1600 +}
1601 +
1602 +void dma_chip_init(void)
1603 +{
1604 + int i;
1605 +
1606 + /* enable DMA from PMU */
1607 + lq_pmu_enable(PMU_DMA);
1608 +
1609 + /* reset DMA */
1610 + lq_w32(lq_r32(LQ_DMA_CTRL) | 1, LQ_DMA_CTRL);
1611 +
1612 + /* disable all interrupts */
1613 + lq_w32(0, LQ_DMA_IRNEN);
1614 +
1615 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1616 + lq_w32(i, LQ_DMA_CS);
1617 + lq_w32(0x2, LQ_DMA_CCTRL);
1618 + lq_w32(0x80000040, LQ_DMA_CPOLL);
1619 + lq_w32(lq_r32(LQ_DMA_CCTRL) & ~0x1, LQ_DMA_CCTRL);
1620 + }
1621 +}
1622 +
1623 +int lq_dma_init(void)
1624 +{
1625 + int i;
1626 +
1627 + dma_chip_init();
1628 +
1629 + if (map_dma_chan(default_dma_map))
1630 + BUG();
1631 +
1632 + g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA));
1633 +
1634 + if (g_desc_list == NULL) {
1635 + printk(KERN_WARNING "no memory for desriptor\n");
1636 + return -ENOMEM;
1637 + }
1638 +
1639 + memset(g_desc_list, 0, PAGE_SIZE);
1640 +
1641 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) {
1642 + dma_chan[i].desc_base = (u32)g_desc_list + i * LQ_DMA_DESCRIPTOR_OFFSET * 8;
1643 + dma_chan[i].curr_desc = 0;
1644 + dma_chan[i].desc_len = LQ_DMA_DESCRIPTOR_OFFSET;
1645 +
1646 + lq_w32(i, LQ_DMA_CS);
1647 + lq_w32((u32)CPHYSADDR(dma_chan[i].desc_base), LQ_DMA_CDBA);
1648 + lq_w32(dma_chan[i].desc_len, LQ_DMA_CDLEN);
1649 + }
1650 + return 0;
1651 +}
1652 +
1653 +arch_initcall(lq_dma_init);
1654 +
1655 +void dma_cleanup(void)
1656 +{
1657 + int i;
1658 +
1659 + free_page(KSEG0ADDR((unsigned long) g_desc_list));
1660 + for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++)
1661 + free_irq(dma_chan[i].irq, (void *)&dma_interrupt);
1662 +}
1663 +
1664 +MODULE_LICENSE("GPL");
1665 --- /dev/null
1666 +++ b/arch/mips/lantiq/xway/pmu.c
1667 @@ -0,0 +1,36 @@
1668 +/*
1669 + * This program is free software; you can redistribute it and/or modify it
1670 + * under the terms of the GNU General Public License version 2 as published
1671 + * by the Free Software Foundation.
1672 + *
1673 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
1674 + */
1675 +
1676 +#include <linux/kernel.h>
1677 +#include <linux/module.h>
1678 +#include <linux/version.h>
1679 +
1680 +#include <xway.h>
1681 +
1682 +#define LQ_PMU_PWDCR ((u32 *)(LQ_PMU_BASE_ADDR + 0x001C))
1683 +#define LQ_PMU_PWDSR ((u32 *)(LQ_PMU_BASE_ADDR + 0x0020))
1684 +
1685 +void
1686 +lq_pmu_enable(unsigned int module)
1687 +{
1688 + int err = 1000000;
1689 +
1690 + lq_w32(lq_r32(LQ_PMU_PWDCR) & ~module, LQ_PMU_PWDCR);
1691 + while (--err && (lq_r32(LQ_PMU_PWDSR) & module));
1692 +
1693 + if (!err)
1694 + panic("activating PMU module failed!");
1695 +}
1696 +EXPORT_SYMBOL(lq_pmu_enable);
1697 +
1698 +void
1699 +lq_pmu_disable(unsigned int module)
1700 +{
1701 + lq_w32(lq_r32(LQ_PMU_PWDCR) | module, LQ_PMU_PWDCR);
1702 +}
1703 +EXPORT_SYMBOL(lq_pmu_disable);
1704 --- /dev/null
1705 +++ b/arch/mips/lantiq/xway/timer.c
1706 @@ -0,0 +1,828 @@
1707 +#include <linux/kernel.h>
1708 +#include <linux/module.h>
1709 +#include <linux/version.h>
1710 +#include <linux/types.h>
1711 +#include <linux/fs.h>
1712 +#include <linux/miscdevice.h>
1713 +#include <linux/init.h>
1714 +#include <linux/uaccess.h>
1715 +#include <linux/unistd.h>
1716 +#include <linux/errno.h>
1717 +#include <linux/interrupt.h>
1718 +#include <linux/sched.h>
1719 +
1720 +#include <asm/irq.h>
1721 +#include <asm/div64.h>
1722 +
1723 +#include <xway.h>
1724 +#include <xway_irq.h>
1725 +#include <lantiq_timer.h>
1726 +
1727 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
1728 +
1729 +#ifdef TIMER1A
1730 +#define FIRST_TIMER TIMER1A
1731 +#else
1732 +#define FIRST_TIMER 2
1733 +#endif
1734 +
1735 +/*
1736 + * GPTC divider is set or not.
1737 + */
1738 +#define GPTU_CLC_RMC_IS_SET 0
1739 +
1740 +/*
1741 + * Timer Interrupt (IRQ)
1742 + */
1743 +/* Must be adjusted when ICU driver is available */
1744 +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
1745 +
1746 +/*
1747 + * Bits Operation
1748 + */
1749 +#define GET_BITS(x, msb, lsb) \
1750 + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
1751 +#define SET_BITS(x, msb, lsb, value) \
1752 + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
1753 + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
1754 +
1755 +/*
1756 + * GPTU Register Mapping
1757 + */
1758 +#define LQ_GPTU (KSEG1 + 0x1E100A00)
1759 +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
1760 +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
1761 +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1762 +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1763 +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1764 +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
1765 +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
1766 +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
1767 +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
1768 +
1769 +/*
1770 + * Clock Control Register
1771 + */
1772 +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
1773 +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
1774 +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
1775 +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
1776 +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
1777 +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
1778 +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
1779 +
1780 +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
1781 +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
1782 +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
1783 +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
1784 +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
1785 +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
1786 +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
1787 +
1788 +/*
1789 + * ID Register
1790 + */
1791 +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
1792 +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
1793 +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
1794 +
1795 +/*
1796 + * Control Register of Timer/Counter nX
1797 + * n is the index of block (1 based index)
1798 + * X is either A or B
1799 + */
1800 +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
1801 +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
1802 +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
1803 +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
1804 +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
1805 +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
1806 +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
1807 +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
1808 +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
1809 +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
1810 +
1811 +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
1812 +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
1813 +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
1814 +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
1815 +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
1816 +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
1817 +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
1818 +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
1819 +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
1820 +
1821 +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
1822 +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
1823 +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
1824 +
1825 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1826 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
1827 +
1828 +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
1829 +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
1830 +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
1831 +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
1832 +#define TIMER_FLAG_NONE_EDGE 0x0000
1833 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
1834 +#define TIMER_FLAG_REAL 0x0000
1835 +#define TIMER_FLAG_INVERT 0x0040
1836 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
1837 +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
1838 +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
1839 +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
1840 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
1841 +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
1842 +
1843 +struct timer_dev_timer {
1844 + unsigned int f_irq_on;
1845 + unsigned int irq;
1846 + unsigned int flag;
1847 + unsigned long arg1;
1848 + unsigned long arg2;
1849 +};
1850 +
1851 +struct timer_dev {
1852 + struct mutex gptu_mutex;
1853 + unsigned int number_of_timers;
1854 + unsigned int occupation;
1855 + unsigned int f_gptu_on;
1856 + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
1857 +};
1858 +
1859 +static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
1860 +static int gptu_open(struct inode *, struct file *);
1861 +static int gptu_release(struct inode *, struct file *);
1862 +
1863 +static struct file_operations gptu_fops = {
1864 + .owner = THIS_MODULE,
1865 + .ioctl = gptu_ioctl,
1866 + .open = gptu_open,
1867 + .release = gptu_release
1868 +};
1869 +
1870 +static struct miscdevice gptu_miscdev = {
1871 + .minor = MISC_DYNAMIC_MINOR,
1872 + .name = "gptu",
1873 + .fops = &gptu_fops,
1874 +};
1875 +
1876 +static struct timer_dev timer_dev;
1877 +
1878 +static irqreturn_t timer_irq_handler(int irq, void *p)
1879 +{
1880 + unsigned int timer;
1881 + unsigned int flag;
1882 + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
1883 +
1884 + timer = irq - TIMER_INTERRUPT;
1885 + if (timer < timer_dev.number_of_timers
1886 + && dev_timer == &timer_dev.timer[timer]) {
1887 + /* Clear interrupt. */
1888 + lq_w32(1 << timer, LQ_GPTU_IRNCR);
1889 +
1890 + /* Call user hanler or signal. */
1891 + flag = dev_timer->flag;
1892 + if (!(timer & 0x01)
1893 + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1894 + /* 16-bit timer or timer A of 32-bit timer */
1895 + switch (TIMER_FLAG_MASK_HANDLE(flag)) {
1896 + case TIMER_FLAG_CALLBACK_IN_IRQ:
1897 + case TIMER_FLAG_CALLBACK_IN_HB:
1898 + if (dev_timer->arg1)
1899 + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
1900 + break;
1901 + case TIMER_FLAG_SIGNAL:
1902 + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
1903 + break;
1904 + }
1905 + }
1906 + }
1907 + return IRQ_HANDLED;
1908 +}
1909 +
1910 +static inline void lq_enable_gptu(void)
1911 +{
1912 + lq_pmu_enable(PMU_GPT);
1913 +
1914 + /* Set divider as 1, disable write protection for SPEN, enable module. */
1915 + *LQ_GPTU_CLC =
1916 + GPTU_CLC_SMC_SET(0x00) |
1917 + GPTU_CLC_RMC_SET(0x01) |
1918 + GPTU_CLC_FSOE_SET(0) |
1919 + GPTU_CLC_SBWE_SET(1) |
1920 + GPTU_CLC_EDIS_SET(0) |
1921 + GPTU_CLC_SPEN_SET(0) |
1922 + GPTU_CLC_DISR_SET(0);
1923 +}
1924 +
1925 +static inline void lq_disable_gptu(void)
1926 +{
1927 + lq_w32(0x00, LQ_GPTU_IRNEN);
1928 + lq_w32(0xfff, LQ_GPTU_IRNCR);
1929 +
1930 + /* Set divider as 0, enable write protection for SPEN, disable module. */
1931 + *LQ_GPTU_CLC =
1932 + GPTU_CLC_SMC_SET(0x00) |
1933 + GPTU_CLC_RMC_SET(0x00) |
1934 + GPTU_CLC_FSOE_SET(0) |
1935 + GPTU_CLC_SBWE_SET(0) |
1936 + GPTU_CLC_EDIS_SET(0) |
1937 + GPTU_CLC_SPEN_SET(0) |
1938 + GPTU_CLC_DISR_SET(1);
1939 +
1940 + lq_pmu_disable(PMU_GPT);
1941 +}
1942 +
1943 +int lq_request_timer(unsigned int timer, unsigned int flag,
1944 + unsigned long value, unsigned long arg1, unsigned long arg2)
1945 +{
1946 + int ret = 0;
1947 + unsigned int con_reg, irnen_reg;
1948 + int n, X;
1949 +
1950 + if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
1951 + return -EINVAL;
1952 +
1953 + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
1954 + timer, flag, value);
1955 +
1956 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
1957 + value &= 0xFFFF;
1958 + else
1959 + timer &= ~0x01;
1960 +
1961 + mutex_lock(&timer_dev.gptu_mutex);
1962 +
1963 + /*
1964 + * Allocate timer.
1965 + */
1966 + if (timer < FIRST_TIMER) {
1967 + unsigned int mask;
1968 + unsigned int shift;
1969 + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
1970 + unsigned int offset = TIMER2A;
1971 +
1972 + /*
1973 + * Pick up a free timer.
1974 + */
1975 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
1976 + mask = 1 << offset;
1977 + shift = 1;
1978 + } else {
1979 + mask = 3 << offset;
1980 + shift = 2;
1981 + }
1982 + for (timer = offset;
1983 + timer < offset + timer_dev.number_of_timers;
1984 + timer += shift, mask <<= shift)
1985 + if (!(timer_dev.occupation & mask)) {
1986 + timer_dev.occupation |= mask;
1987 + break;
1988 + }
1989 + if (timer >= offset + timer_dev.number_of_timers) {
1990 + printk("failed![%d]\n", __LINE__);
1991 + mutex_unlock(&timer_dev.gptu_mutex);
1992 + return -EINVAL;
1993 + } else
1994 + ret = timer;
1995 + } else {
1996 + register unsigned int mask;
1997 +
1998 + /*
1999 + * Check if the requested timer is free.
2000 + */
2001 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2002 + if ((timer_dev.occupation & mask)) {
2003 + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
2004 + __LINE__, mask, timer_dev.occupation);
2005 + mutex_unlock(&timer_dev.gptu_mutex);
2006 + return -EBUSY;
2007 + } else {
2008 + timer_dev.occupation |= mask;
2009 + ret = 0;
2010 + }
2011 + }
2012 +
2013 + /*
2014 + * Prepare control register value.
2015 + */
2016 + switch (TIMER_FLAG_MASK_EDGE(flag)) {
2017 + default:
2018 + case TIMER_FLAG_NONE_EDGE:
2019 + con_reg = GPTU_CON_EDGE_SET(0x00);
2020 + break;
2021 + case TIMER_FLAG_RISE_EDGE:
2022 + con_reg = GPTU_CON_EDGE_SET(0x01);
2023 + break;
2024 + case TIMER_FLAG_FALL_EDGE:
2025 + con_reg = GPTU_CON_EDGE_SET(0x02);
2026 + break;
2027 + case TIMER_FLAG_ANY_EDGE:
2028 + con_reg = GPTU_CON_EDGE_SET(0x03);
2029 + break;
2030 + }
2031 + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
2032 + con_reg |=
2033 + TIMER_FLAG_MASK_SRC(flag) ==
2034 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
2035 + GPTU_CON_SRC_EXT_SET(0);
2036 + else
2037 + con_reg |=
2038 + TIMER_FLAG_MASK_SRC(flag) ==
2039 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
2040 + GPTU_CON_SRC_EG_SET(0);
2041 + con_reg |=
2042 + TIMER_FLAG_MASK_SYNC(flag) ==
2043 + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
2044 + GPTU_CON_SYNC_SET(1);
2045 + con_reg |=
2046 + TIMER_FLAG_MASK_INVERT(flag) ==
2047 + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2048 + con_reg |=
2049 + TIMER_FLAG_MASK_SIZE(flag) ==
2050 + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
2051 + GPTU_CON_EXT_SET(1);
2052 + con_reg |=
2053 + TIMER_FLAG_MASK_STOP(flag) ==
2054 + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2055 + con_reg |=
2056 + TIMER_FLAG_MASK_TYPE(flag) ==
2057 + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
2058 + GPTU_CON_CNT_SET(1);
2059 + con_reg |=
2060 + TIMER_FLAG_MASK_DIR(flag) ==
2061 + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2062 +
2063 + /*
2064 + * Fill up running data.
2065 + */
2066 + timer_dev.timer[timer - FIRST_TIMER].flag = flag;
2067 + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
2068 + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
2069 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2070 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
2071 +
2072 + /*
2073 + * Enable GPTU module.
2074 + */
2075 + if (!timer_dev.f_gptu_on) {
2076 + lq_enable_gptu();
2077 + timer_dev.f_gptu_on = 1;
2078 + }
2079 +
2080 + /*
2081 + * Enable IRQ.
2082 + */
2083 + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
2084 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
2085 + timer_dev.timer[timer - FIRST_TIMER].arg1 =
2086 + (unsigned long) find_task_by_vpid((int) arg1);
2087 +
2088 + irnen_reg = 1 << (timer - FIRST_TIMER);
2089 +
2090 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
2091 + || (TIMER_FLAG_MASK_HANDLE(flag) ==
2092 + TIMER_FLAG_CALLBACK_IN_IRQ
2093 + && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
2094 + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2095 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
2096 + }
2097 + } else
2098 + irnen_reg = 0;
2099 +
2100 + /*
2101 + * Write config register, reload value and enable interrupt.
2102 + */
2103 + n = timer >> 1;
2104 + X = timer & 0x01;
2105 + *LQ_GPTU_CON(n, X) = con_reg;
2106 + *LQ_GPTU_RELOAD(n, X) = value;
2107 + /* printk("reload value = %d\n", (u32)value); */
2108 + *LQ_GPTU_IRNEN |= irnen_reg;
2109 +
2110 + mutex_unlock(&timer_dev.gptu_mutex);
2111 + printk("successful!\n");
2112 + return ret;
2113 +}
2114 +EXPORT_SYMBOL(lq_request_timer);
2115 +
2116 +int lq_free_timer(unsigned int timer)
2117 +{
2118 + unsigned int flag;
2119 + unsigned int mask;
2120 + int n, X;
2121 +
2122 + if (!timer_dev.f_gptu_on)
2123 + return -EINVAL;
2124 +
2125 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2126 + return -EINVAL;
2127 +
2128 + mutex_lock(&timer_dev.gptu_mutex);
2129 +
2130 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2131 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2132 + timer &= ~0x01;
2133 +
2134 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2135 + if (((timer_dev.occupation & mask) ^ mask)) {
2136 + mutex_unlock(&timer_dev.gptu_mutex);
2137 + return -EINVAL;
2138 + }
2139 +
2140 + n = timer >> 1;
2141 + X = timer & 0x01;
2142 +
2143 + if (GPTU_CON_EN(n, X))
2144 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2145 +
2146 + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
2147 + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
2148 +
2149 + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
2150 + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
2151 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
2152 + }
2153 +
2154 + timer_dev.occupation &= ~mask;
2155 + if (!timer_dev.occupation && timer_dev.f_gptu_on) {
2156 + lq_disable_gptu();
2157 + timer_dev.f_gptu_on = 0;
2158 + }
2159 +
2160 + mutex_unlock(&timer_dev.gptu_mutex);
2161 +
2162 + return 0;
2163 +}
2164 +EXPORT_SYMBOL(lq_free_timer);
2165 +
2166 +int lq_start_timer(unsigned int timer, int is_resume)
2167 +{
2168 + unsigned int flag;
2169 + unsigned int mask;
2170 + int n, X;
2171 +
2172 + if (!timer_dev.f_gptu_on)
2173 + return -EINVAL;
2174 +
2175 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2176 + return -EINVAL;
2177 +
2178 + mutex_lock(&timer_dev.gptu_mutex);
2179 +
2180 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2181 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2182 + timer &= ~0x01;
2183 +
2184 + mask = (TIMER_FLAG_MASK_SIZE(flag) ==
2185 + TIMER_FLAG_16BIT ? 1 : 3) << timer;
2186 + if (((timer_dev.occupation & mask) ^ mask)) {
2187 + mutex_unlock(&timer_dev.gptu_mutex);
2188 + return -EINVAL;
2189 + }
2190 +
2191 + n = timer >> 1;
2192 + X = timer & 0x01;
2193 +
2194 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
2195 +
2196 + mutex_unlock(&timer_dev.gptu_mutex);
2197 +
2198 + return 0;
2199 +}
2200 +EXPORT_SYMBOL(lq_start_timer);
2201 +
2202 +int lq_stop_timer(unsigned int timer)
2203 +{
2204 + unsigned int flag;
2205 + unsigned int mask;
2206 + int n, X;
2207 +
2208 + if (!timer_dev.f_gptu_on)
2209 + return -EINVAL;
2210 +
2211 + if (timer < FIRST_TIMER
2212 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2213 + return -EINVAL;
2214 +
2215 + mutex_lock(&timer_dev.gptu_mutex);
2216 +
2217 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2218 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2219 + timer &= ~0x01;
2220 +
2221 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2222 + if (((timer_dev.occupation & mask) ^ mask)) {
2223 + mutex_unlock(&timer_dev.gptu_mutex);
2224 + return -EINVAL;
2225 + }
2226 +
2227 + n = timer >> 1;
2228 + X = timer & 0x01;
2229 +
2230 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
2231 +
2232 + mutex_unlock(&timer_dev.gptu_mutex);
2233 +
2234 + return 0;
2235 +}
2236 +EXPORT_SYMBOL(lq_stop_timer);
2237 +
2238 +int lq_reset_counter_flags(u32 timer, u32 flags)
2239 +{
2240 + unsigned int oflag;
2241 + unsigned int mask, con_reg;
2242 + int n, X;
2243 +
2244 + if (!timer_dev.f_gptu_on)
2245 + return -EINVAL;
2246 +
2247 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2248 + return -EINVAL;
2249 +
2250 + mutex_lock(&timer_dev.gptu_mutex);
2251 +
2252 + oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
2253 + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
2254 + timer &= ~0x01;
2255 +
2256 + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2257 + if (((timer_dev.occupation & mask) ^ mask)) {
2258 + mutex_unlock(&timer_dev.gptu_mutex);
2259 + return -EINVAL;
2260 + }
2261 +
2262 + switch (TIMER_FLAG_MASK_EDGE(flags)) {
2263 + default:
2264 + case TIMER_FLAG_NONE_EDGE:
2265 + con_reg = GPTU_CON_EDGE_SET(0x00);
2266 + break;
2267 + case TIMER_FLAG_RISE_EDGE:
2268 + con_reg = GPTU_CON_EDGE_SET(0x01);
2269 + break;
2270 + case TIMER_FLAG_FALL_EDGE:
2271 + con_reg = GPTU_CON_EDGE_SET(0x02);
2272 + break;
2273 + case TIMER_FLAG_ANY_EDGE:
2274 + con_reg = GPTU_CON_EDGE_SET(0x03);
2275 + break;
2276 + }
2277 + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
2278 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
2279 + else
2280 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
2281 + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
2282 + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
2283 + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
2284 + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
2285 + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
2286 + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
2287 +
2288 + timer_dev.timer[timer - FIRST_TIMER].flag = flags;
2289 + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
2290 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
2291 +
2292 + n = timer >> 1;
2293 + X = timer & 0x01;
2294 +
2295 + *LQ_GPTU_CON(n, X) = con_reg;
2296 + smp_wmb();
2297 + printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
2298 + mutex_unlock(&timer_dev.gptu_mutex);
2299 + return 0;
2300 +}
2301 +EXPORT_SYMBOL(lq_reset_counter_flags);
2302 +
2303 +int lq_get_count_value(unsigned int timer, unsigned long *value)
2304 +{
2305 + unsigned int flag;
2306 + unsigned int mask;
2307 + int n, X;
2308 +
2309 + if (!timer_dev.f_gptu_on)
2310 + return -EINVAL;
2311 +
2312 + if (timer < FIRST_TIMER
2313 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
2314 + return -EINVAL;
2315 +
2316 + mutex_lock(&timer_dev.gptu_mutex);
2317 +
2318 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
2319 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
2320 + timer &= ~0x01;
2321 +
2322 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
2323 + if (((timer_dev.occupation & mask) ^ mask)) {
2324 + mutex_unlock(&timer_dev.gptu_mutex);
2325 + return -EINVAL;
2326 + }
2327 +
2328 + n = timer >> 1;
2329 + X = timer & 0x01;
2330 +
2331 + *value = *LQ_GPTU_COUNT(n, X);
2332 +
2333 + mutex_unlock(&timer_dev.gptu_mutex);
2334 +
2335 + return 0;
2336 +}
2337 +EXPORT_SYMBOL(lq_get_count_value);
2338 +
2339 +u32 lq_cal_divider(unsigned long freq)
2340 +{
2341 + u64 module_freq, fpi = lq_get_fpi_bus_clock(2);
2342 + u32 clock_divider = 1;
2343 + module_freq = fpi * 1000;
2344 + do_div(module_freq, clock_divider * freq);
2345 + return module_freq;
2346 +}
2347 +EXPORT_SYMBOL(lq_cal_divider);
2348 +
2349 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
2350 + int is_ext_src, unsigned int handle_flag, unsigned long arg1,
2351 + unsigned long arg2)
2352 +{
2353 + unsigned long divider;
2354 + unsigned int flag;
2355 +
2356 + divider = lq_cal_divider(freq);
2357 + if (divider == 0)
2358 + return -EINVAL;
2359 + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
2360 + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
2361 + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
2362 + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
2363 + | TIMER_FLAG_MASK_HANDLE(handle_flag);
2364 +
2365 + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
2366 + timer, freq, divider);
2367 + return lq_request_timer(timer, flag, divider, arg1, arg2);
2368 +}
2369 +EXPORT_SYMBOL(lq_set_timer);
2370 +
2371 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
2372 + unsigned long arg1, unsigned long arg2)
2373 +{
2374 + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
2375 + return lq_request_timer(timer, flag, reload, arg1, arg2);
2376 +}
2377 +EXPORT_SYMBOL(lq_set_counter);
2378 +
2379 +static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
2380 + unsigned long arg)
2381 +{
2382 + int ret;
2383 + struct gptu_ioctl_param param;
2384 +
2385 + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
2386 + return -EFAULT;
2387 + copy_from_user(&param, (void *) arg, sizeof(param));
2388 +
2389 + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
2390 + || GPTU_SET_COUNTER) && param.timer < 2)
2391 + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
2392 + && !access_ok(VERIFY_WRITE, arg,
2393 + sizeof(struct gptu_ioctl_param)))
2394 + return -EFAULT;
2395 +
2396 + switch (cmd) {
2397 + case GPTU_REQUEST_TIMER:
2398 + ret = lq_request_timer(param.timer, param.flag, param.value,
2399 + (unsigned long) param.pid,
2400 + (unsigned long) param.sig);
2401 + if (ret > 0) {
2402 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2403 + timer, &ret, sizeof(&ret));
2404 + ret = 0;
2405 + }
2406 + break;
2407 + case GPTU_FREE_TIMER:
2408 + ret = lq_free_timer(param.timer);
2409 + break;
2410 + case GPTU_START_TIMER:
2411 + ret = lq_start_timer(param.timer, param.flag);
2412 + break;
2413 + case GPTU_STOP_TIMER:
2414 + ret = lq_stop_timer(param.timer);
2415 + break;
2416 + case GPTU_GET_COUNT_VALUE:
2417 + ret = lq_get_count_value(param.timer, &param.value);
2418 + if (!ret)
2419 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2420 + value, &param.value,
2421 + sizeof(param.value));
2422 + break;
2423 + case GPTU_CALCULATE_DIVIDER:
2424 + param.value = lq_cal_divider(param.value);
2425 + if (param.value == 0)
2426 + ret = -EINVAL;
2427 + else {
2428 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2429 + value, &param.value,
2430 + sizeof(param.value));
2431 + ret = 0;
2432 + }
2433 + break;
2434 + case GPTU_SET_TIMER:
2435 + ret = lq_set_timer(param.timer, param.value,
2436 + TIMER_FLAG_MASK_STOP(param.flag) !=
2437 + TIMER_FLAG_ONCE ? 1 : 0,
2438 + TIMER_FLAG_MASK_SRC(param.flag) ==
2439 + TIMER_FLAG_EXT_SRC ? 1 : 0,
2440 + TIMER_FLAG_MASK_HANDLE(param.flag) ==
2441 + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
2442 + TIMER_FLAG_NO_HANDLE,
2443 + (unsigned long) param.pid,
2444 + (unsigned long) param.sig);
2445 + if (ret > 0) {
2446 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2447 + timer, &ret, sizeof(&ret));
2448 + ret = 0;
2449 + }
2450 + break;
2451 + case GPTU_SET_COUNTER:
2452 + lq_set_counter(param.timer, param.flag, param.value, 0, 0);
2453 + if (ret > 0) {
2454 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
2455 + timer, &ret, sizeof(&ret));
2456 + ret = 0;
2457 + }
2458 + break;
2459 + default:
2460 + ret = -ENOTTY;
2461 + }
2462 +
2463 + return ret;
2464 +}
2465 +
2466 +static int gptu_open(struct inode *inode, struct file *file)
2467 +{
2468 + return 0;
2469 +}
2470 +
2471 +static int gptu_release(struct inode *inode, struct file *file)
2472 +{
2473 + return 0;
2474 +}
2475 +
2476 +int __init lq_gptu_init(void)
2477 +{
2478 + int ret;
2479 + unsigned int i;
2480 +
2481 + lq_w32(0, LQ_GPTU_IRNEN);
2482 + lq_w32(0xfff, LQ_GPTU_IRNCR);
2483 +
2484 + memset(&timer_dev, 0, sizeof(timer_dev));
2485 + mutex_init(&timer_dev.gptu_mutex);
2486 +
2487 + lq_enable_gptu();
2488 + timer_dev.number_of_timers = GPTU_ID_CFG * 2;
2489 + lq_disable_gptu();
2490 + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
2491 + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
2492 + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
2493 +
2494 + ret = misc_register(&gptu_miscdev);
2495 + if (ret) {
2496 + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
2497 + return ret;
2498 + } else {
2499 + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
2500 + }
2501 +
2502 + for (i = 0; i < timer_dev.number_of_timers; i++) {
2503 + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
2504 + if (ret) {
2505 + for (; i >= 0; i--)
2506 + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
2507 + misc_deregister(&gptu_miscdev);
2508 + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
2509 + return ret;
2510 + } else {
2511 + timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
2512 + disable_irq(timer_dev.timer[i].irq);
2513 + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
2514 + }
2515 + }
2516 +
2517 + return 0;
2518 +}
2519 +
2520 +void __exit lq_gptu_exit(void)
2521 +{
2522 + unsigned int i;
2523 +
2524 + for (i = 0; i < timer_dev.number_of_timers; i++) {
2525 + if (timer_dev.timer[i].f_irq_on)
2526 + disable_irq(timer_dev.timer[i].irq);
2527 + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
2528 + }
2529 + lq_disable_gptu();
2530 + misc_deregister(&gptu_miscdev);
2531 +}
2532 +
2533 +module_init(lq_gptu_init);
2534 +module_exit(lq_gptu_exit);
2535 --- /dev/null
2536 +++ b/arch/mips/lantiq/xway/timer.h
2537 @@ -0,0 +1,155 @@
2538 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2539 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
2540 +
2541 +
2542 +/******************************************************************************
2543 + Copyright (c) 2002, Infineon Technologies. All rights reserved.
2544 +
2545 + No Warranty
2546 + Because the program is licensed free of charge, there is no warranty for
2547 + the program, to the extent permitted by applicable law. Except when
2548 + otherwise stated in writing the copyright holders and/or other parties
2549 + provide the program "as is" without warranty of any kind, either
2550 + expressed or implied, including, but not limited to, the implied
2551 + warranties of merchantability and fitness for a particular purpose. The
2552 + entire risk as to the quality and performance of the program is with
2553 + you. should the program prove defective, you assume the cost of all
2554 + necessary servicing, repair or correction.
2555 +
2556 + In no event unless required by applicable law or agreed to in writing
2557 + will any copyright holder, or any other party who may modify and/or
2558 + redistribute the program as permitted above, be liable to you for
2559 + damages, including any general, special, incidental or consequential
2560 + damages arising out of the use or inability to use the program
2561 + (including but not limited to loss of data or data being rendered
2562 + inaccurate or losses sustained by you or third parties or a failure of
2563 + the program to operate with any other programs), even if such holder or
2564 + other party has been advised of the possibility of such damages.
2565 +******************************************************************************/
2566 +
2567 +
2568 +/*
2569 + * ####################################
2570 + * Definition
2571 + * ####################################
2572 + */
2573 +
2574 +/*
2575 + * Available Timer/Counter Index
2576 + */
2577 +#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
2578 +#define TIMER_ANY 0x00
2579 +#define TIMER1A TIMER(1, 0)
2580 +#define TIMER1B TIMER(1, 1)
2581 +#define TIMER2A TIMER(2, 0)
2582 +#define TIMER2B TIMER(2, 1)
2583 +#define TIMER3A TIMER(3, 0)
2584 +#define TIMER3B TIMER(3, 1)
2585 +
2586 +/*
2587 + * Flag of Timer/Counter
2588 + * These flags specify the way in which timer is configured.
2589 + */
2590 +/* Bit size of timer/counter. */
2591 +#define TIMER_FLAG_16BIT 0x0000
2592 +#define TIMER_FLAG_32BIT 0x0001
2593 +/* Switch between timer and counter. */
2594 +#define TIMER_FLAG_TIMER 0x0000
2595 +#define TIMER_FLAG_COUNTER 0x0002
2596 +/* Stop or continue when overflowing/underflowing. */
2597 +#define TIMER_FLAG_ONCE 0x0000
2598 +#define TIMER_FLAG_CYCLIC 0x0004
2599 +/* Count up or counter down. */
2600 +#define TIMER_FLAG_UP 0x0000
2601 +#define TIMER_FLAG_DOWN 0x0008
2602 +/* Count on specific level or edge. */
2603 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
2604 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
2605 +#define TIMER_FLAG_RISE_EDGE 0x0010
2606 +#define TIMER_FLAG_FALL_EDGE 0x0020
2607 +#define TIMER_FLAG_ANY_EDGE 0x0030
2608 +/* Signal is syncronous to module clock or not. */
2609 +#define TIMER_FLAG_UNSYNC 0x0000
2610 +#define TIMER_FLAG_SYNC 0x0080
2611 +/* Different interrupt handle type. */
2612 +#define TIMER_FLAG_NO_HANDLE 0x0000
2613 +#if defined(__KERNEL__)
2614 + #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
2615 +#endif // defined(__KERNEL__)
2616 +#define TIMER_FLAG_SIGNAL 0x0300
2617 +/* Internal clock source or external clock source */
2618 +#define TIMER_FLAG_INT_SRC 0x0000
2619 +#define TIMER_FLAG_EXT_SRC 0x1000
2620 +
2621 +
2622 +/*
2623 + * ioctl Command
2624 + */
2625 +#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
2626 +#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
2627 +#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
2628 +#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
2629 +#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
2630 +#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
2631 +#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
2632 +#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
2633 +
2634 +/*
2635 + * Data Type Used to Call ioctl
2636 + */
2637 +struct gptu_ioctl_param {
2638 + unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
2639 + * GPTU_SET_COUNTER, this field is ID of expected *
2640 + * timer/counter. If it's zero, a timer/counter would *
2641 + * be dynamically allocated and ID would be stored in *
2642 + * this field. *
2643 + * In command GPTU_GET_COUNT_VALUE, this field is *
2644 + * ignored. *
2645 + * In other command, this field is ID of timer/counter *
2646 + * allocated. */
2647 + unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
2648 + * GPTU_SET_COUNTER, this field contains flags to *
2649 + * specify how to configure timer/counter. *
2650 + * In command GPTU_START_TIMER, zero indicate start *
2651 + * and non-zero indicate resume timer/counter. *
2652 + * In other command, this field is ignored. */
2653 + unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
2654 + * init/reload value. *
2655 + * In command GPTU_SET_TIMER, this field contains *
2656 + * frequency (0.001Hz) of timer. *
2657 + * In command GPTU_GET_COUNT_VALUE, current count *
2658 + * value would be stored in this field. *
2659 + * In command GPTU_CALCULATE_DIVIDER, this field *
2660 + * contains frequency wanted, and after calculation, *
2661 + * divider would be stored in this field to overwrite *
2662 + * the frequency. *
2663 + * In other command, this field is ignored. */
2664 + int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
2665 + * if signal is required, this field contains process *
2666 + * ID to which signal would be sent. *
2667 + * In other command, this field is ignored. */
2668 + int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
2669 + * if signal is required, this field contains signal *
2670 + * number which would be sent. *
2671 + * In other command, this field is ignored. */
2672 +};
2673 +
2674 +/*
2675 + * ####################################
2676 + * Data Type
2677 + * ####################################
2678 + */
2679 +typedef void (*timer_callback)(unsigned long arg);
2680 +
2681 +extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
2682 +extern int ifxmips_free_timer(unsigned int);
2683 +extern int ifxmips_start_timer(unsigned int, int);
2684 +extern int ifxmips_stop_timer(unsigned int);
2685 +extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
2686 +extern int ifxmips_get_count_value(unsigned int, unsigned long *);
2687 +extern u32 ifxmips_cal_divider(unsigned long);
2688 +extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
2689 +extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
2690 + u32 reload, unsigned long arg1, unsigned long arg2);
2691 +
2692 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
2693 --- /dev/null
2694 +++ b/arch/mips/lantiq/xway/Makefile
2695 @@ -0,0 +1,5 @@
2696 +obj-y := pmu.o prom.o dma.o timer.o reset.o clk-xway.o
2697 +obj-y += gpio.o gpio_ebu.o gpio_leds.o devices.o
2698 +obj-$(CONFIG_LANTIQ_MACH_EASY50812) += mach-easy50812.o
2699 +obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
2700 +obj-$(CONFIG_LANTIQ_MACH_EASY4010) += mach-easy4010.o
2701 --- /dev/null
2702 +++ b/arch/mips/lantiq/xway/clk-xway.c
2703 @@ -0,0 +1,219 @@
2704 +/*
2705 + * This program is free software; you can redistribute it and/or modify it
2706 + * under the terms of the GNU General Public License version 2 as published
2707 + * by the Free Software Foundation.
2708 + *
2709 + * Copyright (C) 2007 Xu Liang, infineon
2710 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2711 + */
2712 +
2713 +#include <linux/io.h>
2714 +#include <linux/module.h>
2715 +#include <linux/init.h>
2716 +#include <linux/clk.h>
2717 +
2718 +#include <asm/time.h>
2719 +#include <asm/irq.h>
2720 +#include <asm/div64.h>
2721 +
2722 +#include <xway.h>
2723 +
2724 +static unsigned int lq_ram_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
2725 +#define DDR_HZ lq_ram_clocks[lq_r32(LQ_CGU_SYS) & 0x3]
2726 +
2727 +#define BASIC_FREQUENCY_1 35328000
2728 +#define BASIC_FREQUENCY_2 36000000
2729 +#define BASIS_REQUENCY_USB 12000000
2730 +
2731 +#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
2732 +
2733 +#define CGU_PLL0_PHASE_DIVIDER_ENABLE (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 31))
2734 +#define CGU_PLL0_BYPASS (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 30))
2735 +#define CGU_PLL0_CFG_DSMSEL (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 28))
2736 +#define CGU_PLL0_CFG_FRAC_EN (lq_r32(LQ_CGU_PLL0_CFG) & (1 << 27))
2737 +#define CGU_PLL1_SRC (lq_r32(LQ_CGU_PLL1_CFG) & (1 << 31))
2738 +#define CGU_PLL2_PHASE_DIVIDER_ENABLE (lq_r32(LQ_CGU_PLL2_CFG) & (1 << 20))
2739 +#define CGU_SYS_FPI_SEL (1 << 6)
2740 +#define CGU_SYS_DDR_SEL 0x3
2741 +#define CGU_PLL0_SRC (1 << 29)
2742 +
2743 +#define CGU_PLL0_CFG_PLLK GET_BITS(*LQ_CGU_PLL0_CFG, 26, 17)
2744 +#define CGU_PLL0_CFG_PLLN GET_BITS(*LQ_CGU_PLL0_CFG, 12, 6)
2745 +#define CGU_PLL0_CFG_PLLM GET_BITS(*LQ_CGU_PLL0_CFG, 5, 2)
2746 +#define CGU_PLL2_SRC GET_BITS(*LQ_CGU_PLL2_CFG, 18, 17)
2747 +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*LQ_CGU_PLL2_CFG, 16, 13)
2748 +
2749 +#define LQ_GPTU_GPT_CLC ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
2750 +#define LQ_CGU_PLL0_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x0004))
2751 +#define LQ_CGU_PLL1_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x0008))
2752 +#define LQ_CGU_PLL2_CFG ((u32 *)(LQ_CGU_BASE_ADDR + 0x000C))
2753 +#define LQ_CGU_SYS ((u32 *)(LQ_CGU_BASE_ADDR + 0x0010))
2754 +#define LQ_CGU_UPDATE ((u32 *)(LQ_CGU_BASE_ADDR + 0x0014))
2755 +#define LQ_CGU_IF_CLK ((u32 *)(LQ_CGU_BASE_ADDR + 0x0018))
2756 +#define LQ_CGU_OSC_CON ((u32 *)(LQ_CGU_BASE_ADDR + 0x001C))
2757 +#define LQ_CGU_SMD ((u32 *)(LQ_CGU_BASE_ADDR + 0x0020))
2758 +#define LQ_CGU_CT1SR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0028))
2759 +#define LQ_CGU_CT2SR ((u32 *)(LQ_CGU_BASE_ADDR + 0x002C))
2760 +#define LQ_CGU_PCMCR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0030))
2761 +#define LQ_CGU_PCI_CR ((u32 *)(LQ_CGU_BASE_ADDR + 0x0034))
2762 +#define LQ_CGU_PD_PC ((u32 *)(LQ_CGU_BASE_ADDR + 0x0038))
2763 +#define LQ_CGU_FMR ((u32 *)(LQ_CGU_BASE_ADDR + 0x003C))
2764 +
2765 +static unsigned int lq_get_pll0_fdiv(void);
2766 +
2767 +static inline unsigned int
2768 +get_input_clock(int pll)
2769 +{
2770 + switch (pll) {
2771 + case 0:
2772 + if (lq_r32(LQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
2773 + return BASIS_REQUENCY_USB;
2774 + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2775 + return BASIC_FREQUENCY_1;
2776 + else
2777 + return BASIC_FREQUENCY_2;
2778 + case 1:
2779 + if (CGU_PLL1_SRC)
2780 + return BASIS_REQUENCY_USB;
2781 + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
2782 + return BASIC_FREQUENCY_1;
2783 + else
2784 + return BASIC_FREQUENCY_2;
2785 + case 2:
2786 + switch (CGU_PLL2_SRC) {
2787 + case 0:
2788 + return lq_get_pll0_fdiv();
2789 + case 1:
2790 + return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
2791 + BASIC_FREQUENCY_1 :
2792 + BASIC_FREQUENCY_2;
2793 + case 2:
2794 + return BASIS_REQUENCY_USB;
2795 + }
2796 + default:
2797 + return 0;
2798 + }
2799 +}
2800 +
2801 +static inline unsigned int
2802 +cal_dsm(int pll, unsigned int num, unsigned int den)
2803 +{
2804 + u64 res, clock = get_input_clock(pll);
2805 + res = num * clock;
2806 + do_div(res, den);
2807 + return res;
2808 +}
2809 +
2810 +static inline unsigned int
2811 +mash_dsm(int pll, unsigned int M, unsigned int N, unsigned int K)
2812 +{
2813 + unsigned int num = ((N + 1) << 10) + K;
2814 + unsigned int den = (M + 1) << 10;
2815 + return cal_dsm(pll, num, den);
2816 +}
2817 +
2818 +static inline unsigned int
2819 +ssff_dsm_1(int pll, unsigned int M, unsigned int N, unsigned int K)
2820 +{
2821 + unsigned int num = ((N + 1) << 11) + K + 512;
2822 + unsigned int den = (M + 1) << 11;
2823 + return cal_dsm(pll, num, den);
2824 +}
2825 +
2826 +static inline unsigned int
2827 +ssff_dsm_2(int pll, unsigned int M, unsigned int N, unsigned int K)
2828 +{
2829 + unsigned int num = K >= 512 ?
2830 + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
2831 + unsigned int den = (M + 1) << 12;
2832 + return cal_dsm(pll, num, den);
2833 +}
2834 +
2835 +static inline unsigned int
2836 +dsm(int pll, unsigned int M, unsigned int N, unsigned int K,
2837 + unsigned int dsmsel, unsigned int phase_div_en)
2838 +{
2839 + if (!dsmsel)
2840 + return mash_dsm(pll, M, N, K);
2841 + else if (!phase_div_en)
2842 + return mash_dsm(pll, M, N, K);
2843 + else
2844 + return ssff_dsm_2(pll, M, N, K);
2845 +}
2846 +
2847 +static inline unsigned int
2848 +lq_get_pll0_fosc(void)
2849 +{
2850 + if (CGU_PLL0_BYPASS)
2851 + return get_input_clock(0);
2852 + else
2853 + return !CGU_PLL0_CFG_FRAC_EN
2854 + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
2855 + CGU_PLL0_PHASE_DIVIDER_ENABLE)
2856 + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
2857 + CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
2858 +}
2859 +
2860 +static unsigned int
2861 +lq_get_pll0_fdiv(void)
2862 +{
2863 + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
2864 + return (lq_get_pll0_fosc() + (div >> 1)) / div;
2865 +}
2866 +
2867 +unsigned int
2868 +lq_get_io_region_clock(void)
2869 +{
2870 + unsigned int ret = lq_get_pll0_fosc();
2871 + switch (lq_r32(LQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
2872 + default:
2873 + case 0:
2874 + return (ret + 1) / 2;
2875 + case 1:
2876 + return (ret * 2 + 2) / 5;
2877 + case 2:
2878 + return (ret + 1) / 3;
2879 + case 3:
2880 + return (ret + 2) / 4;
2881 + }
2882 +}
2883 +EXPORT_SYMBOL(lq_get_io_region_clock);
2884 +
2885 +unsigned int
2886 +lq_get_fpi_bus_clock(int fpi)
2887 +{
2888 + unsigned int ret = lq_get_io_region_clock();
2889 + if ((fpi == 2) && (lq_r32(LQ_CGU_SYS) & CGU_SYS_FPI_SEL))
2890 + ret >>= 1;
2891 + return ret;
2892 +}
2893 +EXPORT_SYMBOL(lq_get_fpi_bus_clock);
2894 +
2895 +unsigned int
2896 +lq_get_cpu_hz(void)
2897 +{
2898 + switch (lq_r32(LQ_CGU_SYS) & 0xc)
2899 + {
2900 + case 0:
2901 + return CLOCK_333M;
2902 + case 4:
2903 + return DDR_HZ;
2904 + case 8:
2905 + return DDR_HZ << 1;
2906 + default:
2907 + return DDR_HZ >> 1;
2908 + }
2909 +}
2910 +EXPORT_SYMBOL(lq_get_cpu_hz);
2911 +
2912 +unsigned int
2913 +lq_get_fpi_hz(void)
2914 +{
2915 + unsigned int ddr_clock = DDR_HZ;
2916 + if (lq_r32(LQ_CGU_SYS) & 0x40)
2917 + return ddr_clock >> 1;
2918 + return ddr_clock;
2919 +}
2920 +EXPORT_SYMBOL(lq_get_fpi_hz);
2921 +
2922 +
2923 --- /dev/null
2924 +++ b/arch/mips/lantiq/xway/gpio.c
2925 @@ -0,0 +1,206 @@
2926 +/*
2927 + * This program is free software; you can redistribute it and/or modify it
2928 + * under the terms of the GNU General Public License version 2 as published
2929 + * by the Free Software Foundation.
2930 + *
2931 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
2932 + */
2933 +
2934 +#include <linux/slab.h>
2935 +#include <linux/module.h>
2936 +#include <linux/platform_device.h>
2937 +#include <linux/gpio.h>
2938 +
2939 +#include <lantiq.h>
2940 +
2941 +#define LQ_GPIO0_BASE_ADDR 0x1E100B10
2942 +#define LQ_GPIO1_BASE_ADDR 0x1E100B40
2943 +#define LQ_GPIO_SIZE 0x30
2944 +
2945 +#define LQ_GPIO_OUT 0x00
2946 +#define LQ_GPIO_IN 0x04
2947 +#define LQ_GPIO_DIR 0x08
2948 +#define LQ_GPIO_ALTSEL0 0x0C
2949 +#define LQ_GPIO_ALTSEL1 0x10
2950 +#define LQ_GPIO_OD 0x14
2951 +
2952 +#define PINS_PER_PORT 16
2953 +
2954 +#define lq_gpio_getbit(m, r, p) !!(lq_r32(m + r) & (1 << p))
2955 +#define lq_gpio_setbit(m, r, p) lq_w32_mask(0, (1 << p), m + r)
2956 +#define lq_gpio_clearbit(m, r, p) lq_w32_mask((1 << p), 0, m + r)
2957 +
2958 +struct lq_gpio
2959 +{
2960 + void __iomem *membase;
2961 + struct gpio_chip chip;
2962 +};
2963 +
2964 +int
2965 +gpio_to_irq(unsigned int gpio)
2966 +{
2967 + return -EINVAL;
2968 +}
2969 +EXPORT_SYMBOL(gpio_to_irq);
2970 +
2971 +int
2972 +lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val)
2973 +{
2974 + void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
2975 + if(pin >= (2 * PINS_PER_PORT))
2976 + return -EINVAL;
2977 + if(pin >= PINS_PER_PORT)
2978 + {
2979 + pin -= PINS_PER_PORT;
2980 + membase += LQ_GPIO_SIZE;
2981 + }
2982 + if(val)
2983 + lq_w32_mask(0, (1 << pin), membase + reg);
2984 + else
2985 + lq_w32_mask((1 << pin), 0, membase + reg);
2986 + return 0;
2987 +}
2988 +EXPORT_SYMBOL(lq_gpio_setconfig);
2989 +
2990 +int
2991 +lq_gpio_request(unsigned int pin, unsigned int alt0,
2992 + unsigned int alt1, unsigned int dir, const char *name)
2993 +{
2994 + void __iomem *membase = (void*)KSEG1ADDR(LQ_GPIO0_BASE_ADDR);
2995 + if(pin >= (2 * PINS_PER_PORT))
2996 + return -EINVAL;
2997 + if(gpio_request(pin, name))
2998 + {
2999 + printk("failed to register %s gpio\n", name);
3000 + return -EBUSY;
3001 + }
3002 + if(dir)
3003 + gpio_direction_output(pin, 1);
3004 + else
3005 + gpio_direction_input(pin);
3006 + if(pin >= PINS_PER_PORT)
3007 + {
3008 + pin -= PINS_PER_PORT;
3009 + membase += LQ_GPIO_SIZE;
3010 + }
3011 + if(alt0)
3012 + lq_gpio_setbit(membase, LQ_GPIO_ALTSEL0, pin);
3013 + else
3014 + lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL0, pin);
3015 + if(alt1)
3016 + lq_gpio_setbit(membase, LQ_GPIO_ALTSEL1, pin);
3017 + else
3018 + lq_gpio_clearbit(membase, LQ_GPIO_ALTSEL1, pin);
3019 + return 0;
3020 +}
3021 +EXPORT_SYMBOL(lq_gpio_request);
3022 +
3023 +static void
3024 +lq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
3025 +{
3026 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3027 + if(value)
3028 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
3029 + else
3030 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OUT, offset);
3031 +}
3032 +
3033 +static int
3034 +lq_gpio_get(struct gpio_chip *chip, unsigned int offset)
3035 +{
3036 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3037 + return lq_gpio_getbit(lq_gpio->membase, LQ_GPIO_IN, offset);
3038 +}
3039 +
3040 +static int
3041 +lq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
3042 +{
3043 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3044 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_OD, offset);
3045 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
3046 + return 0;
3047 +}
3048 +
3049 +static int
3050 +lq_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
3051 +{
3052 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3053 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_OD, offset);
3054 + lq_gpio_setbit(lq_gpio->membase, LQ_GPIO_DIR, offset);
3055 + lq_gpio_set(chip, offset, value);
3056 + return 0;
3057 +}
3058 +
3059 +static int
3060 +lq_gpio_req(struct gpio_chip *chip, unsigned offset)
3061 +{
3062 + struct lq_gpio *lq_gpio = container_of(chip, struct lq_gpio, chip);
3063 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL0, offset);
3064 + lq_gpio_clearbit(lq_gpio->membase, LQ_GPIO_ALTSEL1, offset);
3065 + return 0;
3066 +}
3067 +
3068 +static int
3069 +lq_gpio_probe(struct platform_device *pdev)
3070 +{
3071 + struct lq_gpio *lq_gpio = kzalloc(sizeof(struct lq_gpio), GFP_KERNEL);
3072 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3073 + int ret = 0;
3074 + if(!res)
3075 + {
3076 + ret = -ENOENT;
3077 + goto err_free;
3078 + }
3079 + res = request_mem_region(res->start, resource_size(res),
3080 + dev_name(&pdev->dev));
3081 + if(!res)
3082 + {
3083 + ret = -EBUSY;
3084 + goto err_free;
3085 + }
3086 + lq_gpio->membase = ioremap_nocache(res->start, resource_size(res));
3087 + if(!lq_gpio->membase)
3088 + {
3089 + ret = -ENOMEM;
3090 + goto err_release_mem_region;
3091 + }
3092 + lq_gpio->chip.label = "lq_gpio";
3093 + lq_gpio->chip.direction_input = lq_gpio_direction_input;
3094 + lq_gpio->chip.direction_output = lq_gpio_direction_output;
3095 + lq_gpio->chip.get = lq_gpio_get;
3096 + lq_gpio->chip.set = lq_gpio_set;
3097 + lq_gpio->chip.request = lq_gpio_req;
3098 + lq_gpio->chip.base = PINS_PER_PORT * pdev->id;
3099 + lq_gpio->chip.ngpio = PINS_PER_PORT;
3100 + platform_set_drvdata(pdev, lq_gpio);
3101 + ret = gpiochip_add(&lq_gpio->chip);
3102 + if(!ret)
3103 + return 0;
3104 +
3105 + iounmap(lq_gpio->membase);
3106 +err_release_mem_region:
3107 + release_mem_region(res->start, resource_size(res));
3108 +err_free:
3109 + kfree(lq_gpio);
3110 + return ret;
3111 +}
3112 +
3113 +static struct platform_driver
3114 +lq_gpio_driver = {
3115 + .probe = lq_gpio_probe,
3116 + .driver = {
3117 + .name = "lq_gpio",
3118 + .owner = THIS_MODULE,
3119 + },
3120 +};
3121 +
3122 +int __init
3123 +lq_gpio_init(void)
3124 +{
3125 + int ret = platform_driver_register(&lq_gpio_driver);
3126 + if(ret)
3127 + printk(KERN_INFO "lq_gpio : Error registering platfom driver!");
3128 + return ret;
3129 +}
3130 +
3131 +postcore_initcall(lq_gpio_init);
3132 --- /dev/null
3133 +++ b/arch/mips/lantiq/xway/reset.c
3134 @@ -0,0 +1,53 @@
3135 +/*
3136 + * This program is free software; you can redistribute it and/or modify it
3137 + * under the terms of the GNU General Public License version 2 as published
3138 + * by the Free Software Foundation.
3139 + *
3140 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
3141 + */
3142 +
3143 +#include <linux/init.h>
3144 +#include <linux/io.h>
3145 +#include <linux/pm.h>
3146 +#include <asm/reboot.h>
3147 +
3148 +#include <xway.h>
3149 +
3150 +#define LQ_RCU_RST ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
3151 +#define LQ_RCU_RST_ALL 0x40000000
3152 +
3153 +static void
3154 +lq_machine_restart(char *command)
3155 +{
3156 + printk(KERN_NOTICE "System restart\n");
3157 + local_irq_disable();
3158 + lq_w32(lq_r32(LQ_RCU_RST) | LQ_RCU_RST_ALL, LQ_RCU_RST);
3159 + for(;;);
3160 +}
3161 +
3162 +static void
3163 +lq_machine_halt(void)
3164 +{
3165 + printk(KERN_NOTICE "System halted.\n");
3166 + local_irq_disable();
3167 + for(;;);
3168 +}
3169 +
3170 +static void
3171 +lq_machine_power_off(void)
3172 +{
3173 + printk(KERN_NOTICE "Please turn off the power now.\n");
3174 + local_irq_disable();
3175 + for(;;);
3176 +}
3177 +
3178 +static int __init
3179 +mips_reboot_setup(void)
3180 +{
3181 + _machine_restart = lq_machine_restart;
3182 + _machine_halt = lq_machine_halt;
3183 + pm_power_off = lq_machine_power_off;
3184 + return 0;
3185 +}
3186 +
3187 +arch_initcall(mips_reboot_setup);
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