target/linux/generic-2.4/files/crypto/ocf/kirkwood/cesa/mvCesaRegs.h

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  64
  65 #ifndef __mvCesaRegs_h__
  66 #define __mvCesaRegs_h__
  67
  68 #include "mvTypes.h"
  69
  70 typedef struct
  71 {
  72     /* word 0 */
  73     MV_U32  config;
  74     /* word 1 */
  75     MV_U16  cryptoSrcOffset;
  76     MV_U16  cryptoDstOffset;
  77     /* word 2 */
  78     MV_U16  cryptoDataLen;
  79     MV_U16  reserved1;
  80     /* word 3 */
  81     MV_U16  cryptoKeyOffset;
  82     MV_U16  reserved2;
  83     /* word 4 */
  84     MV_U16  cryptoIvOffset;
  85     MV_U16  cryptoIvBufOffset;
  86     /* word 5 */
  87     MV_U16  macSrcOffset;
  88     MV_U16  macTotalLen;
  89     /* word 6 */
  90     MV_U16  macDigestOffset;
  91     MV_U16  macDataLen;
  92     /* word 7 */
  93     MV_U16  macInnerIvOffset;
  94     MV_U16  macOuterIvOffset;
  95
  96 } MV_CESA_DESC;
  97
  98 /* operation */
  99 typedef enum
 100 {
 101     MV_CESA_MAC_ONLY         = 0,
 102     MV_CESA_CRYPTO_ONLY      = 1,
 103     MV_CESA_MAC_THEN_CRYPTO  = 2,
 104     MV_CESA_CRYPTO_THEN_MAC  = 3,
 105
 106     MV_CESA_MAX_OPERATION
 107
 108 } MV_CESA_OPERATION;
 109
 110 #define MV_CESA_OPERATION_OFFSET        0
 111 #define MV_CESA_OPERATION_MASK          (0x3 << MV_CESA_OPERATION_OFFSET)
 112
 113 /* mac algorithm */
 114 typedef enum
 115 {
 116     MV_CESA_MAC_NULL        = 0,
 117     MV_CESA_MAC_MD5         = 4,
 118     MV_CESA_MAC_SHA1        = 5,
 119     MV_CESA_MAC_HMAC_MD5    = 6,
 120     MV_CESA_MAC_HMAC_SHA1   = 7,
 121
 122 } MV_CESA_MAC_MODE;
 123
 124 #define MV_CESA_MAC_MODE_OFFSET         4
 125 #define MV_CESA_MAC_MODE_MASK           (0x7 << MV_CESA_MAC_MODE_OFFSET)
 126
 127 typedef enum
 128 {
 129     MV_CESA_MAC_DIGEST_FULL = 0,
 130     MV_CESA_MAC_DIGEST_96B  = 1,
 131
 132 } MV_CESA_MAC_DIGEST_SIZE;
 133
 134 #define MV_CESA_MAC_DIGEST_SIZE_BIT     7
 135 #define MV_CESA_MAC_DIGEST_SIZE_MASK    (1 << MV_CESA_MAC_DIGEST_SIZE_BIT)
 136
 137
 138 typedef enum
 139 {
 140     MV_CESA_CRYPTO_NULL = 0,
 141     MV_CESA_CRYPTO_DES  = 1,
 142     MV_CESA_CRYPTO_3DES = 2,
 143     MV_CESA_CRYPTO_AES  = 3,
 144
 145 } MV_CESA_CRYPTO_ALG;
 146
 147 #define MV_CESA_CRYPTO_ALG_OFFSET       8
 148 #define MV_CESA_CRYPTO_ALG_MASK         (0x3 << MV_CESA_CRYPTO_ALG_OFFSET)
 149
 150
 151 /* direction */
 152 typedef enum
 153 {
 154     MV_CESA_DIR_ENCODE = 0,
 155     MV_CESA_DIR_DECODE = 1,
 156
 157 } MV_CESA_DIRECTION;
 158
 159 #define MV_CESA_DIRECTION_BIT           12
 160 #define MV_CESA_DIRECTION_MASK          (1 << MV_CESA_DIRECTION_BIT)
 161
 162 /* crypto IV mode */
 163 typedef enum
 164 {
 165     MV_CESA_CRYPTO_ECB = 0,
 166     MV_CESA_CRYPTO_CBC = 1,
 167
 168     /* NO HW Support */
 169     MV_CESA_CRYPTO_CTR = 10,
 170
 171 } MV_CESA_CRYPTO_MODE;
 172
 173 #define MV_CESA_CRYPTO_MODE_BIT         16
 174 #define MV_CESA_CRYPTO_MODE_MASK        (1 << MV_CESA_CRYPTO_MODE_BIT)
 175
 176 /* 3DES mode */
 177 typedef enum
 178 {
 179     MV_CESA_CRYPTO_3DES_EEE = 0,
 180     MV_CESA_CRYPTO_3DES_EDE = 1,
 181
 182 } MV_CESA_CRYPTO_3DES_MODE;
 183
 184 #define MV_CESA_CRYPTO_3DES_MODE_BIT    20
 185 #define MV_CESA_CRYPTO_3DES_MODE_MASK   (1 << MV_CESA_CRYPTO_3DES_MODE_BIT)
 186
 187
 188 /* AES Key Length */
 189 typedef enum
 190 {
 191     MV_CESA_CRYPTO_AES_KEY_128 = 0,
 192     MV_CESA_CRYPTO_AES_KEY_192 = 1,
 193     MV_CESA_CRYPTO_AES_KEY_256 = 2,
 194
 195 } MV_CESA_CRYPTO_AES_KEY_LEN;
 196
 197 #define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET   24
 198 #define MV_CESA_CRYPTO_AES_KEY_LEN_MASK     (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET)
 199
 200 /* Fragmentation mode */
 201 typedef enum
 202 {
 203     MV_CESA_FRAG_NONE   = 0,
 204     MV_CESA_FRAG_FIRST  = 1,
 205     MV_CESA_FRAG_LAST   = 2,
 206     MV_CESA_FRAG_MIDDLE = 3,
 207
 208 } MV_CESA_FRAG_MODE;
 209
 210 #define MV_CESA_FRAG_MODE_OFFSET            30
 211 #define MV_CESA_FRAG_MODE_MASK              (0x3 << MV_CESA_FRAG_MODE_OFFSET)
 212 /*---------------------------------------------------------------------------*/
 213
 214 /********** Security Accelerator Command Register **************/
 215 #define MV_CESA_CMD_REG                     (MV_CESA_REG_BASE + 0xE00)
 216
 217 #define MV_CESA_CMD_CHAN_ENABLE_BIT         0
 218 #define MV_CESA_CMD_CHAN_ENABLE_MASK        (1 << MV_CESA_CMD_CHAN_ENABLE_BIT)
 219
 220 #define MV_CESA_CMD_CHAN_DISABLE_BIT        2
 221 #define MV_CESA_CMD_CHAN_DISABLE_MASK       (1 << MV_CESA_CMD_CHAN_DISABLE_BIT)
 222
 223 /********** Security Accelerator Descriptor Pointers Register **********/
 224 #define MV_CESA_CHAN_DESC_OFFSET_REG        (MV_CESA_REG_BASE + 0xE04)
 225
 226 /********** Security Accelerator Configuration Register **********/
 227 #define MV_CESA_CFG_REG                     (MV_CESA_REG_BASE + 0xE08)
 228
 229 #define MV_CESA_CFG_STOP_DIGEST_ERR_BIT     0
 230 #define MV_CESA_CFG_STOP_DIGEST_ERR_MASK    (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT)
 231
 232 #define MV_CESA_CFG_WAIT_DMA_BIT            7
 233 #define MV_CESA_CFG_WAIT_DMA_MASK           (1 << MV_CESA_CFG_WAIT_DMA_BIT)
 234
 235 #define MV_CESA_CFG_ACT_DMA_BIT             9
 236 #define MV_CESA_CFG_ACT_DMA_MASK            (1 << MV_CESA_CFG_ACT_DMA_BIT)
 237
 238 #define MV_CESA_CFG_CHAIN_MODE_BIT          11
 239 #define MV_CESA_CFG_CHAIN_MODE_MASK         (1 << MV_CESA_CFG_CHAIN_MODE_BIT)
 240
 241 /********** Security Accelerator Status Register ***********/
 242 #define MV_CESA_STATUS_REG                  (MV_CESA_REG_BASE + 0xE0C)
 243
 244 #define MV_CESA_STATUS_ACTIVE_BIT           0
 245 #define MV_CESA_STATUS_ACTIVE_MASK          (1 << MV_CESA_STATUS_ACTIVE_BIT)
 246
 247 #define MV_CESA_STATUS_DIGEST_ERR_BIT       8
 248 #define MV_CESA_STATUS_DIGEST_ERR_MASK      (1 << MV_CESA_STATUS_DIGEST_ERR_BIT)
 249
 250
 251 /* Cryptographic Engines and Security Accelerator Interrupt Cause Register */
 252 #define MV_CESA_ISR_CAUSE_REG               (MV_CESA_REG_BASE + 0xE20)
 253
 254 /* Cryptographic Engines and Security Accelerator Interrupt Mask Register */
 255 #define MV_CESA_ISR_MASK_REG                (MV_CESA_REG_BASE + 0xE24)
 256
 257 #define MV_CESA_CAUSE_AUTH_MASK             (1 << 0)
 258 #define MV_CESA_CAUSE_DES_MASK              (1 << 1)
 259 #define MV_CESA_CAUSE_AES_ENCR_MASK         (1 << 2)
 260 #define MV_CESA_CAUSE_AES_DECR_MASK         (1 << 3)
 261 #define MV_CESA_CAUSE_DES_ALL_MASK          (1 << 4)
 262
 263 #define MV_CESA_CAUSE_ACC_BIT               5
 264 #define MV_CESA_CAUSE_ACC_MASK              (1 << MV_CESA_CAUSE_ACC_BIT)
 265
 266 #define MV_CESA_CAUSE_ACC_DMA_BIT           7
 267 #define MV_CESA_CAUSE_ACC_DMA_MASK          (1 << MV_CESA_CAUSE_ACC_DMA_BIT)
 268 #define MV_CESA_CAUSE_ACC_DMA_ALL_MASK      (3 << MV_CESA_CAUSE_ACC_DMA_BIT)
 269
 270 #define MV_CESA_CAUSE_DMA_COMPL_BIT         9
 271 #define MV_CESA_CAUSE_DMA_COMPL_MASK        (1 << MV_CESA_CAUSE_DMA_COMPL_BIT)
 272
 273 #define MV_CESA_CAUSE_DMA_OWN_ERR_BIT       10
 274 #define MV_CESA_CAUSE_DMA_OWN_ERR_MASK      (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT)
 275
 276 #define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT     11
 277 #define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK    (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT)
 278
 279
 280 #define MV_CESA_AUTH_DATA_IN_REG            (MV_CESA_REG_BASE + 0xd38)
 281 #define MV_CESA_AUTH_BIT_COUNT_LOW_REG      (MV_CESA_REG_BASE + 0xd20)
 282 #define MV_CESA_AUTH_BIT_COUNT_HIGH_REG     (MV_CESA_REG_BASE + 0xd24)
 283
 284 #define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2))
 285
 286 #define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG  (MV_CESA_REG_BASE + 0xd00)
 287 #define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG  (MV_CESA_REG_BASE + 0xd04)
 288 #define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG  (MV_CESA_REG_BASE + 0xd08)
 289 #define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG  (MV_CESA_REG_BASE + 0xd0c)
 290 #define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG  (MV_CESA_REG_BASE + 0xd10)
 291 #define MV_CESA_AUTH_COMMAND_REG            (MV_CESA_REG_BASE + 0xd18)
 292
 293 #define MV_CESA_AUTH_ALGORITHM_BIT          0
 294 #define MV_CESA_AUTH_ALGORITHM_MD5          (0<<AUTH_ALGORITHM_BIT)
 295 #define MV_CESA_AUTH_ALGORITHM_SHA1         (1<<AUTH_ALGORITHM_BIT)
 296
 297 #define MV_CESA_AUTH_IV_MODE_BIT            1
 298 #define MV_CESA_AUTH_IV_MODE_INIT           (0<<AUTH_IV_MODE_BIT)
 299 #define MV_CESA_AUTH_IV_MODE_CONTINUE       (1<<AUTH_IV_MODE_BIT)
 300
 301 #define MV_CESA_AUTH_DATA_BYTE_SWAP_BIT     2
 302 #define MV_CESA_AUTH_DATA_BYTE_SWAP_MASK    (1<<AUTH_DATA_BYTE_SWAP_BIT)
 303
 304
 305 #define MV_CESA_AUTH_IV_BYTE_SWAP_BIT       4
 306 #define MV_CESA_AUTH_IV_BYTE_SWAP_MASK      (1<<AUTH_IV_BYTE_SWAP_BIT)
 307
 308 #define MV_CESA_AUTH_TERMINATION_BIT        31
 309 #define MV_CESA_AUTH_TERMINATION_MASK       (1<<AUTH_TERMINATION_BIT)
 310
 311
 312 /*************** TDMA Control Register ************************************************/
 313 #define MV_CESA_TDMA_CTRL_REG               (MV_CESA_TDMA_REG_BASE + 0x840)
 314
 315 #define MV_CESA_TDMA_BURST_32B              3
 316 #define MV_CESA_TDMA_BURST_128B             4
 317
 318 #define MV_CESA_TDMA_DST_BURST_OFFSET       0
 319 #define MV_CESA_TDMA_DST_BURST_ALL_MASK     (0x7<<MV_CESA_TDMA_DST_BURST_OFFSET)
 320 #define MV_CESA_TDMA_DST_BURST_MASK(burst)  ((burst)<<MV_CESA_TDMA_DST_BURST_OFFSET)
 321
 322 #define MV_CESA_TDMA_OUTSTAND_READ_EN_BIT   4
 323 #define MV_CESA_TDMA_OUTSTAND_READ_EN_MASK  (1<<MV_CESA_TDMA_OUTSTAND_READ_EN_BIT)
 324
 325 #define MV_CESA_TDMA_SRC_BURST_OFFSET       6
 326 #define MV_CESA_TDMA_SRC_BURST_ALL_MASK     (0x7<<MV_CESA_TDMA_SRC_BURST_OFFSET)
 327 #define MV_CESA_TDMA_SRC_BURST_MASK(burst)  ((burst)<<MV_CESA_TDMA_SRC_BURST_OFFSET)
 328
 329 #define MV_CESA_TDMA_CHAIN_MODE_BIT         9
 330 #define MV_CESA_TDMA_NON_CHAIN_MODE_MASK    (1<<MV_CESA_TDMA_CHAIN_MODE_BIT)
 331
 332 #define MV_CESA_TDMA_BYTE_SWAP_BIT          11
 333 #define MV_CESA_TDMA_BYTE_SWAP_MASK         (0 << MV_CESA_TDMA_BYTE_SWAP_BIT)
 334 #define MV_CESA_TDMA_NO_BYTE_SWAP_MASK      (1 << MV_CESA_TDMA_BYTE_SWAP_BIT)
 335
 336 #define MV_CESA_TDMA_ENABLE_BIT             12
 337 #define MV_CESA_TDMA_ENABLE_MASK            (1<<MV_CESA_TDMA_ENABLE_BIT)
 338
 339 #define MV_CESA_TDMA_FETCH_NEXT_DESC_BIT    13
 340 #define MV_CESA_TDMA_FETCH_NEXT_DESC_MASK   (1<<MV_CESA_TDMA_FETCH_NEXT_DESC_BIT)
 341
 342 #define MV_CESA_TDMA_CHAN_ACTIVE_BIT        14
 343 #define MV_CESA_TDMA_CHAN_ACTIVE_MASK       (1<<MV_CESA_TDMA_CHAN_ACTIVE_BIT)
 344 /*------------------------------------------------------------------------------------*/
 345
 346 #define MV_CESA_TDMA_BYTE_COUNT_REG         (MV_CESA_TDMA_REG_BASE + 0x800)
 347 #define MV_CESA_TDMA_SRC_ADDR_REG           (MV_CESA_TDMA_REG_BASE + 0x810)
 348 #define MV_CESA_TDMA_DST_ADDR_REG           (MV_CESA_TDMA_REG_BASE + 0x820)
 349 #define MV_CESA_TDMA_NEXT_DESC_PTR_REG      (MV_CESA_TDMA_REG_BASE + 0x830)
 350 #define MV_CESA_TDMA_CURR_DESC_PTR_REG      (MV_CESA_TDMA_REG_BASE + 0x870)
 351
 352 #define MV_CESA_TDMA_ERROR_CAUSE_REG        (MV_CESA_TDMA_REG_BASE + 0x8C0)
 353 #define MV_CESA_TDMA_ERROR_MASK_REG         (MV_CESA_TDMA_REG_BASE + 0x8C4)
 354
 355
 356 #endif /* __mvCesaRegs_h__ */
 357