target/linux/xburst/patches-2.6.35/004-irq.patch

   1 From f6a9c8215a4553357b8a1939fafb2d6dfbacf944 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 17 Jul 2010 11:08:43 +0000
   4 Subject: [PATCH] MIPS: JZ4740: Add IRQ handler code
   5
   6 Add support for IRQ handling on a JZ4740 SoC.
   7
   8 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
   9 Cc: linux-mips@linux-mips.org
  10 Cc: linux-kernel@vger.kernel.org
  11 Patchwork: https://patchwork.linux-mips.org/patch/1465/
  12 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  13 ---
  14  arch/mips/include/asm/mach-jz4740/irq.h |   57 +++++++++++
  15  arch/mips/jz4740/irq.c                  |  167 +++++++++++++++++++++++++++++++
  16  arch/mips/jz4740/irq.h                  |   21 ++++
  17  3 files changed, 245 insertions(+), 0 deletions(-)
  18  create mode 100644 arch/mips/include/asm/mach-jz4740/irq.h
  19  create mode 100644 arch/mips/jz4740/irq.c
  20  create mode 100644 arch/mips/jz4740/irq.h
  21
  22 --- /dev/null
  23 +++ b/arch/mips/include/asm/mach-jz4740/irq.h
  24 @@ -0,0 +1,57 @@
  25 +/*
  26 + *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  27 + *  JZ4740 IRQ definitions
  28 + *
  29 + *  This program is free software; you can redistribute it and/or modify it
  30 + *  under  the terms of the GNU General  Public License as published by the
  31 + *  Free Software Foundation;  either version 2 of the License, or (at your
  32 + *  option) any later version.
  33 + *
  34 + *  You should have received a copy of the GNU General Public License along
  35 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  36 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  37 + *
  38 + */
  39 +
  40 +#ifndef __ASM_MACH_JZ4740_IRQ_H__
  41 +#define __ASM_MACH_JZ4740_IRQ_H__
  42 +
  43 +#define MIPS_CPU_IRQ_BASE 0
  44 +#define JZ4740_IRQ_BASE 8
  45 +
  46 +/* 1st-level interrupts */
  47 +#define JZ4740_IRQ(x)          (JZ4740_IRQ_BASE + (x))
  48 +#define JZ4740_IRQ_I2C         JZ4740_IRQ(1)
  49 +#define JZ4740_IRQ_UHC         JZ4740_IRQ(3)
  50 +#define JZ4740_IRQ_UART1       JZ4740_IRQ(8)
  51 +#define JZ4740_IRQ_UART0       JZ4740_IRQ(9)
  52 +#define JZ4740_IRQ_SADC                JZ4740_IRQ(12)
  53 +#define JZ4740_IRQ_MSC         JZ4740_IRQ(14)
  54 +#define JZ4740_IRQ_RTC         JZ4740_IRQ(15)
  55 +#define JZ4740_IRQ_SSI         JZ4740_IRQ(16)
  56 +#define JZ4740_IRQ_CIM         JZ4740_IRQ(17)
  57 +#define JZ4740_IRQ_AIC         JZ4740_IRQ(18)
  58 +#define JZ4740_IRQ_ETH         JZ4740_IRQ(19)
  59 +#define JZ4740_IRQ_DMAC                JZ4740_IRQ(20)
  60 +#define JZ4740_IRQ_TCU2                JZ4740_IRQ(21)
  61 +#define JZ4740_IRQ_TCU1                JZ4740_IRQ(22)
  62 +#define JZ4740_IRQ_TCU0                JZ4740_IRQ(23)
  63 +#define JZ4740_IRQ_UDC         JZ4740_IRQ(24)
  64 +#define JZ4740_IRQ_GPIO3       JZ4740_IRQ(25)
  65 +#define JZ4740_IRQ_GPIO2       JZ4740_IRQ(26)
  66 +#define JZ4740_IRQ_GPIO1       JZ4740_IRQ(27)
  67 +#define JZ4740_IRQ_GPIO0       JZ4740_IRQ(28)
  68 +#define JZ4740_IRQ_IPU         JZ4740_IRQ(29)
  69 +#define JZ4740_IRQ_LCD         JZ4740_IRQ(30)
  70 +
  71 +/* 2nd-level interrupts */
  72 +#define JZ4740_IRQ_DMA(x)      (JZ4740_IRQ(32) + (X))
  73 +
  74 +#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
  75 +#define JZ4740_IRQ_GPIO(x)     (JZ4740_IRQ(48) + (x))
  76 +
  77 +#define JZ4740_IRQ_ADC_BASE    JZ4740_IRQ(176)
  78 +
  79 +#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
  80 +
  81 +#endif
  82 --- /dev/null
  83 +++ b/arch/mips/jz4740/irq.c
  84 @@ -0,0 +1,167 @@
  85 +/*
  86 + *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  87 + *  JZ4740 platform IRQ support
  88 + *
  89 + *  This program is free software; you can redistribute it and/or modify it
  90 + *  under  the terms of the GNU General  Public License as published by the
  91 + *  Free Software Foundation;  either version 2 of the License, or (at your
  92 + *  option) any later version.
  93 + *
  94 + *  You should have received a copy of the GNU General Public License along
  95 + *  with this program; if not, write to the Free Software Foundation, Inc.,
  96 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  97 + *
  98 + */
  99 +
 100 +#include <linux/errno.h>
 101 +#include <linux/init.h>
 102 +#include <linux/types.h>
 103 +#include <linux/interrupt.h>
 104 +#include <linux/ioport.h>
 105 +#include <linux/timex.h>
 106 +#include <linux/slab.h>
 107 +#include <linux/delay.h>
 108 +
 109 +#include <linux/debugfs.h>
 110 +#include <linux/seq_file.h>
 111 +
 112 +#include <asm/io.h>
 113 +#include <asm/mipsregs.h>
 114 +#include <asm/irq_cpu.h>
 115 +
 116 +#include <asm/mach-jz4740/base.h>
 117 +
 118 +static void __iomem *jz_intc_base;
 119 +static uint32_t jz_intc_wakeup;
 120 +static uint32_t jz_intc_saved;
 121 +
 122 +#define JZ_REG_INTC_STATUS     0x00
 123 +#define JZ_REG_INTC_MASK       0x04
 124 +#define JZ_REG_INTC_SET_MASK   0x08
 125 +#define JZ_REG_INTC_CLEAR_MASK 0x0c
 126 +#define JZ_REG_INTC_PENDING    0x10
 127 +
 128 +#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
 129 +
 130 +static void intc_irq_unmask(unsigned int irq)
 131 +{
 132 +       writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
 133 +}
 134 +
 135 +static void intc_irq_mask(unsigned int irq)
 136 +{
 137 +       writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
 138 +}
 139 +
 140 +static int intc_irq_set_wake(unsigned int irq, unsigned int on)
 141 +{
 142 +       if (on)
 143 +               jz_intc_wakeup |= IRQ_BIT(irq);
 144 +       else
 145 +               jz_intc_wakeup &= ~IRQ_BIT(irq);
 146 +
 147 +       return 0;
 148 +}
 149 +
 150 +static struct irq_chip intc_irq_type = {
 151 +       .name =         "INTC",
 152 +       .mask =         intc_irq_mask,
 153 +       .mask_ack =     intc_irq_mask,
 154 +       .unmask =       intc_irq_unmask,
 155 +       .set_wake =     intc_irq_set_wake,
 156 +};
 157 +
 158 +static irqreturn_t jz4740_cascade(int irq, void *data)
 159 +{
 160 +       uint32_t irq_reg;
 161 +
 162 +       irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
 163 +
 164 +       if (irq_reg)
 165 +               generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
 166 +
 167 +       return IRQ_HANDLED;
 168 +}
 169 +
 170 +static struct irqaction jz4740_cascade_action = {
 171 +       .handler = jz4740_cascade,
 172 +       .name = "JZ4740 cascade interrupt",
 173 +};
 174 +
 175 +void __init arch_init_irq(void)
 176 +{
 177 +       int i;
 178 +       mips_cpu_irq_init();
 179 +
 180 +       jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
 181 +
 182 +       for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
 183 +               intc_irq_mask(i);
 184 +               set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
 185 +       }
 186 +
 187 +       setup_irq(2, &jz4740_cascade_action);
 188 +}
 189 +
 190 +asmlinkage void plat_irq_dispatch(void)
 191 +{
 192 +       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 193 +       if (pending & STATUSF_IP2)
 194 +               do_IRQ(2);
 195 +       else if (pending & STATUSF_IP3)
 196 +               do_IRQ(3);
 197 +       else
 198 +               spurious_interrupt();
 199 +}
 200 +
 201 +void jz4740_intc_suspend(void)
 202 +{
 203 +       jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
 204 +       writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
 205 +       writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
 206 +}
 207 +
 208 +void jz4740_intc_resume(void)
 209 +{
 210 +       writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
 211 +       writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
 212 +}
 213 +
 214 +#ifdef CONFIG_DEBUG_FS
 215 +
 216 +static inline void intc_seq_reg(struct seq_file *s, const char *name,
 217 +       unsigned int reg)
 218 +{
 219 +       seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
 220 +}
 221 +
 222 +static int intc_regs_show(struct seq_file *s, void *unused)
 223 +{
 224 +       intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
 225 +       intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
 226 +       intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
 227 +
 228 +       return 0;
 229 +}
 230 +
 231 +static int intc_regs_open(struct inode *inode, struct file *file)
 232 +{
 233 +       return single_open(file, intc_regs_show, NULL);
 234 +}
 235 +
 236 +static const struct file_operations intc_regs_operations = {
 237 +       .open           = intc_regs_open,
 238 +       .read           = seq_read,
 239 +       .llseek         = seq_lseek,
 240 +       .release        = single_release,
 241 +};
 242 +
 243 +static int __init intc_debugfs_init(void)
 244 +{
 245 +       (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
 246 +                               NULL, NULL, &intc_regs_operations);
 247 +       return 0;
 248 +}
 249 +subsys_initcall(intc_debugfs_init);
 250 +
 251 +#endif
 252 --- /dev/null
 253 +++ b/arch/mips/jz4740/irq.h
 254 @@ -0,0 +1,21 @@
 255 +/*
 256 + *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
 257 + *
 258 + *  This program is free software; you can redistribute it and/or modify it
 259 + *  under  the terms of the GNU General  Public License as published by the
 260 + *  Free Software Foundation;  either version 2 of the License, or (at your
 261 + *  option) any later version.
 262 + *
 263 + *  You should have received a copy of the GNU General Public License along
 264 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 265 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 266 + *
 267 + */
 268 +
 269 +#ifndef __MIPS_JZ4740_IRQ_H__
 270 +#define __MIPS_JZ4740_IRQ_H__
 271 +
 272 +extern void jz4740_intc_suspend(void);
 273 +extern void jz4740_intc_resume(void);
 274 +
 275 +#endif