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[openwrt.git] / package / ath9k / src / drivers / net / wireless / ath9k / core.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef CORE_H
18 #define CORE_H
19
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ip.h>
30 #include <linux/tcp.h>
31 #include <linux/in.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
40 #include <asm/page.h>
41 #include <net/mac80211.h>
42
43 #include "ath9k.h"
44 #include "rc.h"
45
46 struct ath_node;
47
48 /******************/
49 /* Utility macros */
50 /******************/
51
52 /* An attempt will be made to merge these link list helpers upstream
53 * instead */
54
55 static inline void __list_splice_tail(const struct list_head *list,
56 struct list_head *head)
57 {
58 struct list_head *first = list->next;
59 struct list_head *last = list->prev;
60 struct list_head *current_tail = head->prev;
61
62 current_tail->next = first;
63 last->next = head;
64 head->prev = last;
65 first->prev = current_tail;
66 }
67
68 static inline void __list_cut_position(struct list_head *list,
69 struct list_head *head, struct list_head *entry)
70 {
71 struct list_head *new_first =
72 (entry->next != head) ? entry->next : head;
73 list->next = head->next;
74 list->next->prev = list;
75 list->prev = entry;
76 entry->next = list;
77 head->next = new_first;
78 new_first->prev = head;
79 }
80
81 /**
82 * list_splice_tail - join two lists, each list being a queue
83 * @list: the new list to add.
84 * @head: the place to add it in the first list.
85 */
86 static inline void list_splice_tail(const struct list_head *list,
87 struct list_head *head)
88 {
89 if (!list_empty(list))
90 __list_splice_tail(list, head);
91 }
92
93 /**
94 * list_splice_tail_init - join two lists, each list being a queue, and
95 * reinitialise the emptied list.
96 * @list: the new list to add.
97 * @head: the place to add it in the first list.
98 *
99 * The list at @list is reinitialised
100 */
101 static inline void list_splice_tail_init(struct list_head *list,
102 struct list_head *head)
103 {
104 if (!list_empty(list)) {
105 __list_splice_tail(list, head);
106 INIT_LIST_HEAD(list);
107 }
108 }
109
110 /**
111 * list_cut_position - cut a list into two
112 * @list: a new list to add all removed entries
113 * @head: a list with entries
114 * @entry: an entry within head, could be the head itself
115 * and if so we won't won't cut the list
116 */
117 static inline void list_cut_position(struct list_head *list,
118 struct list_head *head, struct list_head *entry)
119 {
120 BUG_ON(list_empty(head));
121 if (list_is_singular(head))
122 BUG_ON(head->next != entry && head != entry);
123 if (entry == head)
124 INIT_LIST_HEAD(list);
125 else
126 __list_cut_position(list, head, entry);
127 }
128
129 /* Macro to expand scalars to 64-bit objects */
130
131 #define ito64(x) (sizeof(x) == 8) ? \
132 (((unsigned long long int)(x)) & (0xff)) : \
133 (sizeof(x) == 16) ? \
134 (((unsigned long long int)(x)) & 0xffff) : \
135 ((sizeof(x) == 32) ? \
136 (((unsigned long long int)(x)) & 0xffffffff) : \
137 (unsigned long long int)(x))
138
139 /* increment with wrap-around */
140 #define INCR(_l, _sz) do { \
141 (_l)++; \
142 (_l) &= ((_sz) - 1); \
143 } while (0)
144
145 /* decrement with wrap-around */
146 #define DECR(_l, _sz) do { \
147 (_l)--; \
148 (_l) &= ((_sz) - 1); \
149 } while (0)
150
151 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
152
153 #define ASSERT(exp) do { \
154 if (unlikely(!(exp))) { \
155 BUG(); \
156 } \
157 } while (0)
158
159 /* XXX: remove */
160 #define memzero(_buf, _len) memset(_buf, 0, _len)
161
162 #define get_dma_mem_context(var, field) (&((var)->field))
163 #define copy_dma_mem_context(dst, src) (*dst = *src)
164
165 #define ATH9K_BH_STATUS_INTACT 0
166 #define ATH9K_BH_STATUS_CHANGE 1
167
168 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
169
170 static inline unsigned long get_timestamp(void)
171 {
172 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
173 }
174
175 /*************/
176 /* Debugging */
177 /*************/
178
179 enum ATH_DEBUG {
180 ATH_DBG_RESET = 0x00000001,
181 ATH_DBG_PHY_IO = 0x00000002,
182 ATH_DBG_REG_IO = 0x00000004,
183 ATH_DBG_QUEUE = 0x00000008,
184 ATH_DBG_EEPROM = 0x00000010,
185 ATH_DBG_NF_CAL = 0x00000020,
186 ATH_DBG_CALIBRATE = 0x00000040,
187 ATH_DBG_CHANNEL = 0x00000080,
188 ATH_DBG_INTERRUPT = 0x00000100,
189 ATH_DBG_REGULATORY = 0x00000200,
190 ATH_DBG_ANI = 0x00000400,
191 ATH_DBG_POWER_MGMT = 0x00000800,
192 ATH_DBG_XMIT = 0x00001000,
193 ATH_DBG_BEACON = 0x00002000,
194 ATH_DBG_RATE = 0x00004000,
195 ATH_DBG_CONFIG = 0x00008000,
196 ATH_DBG_KEYCACHE = 0x00010000,
197 ATH_DBG_AGGR = 0x00020000,
198 ATH_DBG_FATAL = 0x00040000,
199 ATH_DBG_ANY = 0xffffffff
200 };
201
202 #define DBG_DEFAULT (ATH_DBG_FATAL)
203
204 #define DPRINTF(sc, _m, _fmt, ...) do { \
205 if (sc->sc_debug & (_m)) \
206 printk(_fmt , ##__VA_ARGS__); \
207 } while (0)
208
209 /***************************/
210 /* Load-time Configuration */
211 /***************************/
212
213 /* Per-instance load-time (note: NOT run-time) configurations
214 * for Atheros Device */
215 struct ath_config {
216 u_int32_t ath_aggr_prot;
217 u_int16_t txpowlimit;
218 u_int16_t txpowlimit_override;
219 u_int8_t cabqReadytime; /* Cabq Readytime % */
220 u_int8_t swBeaconProcess; /* Process received beacons
221 in SW (vs HW) */
222 };
223
224 /***********************/
225 /* Chainmask Selection */
226 /***********************/
227
228 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
229 /* Default - Number of last RSSI values that is used for
230 * chainmask selection */
231 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
232 /* Means use 3x3 chainmask instead of configured chainmask */
233 #define ATH_CHAINMASK_SEL_3X3 7
234 /* Default - Rssi threshold below which we have to switch to 3x3 */
235 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
236 /* Default - Rssi threshold above which we have to switch to
237 * user configured values */
238 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
239 /* Struct to store the chainmask select related info */
240 struct ath_chainmask_sel {
241 struct timer_list timer;
242 int cur_tx_mask; /* user configured or 3x3 */
243 int cur_rx_mask; /* user configured or 3x3 */
244 int tx_avgrssi;
245 u8 switch_allowed:1, /* timer will set this */
246 cm_sel_enabled:1;
247 };
248
249 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
250 void ath_update_chainmask(struct ath_softc *sc, int is_ht);
251
252 /*************************/
253 /* Descriptor Management */
254 /*************************/
255
256 /* Number of descriptors per buffer. The only case where we see skbuff
257 chains is due to FF aggregation in the driver. */
258 #define ATH_TXDESC 1
259 /* if there's more fragment for this MSDU */
260 #define ATH_BF_MORE_MPDU 1
261 #define ATH_TXBUF_RESET(_bf) do { \
262 (_bf)->bf_status = 0; \
263 (_bf)->bf_lastbf = NULL; \
264 (_bf)->bf_lastfrm = NULL; \
265 (_bf)->bf_next = NULL; \
266 memzero(&((_bf)->bf_state), \
267 sizeof(struct ath_buf_state)); \
268 } while (0)
269
270 struct ath_buf_state {
271 int bfs_nframes; /* # frames in aggregate */
272 u_int16_t bfs_al; /* length of aggregate */
273 u_int16_t bfs_frmlen; /* length of frame */
274 int bfs_seqno; /* sequence number */
275 int bfs_tidno; /* tid of this frame */
276 int bfs_retries; /* current retries */
277 struct ath_rc_series bfs_rcs[4]; /* rate series */
278 u8 bfs_isdata:1; /* is a data frame/aggregate */
279 u8 bfs_isaggr:1; /* is an aggregate */
280 u8 bfs_isampdu:1; /* is an a-mpdu, aggregate or not */
281 u8 bfs_ht:1; /* is an HT frame */
282 u8 bfs_isretried:1; /* is retried */
283 u8 bfs_isxretried:1; /* is excessive retried */
284 u8 bfs_shpreamble:1; /* is short preamble */
285 u8 bfs_isbar:1; /* is a BAR */
286 u8 bfs_ispspoll:1; /* is a PS-Poll */
287 u8 bfs_aggrburst:1; /* is a aggr burst */
288 u8 bfs_calcairtime:1; /* requests airtime be calculated
289 when set for tx frame */
290 int bfs_rifsburst_elem; /* RIFS burst/bar */
291 int bfs_nrifsubframes; /* # of elements in burst */
292 enum hal_key_type bfs_keytype; /* key type use to encrypt this frame */
293 };
294
295 #define bf_nframes bf_state.bfs_nframes
296 #define bf_al bf_state.bfs_al
297 #define bf_frmlen bf_state.bfs_frmlen
298 #define bf_retries bf_state.bfs_retries
299 #define bf_seqno bf_state.bfs_seqno
300 #define bf_tidno bf_state.bfs_tidno
301 #define bf_rcs bf_state.bfs_rcs
302 #define bf_isdata bf_state.bfs_isdata
303 #define bf_isaggr bf_state.bfs_isaggr
304 #define bf_isampdu bf_state.bfs_isampdu
305 #define bf_ht bf_state.bfs_ht
306 #define bf_isretried bf_state.bfs_isretried
307 #define bf_isxretried bf_state.bfs_isxretried
308 #define bf_shpreamble bf_state.bfs_shpreamble
309 #define bf_rifsburst_elem bf_state.bfs_rifsburst_elem
310 #define bf_nrifsubframes bf_state.bfs_nrifsubframes
311 #define bf_keytype bf_state.bfs_keytype
312 #define bf_isbar bf_state.bfs_isbar
313 #define bf_ispspoll bf_state.bfs_ispspoll
314 #define bf_aggrburst bf_state.bfs_aggrburst
315 #define bf_calcairtime bf_state.bfs_calcairtime
316
317 /*
318 * Abstraction of a contiguous buffer to transmit/receive. There is only
319 * a single hw descriptor encapsulated here.
320 */
321
322 struct ath_buf {
323 struct list_head list;
324 struct list_head *last;
325 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
326 an aggregate) */
327 struct ath_buf *bf_lastfrm; /* last buf of this frame */
328 struct ath_buf *bf_next; /* next subframe in the aggregate */
329 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
330 void *bf_mpdu; /* enclosing frame structure */
331 void *bf_node; /* pointer to the node */
332 struct ath_desc *bf_desc; /* virtual addr of desc */
333 dma_addr_t bf_daddr; /* physical addr of desc */
334 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
335 u_int32_t bf_status;
336 u_int16_t bf_flags; /* tx descriptor flags */
337 struct ath_buf_state bf_state; /* buffer state */
338 dma_addr_t bf_dmacontext;
339 };
340
341 /*
342 * reset the rx buffer.
343 * any new fields added to the athbuf and require
344 * reset need to be added to this macro.
345 * currently bf_status is the only one requires that
346 * requires reset.
347 */
348 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
349
350 /* hw processing complete, desc processed by hal */
351 #define ATH_BUFSTATUS_DONE 0x00000001
352 /* hw processing complete, desc hold for hw */
353 #define ATH_BUFSTATUS_STALE 0x00000002
354 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
355 #define ATH_BUFSTATUS_FREE 0x00000004
356
357 /* DMA state for tx/rx descriptors */
358
359 struct ath_descdma {
360 const char *dd_name;
361 struct ath_desc *dd_desc; /* descriptors */
362 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
363 u_int32_t dd_desc_len; /* size of dd_desc */
364 struct ath_buf *dd_bufptr; /* associated buffers */
365 dma_addr_t dd_dmacontext;
366 };
367
368 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
369
370 struct ath_rx_context {
371 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
372 };
373 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
374
375 int ath_descdma_setup(struct ath_softc *sc,
376 struct ath_descdma *dd,
377 struct list_head *head,
378 const char *name,
379 int nbuf,
380 int ndesc);
381 int ath_desc_alloc(struct ath_softc *sc);
382 void ath_desc_free(struct ath_softc *sc);
383 void ath_descdma_cleanup(struct ath_softc *sc,
384 struct ath_descdma *dd,
385 struct list_head *head);
386
387 /******/
388 /* RX */
389 /******/
390
391 #define ATH_MAX_ANTENNA 3
392 #define ATH_RXBUF 512
393 #define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
394 #define WME_NUM_TID 16
395 #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
396 #define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */
397
398 enum ATH_RX_TYPE {
399 ATH_RX_NON_CONSUMED = 0,
400 ATH_RX_CONSUMED
401 };
402
403 /* per frame rx status block */
404 struct ath_recv_status {
405 u_int64_t tsf; /* mac tsf */
406 int8_t rssi; /* RSSI (noise floor ajusted) */
407 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
408 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
409 int8_t abs_rssi; /* absolute RSSI */
410 u_int8_t rateieee; /* data rate received (IEEE rate code) */
411 u_int8_t ratecode; /* phy rate code */
412 int rateKbps; /* data rate received (Kbps) */
413 int antenna; /* rx antenna */
414 int flags; /* status of associated skb */
415 #define ATH_RX_FCS_ERROR 0x01
416 #define ATH_RX_MIC_ERROR 0x02
417 #define ATH_RX_DECRYPT_ERROR 0x04
418 #define ATH_RX_RSSI_VALID 0x08
419 /* if any of ctl,extn chainrssis are valid */
420 #define ATH_RX_CHAIN_RSSI_VALID 0x10
421 /* if extn chain rssis are valid */
422 #define ATH_RX_RSSI_EXTN_VALID 0x20
423 /* set if 40Mhz, clear if 20Mhz */
424 #define ATH_RX_40MHZ 0x40
425 /* set if short GI, clear if full GI */
426 #define ATH_RX_SHORT_GI 0x80
427 };
428
429 struct ath_rxbuf {
430 struct sk_buff *rx_wbuf; /* buffer */
431 unsigned long rx_time; /* system time when received */
432 struct ath_recv_status rx_status; /* cached rx status */
433 };
434
435 /* Per-TID aggregate receiver state for a node */
436 struct ath_arx_tid {
437 struct ath_node *an; /* parent ath node */
438 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
439 struct timer_list timer;
440 spinlock_t tidlock; /* lock to protect this TID structure */
441 int baw_head; /* seq_next at head */
442 int baw_tail; /* tail of block-ack window */
443 int seq_reset; /* need to reset start sequence */
444 int addba_exchangecomplete;
445 u_int16_t seq_next; /* next expected sequence */
446 u_int16_t baw_size; /* block-ack window size */
447 };
448
449 /* Per-node receiver aggregate state */
450 struct ath_arx {
451 struct ath_arx_tid tid[WME_NUM_TID];
452 };
453
454 int ath_startrecv(struct ath_softc *sc);
455 bool ath_stoprecv(struct ath_softc *sc);
456 void ath_flushrecv(struct ath_softc *sc);
457 u_int32_t ath_calcrxfilter(struct ath_softc *sc);
458 void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
459 void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
460 void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
461 void ath_handle_rx_intr(struct ath_softc *sc);
462 int ath_rx_init(struct ath_softc *sc, int nbufs);
463 void ath_rx_cleanup(struct ath_softc *sc);
464 int ath_rx_tasklet(struct ath_softc *sc, int flush);
465 int ath_rx_input(struct ath_softc *sc,
466 struct ath_node *node,
467 int is_ampdu,
468 struct sk_buff *skb,
469 struct ath_recv_status *rx_status,
470 enum ATH_RX_TYPE *status);
471 int ath__rx_indicate(struct ath_softc *sc,
472 struct sk_buff *skb,
473 struct ath_recv_status *status,
474 u_int16_t keyix);
475 int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
476 struct ath_recv_status *status);
477
478 /******/
479 /* TX */
480 /******/
481
482 #define ATH_FRAG_PER_MSDU 1
483 #define ATH_TXBUF (512/ATH_FRAG_PER_MSDU)
484 /* max number of transmit attempts (tries) */
485 #define ATH_TXMAXTRY 13
486 /* max number of 11n transmit attempts (tries) */
487 #define ATH_11N_TXMAXTRY 10
488 /* max number of tries for management and control frames */
489 #define ATH_MGT_TXMAXTRY 4
490 #define WME_BA_BMP_SIZE 64
491 #define WME_MAX_BA WME_BA_BMP_SIZE
492 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
493 #define TID_TO_WME_AC(_tid) \
494 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
495 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
496 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
497 WME_AC_VO)
498
499
500 /* Wireless Multimedia Extension Defines */
501 #define WME_AC_BE 0 /* best effort */
502 #define WME_AC_BK 1 /* background */
503 #define WME_AC_VI 2 /* video */
504 #define WME_AC_VO 3 /* voice */
505 #define WME_NUM_AC 4
506
507 enum ATH_SM_PWRSAV{
508 ATH_SM_ENABLE,
509 ATH_SM_PWRSAV_STATIC,
510 ATH_SM_PWRSAV_DYNAMIC,
511 };
512
513 /*
514 * Data transmit queue state. One of these exists for each
515 * hardware transmit queue. Packets sent to us from above
516 * are assigned to queues based on their priority. Not all
517 * devices support a complete set of hardware transmit queues.
518 * For those devices the array sc_ac2q will map multiple
519 * priorities to fewer hardware queues (typically all to one
520 * hardware queue).
521 */
522 struct ath_txq {
523 u_int axq_qnum; /* hardware q number */
524 u_int32_t *axq_link; /* link ptr in last TX desc */
525 struct list_head axq_q; /* transmit queue */
526 spinlock_t axq_lock; /* lock on q and link */
527 unsigned long axq_lockflags; /* intr state when must cli */
528 u_int axq_depth; /* queue depth */
529 u_int8_t axq_aggr_depth; /* aggregates queued */
530 u_int32_t axq_totalqueued;/* total ever queued */
531 u_int axq_intrcnt; /* count to determine
532 if descriptor should generate
533 int on this txq. */
534 bool stopped; /* Is mac80211 queue
535 stopped ? */
536 /* State for patching up CTS when bursting */
537 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
538 struct ath_desc *axq_lastdsWithCTS; /* first desc of the
539 last descriptor that contains CTS */
540 struct ath_desc *axq_gatingds; /* final desc of the gating desc
541 * that determines whether lastdsWithCTS has
542 * been DMA'ed or not */
543 struct list_head axq_acq;
544 };
545
546 /* per TID aggregate tx state for a destination */
547 struct ath_atx_tid {
548 struct list_head list; /* round-robin tid entry */
549 struct list_head buf_q; /* pending buffers */
550 struct ath_node *an; /* parent node structure */
551 struct ath_atx_ac *ac; /* parent access category */
552 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];/* active tx frames */
553 u_int16_t seq_start; /* starting seq of BA window */
554 u_int16_t seq_next; /* next seq to be used */
555 u_int16_t baw_size; /* BA window size */
556 int tidno; /* TID number */
557 int baw_head; /* first un-acked tx buffer */
558 int baw_tail; /* next unused tx buffer slot */
559 int sched; /* TID is scheduled */
560 int paused; /* TID is paused */
561 int cleanup_inprogress; /* aggr of this TID is
562 being teared down */
563 u_int32_t addba_exchangecomplete:1; /* ADDBA state */
564 int32_t addba_exchangeinprogress;
565 int addba_exchangeattempts;
566 };
567
568 /* per access-category aggregate tx state for a destination */
569 struct ath_atx_ac {
570 int sched; /* dest-ac is scheduled */
571 int qnum; /* H/W queue number associated
572 with this AC */
573 struct list_head list; /* round-robin txq entry */
574 struct list_head tid_q; /* queue of TIDs with buffers */
575 };
576
577 /* per dest tx state */
578 struct ath_atx {
579 struct ath_atx_tid tid[WME_NUM_TID];
580 struct ath_atx_ac ac[WME_NUM_AC];
581 };
582
583 /* per-frame tx control block */
584 struct ath_tx_control {
585 struct ath_node *an; /* destination to sent to */
586 int if_id; /* only valid for cab traffic */
587 int qnum; /* h/w queue number */
588 u_int ht:1; /* if it can be transmitted using HT */
589 u_int ps:1; /* if one or more stations are in PS mode */
590 u_int use_minrate:1; /* if this frame should transmitted using
591 minimum rate */
592 enum hal_pkt_type atype; /* Atheros packet type */
593 enum hal_key_type keytype; /* key type */
594 u_int flags; /* HAL flags */
595 u_int16_t seqno; /* sequence number */
596 u_int16_t tidno; /* tid number */
597 u_int16_t txpower; /* transmit power */
598 u_int16_t frmlen; /* frame length */
599 u_int32_t keyix; /* key index */
600 int min_rate; /* minimum rate */
601 int mcast_rate; /* multicast rate */
602 u_int16_t nextfraglen; /* next fragment length */
603 /* below is set only by ath_dev */
604 struct ath_softc *dev; /* device handle */
605 dma_addr_t dmacontext;
606 };
607
608 /* per frame tx status block */
609 struct ath_xmit_status {
610 int retries; /* number of retries to successufully
611 transmit this frame */
612 int flags; /* status of transmit */
613 #define ATH_TX_ERROR 0x01
614 #define ATH_TX_XRETRY 0x02
615 #define ATH_TX_BAR 0x04
616 };
617
618 struct ath_tx_stat {
619 int rssi; /* RSSI (noise floor ajusted) */
620 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
621 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
622 int rateieee; /* data rate xmitted (IEEE rate code) */
623 int rateKbps; /* data rate xmitted (Kbps) */
624 int ratecode; /* phy rate code */
625 int flags; /* validity flags */
626 /* if any of ctl,extn chain rssis are valid */
627 #define ATH_TX_CHAIN_RSSI_VALID 0x01
628 /* if extn chain rssis are valid */
629 #define ATH_TX_RSSI_EXTN_VALID 0x02
630 u_int32_t airtime; /* time on air per final tx rate */
631 };
632
633 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
634 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
635 int ath_tx_setup(struct ath_softc *sc, int haltype);
636 void ath_draintxq(struct ath_softc *sc, bool retry_tx);
637 void ath_tx_draintxq(struct ath_softc *sc,
638 struct ath_txq *txq, bool retry_tx);
639 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
640 void ath_tx_node_cleanup(struct ath_softc *sc,
641 struct ath_node *an, bool bh_flag);
642 void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
643 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
644 int ath_tx_init(struct ath_softc *sc, int nbufs);
645 int ath_tx_cleanup(struct ath_softc *sc);
646 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
647 int ath_txq_update(struct ath_softc *sc, int qnum, struct hal_txq_info *q);
648 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
649 void ath_tx_tasklet(struct ath_softc *sc);
650 u_int32_t ath_txq_depth(struct ath_softc *sc, int qnum);
651 u_int32_t ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
652 void ath_notify_txq_status(struct ath_softc *sc, u_int16_t queue_depth);
653 void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
654 struct ath_xmit_status *tx_status, struct ath_node *an);
655
656 /**********************/
657 /* Node / Aggregation */
658 /**********************/
659
660 /* indicates the node is clened up */
661 #define ATH_NODE_CLEAN 0x1
662 /* indicates the node is 80211 power save */
663 #define ATH_NODE_PWRSAVE 0x2
664
665 #define ADDBA_TIMEOUT 200 /* 200 milliseconds */
666 #define ADDBA_EXCHANGE_ATTEMPTS 10
667 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
668 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
669 /* number of delimiters for encryption padding */
670 #define ATH_AGGR_ENCRYPTDELIM 10
671 /* minimum h/w qdepth to be sustained to maximize aggregation */
672 #define ATH_AGGR_MIN_QDEPTH 2
673 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
674 #define IEEE80211_SEQ_SEQ_SHIFT 4
675 #define IEEE80211_SEQ_MAX 4096
676 #define IEEE80211_MIN_AMPDU_BUF 0x8
677
678 /* return whether a bit at index _n in bitmap _bm is set
679 * _sz is the size of the bitmap */
680 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
681 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
682
683 /* return block-ack bitmap index given sequence and starting sequence */
684 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
685
686 /* returns delimiter padding required given the packet length */
687 #define ATH_AGGR_GET_NDELIM(_len) \
688 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
689 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
690
691 #define BAW_WITHIN(_start, _bawsz, _seqno) \
692 ((((_seqno) - (_start)) & 4095) < (_bawsz))
693
694 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
695 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
696 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
697 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
698
699 enum ATH_AGGR_STATUS {
700 ATH_AGGR_DONE,
701 ATH_AGGR_BAW_CLOSED,
702 ATH_AGGR_LIMITED,
703 ATH_AGGR_SHORTPKT,
704 ATH_AGGR_8K_LIMITED,
705 };
706
707 enum ATH_AGGR_CHECK {
708 AGGR_NOT_REQUIRED,
709 AGGR_REQUIRED,
710 AGGR_CLEANUP_PROGRESS,
711 AGGR_EXCHANGE_PROGRESS,
712 AGGR_EXCHANGE_DONE
713 };
714
715 struct aggr_rifs_param {
716 int param_max_frames;
717 int param_max_len;
718 int param_rl;
719 int param_al;
720 struct ath_rc_series *param_rcs;
721 };
722
723 /* Per-node aggregation state */
724 struct ath_node_aggr {
725 struct ath_atx tx; /* node transmit state */
726 struct ath_arx rx; /* node receive state */
727 };
728
729 /* driver-specific node state */
730 struct ath_node {
731 struct list_head list;
732 struct ath_softc *an_sc; /* back pointer */
733 atomic_t an_refcnt;
734 struct ath_chainmask_sel an_chainmask_sel;
735 struct ath_node_aggr an_aggr; /* A-MPDU aggregation state */
736 u_int8_t an_smmode; /* SM Power save mode */
737 u_int8_t an_flags;
738 u8 an_addr[ETH_ALEN];
739 };
740
741 void ath_tx_resume_tid(struct ath_softc *sc,
742 struct ath_atx_tid *tid);
743 enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
744 struct ath_node *an, u8 tidno);
745 void ath_tx_aggr_teardown(struct ath_softc *sc,
746 struct ath_node *an, u_int8_t tidno);
747 void ath_rx_aggr_teardown(struct ath_softc *sc,
748 struct ath_node *an, u_int8_t tidno);
749 int ath_rx_aggr_start(struct ath_softc *sc,
750 const u8 *addr,
751 u16 tid,
752 u16 *ssn);
753 int ath_rx_aggr_stop(struct ath_softc *sc,
754 const u8 *addr,
755 u16 tid);
756 int ath_tx_aggr_start(struct ath_softc *sc,
757 const u8 *addr,
758 u16 tid,
759 u16 *ssn);
760 int ath_tx_aggr_stop(struct ath_softc *sc,
761 const u8 *addr,
762 u16 tid);
763 void ath_newassoc(struct ath_softc *sc,
764 struct ath_node *node, int isnew, int isuapsd);
765 struct ath_node *ath_node_attach(struct ath_softc *sc,
766 u_int8_t addr[ETH_ALEN], int if_id);
767 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
768 struct ath_node *ath_node_get(struct ath_softc *sc, u_int8_t addr[ETH_ALEN]);
769 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
770 struct ath_node *ath_node_find(struct ath_softc *sc, u_int8_t *addr);
771
772 /*******************/
773 /* Beacon Handling */
774 /*******************/
775
776 /*
777 * Regardless of the number of beacons we stagger, (i.e. regardless of the
778 * number of BSSIDs) if a given beacon does not go out even after waiting this
779 * number of beacon intervals, the game's up.
780 */
781 #define BSTUCK_THRESH (9 * ATH_BCBUF)
782 #define ATH_BCBUF 4 /* number of beacon buffers */
783 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
784 #define ATH_DEFAULT_BMISS_LIMIT 10
785 #define ATH_BEACON_AIFS_DEFAULT 0 /* Default aifs for ap beacon q */
786 #define ATH_BEACON_CWMIN_DEFAULT 0 /* Default cwmin for ap beacon q */
787 #define ATH_BEACON_CWMAX_DEFAULT 0 /* Default cwmax for ap beacon q */
788 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
789
790 /* beacon configuration */
791 struct ath_beacon_config {
792 u_int16_t beacon_interval;
793 u_int16_t listen_interval;
794 u_int16_t dtim_period;
795 u_int16_t bmiss_timeout;
796 u_int8_t dtim_count;
797 u_int8_t tim_offset;
798 union {
799 u_int64_t last_tsf;
800 u_int8_t last_tstamp[8];
801 } u; /* last received beacon/probe response timestamp of this BSS. */
802 };
803
804 /* offsets in a beacon frame for
805 * quick acess of beacon content by low-level driver */
806 struct ath_beacon_offset {
807 u_int8_t *bo_tim; /* start of atim/dtim */
808 };
809
810 void ath9k_beacon_tasklet(unsigned long data);
811 void ath_beacon_config(struct ath_softc *sc, int if_id);
812 int ath_beaconq_setup(struct ath_hal *ah);
813 int ath_beacon_alloc(struct ath_softc *sc, int if_id);
814 void ath_bstuck_process(struct ath_softc *sc);
815 void ath_beacon_tasklet(struct ath_softc *sc, int *needmark);
816 void ath_beacon_free(struct ath_softc *sc);
817 void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
818 void ath_beacon_sync(struct ath_softc *sc, int if_id);
819 void ath_update_beacon_info(struct ath_softc *sc, int avgbrssi);
820 void ath_get_beaconconfig(struct ath_softc *sc,
821 int if_id,
822 struct ath_beacon_config *conf);
823 int ath_update_beacon(struct ath_softc *sc,
824 int if_id,
825 struct ath_beacon_offset *bo,
826 struct sk_buff *skb,
827 int mcast);
828 /********/
829 /* VAPs */
830 /********/
831
832 #define ATH_IF_HW_OFF 0x0001 /* hardware state needs to turn off */
833 #define ATH_IF_HW_ON 0x0002 /* hardware state needs to turn on */
834 /* STA only: the associated AP is HT capable */
835 #define ATH_IF_HT 0x0004
836 /* AP/IBSS only: current BSS has privacy on */
837 #define ATH_IF_PRIVACY 0x0008
838 #define ATH_IF_BEACON_ENABLE 0x0010 /* AP/IBSS only: enable beacon */
839 #define ATH_IF_BEACON_SYNC 0x0020 /* IBSS only: need to sync beacon */
840
841 /*
842 * Define the scheme that we select MAC address for multiple
843 * BSS on the same radio. The very first VAP will just use the MAC
844 * address from the EEPROM. For the next 3 VAPs, we set the
845 * U/L bit (bit 1) in MAC address, and use the next two bits as the
846 * index of the VAP.
847 */
848
849 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
850 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
851
852 /* VAP configuration (from protocol layer) */
853 struct ath_vap_config {
854 u_int32_t av_fixed_rateset;
855 u_int32_t av_fixed_retryset;
856 };
857
858 /* driver-specific vap state */
859 struct ath_vap {
860 struct ieee80211_vif *av_if_data; /* interface(vap)
861 instance from 802.11 protocal layer */
862 enum hal_opmode av_opmode; /* VAP operational mode */
863 struct ath_buf *av_bcbuf; /* beacon buffer */
864 struct ath_beacon_offset av_boff; /* dynamic update state */
865 struct ath_tx_control av_btxctl; /* tx control information
866 for beacon */
867 int av_bslot; /* beacon slot index */
868 struct ath_txq av_mcastq; /* multicast
869 transmit queue */
870 struct ath_vap_config av_config; /* vap configuration
871 parameters from 802.11 protocol layer*/
872 };
873
874 int ath_vap_attach(struct ath_softc *sc,
875 int if_id,
876 struct ieee80211_vif *if_data,
877 enum hal_opmode opmode);
878 int ath_vap_detach(struct ath_softc *sc, int if_id);
879 int ath_vap_config(struct ath_softc *sc,
880 int if_id, struct ath_vap_config *if_config);
881 int ath_vap_listen(struct ath_softc *sc, int if_id);
882
883 /*********************/
884 /* Antenna diversity */
885 /*********************/
886
887 #define ATH_ANT_DIV_MAX_CFG 2
888 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
889 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
890
891 enum ATH_ANT_DIV_STATE{
892 ATH_ANT_DIV_IDLE,
893 ATH_ANT_DIV_SCAN, /* evaluating antenna */
894 };
895
896 struct ath_antdiv {
897 struct ath_softc *antdiv_sc;
898 u_int8_t antdiv_start;
899 enum ATH_ANT_DIV_STATE antdiv_state;
900 u_int8_t antdiv_num_antcfg;
901 u_int8_t antdiv_curcfg;
902 u_int8_t antdiv_bestcfg;
903 int32_t antdivf_rssitrig;
904 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
905 u_int64_t antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
906 u_int64_t antdiv_laststatetsf;
907 u_int8_t antdiv_bssid[ETH_ALEN];
908 };
909
910 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
911 struct ath_softc *sc, int32_t rssitrig);
912 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
913 u_int8_t num_antcfg,
914 const u_int8_t *bssid);
915 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
916 void ath_slow_ant_div(struct ath_antdiv *antdiv,
917 struct ieee80211_hdr *wh,
918 struct ath_rx_status *rx_stats);
919 void ath_setdefantenna(void *sc, u_int antenna);
920
921 /********************/
922 /* Main driver core */
923 /********************/
924
925 /*
926 * Default cache line size, in bytes.
927 * Used when PCI device not fully initialized by bootrom/BIOS
928 */
929 #define DEFAULT_CACHELINE 32
930 #define ATH_DEFAULT_NOISE_FLOOR -95
931 #define ATH_REGCLASSIDS_MAX 10
932 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
933 #define ATH_PREAMBLE_SHORT (1<<0)
934 #define ATH_PROTECT_ENABLE (1<<1)
935 #define ATH_MAX_SW_RETRIES 10
936 /* Num farmes difference in tx to flip default recv */
937 #define ATH_ANTENNA_DIFF 2
938 #define ATH_CHAN_MAX 255
939 #define IEEE80211_WEP_NKID 4 /* number of key ids */
940 #define IEEE80211_RATE_VAL 0x7f
941 /*
942 * The key cache is used for h/w cipher state and also for
943 * tracking station state such as the current tx antenna.
944 * We also setup a mapping table between key cache slot indices
945 * and station state to short-circuit node lookups on rx.
946 * Different parts have different size key caches. We handle
947 * up to ATH_KEYMAX entries (could dynamically allocate state).
948 */
949 #define ATH_KEYMAX 128 /* max key cache size we handle */
950 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
951
952 #define RESET_RETRY_TXQ 0x00000001
953 #define ATH_IF_ID_ANY 0xff
954
955 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
956
957 #define RSSI_LPF_THRESHOLD -20
958 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
959 #define ATH_RATE_DUMMY_MARKER 0
960 #define ATH_RSSI_LPF_LEN 10
961 #define ATH_RSSI_DUMMY_MARKER 0x127
962
963 #define ATH_EP_MUL(x, mul) ((x) * (mul))
964 #define ATH_EP_RND(x, mul) \
965 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
966 #define ATH_RSSI_OUT(x) \
967 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
968 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
969 #define ATH_RSSI_IN(x) \
970 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
971 #define ATH_LPF_RSSI(x, y, len) \
972 ((x != ATH_RSSI_DUMMY_MARKER) ? \
973 (((x) * ((len) - 1) + (y)) / (len)) : (y))
974 #define ATH_RSSI_LPF(x, y) do { \
975 if ((y) >= RSSI_LPF_THRESHOLD) \
976 x = ATH_LPF_RSSI((x), \
977 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
978 } while (0)
979
980
981 enum PROT_MODE {
982 PROT_M_NONE = 0,
983 PROT_M_RTSCTS,
984 PROT_M_CTSONLY
985 };
986
987 enum ieee80211_clist_cmd {
988 CLIST_UPDATE,
989 CLIST_DFS_UPDATE,
990 CLIST_NEW_COUNTRY
991 };
992
993 enum RATE_TYPE {
994 NORMAL_RATE = 0,
995 HALF_RATE,
996 QUARTER_RATE
997 };
998
999 struct ath_ht_info {
1000 enum hal_ht_macmode tx_chan_width;
1001 u_int16_t maxampdu;
1002 u_int8_t mpdudensity;
1003 u_int8_t ext_chan_offset;
1004 };
1005
1006 struct ath_softc {
1007 struct ieee80211_hw *hw; /* mac80211 instance */
1008 struct pci_dev *pdev; /* Bus handle */
1009 void __iomem *mem; /* address of the device */
1010 struct tasklet_struct intr_tq; /* General tasklet */
1011 struct tasklet_struct bcon_tasklet; /* Beacon tasklet */
1012 struct ath_config sc_config; /* per-instance load-time
1013 parameters */
1014 int sc_debug; /* Debug masks */
1015 struct ath_hal *sc_ah; /* HAL Instance */
1016 struct ath_rate_softc *sc_rc; /* tx rate control support */
1017 u_int32_t sc_intrstatus; /* HAL_STATUS */
1018 enum hal_opmode sc_opmode; /* current operating mode */
1019
1020 /* Properties, Config */
1021 u_int8_t sc_invalid; /* being detached */
1022 u_int8_t sc_beacons; /* beacons running */
1023 u_int8_t sc_scanning; /* scanning active */
1024 u_int8_t sc_txaggr; /* enable 11n tx aggregation */
1025 u_int8_t sc_rxaggr; /* enable 11n rx aggregation */
1026 u_int8_t sc_update_chainmask; /* change chain mask */
1027 u_int8_t sc_full_reset; /* force full reset */
1028 enum wireless_mode sc_curmode; /* current phy mode */
1029 u_int16_t sc_curtxpow; /* current tx power limit */
1030 u_int16_t sc_curaid; /* current association id */
1031 u_int8_t sc_curbssid[ETH_ALEN];
1032 u_int8_t sc_myaddr[ETH_ALEN];
1033 enum PROT_MODE sc_protmode; /* protection mode */
1034 u_int8_t sc_mcastantenna;/* Multicast antenna number */
1035 u_int8_t sc_txantenna; /* data tx antenna
1036 (fixed or auto) */
1037 u_int8_t sc_nbcnvaps; /* # of vaps sending beacons */
1038 u_int16_t sc_nvaps; /* # of active virtual ap's */
1039 struct ath_vap *sc_vaps[ATH_BCBUF]; /* interface id
1040 to avp map */
1041 enum hal_int sc_imask; /* interrupt mask copy */
1042 u_int8_t sc_bssidmask[ETH_ALEN];
1043 u_int8_t sc_defant; /* current default antenna */
1044 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
1045 u_int16_t sc_cachelsz; /* cache line size */
1046 int sc_slotupdate; /* slot to next advance fsm */
1047 int sc_slottime; /* slot time */
1048 u_int8_t sc_noreset;
1049 int sc_bslot[ATH_BCBUF];/* beacon xmit slots */
1050 struct hal_node_stats sc_halstats; /* station-mode rssi stats */
1051 struct list_head node_list;
1052 struct ath_ht_info sc_ht_info;
1053 int16_t sc_noise_floor; /* signal noise floor in dBm */
1054 enum hal_ht_extprotspacing sc_ht_extprotspacing;
1055 u_int8_t sc_tx_chainmask;
1056 u_int8_t sc_rx_chainmask;
1057 u_int8_t sc_rxchaindetect_ref;
1058 u_int8_t sc_rxchaindetect_thresh5GHz;
1059 u_int8_t sc_rxchaindetect_thresh2GHz;
1060 u_int8_t sc_rxchaindetect_delta5GHz;
1061 u_int8_t sc_rxchaindetect_delta2GHz;
1062 u_int32_t sc_rtsaggrlimit; /* Chipset specific
1063 aggr limit */
1064 u32 sc_flags;
1065 #ifdef CONFIG_SLOW_ANT_DIV
1066 /* Slow antenna diversity */
1067 struct ath_antdiv sc_antdiv;
1068 #endif
1069 enum {
1070 OK, /* no change needed */
1071 UPDATE, /* update pending */
1072 COMMIT /* beacon sent, commit change */
1073 } sc_updateslot; /* slot time update fsm */
1074
1075 /* Crypto */
1076 u_int sc_keymax; /* size of key cache */
1077 DECLARE_BITMAP (sc_keymap, ATH_KEYBYTES);/* key use bit map */
1078 u_int8_t sc_splitmic; /* split TKIP MIC keys */
1079 int sc_keytype; /* type of the key being used */
1080
1081 /* RX */
1082 struct list_head sc_rxbuf; /* receive buffer */
1083 struct ath_descdma sc_rxdma; /* RX descriptors */
1084 int sc_rxbufsize; /* rx size based on mtu */
1085 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
1086 u_int32_t sc_rxflush; /* rx flush in progress */
1087 u_int64_t sc_lastrx; /* tsf of last rx'd frame */
1088
1089 /* TX */
1090 struct list_head sc_txbuf; /* transmit buffer */
1091 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
1092 struct ath_descdma sc_txdma; /* TX descriptors */
1093 u_int sc_txqsetup; /* h/w queues setup */
1094 u_int sc_txintrperiod;/* tx interrupt batching */
1095 int sc_haltype2q[HAL_WME_AC_VO+1]; /* HAL WME
1096 AC -> h/w qnum */
1097 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
1098
1099 /* Beacon */
1100 struct hal_txq_info sc_beacon_qi; /* adhoc only: beacon
1101 queue parameters */
1102 struct ath_descdma sc_bdma; /* beacon descriptors */
1103 struct ath_txq *sc_cabq; /* tx q for cab frames */
1104 struct list_head sc_bbuf; /* beacon buffers */
1105 u_int sc_bhalq; /* HAL q for outgoing beacons */
1106 u_int sc_bmisscount; /* missed beacon transmits */
1107 u_int32_t ast_be_xmit; /* beacons transmitted */
1108
1109 /* Rate */
1110 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
1111 const struct hal_rate_table *sc_rates[WIRELESS_MODE_MAX];
1112 const struct hal_rate_table *sc_currates; /* current rate table */
1113 u_int8_t sc_rixmap[256]; /* IEEE to h/w
1114 rate table ix */
1115 u_int8_t sc_minrateix; /* min h/w rate index */
1116 u_int8_t sc_protrix; /* protection rate index */
1117 struct {
1118 u_int32_t rateKbps; /* transfer rate in kbs */
1119 u_int8_t ieeerate; /* IEEE rate */
1120 } sc_hwmap[256]; /* h/w rate ix mappings */
1121
1122 /* Channel, Band */
1123 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
1124 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1125 struct hal_channel sc_curchan; /* current h/w channel */
1126
1127 /* Locks */
1128 spinlock_t sc_rxflushlock; /* lock of RX flush */
1129 spinlock_t sc_rxbuflock; /* rxbuf lock */
1130 spinlock_t sc_txbuflock; /* txbuf lock */
1131 spinlock_t sc_resetlock;
1132 spinlock_t node_lock;
1133 };
1134
1135 int ath_init(u_int16_t devid, struct ath_softc *sc);
1136 void ath_deinit(struct ath_softc *sc);
1137 int ath_open(struct ath_softc *sc, struct hal_channel *initial_chan);
1138 int ath_suspend(struct ath_softc *sc);
1139 irqreturn_t ath_isr(int irq, void *dev);
1140 int ath_reset(struct ath_softc *sc);
1141 void ath_scan_start(struct ath_softc *sc);
1142 void ath_scan_end(struct ath_softc *sc);
1143 int ath_set_channel(struct ath_softc *sc, struct hal_channel *hchan);
1144 void ath_setup_channel_list(struct ath_softc *sc,
1145 enum ieee80211_clist_cmd cmd,
1146 const struct hal_channel *chans,
1147 int nchan,
1148 const u_int8_t *regclassids,
1149 u_int nregclass,
1150 int countrycode);
1151 void ath_setup_rate(struct ath_softc *sc,
1152 enum wireless_mode wMode,
1153 enum RATE_TYPE type,
1154 const struct hal_rate_table *rt);
1155
1156 /*********************/
1157 /* Utility Functions */
1158 /*********************/
1159
1160 void ath_key_reset(struct ath_softc *sc, u_int16_t keyix, int freeslot);
1161 int ath_keyset(struct ath_softc *sc,
1162 u_int16_t keyix,
1163 struct hal_keyval *hk,
1164 const u_int8_t mac[ETH_ALEN]);
1165 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1166 int ath_get_mac80211_qnum(u_int queue, struct ath_softc *sc);
1167 void ath_setslottime(struct ath_softc *sc);
1168 void ath_update_txpow(struct ath_softc *sc);
1169 int ath_cabq_update(struct ath_softc *);
1170 void ath_get_currentCountry(struct ath_softc *sc,
1171 struct hal_country_entry *ctry);
1172 u_int64_t ath_extend_tsf(struct ath_softc *sc, u_int32_t rstamp);
1173 void ath_internal_reset(struct ath_softc *sc);
1174 u_int32_t ath_chan2flags(struct ieee80211_channel *chan, struct ath_softc *sc);
1175 dma_addr_t ath_skb_map_single(struct ath_softc *sc,
1176 struct sk_buff *skb,
1177 int direction,
1178 dma_addr_t *pa);
1179 void ath_skb_unmap_single(struct ath_softc *sc,
1180 struct sk_buff *skb,
1181 int direction,
1182 dma_addr_t *pa);
1183 void ath_mcast_merge(struct ath_softc *sc, u_int32_t mfilt[2]);
1184 enum hal_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
1185
1186 #endif /* CORE_H */
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