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[adm5120] switch to 2.6.28
[openwrt.git] / target / linux / brcm47xx / patches-2.6.28 / 810-ssb-add-pmu-support.patch
1 Sent to mainline on 2009 Feb 03.
2
3 For further modifications, please use separate patch files. This simpifies
4 keeping track of what is upstream and what is not. Thanks.
5
6 --mb
7
8
9 --- a/drivers/ssb/Makefile
10 +++ b/drivers/ssb/Makefile
11 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.
12
13 # built-in drivers
14 ssb-y += driver_chipcommon.o
15 +ssb-y += driver_chipcommon_pmu.o
16 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
17 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
18 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
19 --- /dev/null
20 +++ b/drivers/ssb/driver_chipcommon_pmu.c
21 @@ -0,0 +1,508 @@
22 +/*
23 + * Sonics Silicon Backplane
24 + * Broadcom ChipCommon Power Management Unit driver
25 + *
26 + * Copyright 2009, Michael Buesch <mb@bu3sch.de>
27 + * Copyright 2007, Broadcom Corporation
28 + *
29 + * Licensed under the GNU/GPL. See COPYING for details.
30 + */
31 +
32 +#include <linux/ssb/ssb.h>
33 +#include <linux/ssb/ssb_regs.h>
34 +#include <linux/ssb/ssb_driver_chipcommon.h>
35 +#include <linux/delay.h>
36 +
37 +#include "ssb_private.h"
38 +
39 +static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
40 +{
41 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
42 + return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
43 +}
44 +
45 +static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
46 + u32 offset, u32 value)
47 +{
48 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
49 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
50 +}
51 +
52 +struct pmu0_plltab_entry {
53 + u16 freq; /* Crystal frequency in kHz.*/
54 + u8 xf; /* Crystal frequency value for PMU control */
55 + u8 wb_int;
56 + u32 wb_frac;
57 +};
58 +
59 +static const struct pmu0_plltab_entry pmu0_plltab[] = {
60 + { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
61 + { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
62 + { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
63 + { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
64 + { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
65 + { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
66 + { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
67 + { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
68 + { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
69 + { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
70 + { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
71 + { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
72 + { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
73 + { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
74 +};
75 +#define SSB_PMU0_DEFAULT_XTALFREQ 20000
76 +
77 +static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq)
78 +{
79 + const struct pmu0_plltab_entry *e;
80 + unsigned int i;
81 +
82 + for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {
83 + e = &pmu0_plltab[i];
84 + if (e->freq == crystalfreq)
85 + return e;
86 + }
87 +
88 + return NULL;
89 +}
90 +
91 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
92 +static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
93 + u32 crystalfreq)
94 +{
95 + struct ssb_bus *bus = cc->dev->bus;
96 + const struct pmu0_plltab_entry *e = NULL;
97 + u32 pmuctl, tmp, pllctl;
98 + unsigned int i;
99 +
100 + if ((bus->chip_id == 0x5354) && !crystalfreq) {
101 + /* The 5354 crystal freq is 25MHz */
102 + crystalfreq = 25000;
103 + }
104 + if (crystalfreq)
105 + e = pmu0_plltab_find_entry(crystalfreq);
106 + if (!e)
107 + e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ);
108 + BUG_ON(!e);
109 + crystalfreq = e->freq;
110 + cc->pmu.crystalfreq = e->freq;
111 +
112 + /* Check if the PLL already is programmed to this frequency. */
113 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
114 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
115 + /* We're already there... */
116 + return;
117 + }
118 +
119 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
120 + (crystalfreq / 1000), (crystalfreq % 1000));
121 +
122 + /* First turn the PLL off. */
123 + switch (bus->chip_id) {
124 + case 0x4328:
125 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
126 + ~(1 << SSB_PMURES_4328_BB_PLL_PU));
127 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
128 + ~(1 << SSB_PMURES_4328_BB_PLL_PU));
129 + break;
130 + case 0x5354:
131 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
132 + ~(1 << SSB_PMURES_5354_BB_PLL_PU));
133 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
134 + ~(1 << SSB_PMURES_5354_BB_PLL_PU));
135 + break;
136 + default:
137 + SSB_WARN_ON(1);
138 + }
139 + for (i = 1500; i; i--) {
140 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
141 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
142 + break;
143 + udelay(10);
144 + }
145 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
146 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
147 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
148 +
149 + /* Set PDIV in PLL control 0. */
150 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
151 + if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ)
152 + pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK;
153 + else
154 + pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK;
155 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
156 +
157 + /* Set WILD in PLL control 1. */
158 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
159 + pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD;
160 + pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK);
161 + pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK;
162 + pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK;
163 + if (e->wb_frac == 0)
164 + pllctl |= SSB_PMU0_PLLCTL1_STOPMOD;
165 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
166 +
167 + /* Set WILD in PLL control 2. */
168 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
169 + pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI;
170 + pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI;
171 + ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
172 +
173 + /* Set the crystalfrequency and the divisor. */
174 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
175 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;
176 + pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
177 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
178 + pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;
179 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
180 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
181 +}
182 +
183 +struct pmu1_plltab_entry {
184 + u16 freq; /* Crystal frequency in kHz.*/
185 + u8 xf; /* Crystal frequency value for PMU control */
186 + u8 ndiv_int;
187 + u32 ndiv_frac;
188 + u8 p1div;
189 + u8 p2div;
190 +};
191 +
192 +static const struct pmu1_plltab_entry pmu1_plltab[] = {
193 + { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, },
194 + { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, },
195 + { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, },
196 + { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, },
197 + { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, },
198 + { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, },
199 + { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, },
200 + { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, },
201 + { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, },
202 + { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, },
203 + { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, },
204 + { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
205 + { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, },
206 + { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, },
207 + { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, },
208 +};
209 +
210 +#define SSB_PMU1_DEFAULT_XTALFREQ 15360
211 +
212 +static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq)
213 +{
214 + const struct pmu1_plltab_entry *e;
215 + unsigned int i;
216 +
217 + for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) {
218 + e = &pmu1_plltab[i];
219 + if (e->freq == crystalfreq)
220 + return e;
221 + }
222 +
223 + return NULL;
224 +}
225 +
226 +/* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
227 +static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
228 + u32 crystalfreq)
229 +{
230 + struct ssb_bus *bus = cc->dev->bus;
231 + const struct pmu1_plltab_entry *e = NULL;
232 + u32 buffer_strength = 0;
233 + u32 tmp, pllctl, pmuctl;
234 + unsigned int i;
235 +
236 + if (bus->chip_id == 0x4312) {
237 + /* We do not touch the BCM4312 PLL and assume
238 + * the default crystal settings work out-of-the-box. */
239 + cc->pmu.crystalfreq = 20000;
240 + return;
241 + }
242 +
243 + if (crystalfreq)
244 + e = pmu1_plltab_find_entry(crystalfreq);
245 + if (!e)
246 + e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ);
247 + BUG_ON(!e);
248 + crystalfreq = e->freq;
249 + cc->pmu.crystalfreq = e->freq;
250 +
251 + /* Check if the PLL already is programmed to this frequency. */
252 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
253 + if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
254 + /* We're already there... */
255 + return;
256 + }
257 +
258 + ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
259 + (crystalfreq / 1000), (crystalfreq % 1000));
260 +
261 + /* First turn the PLL off. */
262 + switch (bus->chip_id) {
263 + case 0x4325:
264 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
265 + ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
266 + (1 << SSB_PMURES_4325_HT_AVAIL)));
267 + chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
268 + ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
269 + (1 << SSB_PMURES_4325_HT_AVAIL)));
270 + /* Adjust the BBPLL to 2 on all channels later. */
271 + buffer_strength = 0x222222;
272 + break;
273 + default:
274 + SSB_WARN_ON(1);
275 + }
276 + for (i = 1500; i; i--) {
277 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
278 + if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
279 + break;
280 + udelay(10);
281 + }
282 + tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
283 + if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
284 + ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
285 +
286 + /* Set p1div and p2div. */
287 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
288 + pllctl &= ~(SSB_PMU1_PLLCTL0_P1DIV | SSB_PMU1_PLLCTL0_P2DIV);
289 + pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV;
290 + pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV;
291 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
292 +
293 + /* Set ndiv int and ndiv mode */
294 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2);
295 + pllctl &= ~(SSB_PMU1_PLLCTL2_NDIVINT | SSB_PMU1_PLLCTL2_NDIVMODE);
296 + pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT;
297 + pllctl |= (1 << SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT) & SSB_PMU1_PLLCTL2_NDIVMODE;
298 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
299 +
300 + /* Set ndiv frac */
301 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3);
302 + pllctl &= ~SSB_PMU1_PLLCTL3_NDIVFRAC;
303 + pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC;
304 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
305 +
306 + /* Change the drive strength, if required. */
307 + if (buffer_strength) {
308 + pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5);
309 + pllctl &= ~SSB_PMU1_PLLCTL5_CLKDRV;
310 + pllctl |= (buffer_strength << SSB_PMU1_PLLCTL5_CLKDRV_SHIFT) & SSB_PMU1_PLLCTL5_CLKDRV;
311 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
312 + }
313 +
314 + /* Tune the crystalfreq and the divisor. */
315 + pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
316 + pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ);
317 + pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
318 + & SSB_CHIPCO_PMU_CTL_ILP_DIV;
319 + pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
320 + chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
321 +}
322 +
323 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
324 +{
325 + struct ssb_bus *bus = cc->dev->bus;
326 + u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
327 +
328 + if (bus->bustype == SSB_BUSTYPE_SSB) {
329 + /* TODO: The user may override the crystal frequency. */
330 + }
331 +
332 + switch (bus->chip_id) {
333 + case 0x4312:
334 + case 0x4325:
335 + ssb_pmu1_pllinit_r0(cc, crystalfreq);
336 + break;
337 + case 0x4328:
338 + case 0x5354:
339 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
340 + break;
341 + default:
342 + ssb_printk(KERN_ERR PFX
343 + "ERROR: PLL init unknown for device %04X\n",
344 + bus->chip_id);
345 + }
346 +}
347 +
348 +struct pmu_res_updown_tab_entry {
349 + u8 resource; /* The resource number */
350 + u16 updown; /* The updown value */
351 +};
352 +
353 +enum pmu_res_depend_tab_task {
354 + PMU_RES_DEP_SET = 1,
355 + PMU_RES_DEP_ADD,
356 + PMU_RES_DEP_REMOVE,
357 +};
358 +
359 +struct pmu_res_depend_tab_entry {
360 + u8 resource; /* The resource number */
361 + u8 task; /* SET | ADD | REMOVE */
362 + u32 depend; /* The depend mask */
363 +};
364 +
365 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
366 + { .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
367 + { .resource = SSB_PMURES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
368 + { .resource = SSB_PMURES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
369 + { .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
370 + { .resource = SSB_PMURES_4328_ILP_REQUEST, .updown = 0x0202, },
371 + { .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
372 + { .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
373 + { .resource = SSB_PMURES_4328_ROM_SWITCH, .updown = 0x0101, },
374 + { .resource = SSB_PMURES_4328_PA_REF_LDO, .updown = 0x0F01, },
375 + { .resource = SSB_PMURES_4328_RADIO_LDO, .updown = 0x0F01, },
376 + { .resource = SSB_PMURES_4328_AFE_LDO, .updown = 0x0F01, },
377 + { .resource = SSB_PMURES_4328_PLL_LDO, .updown = 0x0F01, },
378 + { .resource = SSB_PMURES_4328_BG_FILTBYP, .updown = 0x0101, },
379 + { .resource = SSB_PMURES_4328_TX_FILTBYP, .updown = 0x0101, },
380 + { .resource = SSB_PMURES_4328_RX_FILTBYP, .updown = 0x0101, },
381 + { .resource = SSB_PMURES_4328_XTAL_PU, .updown = 0x0101, },
382 + { .resource = SSB_PMURES_4328_XTAL_EN, .updown = 0xA001, },
383 + { .resource = SSB_PMURES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
384 + { .resource = SSB_PMURES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
385 + { .resource = SSB_PMURES_4328_BB_PLL_PU, .updown = 0x0701, },
386 +};
387 +
388 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
389 + {
390 + /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
391 + .resource = SSB_PMURES_4328_ILP_REQUEST,
392 + .task = PMU_RES_DEP_SET,
393 + .depend = ((1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
394 + (1 << SSB_PMURES_4328_BB_SWITCHER_PWM)),
395 + },
396 +};
397 +
398 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
399 + { .resource = SSB_PMURES_4325_XTAL_PU, .updown = 0x1501, },
400 +};
401 +
402 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
403 + {
404 + /* Adjust HT-Available dependencies. */
405 + .resource = SSB_PMURES_4325_HT_AVAIL,
406 + .task = PMU_RES_DEP_ADD,
407 + .depend = ((1 << SSB_PMURES_4325_RX_PWRSW_PU) |
408 + (1 << SSB_PMURES_4325_TX_PWRSW_PU) |
409 + (1 << SSB_PMURES_4325_LOGEN_PWRSW_PU) |
410 + (1 << SSB_PMURES_4325_AFE_PWRSW_PU)),
411 + },
412 +};
413 +
414 +static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
415 +{
416 + struct ssb_bus *bus = cc->dev->bus;
417 + u32 min_msk = 0, max_msk = 0;
418 + unsigned int i;
419 + const struct pmu_res_updown_tab_entry *updown_tab = NULL;
420 + unsigned int updown_tab_size;
421 + const struct pmu_res_depend_tab_entry *depend_tab = NULL;
422 + unsigned int depend_tab_size;
423 +
424 + switch (bus->chip_id) {
425 + case 0x4312:
426 + /* We keep the default settings:
427 + * min_msk = 0xCBB
428 + * max_msk = 0x7FFFF
429 + */
430 + break;
431 + case 0x4325:
432 + /* Power OTP down later. */
433 + min_msk = (1 << SSB_PMURES_4325_CBUCK_BURST) |
434 + (1 << SSB_PMURES_4325_LNLDO2_PU);
435 + if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
436 + SSB_CHIPCO_CHST_4325_PMUTOP_2B)
437 + min_msk |= (1 << SSB_PMURES_4325_CLDO_CBUCK_BURST);
438 + /* The PLL may turn on, if it decides so. */
439 + max_msk = 0xFFFFF;
440 + updown_tab = pmu_res_updown_tab_4325a0;
441 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4325a0);
442 + depend_tab = pmu_res_depend_tab_4325a0;
443 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
444 + break;
445 + case 0x4328:
446 + min_msk = (1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
447 + (1 << SSB_PMURES_4328_BB_SWITCHER_PWM) |
448 + (1 << SSB_PMURES_4328_XTAL_EN);
449 + /* The PLL may turn on, if it decides so. */
450 + max_msk = 0xFFFFF;
451 + updown_tab = pmu_res_updown_tab_4328a0;
452 + updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4328a0);
453 + depend_tab = pmu_res_depend_tab_4328a0;
454 + depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4328a0);
455 + break;
456 + case 0x5354:
457 + /* The PLL may turn on, if it decides so. */
458 + max_msk = 0xFFFFF;
459 + break;
460 + default:
461 + ssb_printk(KERN_ERR PFX
462 + "ERROR: PMU resource config unknown for device %04X\n",
463 + bus->chip_id);
464 + }
465 +
466 + if (updown_tab) {
467 + for (i = 0; i < updown_tab_size; i++) {
468 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
469 + updown_tab[i].resource);
470 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM,
471 + updown_tab[i].updown);
472 + }
473 + }
474 + if (depend_tab) {
475 + for (i = 0; i < depend_tab_size; i++) {
476 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
477 + depend_tab[i].resource);
478 + switch (depend_tab[i].task) {
479 + case PMU_RES_DEP_SET:
480 + chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
481 + depend_tab[i].depend);
482 + break;
483 + case PMU_RES_DEP_ADD:
484 + chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
485 + depend_tab[i].depend);
486 + break;
487 + case PMU_RES_DEP_REMOVE:
488 + chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
489 + ~(depend_tab[i].depend));
490 + break;
491 + default:
492 + SSB_WARN_ON(1);
493 + }
494 + }
495 + }
496 +
497 + /* Set the resource masks. */
498 + if (min_msk)
499 + chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
500 + if (max_msk)
501 + chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
502 +}
503 +
504 +void ssb_pmu_init(struct ssb_chipcommon *cc)
505 +{
506 + struct ssb_bus *bus = cc->dev->bus;
507 + u32 pmucap;
508 +
509 + if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
510 + return;
511 +
512 + pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
513 + cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
514 +
515 + ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
516 + cc->pmu.rev, pmucap);
517 +
518 + if (cc->pmu.rev >= 1) {
519 + if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
520 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
521 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
522 + } else {
523 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
524 + SSB_CHIPCO_PMU_CTL_NOILPONW);
525 + }
526 + }
527 + ssb_pmu_pll_init(cc);
528 + ssb_pmu_resources_init(cc);
529 +}
530 --- a/drivers/ssb/driver_chipcommon.c
531 +++ b/drivers/ssb/driver_chipcommon.c
532 @@ -26,19 +26,6 @@ enum ssb_clksrc {
533 };
534
535
536 -static inline u32 chipco_read32(struct ssb_chipcommon *cc,
537 - u16 offset)
538 -{
539 - return ssb_read32(cc->dev, offset);
540 -}
541 -
542 -static inline void chipco_write32(struct ssb_chipcommon *cc,
543 - u16 offset,
544 - u32 value)
545 -{
546 - ssb_write32(cc->dev, offset, value);
547 -}
548 -
549 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
550 u32 mask, u32 value)
551 {
552 @@ -246,6 +233,7 @@ void ssb_chipcommon_init(struct ssb_chip
553 {
554 if (!cc->dev)
555 return; /* We don't have a ChipCommon */
556 + ssb_pmu_init(cc);
557 chipco_powercontrol_init(cc);
558 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
559 calc_fast_powerup_delay(cc);
560 --- a/include/linux/ssb/ssb_driver_chipcommon.h
561 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
562 @@ -181,6 +181,16 @@
563 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
564 #define SSB_CHIPCO_FLASH_CFG 0x0128
565 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
566 +#define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
567 +#define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
568 +#define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
569 +#define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
570 +#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
571 +#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
572 +#define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
573 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
574 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
575 +#define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
576 #define SSB_CHIPCO_UART0_DATA 0x0300
577 #define SSB_CHIPCO_UART0_IMR 0x0304
578 #define SSB_CHIPCO_UART0_FCR 0x0308
579 @@ -197,6 +207,196 @@
580 #define SSB_CHIPCO_UART1_LSR 0x0414
581 #define SSB_CHIPCO_UART1_MSR 0x0418
582 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
583 +/* PMU registers (rev >= 20) */
584 +#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
585 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
586 +#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
587 +#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
588 +#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
589 +#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
590 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
591 +#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2
592 +#define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
593 +#define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
594 +#define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */
595 +#define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */
596 +#define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
597 +#define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
598 +#define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
599 +#define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
600 +#define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */
601 +#define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */
602 +#define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
603 +#define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */
604 +#define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */
605 +#define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
606 +#define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
607 +#define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
608 +#define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
609 +#define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
610 +#define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */
611 +#define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
612 +#define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */
613 +#define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
614 +#define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */
615 +#define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */
616 +#define SSB_CHIPCO_CHIPCTL_ADDR 0x0650
617 +#define SSB_CHIPCO_CHIPCTL_DATA 0x0654
618 +#define SSB_CHIPCO_REGCTL_ADDR 0x0658
619 +#define SSB_CHIPCO_REGCTL_DATA 0x065C
620 +#define SSB_CHIPCO_PLLCTL_ADDR 0x0660
621 +#define SSB_CHIPCO_PLLCTL_DATA 0x0664
622 +
623 +
624 +
625 +/** PMU PLL registers */
626 +
627 +/* PMU rev 0 PLL registers */
628 +#define SSB_PMU0_PLLCTL0 0
629 +#define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001
630 +#define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */
631 +#define SSB_PMU0_PLLCTL1 1
632 +#define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
633 +#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28
634 +#define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */
635 +#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8
636 +#define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */
637 +#define SSB_PMU0_PLLCTL2 2
638 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */
639 +#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0
640 +
641 +/* PMU rev 1 PLL registers */
642 +#define SSB_PMU1_PLLCTL0 0
643 +#define SSB_PMU1_PLLCTL0_P1DIV 0x00F00000 /* P1 div */
644 +#define SSB_PMU1_PLLCTL0_P1DIV_SHIFT 20
645 +#define SSB_PMU1_PLLCTL0_P2DIV 0x0F000000 /* P2 div */
646 +#define SSB_PMU1_PLLCTL0_P2DIV_SHIFT 24
647 +#define SSB_PMU1_PLLCTL1 1
648 +#define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */
649 +#define SSB_PMU1_PLLCTL1_M1DIV_SHIFT 0
650 +#define SSB_PMU1_PLLCTL1_M2DIV 0x0000FF00 /* M2 div */
651 +#define SSB_PMU1_PLLCTL1_M2DIV_SHIFT 8
652 +#define SSB_PMU1_PLLCTL1_M3DIV 0x00FF0000 /* M3 div */
653 +#define SSB_PMU1_PLLCTL1_M3DIV_SHIFT 16
654 +#define SSB_PMU1_PLLCTL1_M4DIV 0xFF000000 /* M4 div */
655 +#define SSB_PMU1_PLLCTL1_M4DIV_SHIFT 24
656 +#define SSB_PMU1_PLLCTL2 2
657 +#define SSB_PMU1_PLLCTL2_M5DIV 0x000000FF /* M5 div */
658 +#define SSB_PMU1_PLLCTL2_M5DIV_SHIFT 0
659 +#define SSB_PMU1_PLLCTL2_M6DIV 0x0000FF00 /* M6 div */
660 +#define SSB_PMU1_PLLCTL2_M6DIV_SHIFT 8
661 +#define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
662 +#define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT 17
663 +#define SSB_PMU1_PLLCTL2_NDIVINT 0x1FF00000 /* NDIV int */
664 +#define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT 20
665 +#define SSB_PMU1_PLLCTL3 3
666 +#define SSB_PMU1_PLLCTL3_NDIVFRAC 0x00FFFFFF /* NDIV frac */
667 +#define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT 0
668 +#define SSB_PMU1_PLLCTL4 4
669 +#define SSB_PMU1_PLLCTL5 5
670 +#define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */
671 +#define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT 8
672 +
673 +/* BCM4312 PLL resource numbers. */
674 +#define SSB_PMURES_4312_SWITCHER_BURST 0
675 +#define SSB_PMURES_4312_SWITCHER_PWM 1
676 +#define SSB_PMURES_4312_PA_REF_LDO 2
677 +#define SSB_PMURES_4312_CORE_LDO_BURST 3
678 +#define SSB_PMURES_4312_CORE_LDO_PWM 4
679 +#define SSB_PMURES_4312_RADIO_LDO 5
680 +#define SSB_PMURES_4312_ILP_REQUEST 6
681 +#define SSB_PMURES_4312_BG_FILTBYP 7
682 +#define SSB_PMURES_4312_TX_FILTBYP 8
683 +#define SSB_PMURES_4312_RX_FILTBYP 9
684 +#define SSB_PMURES_4312_XTAL_PU 10
685 +#define SSB_PMURES_4312_ALP_AVAIL 11
686 +#define SSB_PMURES_4312_BB_PLL_FILTBYP 12
687 +#define SSB_PMURES_4312_RF_PLL_FILTBYP 13
688 +#define SSB_PMURES_4312_HT_AVAIL 14
689 +
690 +/* BCM4325 PLL resource numbers. */
691 +#define SSB_PMURES_4325_BUCK_BOOST_BURST 0
692 +#define SSB_PMURES_4325_CBUCK_BURST 1
693 +#define SSB_PMURES_4325_CBUCK_PWM 2
694 +#define SSB_PMURES_4325_CLDO_CBUCK_BURST 3
695 +#define SSB_PMURES_4325_CLDO_CBUCK_PWM 4
696 +#define SSB_PMURES_4325_BUCK_BOOST_PWM 5
697 +#define SSB_PMURES_4325_ILP_REQUEST 6
698 +#define SSB_PMURES_4325_ABUCK_BURST 7
699 +#define SSB_PMURES_4325_ABUCK_PWM 8
700 +#define SSB_PMURES_4325_LNLDO1_PU 9
701 +#define SSB_PMURES_4325_LNLDO2_PU 10
702 +#define SSB_PMURES_4325_LNLDO3_PU 11
703 +#define SSB_PMURES_4325_LNLDO4_PU 12
704 +#define SSB_PMURES_4325_XTAL_PU 13
705 +#define SSB_PMURES_4325_ALP_AVAIL 14
706 +#define SSB_PMURES_4325_RX_PWRSW_PU 15
707 +#define SSB_PMURES_4325_TX_PWRSW_PU 16
708 +#define SSB_PMURES_4325_RFPLL_PWRSW_PU 17
709 +#define SSB_PMURES_4325_LOGEN_PWRSW_PU 18
710 +#define SSB_PMURES_4325_AFE_PWRSW_PU 19
711 +#define SSB_PMURES_4325_BBPLL_PWRSW_PU 20
712 +#define SSB_PMURES_4325_HT_AVAIL 21
713 +
714 +/* BCM4328 PLL resource numbers. */
715 +#define SSB_PMURES_4328_EXT_SWITCHER_PWM 0
716 +#define SSB_PMURES_4328_BB_SWITCHER_PWM 1
717 +#define SSB_PMURES_4328_BB_SWITCHER_BURST 2
718 +#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST 3
719 +#define SSB_PMURES_4328_ILP_REQUEST 4
720 +#define SSB_PMURES_4328_RADIO_SWITCHER_PWM 5
721 +#define SSB_PMURES_4328_RADIO_SWITCHER_BURST 6
722 +#define SSB_PMURES_4328_ROM_SWITCH 7
723 +#define SSB_PMURES_4328_PA_REF_LDO 8
724 +#define SSB_PMURES_4328_RADIO_LDO 9
725 +#define SSB_PMURES_4328_AFE_LDO 10
726 +#define SSB_PMURES_4328_PLL_LDO 11
727 +#define SSB_PMURES_4328_BG_FILTBYP 12
728 +#define SSB_PMURES_4328_TX_FILTBYP 13
729 +#define SSB_PMURES_4328_RX_FILTBYP 14
730 +#define SSB_PMURES_4328_XTAL_PU 15
731 +#define SSB_PMURES_4328_XTAL_EN 16
732 +#define SSB_PMURES_4328_BB_PLL_FILTBYP 17
733 +#define SSB_PMURES_4328_RF_PLL_FILTBYP 18
734 +#define SSB_PMURES_4328_BB_PLL_PU 19
735 +
736 +/* BCM5354 PLL resource numbers. */
737 +#define SSB_PMURES_5354_EXT_SWITCHER_PWM 0
738 +#define SSB_PMURES_5354_BB_SWITCHER_PWM 1
739 +#define SSB_PMURES_5354_BB_SWITCHER_BURST 2
740 +#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST 3
741 +#define SSB_PMURES_5354_ILP_REQUEST 4
742 +#define SSB_PMURES_5354_RADIO_SWITCHER_PWM 5
743 +#define SSB_PMURES_5354_RADIO_SWITCHER_BURST 6
744 +#define SSB_PMURES_5354_ROM_SWITCH 7
745 +#define SSB_PMURES_5354_PA_REF_LDO 8
746 +#define SSB_PMURES_5354_RADIO_LDO 9
747 +#define SSB_PMURES_5354_AFE_LDO 10
748 +#define SSB_PMURES_5354_PLL_LDO 11
749 +#define SSB_PMURES_5354_BG_FILTBYP 12
750 +#define SSB_PMURES_5354_TX_FILTBYP 13
751 +#define SSB_PMURES_5354_RX_FILTBYP 14
752 +#define SSB_PMURES_5354_XTAL_PU 15
753 +#define SSB_PMURES_5354_XTAL_EN 16
754 +#define SSB_PMURES_5354_BB_PLL_FILTBYP 17
755 +#define SSB_PMURES_5354_RF_PLL_FILTBYP 18
756 +#define SSB_PMURES_5354_BB_PLL_PU 19
757 +
758 +
759 +
760 +/** Chip specific Chip-Status register contents. */
761 +#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
762 +#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
763 +#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
764 +#define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
765 +#define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
766 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004
767 +#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2
768 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008
769 +#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT 3
770 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0
771 +#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
772 +#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
773
774
775
776 @@ -353,11 +553,20 @@
777 struct ssb_device;
778 struct ssb_serial_port;
779
780 +/* Data for the PMU, if available.
781 + * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU)
782 + */
783 +struct ssb_chipcommon_pmu {
784 + u8 rev; /* PMU revision */
785 + u32 crystalfreq; /* The active crystal frequency (in kHz) */
786 +};
787 +
788 struct ssb_chipcommon {
789 struct ssb_device *dev;
790 u32 capabilities;
791 /* Fast Powerup Delay constant */
792 u16 fast_pwrup_delay;
793 + struct ssb_chipcommon_pmu pmu;
794 };
795
796 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
797 @@ -365,6 +574,17 @@ static inline bool ssb_chipco_available(
798 return (cc->dev != NULL);
799 }
800
801 +/* Register access */
802 +#define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset)
803 +#define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val)
804 +
805 +#define chipco_mask32(cc, offset, mask) \
806 + chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
807 +#define chipco_set32(cc, offset, set) \
808 + chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
809 +#define chipco_maskset32(cc, offset, mask, set) \
810 + chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
811 +
812 extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
813
814 extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
815 @@ -406,4 +626,8 @@ extern int ssb_chipco_serial_init(struct
816 struct ssb_serial_port *ports);
817 #endif /* CONFIG_SSB_SERIAL */
818
819 +/* PMU support */
820 +extern void ssb_pmu_init(struct ssb_chipcommon *cc);
821 +
822 +
823 #endif /* LINUX_SSB_CHIPCO_H_ */
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