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[openwrt.git] / target / linux / brcm-2.4 / patches / 008-b44_bcm47xx_support.patch
1 Index: linux-2.4.35.4/drivers/net/b44.c
2 ===================================================================
3 --- linux-2.4.35.4.orig/drivers/net/b44.c 2007-12-15 05:19:36.094477944 +0100
4 +++ linux-2.4.35.4/drivers/net/b44.c 2007-12-15 05:20:16.020753214 +0100
5 @@ -1,7 +1,9 @@
6 /* b44.c: Broadcom 4400 device driver.
7 *
8 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
9 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
10 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
11 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
12 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
13 *
14 * Distribute under GPL.
15 */
16 @@ -25,6 +27,39 @@
17
18 #include "b44.h"
19
20 +#include <typedefs.h>
21 +#include <bcmdevs.h>
22 +#include <osl.h>
23 +#include <bcmnvram.h>
24 +#include <sbconfig.h>
25 +#include <sbchipc.h>
26 +#include <sflash.h>
27 +
28 +#ifdef CONFIG_BCM947XX
29 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
30 +
31 +static inline void e_aton(char *str, char *dest)
32 +{
33 + int i = 0;
34 + u16 *d = (u16 *) dest;
35 +
36 + if (str == NULL) {
37 + memset(dest, 0, 6);
38 + return;
39 + }
40 +
41 + for (;;) {
42 + dest[i++] = (char) simple_strtoul(str, NULL, 16);
43 + str += 2;
44 + if (!*str++ || i == 6)
45 + break;
46 + }
47 +}
48 +
49 +static int instance = 0;
50 +#endif
51 +
52 +
53 #define DRV_MODULE_NAME "b44"
54 #define PFX DRV_MODULE_NAME ": "
55 #define DRV_MODULE_VERSION "0.93"
56 @@ -75,7 +112,7 @@
57 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
58
59 MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
60 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
61 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
62 MODULE_LICENSE("GPL");
63 MODULE_PARM(b44_debug, "i");
64 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
65 @@ -89,6 +126,8 @@
66 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
67 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
68 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
69 + { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
70 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
71 { } /* terminate list with empty entry */
72 };
73
74 @@ -113,11 +152,13 @@
75 udelay(10);
76 }
77 if (i == timeout) {
78 +#ifdef DEBUG
79 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
80 "%lx to %s.\n",
81 bp->dev->name,
82 bit, reg,
83 (clear ? "clear" : "set"));
84 +#endif
85 return -ENODEV;
86 }
87 return 0;
88 @@ -236,6 +277,8 @@
89 udelay(1);
90 }
91
92 +static int b44_4713_instance;
93 +
94 static int ssb_core_unit(struct b44 *bp)
95 {
96 #if 0
97 @@ -258,6 +301,9 @@
98 break;
99 };
100 #endif
101 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
102 + return b44_4713_instance++;
103 + else
104 return 0;
105 }
106
107 @@ -267,6 +313,28 @@
108 == SBTMSLOW_CLOCK);
109 }
110
111 +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
112 +{
113 + u32 val;
114 +
115 + bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
116 + (index << CAM_CTRL_INDEX_SHIFT)));
117 +
118 + b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
119 +
120 + val = br32(B44_CAM_DATA_LO);
121 +
122 + data[2] = (val >> 24) & 0xFF;
123 + data[3] = (val >> 16) & 0xFF;
124 + data[4] = (val >> 8) & 0xFF;
125 + data[5] = (val >> 0) & 0xFF;
126 +
127 + val = br32(B44_CAM_DATA_HI);
128 +
129 + data[0] = (val >> 8) & 0xFF;
130 + data[1] = (val >> 0) & 0xFF;
131 +}
132 +
133 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
134 {
135 u32 val;
136 @@ -287,7 +355,7 @@
137
138 static inline void __b44_disable_ints(struct b44 *bp)
139 {
140 - bw32(B44_IMASK, 0);
141 + bw32(B44_IMASK, ISTAT_TO); /* leave the timeout interrupt active */
142 }
143
144 static void b44_disable_ints(struct b44 *bp)
145 @@ -303,14 +371,14 @@
146 bw32(B44_IMASK, bp->imask);
147 }
148
149 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
150 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
151 {
152 int err;
153
154 bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
155 bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
156 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
157 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
158 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
159 (reg << MDIO_DATA_RA_SHIFT) |
160 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
161 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
162 @@ -319,23 +387,42 @@
163 return err;
164 }
165
166 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
167 +static int b44_readphy(struct b44 *bp, int reg, u32 *val)
168 +{
169 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
170 + return 0;
171 +
172 + return __b44_readphy(bp, bp->phy_addr, reg, val);
173 +}
174 +
175 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
176 {
177 bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
178 bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
179 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
180 - (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
181 + (phy_addr << MDIO_DATA_PMD_SHIFT) |
182 (reg << MDIO_DATA_RA_SHIFT) |
183 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
184 (val & MDIO_DATA_DATA)));
185 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
186 }
187
188 +static int b44_writephy(struct b44 *bp, int reg, u32 val)
189 +{
190 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
191 + return 0;
192 +
193 + return __b44_writephy(bp, bp->phy_addr, reg, val);
194 +}
195 +
196 static int b44_phy_reset(struct b44 *bp)
197 {
198 u32 val;
199 int err;
200
201 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
202 + return 0;
203 +
204 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
205 if (err)
206 return err;
207 @@ -406,6 +493,23 @@
208 u32 val;
209 int err;
210
211 +
212 + /*
213 + * workaround for bad hardware design in Linksys WAP54G v1.0
214 + * see https://dev.openwrt.org/ticket/146
215 + * check and reset bit "isolate"
216 + */
217 + if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) &&
218 + (atoi(nvram_get("boardnum")) == 2) &&
219 + (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
220 + (val & BMCR_ISOLATE) &&
221 + (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
222 + printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
223 + }
224 +
225 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
226 + return 0;
227 +
228 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
229 goto out;
230 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
231 @@ -498,6 +602,19 @@
232 {
233 u32 bmsr, aux;
234
235 + if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
236 + bp->flags |= B44_FLAG_100_BASE_T;
237 + bp->flags |= B44_FLAG_FULL_DUPLEX;
238 + if (!netif_carrier_ok(bp->dev)) {
239 + u32 val = br32(B44_TX_CTRL);
240 + val |= TX_CTRL_DUPLEX;
241 + bw32(B44_TX_CTRL, val);
242 + netif_carrier_on(bp->dev);
243 + b44_link_report(bp);
244 + }
245 + return;
246 + }
247 +
248 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
249 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
250 (bmsr != 0xffff)) {
251 @@ -765,6 +882,25 @@
252 return received;
253 }
254
255 +
256 +static inline void __b44_reset(struct b44 *bp)
257 +{
258 + spin_lock_irq(&bp->lock);
259 + b44_halt(bp);
260 + b44_init_rings(bp);
261 + b44_init_hw(bp);
262 + spin_unlock_irq(&bp->lock);
263 +
264 + b44_enable_ints(bp);
265 + netif_wake_queue(bp->dev);
266 +}
267 +
268 +static inline void __b44_set_timeout(struct b44 *bp, int timeout)
269 +{
270 + /* Set timeout for Rx to two seconds after the last Tx */
271 + bw32(B44_GPTIMER, timeout ? 2 * 125000000 : 0);
272 +}
273 +
274 static int b44_poll(struct net_device *netdev, int *budget)
275 {
276 struct b44 *bp = netdev->priv;
277 @@ -772,13 +908,13 @@
278
279 spin_lock_irq(&bp->lock);
280
281 - if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
282 + if (bp->istat & ISTAT_TX) {
283 /* spin_lock(&bp->tx_lock); */
284 b44_tx(bp);
285 /* spin_unlock(&bp->tx_lock); */
286 }
287 spin_unlock_irq(&bp->lock);
288 -
289 +
290 done = 1;
291 if (bp->istat & ISTAT_RX) {
292 int orig_budget = *budget;
293 @@ -796,24 +932,18 @@
294 done = 0;
295 }
296
297 - if (bp->istat & ISTAT_ERRORS) {
298 - spin_lock_irq(&bp->lock);
299 - b44_halt(bp);
300 - b44_init_rings(bp);
301 - b44_init_hw(bp);
302 - netif_wake_queue(bp->dev);
303 - spin_unlock_irq(&bp->lock);
304 - done = 1;
305 - }
306 -
307 if (done) {
308 netif_rx_complete(netdev);
309 b44_enable_ints(bp);
310 }
311
312 + if ((bp->core_unit == 1) && (bp->istat & (ISTAT_TX | ISTAT_RX)))
313 + __b44_set_timeout(bp, (bp->istat & ISTAT_TX) ? 1 : 0);
314 +
315 return (done ? 0 : 1);
316 }
317
318 +
319 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
320 {
321 struct net_device *dev = dev_id;
322 @@ -832,6 +962,18 @@
323 */
324 istat &= imask;
325 if (istat) {
326 + /* Workaround for the WL-500g WAN port hang */
327 + if (istat & (ISTAT_TO | ISTAT_ERRORS)) {
328 + /*
329 + * no rx before the watchdog timeout
330 + * reset the interface
331 + */
332 + __b44_reset(bp);
333 + }
334 +
335 + if ((bp->core_unit == 1) && (bp->istat & (ISTAT_TX | ISTAT_RX)))
336 + __b44_set_timeout(bp, (bp->istat & ISTAT_TX) ? 1 : 0);
337 +
338 handled = 1;
339 if (netif_rx_schedule_prep(dev)) {
340 /* NOTE: These writes are posted by the readback of
341 @@ -848,6 +990,7 @@
342 bw32(B44_ISTAT, istat);
343 br32(B44_ISTAT);
344 }
345 +
346 spin_unlock_irqrestore(&bp->lock, flags);
347 return IRQ_RETVAL(handled);
348 }
349 @@ -859,16 +1002,7 @@
350 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
351 dev->name);
352
353 - spin_lock_irq(&bp->lock);
354 -
355 - b44_halt(bp);
356 - b44_init_rings(bp);
357 - b44_init_hw(bp);
358 -
359 - spin_unlock_irq(&bp->lock);
360 -
361 - b44_enable_ints(bp);
362 -
363 + __b44_reset(bp);
364 netif_wake_queue(dev);
365 }
366
367 @@ -1092,6 +1226,8 @@
368 /* bp->lock is held. */
369 static void b44_chip_reset(struct b44 *bp)
370 {
371 + unsigned int sb_clock;
372 +
373 if (ssb_is_core_up(bp)) {
374 bw32(B44_RCV_LAZY, 0);
375 bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
376 @@ -1105,9 +1241,10 @@
377 bw32(B44_DMARX_CTRL, 0);
378 bp->rx_prod = bp->rx_cons = 0;
379 } else {
380 - ssb_pci_setup(bp, (bp->core_unit == 0 ?
381 - SBINTVEC_ENET0 :
382 - SBINTVEC_ENET1));
383 + /*if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)*/
384 + ssb_pci_setup(bp, (bp->core_unit == 0 ?
385 + SBINTVEC_ENET0 :
386 + SBINTVEC_ENET1));
387 }
388
389 ssb_core_reset(bp);
390 @@ -1115,6 +1252,11 @@
391 b44_clear_stats(bp);
392
393 /* Make PHY accessible. */
394 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
395 + sb_clock = 100000000; /* 100 MHz */
396 + else
397 + sb_clock = 62500000; /* 62.5 MHz */
398 +
399 bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
400 (0x0d & MDIO_CTRL_MAXF_MASK)));
401 br32(B44_MDIO_CTRL);
402 @@ -1216,6 +1358,8 @@
403 struct b44 *bp = dev->priv;
404 int err;
405
406 + netif_carrier_off(dev);
407 +
408 err = b44_alloc_consistent(bp);
409 if (err)
410 return err;
411 @@ -1236,9 +1380,10 @@
412 bp->timer.expires = jiffies + HZ;
413 bp->timer.data = (unsigned long) bp;
414 bp->timer.function = b44_timer;
415 - add_timer(&bp->timer);
416 + b44_timer((unsigned long) bp);
417
418 b44_enable_ints(bp);
419 + netif_start_queue(dev);
420
421 return 0;
422
423 @@ -1638,7 +1783,7 @@
424 u32 mii_regval;
425
426 spin_lock_irq(&bp->lock);
427 - err = b44_readphy(bp, data->reg_num & 0x1f, &mii_regval);
428 + err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
429 spin_unlock_irq(&bp->lock);
430
431 data->val_out = mii_regval;
432 @@ -1651,7 +1796,7 @@
433 return -EPERM;
434
435 spin_lock_irq(&bp->lock);
436 - err = b44_writephy(bp, data->reg_num & 0x1f, data->val_in);
437 + err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
438 spin_unlock_irq(&bp->lock);
439
440 return err;
441 @@ -1678,21 +1823,52 @@
442 static int __devinit b44_get_invariants(struct b44 *bp)
443 {
444 u8 eeprom[128];
445 + u8 buf[32];
446 int err;
447 + unsigned long flags;
448
449 - err = b44_read_eeprom(bp, &eeprom[0]);
450 - if (err)
451 - goto out;
452 -
453 - bp->dev->dev_addr[0] = eeprom[79];
454 - bp->dev->dev_addr[1] = eeprom[78];
455 - bp->dev->dev_addr[2] = eeprom[81];
456 - bp->dev->dev_addr[3] = eeprom[80];
457 - bp->dev->dev_addr[4] = eeprom[83];
458 - bp->dev->dev_addr[5] = eeprom[82];
459 -
460 - bp->phy_addr = eeprom[90] & 0x1f;
461 - bp->mdc_port = (eeprom[90] >> 14) & 0x1;
462 + if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
463 +#ifdef CONFIG_BCM947XX
464 + sprintf(buf, "et%dmacaddr", instance - 1);
465 + e_aton(nvram_get(buf), bp->dev->dev_addr);
466 +
467 + sprintf(buf, "et%dphyaddr", instance - 1);
468 + bp->phy_addr = B44_PHY_ADDR_NO_PHY;
469 +#else
470 + /*
471 + * BCM47xx boards don't have a EEPROM. The MAC is stored in
472 + * a NVRAM area somewhere in the flash memory. As we don't
473 + * know the location and/or the format of the NVRAM area
474 + * here, we simply rely on the bootloader to write the
475 + * MAC into the CAM.
476 + */
477 + spin_lock_irqsave(&bp->lock, flags);
478 + __b44_cam_read(bp, bp->dev->dev_addr, 0);
479 + spin_unlock_irqrestore(&bp->lock, flags);
480 +
481 + /*
482 + * BCM47xx boards don't have a PHY. Usually there is a switch
483 + * chip with multiple PHYs connected to the PHY port.
484 + */
485 + bp->phy_addr = B44_PHY_ADDR_NO_PHY;
486 +#endif
487 + bp->dma_offset = 0;
488 + } else {
489 + err = b44_read_eeprom(bp, &eeprom[0]);
490 + if (err)
491 + return err;
492 +
493 + bp->dev->dev_addr[0] = eeprom[79];
494 + bp->dev->dev_addr[1] = eeprom[78];
495 + bp->dev->dev_addr[2] = eeprom[81];
496 + bp->dev->dev_addr[3] = eeprom[80];
497 + bp->dev->dev_addr[4] = eeprom[83];
498 + bp->dev->dev_addr[5] = eeprom[82];
499 +
500 + bp->phy_addr = eeprom[90] & 0x1f;
501 + bp->dma_offset = SB_PCI_DMA;
502 + bp->mdc_port = (eeprom[90] >> 14) & 0x1;
503 + }
504
505 /* With this, plus the rx_header prepended to the data by the
506 * hardware, we'll land the ethernet header on a 2-byte boundary.
507 @@ -1702,13 +1878,12 @@
508 bp->imask = IMASK_DEF;
509
510 bp->core_unit = ssb_core_unit(bp);
511 - bp->dma_offset = ssb_get_addr(bp, SBID_PCI_DMA, 0);
512
513 /* XXX - really required?
514 bp->flags |= B44_FLAG_BUGGY_TXPTR;
515 */
516 -out:
517 - return err;
518 +
519 + return 0;
520 }
521
522 static int __devinit b44_init_one(struct pci_dev *pdev,
523 @@ -1720,6 +1895,10 @@
524 struct b44 *bp;
525 int err, i;
526
527 +#ifdef CONFIG_BCM947XX
528 + instance++;
529 +#endif
530 +
531 if (b44_version_printed++ == 0)
532 printk(KERN_INFO "%s", version);
533
534 @@ -1834,11 +2013,17 @@
535 */
536 b44_chip_reset(bp);
537
538 - printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
539 + printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
540 + (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
541 for (i = 0; i < 6; i++)
542 printk("%2.2x%c", dev->dev_addr[i],
543 i == 5 ? '\n' : ':');
544
545 + /* Initialize phy */
546 + spin_lock_irq(&bp->lock);
547 + b44_chip_reset(bp);
548 + spin_unlock_irq(&bp->lock);
549 +
550 return 0;
551
552 err_out_iounmap:
553 Index: linux-2.4.35.4/drivers/net/b44.h
554 ===================================================================
555 --- linux-2.4.35.4.orig/drivers/net/b44.h 2007-12-15 05:19:36.102478402 +0100
556 +++ linux-2.4.35.4/drivers/net/b44.h 2007-12-15 05:20:16.028753670 +0100
557 @@ -229,8 +229,6 @@
558 #define SBIPSFLAG_IMASK4 0x3f000000 /* Which sbflags --> mips interrupt 4 */
559 #define SBIPSFLAG_ISHIFT4 24
560 #define B44_SBTPSFLAG 0x0F18UL /* SB Target Port OCP Slave Flag */
561 -#define SBTPS_NUM0_MASK 0x0000003f
562 -#define SBTPS_F0EN0 0x00000040
563 #define B44_SBADMATCH3 0x0F60UL /* SB Address Match 3 */
564 #define B44_SBADMATCH2 0x0F68UL /* SB Address Match 2 */
565 #define B44_SBADMATCH1 0x0F70UL /* SB Address Match 1 */
566 @@ -461,6 +459,8 @@
567 };
568
569 #define B44_MCAST_TABLE_SIZE 32
570 +#define B44_PHY_ADDR_NO_PHY 30
571 +#define B44_MDC_RATIO 5000000
572
573 /* SW copy of device statistics, kept up to date by periodic timer
574 * which probes HW values. Must have same relative layout as HW
575 Index: linux-2.4.35.4/include/linux/pci_ids.h
576 ===================================================================
577 --- linux-2.4.35.4.orig/include/linux/pci_ids.h 2007-12-15 05:19:36.114479084 +0100
578 +++ linux-2.4.35.4/include/linux/pci_ids.h 2007-12-15 05:20:16.032753896 +0100
579 @@ -1756,6 +1756,7 @@
580 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
581 #define PCI_DEVICE_ID_BCM4401 0x4401
582 #define PCI_DEVICE_ID_BCM4401B0 0x4402
583 +#define PCI_DEVICE_ID_BCM4713 0x4713
584
585 #define PCI_VENDOR_ID_ENE 0x1524
586 #define PCI_DEVICE_ID_ENE_1211 0x1211
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