[ixp4xx] add inital support for the kendin switch on the gtwx5717 board
[openwrt.git] / target / linux / brcm47xx / patches-2.6.25 / 130-remove_scache.patch
1 Index: linux-2.6.25.4/arch/mips/Kconfig
2 ===================================================================
3 --- linux-2.6.25.4.orig/arch/mips/Kconfig
4 +++ linux-2.6.25.4/arch/mips/Kconfig
5 @@ -228,7 +228,6 @@ config MIPS_MALTA
6 select I8259
7 select MIPS_BOARDS_GEN
8 select MIPS_BONITO64
9 - select MIPS_CPU_SCACHE
10 select PCI_GT64XXX_PCI0
11 select MIPS_MSC
12 select SWAP_IO_SPACE
13 @@ -1421,13 +1420,6 @@ config IP22_CPU_SCACHE
14 bool
15 select BOARD_SCACHE
16
17 -#
18 -# Support for a MIPS32 / MIPS64 style S-caches
19 -#
20 -config MIPS_CPU_SCACHE
21 - bool
22 - select BOARD_SCACHE
23 -
24 config R5000_CPU_SCACHE
25 bool
26 select BOARD_SCACHE
27 Index: linux-2.6.25.4/arch/mips/kernel/cpu-probe.c
28 ===================================================================
29 --- linux-2.6.25.4.orig/arch/mips/kernel/cpu-probe.c
30 +++ linux-2.6.25.4/arch/mips/kernel/cpu-probe.c
31 @@ -704,6 +704,8 @@ static inline void cpu_probe_mips(struct
32 break;
33 case PRID_IMP_25KF:
34 c->cputype = CPU_25KF;
35 + /* Probe for L2 cache */
36 + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
37 break;
38 case PRID_IMP_34K:
39 c->cputype = CPU_34K;
40 Index: linux-2.6.25.4/arch/mips/mm/c-r4k.c
41 ===================================================================
42 --- linux-2.6.25.4.orig/arch/mips/mm/c-r4k.c
43 +++ linux-2.6.25.4/arch/mips/mm/c-r4k.c
44 @@ -1103,7 +1103,6 @@ static void __init loongson2_sc_init(voi
45
46 extern int r5k_sc_init(void);
47 extern int rm7k_sc_init(void);
48 -extern int mips_sc_init(void);
49
50 static void __cpuinit setup_scache(void)
51 {
52 @@ -1157,29 +1156,17 @@ static void __cpuinit setup_scache(void)
53 #endif
54
55 default:
56 - if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
57 - c->isa_level == MIPS_CPU_ISA_M32R2 ||
58 - c->isa_level == MIPS_CPU_ISA_M64R1 ||
59 - c->isa_level == MIPS_CPU_ISA_M64R2) {
60 -#ifdef CONFIG_MIPS_CPU_SCACHE
61 - if (mips_sc_init ()) {
62 - scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
63 - printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
64 - scache_size >> 10,
65 - way_string[c->scache.ways], c->scache.linesz);
66 - }
67 -#else
68 - if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
69 - panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
70 -#endif
71 - return;
72 - }
73 sc_present = 0;
74 }
75
76 if (!sc_present)
77 return;
78
79 + if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
80 + c->isa_level == MIPS_CPU_ISA_M64R1) &&
81 + !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
82 + panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
83 +
84 /* compute a couple of other cache variables */
85 c->scache.waysize = scache_size / c->scache.ways;
86
87 Index: linux-2.6.25.4/arch/mips/mm/Makefile
88 ===================================================================
89 --- linux-2.6.25.4.orig/arch/mips/mm/Makefile
90 +++ linux-2.6.25.4/arch/mips/mm/Makefile
91 @@ -32,6 +32,5 @@ obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-
92 obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
93 obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
94 obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
95 -obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
96
97 EXTRA_CFLAGS += -Werror
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