target/linux/ar71xx/files/drivers/mtd/nand/rb4xx_nand.c

   1 /*
   2  *  NAND flash driver for the MikroTik RouterBoard 4xx series
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This file was based on the driver for Linux 2.6.22 published by
   8  *  MikroTik for their RouterBoard 4xx series devices.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License version 2 as published
  12  *  by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/partitions.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/io.h>
  22 #include <linux/gpio.h>
  23
  24 #include <asm/mach-ar71xx/ar71xx.h>
  25
  26 #define DRV_NAME        "rb4xx-nand"
  27 #define DRV_VERSION     "0.1.9"
  28 #define DRV_DESC        "NAND flash driver for RouterBoard 4xx series"
  29
  30 #define USE_FAST_READ   1
  31 #define USE_FAST_WRITE  1
  32 #undef RB4XX_NAND_DEBUG
  33
  34 #ifdef RB4XX_NAND_DEBUG
  35 #define DBG(fmt, arg...)        printk(KERN_DEBUG DRV_NAME ": " fmt, ## arg)
  36 #else
  37 #define DBG(fmt, arg...)        do {} while (0)
  38 #endif
  39
  40 #define RB4XX_NAND_GPIO_RDY     5
  41 #define RB4XX_FLASH_HZ          33333334
  42 #define RB4XX_NAND_HZ           33333334
  43
  44 #define SPI_CTRL_FASTEST        0x40
  45 #define SPI_CTRL_SAFE           0x43    /* 25 MHz for AHB 200 MHz */
  46 #define SBIT_IOC_BASE           SPI_IOC_CS1
  47 #define SBIT_IOC_DO_SHIFT       0
  48 #define SBIT_IOC_DO             (1u << SBIT_IOC_DO_SHIFT)
  49 #define SBIT_IOC_DO2_SHIFT      18
  50 #define SBIT_IOC_DO2            (1u << SBIT_IOC_DO2_SHIFT)
  51
  52 #define CPLD_CMD_WRITE_MULT     0x08    /* send cmd, n x send data, read data */
  53 #define CPLD_CMD_WRITE_CFG      0x09    /* send cmd, n x send cfg */
  54 #define CPLD_CMD_READ_MULT      0x0a    /* send cmd, send idle, n x read data */
  55 #define CPLD_CMD_READ_FAST      0x0b    /* send cmd, 4 x idle, n x read data */
  56
  57 #define CFG_BIT_nCE     0x80
  58 #define CFG_BIT_CLE     0x40
  59 #define CFG_BIT_ALE     0x20
  60 #define CFG_BIT_FAN     0x10
  61 #define CFG_BIT_nLED4   0x08
  62 #define CFG_BIT_nLED3   0x04
  63 #define CFG_BIT_nLED2   0x02
  64 #define CFG_BIT_nLED1   0x01
  65
  66 #define CFG_BIT_nLEDS \
  67         (CFG_BIT_nLED1 | CFG_BIT_nLED2 | CFG_BIT_nLED3 | CFG_BIT_nLED4)
  68
  69 struct rb4xx_nand_info {
  70         struct nand_chip        chip;
  71         struct mtd_info         mtd;
  72 };
  73
  74 /*
  75  * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
  76  * will not be able to find the kernel that we load.
  77  */
  78 static struct nand_ecclayout rb4xx_nand_ecclayout = {
  79         .eccbytes       = 6,
  80         .eccpos         = { 8, 9, 10, 13, 14, 15 },
  81         .oobavail       = 9,
  82         .oobfree        = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  83 };
  84
  85 static struct mtd_partition rb4xx_nand_partitions[] = {
  86         {
  87                 .name   = "kernel",
  88                 .offset = (256 * 1024),
  89                 .size   = (4 * 1024 * 1024) - (256 * 1024),
  90         },
  91         {
  92                 .name   = "rootfs",
  93                 .offset = MTDPART_OFS_NXTBLK,
  94                 .size   = MTDPART_SIZ_FULL,
  95         },
  96         {
  97                 .name   = "booter",
  98                 .offset = 0,
  99                 .size   = (256 * 1024),
 100                 .mask_flags = MTD_WRITEABLE,
 101         }
 102 };
 103
 104 #if USE_FAST_READ
 105 #define SPI_NDATA_BASE  0x00800000
 106 static unsigned spi_ctrl_fread = SPI_CTRL_SAFE;
 107 static unsigned spi_ctrl_flash = SPI_CTRL_SAFE;
 108 extern unsigned mips_hpt_frequency;
 109 #endif
 110
 111 static inline unsigned rb4xx_spi_rreg(unsigned r)
 112 {
 113         return __raw_readl((void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r));
 114 }
 115
 116 static inline void rb4xx_spi_wreg(unsigned r, unsigned v)
 117 {
 118         __raw_writel(v, (void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r));
 119 }
 120
 121 static inline void do_spi_clk(int bit)
 122 {
 123         unsigned bval = SBIT_IOC_BASE | (bit & 1);
 124
 125         rb4xx_spi_wreg(SPI_REG_IOC, bval);
 126         rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK);
 127 }
 128
 129 static void do_spi_byte(uint8_t byte)
 130 {
 131         do_spi_clk(byte >> 7);
 132         do_spi_clk(byte >> 6);
 133         do_spi_clk(byte >> 5);
 134         do_spi_clk(byte >> 4);
 135         do_spi_clk(byte >> 3);
 136         do_spi_clk(byte >> 2);
 137         do_spi_clk(byte >> 1);
 138         do_spi_clk(byte);
 139
 140         DBG("spi_byte sent 0x%02x got 0x%x\n",
 141                                         byte, rb4xx_spi_rreg(SPI_REG_RDS));
 142 }
 143
 144 #if USE_FAST_WRITE
 145 static inline void do_spi_clk_fast(int bit1, int bit2)
 146 {
 147         unsigned bval = (SBIT_IOC_BASE |
 148                         ((bit1 << SBIT_IOC_DO_SHIFT) & SBIT_IOC_DO) |
 149                         ((bit2 << SBIT_IOC_DO2_SHIFT) & SBIT_IOC_DO2));
 150
 151         rb4xx_spi_wreg(SPI_REG_IOC, bval);
 152         rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK);
 153 }
 154
 155 static inline void do_spi_byte_fast(uint8_t byte)
 156 {
 157         do_spi_clk_fast(byte >> 7, byte >> 6);
 158         do_spi_clk_fast(byte >> 5, byte >> 4);
 159         do_spi_clk_fast(byte >> 3, byte >> 2);
 160         do_spi_clk_fast(byte >> 1, byte >> 0);
 161
 162         DBG("spi_byte_fast sent 0x%02x got 0x%x\n",
 163                                         byte, rb4xx_spi_rreg(SPI_REG_RDS));
 164 }
 165 #else
 166 static inline void do_spi_byte_fast(uint8_t byte)
 167 {
 168         do_spi_byte(byte);
 169 }
 170 #endif /* USE_FAST_WRITE */
 171
 172 static int do_spi_cmd(unsigned cmd, unsigned sendCnt, const uint8_t *sendData,
 173                 unsigned recvCnt, uint8_t *recvData,
 174                 const uint8_t *verifyData, int fastWrite)
 175 {
 176         unsigned i;
 177
 178         DBG("SPI cmd 0x%x send %u recv %u\n", cmd, sendCnt, recvCnt);
 179
 180         rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO);
 181         rb4xx_spi_wreg(SPI_REG_CTRL, SPI_CTRL_FASTEST);
 182
 183         do_spi_byte(cmd);
 184 #if 0
 185         if (cmd == CPLD_CMD_READ_FAST) {
 186                 do_spi_byte(0x80);
 187                 do_spi_byte(0);
 188                 do_spi_byte(0);
 189         }
 190 #endif
 191         for (i = 0; i < sendCnt; ++i) {
 192                 if (fastWrite)
 193                         do_spi_byte_fast(sendData[i]);
 194                 else
 195                         do_spi_byte(sendData[i]);
 196         }
 197
 198         for (i = 0; i < recvCnt; ++i) {
 199                 if (fastWrite)
 200                         do_spi_byte_fast(0);
 201                 else
 202                         do_spi_byte(0);
 203
 204                 if (recvData) {
 205                         recvData[i] = rb4xx_spi_rreg(SPI_REG_RDS) & 0xff;
 206                 } else if (verifyData) {
 207                         if (verifyData[i] != (rb4xx_spi_rreg(SPI_REG_RDS)
 208                                                          & 0xff))
 209                                 break;
 210                 }
 211         }
 212
 213         rb4xx_spi_wreg(SPI_REG_IOC, SBIT_IOC_BASE | SPI_IOC_CS0);
 214         rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_flash);
 215         rb4xx_spi_wreg(SPI_REG_FS, 0);
 216
 217         return i == recvCnt;
 218 }
 219
 220 static int got_write = 1;
 221
 222 static void rb4xx_nand_write_data(const uint8_t *byte, unsigned cnt)
 223 {
 224         do_spi_cmd(CPLD_CMD_WRITE_MULT, cnt, byte, 1, NULL, NULL, 1);
 225         got_write = 1;
 226 }
 227
 228 static void rb4xx_nand_write_byte(uint8_t byte)
 229 {
 230         rb4xx_nand_write_data(&byte, 1);
 231 }
 232
 233 #if USE_FAST_READ
 234 static uint8_t *rb4xx_nand_read_getaddr(unsigned cnt)
 235 {
 236         static unsigned nboffset = 0x100000;
 237         unsigned addr;
 238
 239         if (got_write) {
 240                 nboffset = (nboffset + 31) & ~31;
 241                 if (nboffset >= 0x100000)       /* 1MB */
 242                         nboffset = 0;
 243
 244                 got_write = 0;
 245                 rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO);
 246                 rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_fread);
 247                 rb4xx_spi_wreg(SPI_REG_FS, 0);
 248         }
 249
 250         addr = KSEG1ADDR(AR71XX_SPI_BASE + SPI_NDATA_BASE) + nboffset;
 251         DBG("rb4xx_nand_read_getaddr 0x%x cnt 0x%x\n", addr, cnt);
 252
 253         nboffset += cnt;
 254         return (uint8_t *)addr;
 255 }
 256
 257 static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt)
 258 {
 259         unsigned size32 = cnt & ~31;
 260         unsigned remain = cnt & 31;
 261
 262         if (size32) {
 263                 uint8_t *addr = rb4xx_nand_read_getaddr(size32);
 264                 memcpy(buf, (void *)addr, size32);
 265         }
 266
 267         if (remain) {
 268                 do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain,
 269                            buf + size32, NULL, 0);
 270         }
 271 }
 272
 273 static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt)
 274 {
 275         unsigned size32 = cnt & ~31;
 276         unsigned remain = cnt & 31;
 277
 278         if (size32) {
 279                 uint8_t *addr = rb4xx_nand_read_getaddr(size32);
 280                 if (memcmp(buf, (void *)addr, size32) != 0)
 281                         return 0;
 282         }
 283
 284         if (remain) {
 285                 return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain,
 286                                   NULL, buf + size32, 0);
 287         }
 288         return 1;
 289 }
 290 #else /* USE_FAST_READ */
 291 static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt)
 292 {
 293         do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, buf, NULL, 0);
 294 }
 295
 296 static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt)
 297 {
 298         return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, NULL, buf, 0);
 299 }
 300 #endif /* USE_FAST_READ */
 301
 302 static void rb4xx_nand_write_cfg(uint8_t byte)
 303 {
 304         do_spi_cmd(CPLD_CMD_WRITE_CFG, 1, &byte, 0, NULL, NULL, 0);
 305         got_write = 1;
 306 }
 307
 308 static int rb4xx_nand_dev_ready(struct mtd_info *mtd)
 309 {
 310         return gpio_get_value(RB4XX_NAND_GPIO_RDY);
 311 }
 312
 313 static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 314                                 unsigned int ctrl)
 315 {
 316         if (ctrl & NAND_CTRL_CHANGE) {
 317                 uint8_t cfg = CFG_BIT_nLEDS;
 318
 319                 cfg |= (ctrl & NAND_CLE) ? CFG_BIT_CLE : 0;
 320                 cfg |= (ctrl & NAND_ALE) ? CFG_BIT_ALE : 0;
 321                 cfg |= (ctrl & NAND_NCE) ? 0 : CFG_BIT_nCE;
 322
 323                 rb4xx_nand_write_cfg(cfg);
 324         }
 325
 326         if (cmd != NAND_CMD_NONE)
 327                 rb4xx_nand_write_byte(cmd);
 328 }
 329
 330 static uint8_t rb4xx_nand_read_byte(struct mtd_info *mtd)
 331 {
 332         uint8_t byte = 0;
 333
 334         rb4xx_nand_read_data(&byte, 1);
 335         return byte;
 336 }
 337
 338 static void rb4xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 339                                 int len)
 340 {
 341         rb4xx_nand_write_data(buf, len);
 342 }
 343
 344 static void rb4xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf,
 345                                 int len)
 346 {
 347         rb4xx_nand_read_data(buf, len);
 348 }
 349
 350 static int rb4xx_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
 351                                 int len)
 352 {
 353         if (!rb4xx_nand_verify_data(buf, len))
 354                 return -EFAULT;
 355
 356         return 0;
 357 }
 358
 359 static unsigned get_spi_ctrl(unsigned hz_max, const char *name)
 360 {
 361         unsigned div;
 362
 363         div = (ar71xx_ahb_freq - 1) / (2 * hz_max);
 364         /*
 365          * CPU has a bug at (div == 0) - first bit read is random
 366          */
 367         if (div == 0)
 368                 ++div;
 369
 370         if (name) {
 371                 unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000;
 372                 unsigned div_real = 2 * (div + 1);
 373                 printk(KERN_INFO "%s SPI clock %u kHz (AHB %u kHz / %u)\n",
 374                        name,
 375                        ahb_khz / div_real,
 376                        ahb_khz, div_real);
 377         }
 378
 379         return SPI_CTRL_FASTEST + div;
 380 }
 381
 382 static int __init rb4xx_nand_probe(struct platform_device *pdev)
 383 {
 384         struct rb4xx_nand_info  *info;
 385         int ret;
 386
 387         printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
 388
 389         ret = gpio_request(RB4XX_NAND_GPIO_RDY, "NAND RDY");
 390         if (ret) {
 391                 printk(KERN_ERR "rb4xx-nand: gpio request failed\n");
 392                 return ret;
 393         }
 394
 395         ret = gpio_direction_input(RB4XX_NAND_GPIO_RDY);
 396         if (ret) {
 397                 printk(KERN_ERR "rb4xx-nand: unable to set input mode "
 398                                         "on gpio%d\n", RB4XX_NAND_GPIO_RDY);
 399                 goto err_free_gpio;
 400         }
 401
 402         info = kzalloc(sizeof(*info), GFP_KERNEL);
 403         if (!info) {
 404                 printk(KERN_ERR "rb4xx-nand: no memory for private data\n");
 405                 ret = -ENOMEM;
 406                 goto err_free_gpio;
 407         }
 408
 409 #if USE_FAST_READ
 410         spi_ctrl_fread = get_spi_ctrl(RB4XX_NAND_HZ, "NAND");
 411 #endif
 412         spi_ctrl_flash = get_spi_ctrl(RB4XX_FLASH_HZ, "FLASH");
 413
 414         rb4xx_nand_write_cfg(CFG_BIT_nLEDS | CFG_BIT_nCE);
 415
 416         info->chip.priv = &info;
 417         info->mtd.priv  = &info->chip;
 418         info->mtd.owner = THIS_MODULE;
 419
 420         info->chip.cmd_ctrl     = rb4xx_nand_cmd_ctrl;
 421         info->chip.dev_ready    = rb4xx_nand_dev_ready;
 422         info->chip.read_byte    = rb4xx_nand_read_byte;
 423         info->chip.write_buf    = rb4xx_nand_write_buf;
 424         info->chip.read_buf     = rb4xx_nand_read_buf;
 425         info->chip.verify_buf   = rb4xx_nand_verify_buf;
 426
 427         info->chip.chip_delay   = 25;
 428         info->chip.ecc.mode     = NAND_ECC_SOFT;
 429         info->chip.options      |= NAND_NO_AUTOINCR;
 430
 431         platform_set_drvdata(pdev, info);
 432
 433         ret = nand_scan_ident(&info->mtd, 1);
 434         if (ret) {
 435                 ret = -ENXIO;
 436                 goto err_free_info;
 437         }
 438
 439         if (info->mtd.writesize == 512)
 440                 info->chip.ecc.layout = &rb4xx_nand_ecclayout;
 441
 442         ret = nand_scan_tail(&info->mtd);
 443         if (ret) {
 444                 return -ENXIO;
 445                 goto err_set_drvdata;
 446         }
 447
 448 #ifdef CONFIG_MTD_PARTITIONS
 449         ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions,
 450                                 ARRAY_SIZE(rb4xx_nand_partitions));
 451 #else
 452         ret = add_mtd_device(&info->mtd);
 453 #endif
 454         if (ret)
 455                 goto err_release_nand;
 456
 457         return 0;
 458
 459 err_release_nand:
 460         nand_release(&info->mtd);
 461 err_set_drvdata:
 462         platform_set_drvdata(pdev, NULL);
 463 err_free_info:
 464         kfree(info);
 465 err_free_gpio:
 466         gpio_free(RB4XX_NAND_GPIO_RDY);
 467         return ret;
 468 }
 469
 470 static int __devexit rb4xx_nand_remove(struct platform_device *pdev)
 471 {
 472         struct rb4xx_nand_info *info = platform_get_drvdata(pdev);
 473
 474         nand_release(&info->mtd);
 475         platform_set_drvdata(pdev, NULL);
 476         kfree(info);
 477
 478         return 0;
 479 }
 480
 481 static struct platform_driver rb4xx_nand_driver = {
 482         .probe  = rb4xx_nand_probe,
 483         .remove = __devexit_p(rb4xx_nand_remove),
 484         .driver = {
 485                 .name   = DRV_NAME,
 486                 .owner  = THIS_MODULE,
 487         },
 488 };
 489
 490 static int __init rb4xx_nand_init(void)
 491 {
 492         return platform_driver_register(&rb4xx_nand_driver);
 493 }
 494
 495 static void __exit rb4xx_nand_exit(void)
 496 {
 497         platform_driver_unregister(&rb4xx_nand_driver);
 498 }
 499
 500 module_init(rb4xx_nand_init);
 501 module_exit(rb4xx_nand_exit);
 502
 503 MODULE_DESCRIPTION(DRV_DESC);
 504 MODULE_VERSION(DRV_VERSION);
 505 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 506 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
 507 MODULE_LICENSE("GPL v2");